Method and device for testing internal parasitic parameters of a chip

Abstract

The application discloses a chip internal parasitic parameter testing method and a device for realizing the method, wherein the chip internal parasitic parameter testing method comprises the following steps: obtaining a high-level threshold voltage of a to-be-tested pin; configuring the to-be-tested pin as a timer trigger mode; setting a signal output pin as a high level, so that a counter of a timer in the chip starts counting, and a voltage value of a parasitic capacitor rises to the high-level threshold voltage; obtaining a counting value of the timer at this time; changing a resistance value of an adjustable resistor multiple times and obtaining multiple counting values of the timer; and obtaining a capacitance value of a first equivalent parasitic capacitor according to the above parameters. Thus, the chip internal parasitic parameter is measured by means of the chip itself pin, the parasitic parameter conforming to the actual working scene of the chip is obtained, and the test cost is reduced without relying on external equipment.

Description

Technical Field

[0001] This invention relates to the field of chip testing, and in particular to a method and chip for testing internal parasitic parameters of a chip. Background Technology

[0002] After a chip is designed and manufactured, parasitic resistance and capacitance exist within its signal paths. These parasitic resistance and capacitance values ​​are known as the chip's internal parasitic parameters. When the chip is used in high-speed communication or fast ADC sampling applications, these internal parasitic resistance and capacitance must be comprehensively considered. Therefore, parasitic parameters that closely approximate the actual internal conditions of the chip are needed. Existing instruments for measuring resistance and capacitance are generally used when the device is not powered. However, the parasitic resistance and capacitance within a chip exhibit different values ​​when the chip is powered on and off. Furthermore, only the parasitic resistance and capacitance values ​​when the chip is powered on are the closest to the actual internal conditions of the chip. Therefore, current technologies cannot provide parasitic parameters that most closely approximate the actual internal conditions of the chip. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a method for testing internal parasitic parameters of a chip, which can test internal parasitic parameters using the chip's own pins, thereby measuring parasitic parameters that conform to the actual operating scenario of the chip.

[0004] The present invention also proposes an apparatus for testing the above-mentioned internal parasitic parameters of the chip.

[0005] The present invention also proposes a computer-readable storage medium.

[0006] A method for testing internal parasitic parameters of a chip according to a first aspect of the present invention is applied to a chip, the chip comprising: a timer, a PWM signal output pin, a GPIO pin, and a first equivalent parasitic capacitance, wherein the PWM signal output pin is electrically connected to the GPIO pin via an adjustable resistor, and the GPIO pin is connected to the first equivalent parasitic capacitance; the method for testing internal parasitic parameters of the chip includes:

[0007] Obtain the high-level threshold voltage of the GPIO pin;

[0008] Configure the GPIO pin to timer trigger mode;

[0009] Set the PWM signal output pin to high level and clear the timer counter to zero, then start the timer counter to start counting.

[0010] The PWM signal output pin charges the GPIO pin through the adjustable resistor, causing the voltage value of the first equivalent parasitic capacitance to rise to the high-level threshold voltage, and the count value of the timer at this time is obtained.

[0011] By repeatedly changing the resistance value of the adjustable resistor and returning to the steps of setting the PWM signal output pin to a high level, clearing the timer counter, and then starting the timer counter to start counting, multiple count values ​​of the timer are obtained.

[0012] The capacitance value of the first equivalent parasitic capacitance is obtained based on the multiple count values, the output voltage of the PWM signal output pin, and the high-level threshold voltage.

[0013] According to some embodiments of the present invention, obtaining the high-level threshold voltage of the GPIO pin includes:

[0014] Set the GPIO pin to normal input mode;

[0015] A gradually increasing voltage is applied to the GPIO pin;

[0016] When the input value of the GPIO pin is high, the voltage value is recorded, and the voltage value is the high-level threshold voltage.

[0017] According to some embodiments of the present invention, obtaining the capacitance value of the first equivalent parasitic capacitance based on a plurality of the count values, the output voltage of the PWM signal output pin, and the high-level threshold voltage includes:

[0018] Based on the multiple count values ​​and the clock value of the timer, multiple recognition times for the GPIO pin to recognize a high level are calculated;

[0019] Substituting the multiple recognition times, the resistance values ​​of the multiple adjustable resistors, the output voltage of the PWM signal output pin, and the high-level threshold voltage into the capacitor charging formula, we obtain the first set of charging equations.

[0020] Solve the first set of charging equations to obtain the capacitance value of the first equivalent parasitic capacitance.

[0021] According to some embodiments of the present invention, when the GPIO pin is an ADC pin with ADC function, the chip further includes: an equivalent parasitic resistance, a second equivalent parasitic capacitance, the PWM signal output pin being electrically connected to the ADC pin through an adjustable resistor, the ADC pin being connected to the first equivalent parasitic capacitance, the ADC pin also being connected to one end of the equivalent parasitic resistance, and the other end of the equivalent parasitic resistance being connected to the second equivalent parasitic capacitance; the method for testing the internal parasitic parameters of the chip further includes:

[0022] Configure the ADC pin to analog input mode;

[0023] Set the sampling time setting value of the ADC pin;

[0024] After setting the PWM signal output pin to a high level and clearing the timer counter to zero, the timer counter starts counting, and the ADC pin is triggered to sample.

[0025] When the timer count reaches the sampling time set value, the sampling voltage of the ADC pin at this time is obtained;

[0026] By repeatedly changing the resistance value of the adjustable resistor and returning to the step of configuring the ADC pin in analog input mode, multiple sampling voltages are obtained;

[0027] The capacitance value of the second equivalent parasitic capacitor and the resistance value of the parasitic resistor are obtained based on the multiple sampling voltages, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitor.

[0028] According to some embodiments of the present invention, obtaining the capacitance value of the second equivalent parasitic capacitance and the resistance value of the parasitic resistance based on the plurality of sampled voltages, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitance includes:

[0029] Substituting the multiple sampling voltages, the resistance values ​​of the multiple adjustable resistors, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitance into the capacitor charging formula, we obtain the second charging equation set.

[0030] Solve the second set of charging equations to obtain the capacitance value of the second equivalent parasitic capacitance and the resistance value of the equivalent parasitic resistance.

[0031] According to some embodiments of the present invention, the chip further includes a sampling switch disposed between the ADC pin and the equivalent parasitic resistance, and a method for testing the internal parasitic parameters of the chip includes:

[0032] When the sampling switch is off, the GPIO pin does not have ADC function;

[0033] When the sampling switch is closed, the GPIO pin has ADC functionality.

[0034] According to some embodiments of the present invention, the capacitor charging formula is as follows:

[0035] ;

[0036] in, It is the voltage across the capacitor at time t. R is the output voltage of the PWM signal output pin, R is the resistance value of the adjustable resistor, and C is the capacitance value of the first equivalent parasitic capacitance.

[0037] According to some embodiments of the present invention, the second set of charging equations is as follows:

[0038] ;

[0039] Wherein, Vs is the voltage value of the sampling voltage, Rx is the resistance value of the adjustable resistor, Vout is the output voltage value of the PWM signal output pin, C1 is the capacitance value of the first equivalent parasitic capacitance, C2 is the capacitance value of the second equivalent parasitic capacitance, Ts is the sampling time setting value of the ADC pin, and R1 is the resistance value of the equivalent parasitic resistor.

[0040] An apparatus for testing internal parasitic parameters of a chip according to a second aspect of the present invention, the chip comprising:

[0041] One or more processors;

[0042] Memory;

[0043] One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, wherein when the programs are executed by the processors, they implement the steps of a method for testing internal parasitic parameters of a chip as described in any of the above embodiments.

[0044] According to a third aspect of the present invention, a computer-readable storage medium thereon stores a computer program that, when executed by a processor, implements the steps of a method for testing internal parasitic parameters of a chip as described in any of the above embodiments.

[0045] The method for testing internal parasitic parameters of a chip according to embodiments of the present invention has at least the following advantages: by electrically connecting the PWM signal output pin to the GPIO pin through an adjustable resistor, and changing the level of the PWM signal output pin, the capacitance value of the parasitic capacitance is calculated by recording the corresponding parameters. This allows for the measurement of internal parasitic parameters of the chip using the chip's own pins while the chip is powered on, thus obtaining parasitic parameters that conform to the actual working scenario of the chip without relying on external instruments and equipment, thereby reducing testing costs.

[0046] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0047] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0048] Figure 1 This is a flowchart illustrating the method for testing internal parasitic parameters of a chip according to an embodiment of the present invention.

[0049] Figure 2 for Figure 1 The flowchart illustrates the additional steps in the test method for internal parasitic parameters of the chip when the GPIO pin is an ADC pin with ADC function.

[0050] Figure 3 This is a schematic diagram of the electrical connections of the GPIO pins without ADC function in the test device for testing internal parasitic parameters of a chip according to an embodiment of the present invention.

[0051] Figure 4 for Figure 3 The diagram shows the signal waveforms of the GPIO pins without ADC function in the test device for testing internal parasitic parameters of the chip.

[0052] Figure 5 This is a schematic diagram of the electrical connection of the ADC pin with ADC function in the chip internal parasitic parameter testing device according to an embodiment of the present invention.

[0053] Figure 6 for Figure 5 The diagram shows the signal waveform of the ADC pin with ADC function in the test device for testing internal parasitic parameters of the chip. Detailed Implementation

[0054] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0055] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0056] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0057] In the description of this invention, unless otherwise explicitly defined, terms such as "setting," "installing," and "connecting" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0058] The following is in conjunction with the appendix Figure 1-6 This invention provides a detailed description of the testing method and apparatus for internal parasitic parameters of a chip according to embodiments of the present invention.

[0059] Reference Figure 1 and Figure 3 This invention proposes a method for testing internal parasitic parameters of a chip, applied to a microcontroller (MCU). The MCU includes a timer, a PWM signal output pin, a GPIO pin, and a first equivalent parasitic capacitance C1. The PWM signal output pin is electrically connected to the GPIO pin via an adjustable resistor Rx, and the GPIO pin is connected to the first equivalent parasitic capacitance C1. The method for testing internal parasitic parameters of the chip includes:

[0060] S100: Obtain the high-level threshold voltage VIH of the GPIO pin;

[0061] S200: Configure the GPIO pin to timer trigger mode;

[0062] S300: Sets the PWM signal output pin to high level and clears the timer counter, then starts the timer counter counting.

[0063] S400: The PWM signal output pin charges the GPIO pin through the adjustable resistor Rx, causing the voltage value of the first equivalent parasitic capacitance C1 to rise to the high-level threshold voltage, and the count value of the timer at this time is obtained.

[0064] S500: After repeatedly changing the resistance value of the adjustable resistor Rx, and returning to the steps of setting the PWM signal output pin to a high level, clearing the timer counter, and then starting the timer counter to start counting, the count values ​​of multiple timers are obtained.

[0065] S600: Based on multiple count values ​​Count, the output voltage Vout of the PWM signal output pin, and the high-level threshold voltage VIH, obtain the capacitance value of the first equivalent parasitic capacitance C1.

[0066] Specifically, in this embodiment, referring to Figure 3 The PWM signal output pin of the MCU chip is electrically connected to the GPIO pin via an externally soldered or detachably electrically connected adjustable resistor Rx. The GPIO pin is internally connected to one end of the first equivalent parasitic capacitance C1 within the MCU chip. The GPIO pin is also internally connected to a Schmitt trigger (SCHMITT). The Schmitt trigger is used for signal processing and waveform shaping of the GPIO pin, effectively eliminating noise interference and preventing false triggering caused by small fluctuations, thereby improving signal quality and stability. (Refer to...) Figure 1 Regarding the method for measuring internal parasitic parameters of the chip in this embodiment, step S100 specifically involves: setting the GPIO to normal input mode, applying a gradually increasing voltage to the GPIO pin, and recording the voltage value of the GPIO pin when the input value of the GPIO pin is high. This voltage value is the high-level threshold voltage VIH. For steps S300 and S400, refer to... Figure 4 Configure the GPIO pin to timer trigger mode and set the timer clock value to Clk. At time a, the PWM signal output pin outputs a high level. Simultaneously, the internal timer counter starts counting. The PWM signal output pin charges the internal circuitry of the GPIO pin through the adjustable resistor Rx, specifically charging the first equivalent parasitic capacitance C1 electrically connected to the GPIO pin inside the MCU. This causes the voltage at one end of the first equivalent parasitic capacitance C1 to increase synchronously with the voltage level of the GPIO pin. At time b, the voltage of the GPIO pin reaches the high-level threshold voltage VIH, and the internal timer counter stops counting, yielding the count value Count. According to the formula... Calculate the time Tx from when the PWM signal output pin outputs a high level at time a to when the GPIO pin recognizes a high level at time b. Step S500 specifically involves: changing the value of the adjustable resistor Rx to obtain several different sets of adjustable resistor Rx values ​​and corresponding time Tx values ​​from time a to time b. The output voltage of the PWM signal output pin is Vout. Based on the capacitor charging formula... List the equations The equation is obtained through mathematical transformation. By changing the value of the adjustable resistor Rx, several different sets of adjustable resistor Rx values ​​and the corresponding time Tx values ​​from time a to time b are obtained. These, along with the high-level threshold voltage VIH and the output voltage Vout of the PWM signal output pin, are substituted into the equation. In this process, the corresponding set of equations is obtained, and the capacitance value of the first equivalent parasitic capacitance C1 is calculated by solving the set of equations.

[0067] Reference Figure 1 and Figure 3 Furthermore, in some embodiments of the present invention, step S100: obtaining the high-level threshold voltage VIH of the GPIO pin includes:

[0068] (1) Set the GPIO pin to normal input mode;

[0069] (2) Provide a gradually increasing voltage to the GPIO pin;

[0070] (3) When the input value of the GPIO pin is high, record the voltage value of the GPIO pin. The voltage value is the high-level threshold voltage VIH.

[0071] Specifically, in this embodiment, step S100 is as follows: set GPIO to normal input mode, apply a gradually increasing voltage to the GPIO pin, and when the input value of the GPIO pin is high, record the voltage value of the GPIO pin at this time. This voltage value is the high-level threshold voltage VIH.

[0072] Reference Figure 1 Furthermore, in some embodiments of the present invention, step S600: obtaining the capacitance value of the first equivalent parasitic capacitance C1 based on multiple count values ​​Count, the output voltage Vout of the PWM signal output pin, and the high-level threshold voltage VIH, includes:

[0073] (1) Calculate the multiple recognition times Tx for the GPIO pin to recognize the high level based on multiple count values ​​Count and the clock value Clk of the timer;

[0074] (2) Substitute the multiple recognition time Counts, the resistance values ​​of multiple adjustable resistors Rx, the output voltage Vout of the PWM signal output pin, and the high-level threshold voltage VIH into the capacitor charging formula to obtain the first charging equation set;

[0075] (3) Solve the first charging equation set to obtain the capacitance value of the first equivalent parasitic capacitance C1.

[0076] Specifically, in this embodiment, step (1) involves substituting the multiple count values ​​Count and the clock value Clk of the timer into the formula. In this way, several different variable resistor Rx values ​​and corresponding time Tx values ​​from time a to time b are obtained.

[0077] Steps (2) and (3) are as follows: Based on the capacitor charging formula, list the equations. The equation is obtained through mathematical transformation. By changing the value of the adjustable resistor Rx, several different sets of adjustable resistor Rx values ​​and the corresponding time Tx values ​​from time a to time b are substituted together with the high-level threshold voltage VIH and the output voltage Vout of the PWM signal output pin into the equation. In this process, the corresponding first set of equations is obtained, and the capacitance value of the first equivalent parasitic capacitance C1 is calculated by solving the first set of equations. By changing the resistance value of the adjustable resistor Rx, several different sets of time Tx values ​​are formed, thus forming a set of equations, making the calculated capacitance value of the first equivalent parasitic capacitance C1 more accurate and reliable.

[0078] Reference Figure 2 and Figure 5 Furthermore, in some embodiments of the present invention, when the GPIO pin is an ADC pin with ADC function, the chip MCU further includes: an equivalent parasitic resistance R1, a second equivalent parasitic capacitance C2, a PWM signal output pin electrically connected to the ADC pin through an adjustable resistor Rx, the ADC pin connected to the first equivalent parasitic capacitance C1, the ADC pin also connected to one end of the equivalent parasitic resistance R1, and the other end of the equivalent parasitic resistance R1 connected to the second equivalent parasitic capacitance C2; ​​the method for testing the internal parasitic parameters of the chip further includes:

[0079] S710: Configure the ADC pin to analog input mode;

[0080] S720: Sets the sampling time setting value Ts for the ADC pin;

[0081] S730: After setting the PWM signal output pin to a high level and clearing the timer counter, the timer counter starts counting, and the ADC pin triggers sampling.

[0082] S740: When the timer count reaches the sampling time set value Ts, obtain the sampling voltage Vs of the ADC pin at this time;

[0083] S750: Change the resistance value of the adjustable resistor Rx multiple times and return to the steps of configuring the ADC pin to analog input mode to obtain multiple sampled voltages Vs;

[0084] S760: Based on multiple sampled voltages Vs, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitance C1, the capacitance value of the second equivalent parasitic capacitance C2 and the resistance value of the parasitic resistance R1 are obtained.

[0085] Specifically, in this embodiment, referring to Figure 5 When a GPIO pin has ADC functionality, it becomes an ADC pin. The ADC pin is connected to the first equivalent parasitic capacitance C1. The ADC pin is also connected to one end of the equivalent parasitic resistance R1 via a sampling switch Ks. The other end of the equivalent parasitic resistance R1 is connected to the second equivalent parasitic capacitance C2. The other end of the equivalent parasitic resistance R1 is also electrically connected to the analog-to-digital conversion module inside the chip's MCU. Therefore, when the sampling switch Ks is open, the GPIO pin does not have ADC functionality; when the sampling switch Ks is closed, the GPIO pin becomes an ADC pin with ADC functionality. Steps S710 to S760 are additional steps based on steps S100 to S600 when the GPIO pin has ADC functionality. For steps S730 and S740, refer to... Figure 6 At time a, the PWM signal output pin changes from low to high, charging the ADC pin through the adjustable resistor Rx, i.e., charging the first equivalent parasitic capacitance C1 and the second equivalent parasitic capacitance C2. At this time, the timer inside the MCU enables the chip to start counting, and the ADC pin level gradually increases. At time b, when the timer reaches the sampling time set value Ts, the sampling voltage Vs is recorded. Then, step S750 is executed, changing the resistance value of the adjustable resistor Rx, and measuring the sampling voltage Vs corresponding to several sets of different adjustable resistor Rx values. For example, measuring two sets of data, resistance value Rx1 corresponds to sampling voltage Vs1, and resistance value Rx2 corresponds to sampling voltage Vs2. Then, step S760 is executed, according to... Figure 5 Based on the circuit shown and the capacitor charging equation, the second set of charging equations can be derived. Then, the resistance value Rx1 and its corresponding sampling voltage Vs1, the resistance value Rx2 and its corresponding sampling voltage Vs2, the first equivalent parasitic capacitance C1 obtained from steps S100 to S600, and the output voltage Vout of the PWM signal output pin are substituted into the second charging equation to obtain the following set of second charging equations:

[0086]

[0087] Solving this system of equations yields the equivalent parasitic resistance R1 and the second equivalent parasitic capacitance C2. The parasitic resistance of the ADC pin is the same as the equivalent parasitic resistance R1, and the parasitic capacitance of the ADC pin is the sum of the first equivalent parasitic capacitance C1 and the second equivalent parasitic capacitance C2.

[0088] Reference Figure 2 Furthermore, in some embodiments of the present invention, step S760: obtaining the capacitance value of the second equivalent parasitic capacitance C2 and the resistance value of the parasitic resistance R1 based on multiple sampled voltages Vs, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitance C1, includes:

[0089] Substituting the multiple sampled voltages Vs, the resistance values ​​Rx of multiple adjustable resistors, the output voltage Vout of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitance into the capacitor charging formula, we obtain the second charging equation set.

[0090] Solve the second set of charging equations to obtain the second parasitic capacitance value C2 and parasitic resistance value R1.

[0091] Specifically, in this embodiment, after changing the resistance value of the adjustable resistor Rx and measuring the sampling voltage Vs corresponding to several different adjustable resistor Rx values—for example, measuring two sets of data where resistance value Rx1 corresponds to sampling voltage Vs1 and resistance value Rx2 corresponds to sampling voltage Vs2—then according to… Figure 5 Based on the circuit shown and the capacitor charging equation, the second set of charging equations can be derived. Substituting the resistance value Rx1 and its corresponding sampling voltage Vs1, the resistance value Rx2 and its corresponding sampling voltage Vs2, the first equivalent parasitic capacitance C1 obtained from steps S100 to S600, and the output voltage Vout of the PWM signal output pin into the charging equation, we obtain the following second set of charging equations:

[0092]

[0093] Solving the second charging equations yields the equivalent parasitic resistance R1 and the second equivalent parasitic capacitance C2. The parasitic resistance of the ADC pin is the same as the equivalent parasitic resistance R1, and the parasitic capacitance of the ADC pin is the sum of the first equivalent parasitic capacitance C1 and the second equivalent parasitic capacitance C2.

[0094] Reference Figure 5Furthermore, in some embodiments of the present invention, the chip MCU further includes a sampling switch Ks, which is disposed between the ADC pin and the equivalent parasitic resistance R1. The method for testing the internal parasitic parameters of the chip further includes:

[0095] When the sampling switch Ks is off, the GPIO pin does not have ADC function;

[0096] When the sampling switch Ks is closed, the GPIO pin has ADC functionality.

[0097] Specifically, in this embodiment, since the ADC pin is also connected to one end of the equivalent parasitic resistance R1 through the sampling switch Ks, and the other end of the equivalent parasitic resistance R1 is connected to the second equivalent parasitic capacitance C2, and the other end of the equivalent parasitic resistance R1 is also electrically connected to the analog-to-digital conversion module ADC inside the chip MCU, when the sampling switch Ks is open, the GPIO pin is a GPIO pin without ADC function, and when the sampling switch Ks is closed, the GPIO pin is an ADC pin with ADC function.

[0098] Furthermore, in some embodiments of the present invention, the above-mentioned capacitor charging formula is as follows:

[0099] ;

[0100] in, It is the voltage across the capacitor at time t. R is the output voltage of the PWM signal output pin, R is the resistance value of the adjustable resistor, and C is the capacitance value of the first equivalent parasitic capacitance.

[0101] Furthermore, in some embodiments of the present invention, the above-mentioned second charging equation set is as follows:

[0102] ;

[0103] Where Vs is the sampling voltage value, Rx is the resistance value of the adjustable resistor, Vout is the output voltage value of the PWM signal output pin, C1 is the capacitance value of the first equivalent parasitic capacitance, C2 is the capacitance value of the second equivalent parasitic capacitance, Ts is the sampling time setting value of the ADC pin, and R1 is the resistance value of the equivalent parasitic resistance.

[0104] The present invention also proposes a testing device for internal parasitic parameters of a chip, wherein the chip MCU includes: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, and when the programs are executed by the processors, they implement the steps of the chip internal parasitic parameter testing method as described above.

[0105] The present invention also proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the chip internal parasitic parameter testing method as described above.

[0106] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. In the context of this invention, the computer-readable medium can be considered tangible and non-transitory. Non-limiting examples of non-transitory tangible computer-readable media include non-volatile memory circuits (e.g., flash memory circuits, erasable programmable read-only memory circuits, or mask read-only memory circuits), volatile memory circuits (e.g., static random access memory circuits or dynamic random access memory circuits), magnetic storage media (e.g., analog or digital magnetic tape or hard disk drives), and optical storage media (e.g., CDs, DVDs, or Blu-ray discs). Program code for implementing the methods of this invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can be executed entirely on the machine, partially on the machine, or as a standalone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0107] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0108] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for testing internal parasitic parameters of a chip, characterized in that, The application is to a chip, which includes: a timer, a PWM signal output pin, a GPIO pin, and a first equivalent parasitic capacitance. The PWM signal output pin is electrically connected to the GPIO pin via an adjustable resistor, and the GPIO pin is connected to the first equivalent parasitic capacitance. The method for testing the internal parasitic parameters of the chip includes: Obtain the high-level threshold voltage of the GPIO pin; Configure the GPIO pin to timer trigger mode; Set the PWM signal output pin to high level and clear the timer counter to zero, then start the timer counter to start counting. The PWM signal output pin charges the GPIO pin through the adjustable resistor, causing the voltage value of the first equivalent parasitic capacitance to rise to the high-level threshold voltage, and the count value of the timer at this time is obtained. By repeatedly changing the resistance value of the adjustable resistor, and returning to the steps of setting the PWM signal output pin to a high level, clearing the timer counter, and then starting the timer counter to start counting, multiple count values ​​of the timer are obtained. The capacitance value of the first equivalent parasitic capacitance is obtained based on the multiple count values, the output voltage of the PWM signal output pin, and the high-level threshold voltage.

2. The method for testing internal parasitic parameters of a chip according to claim 1, characterized in that, The step of obtaining the high-level threshold voltage of the GPIO pin includes: Set the GPIO pin to normal input mode; A gradually increasing voltage is applied to the GPIO pin; When the input value of the GPIO pin is high, the voltage value is recorded, and the voltage value is the high-level threshold voltage.

3. The method for testing internal parasitic parameters of a chip according to claim 1, characterized in that, The step of obtaining the capacitance value of the first equivalent parasitic capacitance based on multiple count values, the output voltage of the PWM signal output pin, and the high-level threshold voltage includes: Based on the multiple count values ​​and the clock value of the timer, multiple recognition times for the GPIO pin to recognize a high level are calculated; Substituting the multiple recognition times, the resistance values ​​of the multiple adjustable resistors, the output voltage of the PWM signal output pin, and the high-level threshold voltage into the capacitor charging formula, we obtain the first set of charging equations. Solve the first set of charging equations to obtain the capacitance value of the first equivalent parasitic capacitance.

4. The method for testing internal parasitic parameters of a chip according to claim 1, characterized in that, When the GPIO pin is an ADC pin with ADC function, the chip further includes: an equivalent parasitic resistance and a second equivalent parasitic capacitance. The PWM signal output pin is electrically connected to the ADC pin through an adjustable resistor. The ADC pin is connected to the first equivalent parasitic capacitance. The ADC pin is also connected to one end of the equivalent parasitic resistance, and the other end of the equivalent parasitic resistance is connected to the second equivalent parasitic capacitance. The method for testing the internal parasitic parameters of the chip further includes: Configure the ADC pin to analog input mode; Set the sampling time setting value of the ADC pin; After setting the PWM signal output pin to a high level and clearing the timer counter to zero, the timer counter starts counting, and the ADC pin is triggered to sample. When the timer count reaches the sampling time set value, the sampling voltage of the ADC pin at this time is obtained; By repeatedly changing the resistance value of the adjustable resistor and returning to the step of configuring the ADC pin in analog input mode, multiple sampling voltages are obtained; The capacitance value of the second equivalent parasitic capacitor and the resistance value of the equivalent parasitic resistor are obtained based on the multiple sampling voltages, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitor.

5. The method for testing internal parasitic parameters of a chip according to claim 4, characterized in that, The step of obtaining the capacitance value of the second equivalent parasitic capacitance and the resistance value of the equivalent parasitic resistance based on the plurality of sampled voltages, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitance includes: Substituting the multiple sampling voltages, the resistance values ​​of the multiple adjustable resistors, the output voltage of the PWM signal output pin, the sampling time setting value of the ADC pin, and the capacitance value of the first equivalent parasitic capacitance into the capacitor charging formula, we obtain the second charging equation set. Solve the second set of charging equations to obtain the capacitance value of the second equivalent parasitic capacitance and the resistance value of the equivalent parasitic resistance.

6. The method for testing internal parasitic parameters of a chip according to claim 4, characterized in that, The chip also includes a sampling switch disposed between the ADC pin and the equivalent parasitic resistance. The method for testing the internal parasitic parameters of the chip further includes: When the sampling switch is off, the GPIO pin does not have ADC function; When the sampling switch is closed, the GPIO pin has ADC functionality.

7. The method for testing internal parasitic parameters of a chip according to claim 3, characterized in that, The capacitor charging formula is as follows: ； in, It is the voltage across the capacitor at time t. R is the output voltage of the PWM signal output pin, R is the resistance value of the adjustable resistor, and C is the capacitance value of the first equivalent parasitic capacitance.

8. The method for testing internal parasitic parameters of a chip according to claim 5, characterized in that, The second set of charging equations is: ； Wherein, Vs is the voltage value of the sampling voltage, Rx is the resistance value of the adjustable resistor, Vout is the output voltage value of the PWM signal output pin, C1 is the capacitance value of the first equivalent parasitic capacitance, C2 is the capacitance value of the second equivalent parasitic capacitance, Ts is the sampling time setting value of the ADC pin, and R1 is the resistance value of the equivalent parasitic resistor.

9. A testing device for internal parasitic parameters of a chip, characterized in that, The chip includes: One or more processors; Memory; One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, wherein when the programs are executed by the processors, they implement the steps of the method for testing internal parasitic parameters of a chip as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for testing internal parasitic parameters of a chip as described in any one of claims 1-8.

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