Method for debugging assembly and C code in chip verification environment and related device
By integrating components automatically parsing and matching C functions and assembly instructions in the SOC verification environment, the problem of low manual verification efficiency in the prior art is solved, and the automation and efficiency of SOC chip verification is improved.
Patent Information
- Application Number
- CN202411844704.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-04-11
AI Technical Summary
In the verification of SOC chips, the efficiency of the assembly code and C code functions is low due to manual analysis and verification, resulting in low verification efficiency.
Integrate components in the SOC verification environment, parse the compiled assembly result text through the sverilog language, automatically match the currently executed C functions and assembly instructions, and save the results as visual signals to display them on the EDA tool interface.
It realizes automated verification and positioning assembly code and C code functions, improves SOC chip verification efficiency, and reduces the complexity and workload of manual analysis.
Smart Images
Figure CN119806927A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip verification technology, and in particular to a method and related devices for debugging assembly and C code in a chip verification environment. Background Art
[0002] In the SOC (System on Chip) chip verification, it is necessary to use EDA (Electronic Design Automation) tools to simulate the RTL (Register Transfer Level) code of the entire chip in the SOC environment. After the simulation, a waveform file is generated so that when problems are encountered, the waveform file can be viewed for problem analysis and location. The commonly used EDA simulation tools in the industry for making chips are vcs (Virtual Cyber Security) and verdi. The results of the RTL code simulation and the signal change process in the code are saved in the waveform file. By opening these waveform files through verdi, you can intuitively view the changes in the internal signals of the chip, so as to analyze and determine whether the working status of the chip is normal.
[0003] The SOC chip is integrated with a CPU, which executes programs composed of binary codes compiled in C language and assembly language. These programs control the operation of the CPU and various peripherals inside the chip. During the chip simulation process, these binary files will be stored in the CPU's storage space and read out in the form of binary data when the CPU executes the program. Through the waveform file generated by Verdi, you can view the signal changes of the CPU and other peripherals when the binary code is executed.
[0004] However, the existing technology usually relies on manual analysis, verification, and positioning of assembly code and C code functions, which has the defect of low SOC chip verification efficiency. Summary of the invention
[0005] The purpose of this application is to provide a method and related device for debugging assembly and C code in a chip verification environment, which can automatically check and locate assembly code and C code functions, and improve the efficiency of SOC chip verification.
[0006] To achieve the above objectives, this application provides the following solutions:
[0007] In a first aspect, the present application provides a method for debugging assembly and C code in a chip verification environment, comprising:
[0008] Obtaining the current PC pointer value during the SOC chip simulation process, wherein the current PC pointer value is the memory address of the instruction currently executed by the CPU in the SOC chip, and the currently executed instruction refers to the instruction in the machine file currently executed by the CPU;
[0009] According to the current PC pointer value, the corresponding C function is matched in the function storage variable set, and the corresponding assembly instruction is matched in the instruction storage variable set, wherein the function storage variable set includes several C functions in the assembly result file, each of the C function includes a function name and a function storage address, the instruction storage variable set includes several assembly instructions in the assembly result file, each of the assembly instruction includes an instruction storage address and instruction content, the function storage variable set and the instruction storage variable set are variable sets obtained by processing the assembly result file according to the component, the component is integrated into the SOC verification environment, the component is used to read the assembly result text, identify all the C functions and the assembly instructions in the assembly result text, and store all the identified C functions and the assembly instructions in the function storage variable set and the instruction storage variable set, and the assembly result file corresponds to the machine file.
[0010] In a second aspect, the present application provides a device for debugging assembly and C code in a chip verification environment, comprising:
[0011] A pointer value acquisition module is used to obtain the current PC pointer value during the SOC chip simulation process, wherein the current PC pointer value is the memory address of the instruction currently executed by the CPU in the SOC chip, and the currently executed instruction refers to the instruction in the machine file currently executed by the CPU;
[0012] A matching module is used to match the corresponding C function in the function storage variable set and the corresponding assembly instruction in the instruction storage variable set according to the current PC pointer value, wherein the function storage variable set includes several C functions in the assembly result file, each of the C function includes a function name and a function storage address, the instruction storage variable set includes several assembly instructions in the assembly result file, each of the assembly instruction includes an instruction storage address and instruction content, the function storage variable set and the instruction storage variable set are variable sets obtained by processing the assembly result file according to the component, the component is integrated into the SOC verification environment, the component is used to read the assembly result text, identify all the C functions and the assembly instructions in the assembly result text, and store all the identified C functions and the assembly instructions in the function storage variable set and the instruction storage variable set, and the assembly result file corresponds to the machine file.
[0013] In a third aspect, the present application provides a computer device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for debugging assembly and C code in a chip verification environment as described in the first aspect above.
[0014] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method for debugging assembly and C code in a chip verification environment described in the first aspect above.
[0015] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the method for debugging assembly and C code in a chip verification environment described in the first aspect above.
[0016] According to the specific embodiments provided in this application, this application has the following technical effects:
[0017] The present application provides a method and related device for debugging assembly and C code in a chip verification environment, the method comprising: obtaining the current PC pointer value during the SOC chip simulation process; matching the corresponding C function in the function storage variable set and the corresponding assembly instruction in the instruction storage variable set according to the current PC pointer value. By integrating components in the SOC verification environment, the component can read the compiled assembly result text, parse out the C functions and assembly instructions contained therein, and save them in a specific format. When simulating the CPU execution code, the component automatically determines the currently executed C function and assembly instruction based on the PC pointer inside the chip RTL and the parsed results, thereby realizing automatic verification and positioning of assembly code and C code functions, and improving the SOC chip verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0019] Figure 1 This is a flow chart of a method for debugging assembly and C code in a chip verification environment in Example 1 of the present application;
[0020] Figure 2 A schematic diagram of the overall concept of a method for debugging assembly and C code in a chip verification environment provided in Example 1 of the present application;
[0021] Figure 3A schematic diagram of the structure of a computer device provided in Example 3 of the present application. DETAILED DESCRIPTION
[0022] After research, it was found that in the existing technology, when the simulation does not meet expectations during the simulation of RTL code, it is necessary to find the problem based on the waveform on verdi. In the verdi software, you can see the process of these binary values being taken away, but you cannot see the corresponding original assembly code text, nor can you tell which specific function in the C language source code the currently executed instruction corresponds to. This makes the location and solution of the problem more complicated and difficult.
[0023] In addition, currently in the SOC chip verification process, the conventional methods for debugging assembly and C code include:
[0024] 1. Identify the current program counter (PC) pointer in the verdi waveform;
[0025] 2. Open the assembly text file generated by compiling C language and assembly language, and manually locate the line of the specific function being executed in the file based on the value of the current PC pointer;
[0026] 3. After analyzing one instruction, return to the Verdi waveform again, find the next instruction according to the PC pointer for analysis, and repeat this process.
[0027] However, in the SOC simulation stage, a test case may generate thousands to tens of thousands of assembly instructions. This method of relying on manual verification and code location is inefficient and particularly cumbersome when analyzing problems.
[0028] In view of the above problems, this embodiment proposes a new automated method for debugging assembly and C code. By using sverilog language to make a set of components in the SOC verification environment, the component can read the compiled assembly result text, parse out the C function name and assembly instruction contained therein, and save it in a specific format. When simulating the CPU execution code, the component automatically judges the currently executed C function and assembly instruction based on the PC pointer inside the chip RTL, combined with the parsed results, and saves the result to a specific string variable. The string variable is a string variable of sverilog type, which can be displayed on the interface by verdi like other RTL internal signals. This method uses scripts to complete some analysis work that can only be completed manually, and then displays it on the interface of the EDA tool in a visual way like other chip internal signals, which can make it easier to locate and analyze problems and improve work efficiency.
[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0031] Example 1
[0032] like Figure 1 As shown, the method for debugging assembly and C code in a chip verification environment provided by an embodiment of the present application includes:
[0033] S1, obtaining the current PC pointer value in the SOC chip simulation process, wherein the current PC pointer value is the memory address of the instruction currently executed by the CPU in the SOC chip, and the currently executed instruction refers to the instruction in the machine file currently executed by the CPU.
[0034] S2, according to the current PC pointer value, matching the corresponding C function in the function storage variable set, matching the corresponding assembly instruction in the instruction storage variable set, wherein the function storage variable set includes several C functions in the assembly result file, each of the C function includes a function name and a function storage address, the instruction storage variable set includes several assembly instructions in the assembly result file, each of the assembly instruction includes an instruction storage address and instruction content, the function storage variable set and the instruction storage variable set are variable sets obtained by processing the assembly result file according to the component, the component is integrated into the SOC verification environment, the component is used to read the assembly result text, identify all the C functions and the assembly instructions in the assembly result text, and store all the identified C functions and the assembly instructions in the function storage variable set and the instruction storage variable set, and the assembly result file corresponds to the machine file.
[0035] By adopting the above steps S1-S2, by integrating components in the SOC verification environment, the component can read the compiled assembly result text, parse out the C functions and assembly instructions contained therein, and save them in a specific format. When simulating the CPU execution code, the component automatically determines the currently executing C function and assembly instruction based on the PC pointer inside the chip RTL and the parsed results, thereby realizing automatic verification and positioning of assembly code and C code functions, and improving the SOC chip verification efficiency.
[0036] The following combination Figure 2 , the specific execution process of the method for debugging assembly and C code in the chip verification environment provided by this embodiment is explained.
[0037] 1. Integrate components into the SOC verification environment.
[0038] This component is a class code written in System Verilog. When building a SOC verification environment, you need to put the component code in the header file format and include it in the environment. In addition to integrating this component, you also need to write some code that calls this component and matches C functions and assembly instructions in the module of the verification environment.
[0039] 2. SOC simulation starts.
[0040] In the SOC verification environment, before the vcs simulation starts, the gcc compiler will compile the C code first, generating at least one assembly result file and a hexadecimal file (i.e., machine file). The hexadecimal file will be loaded into the CPU storage at the beginning of the simulation. At the beginning of the simulation, the class of the component is instantiated inside the verification environment module.
[0041] 3. The component automatically reads the compiled assembly result text.
[0042] For the instantiated component, calling method 1 inside the component can read the assembly result text, and calling method 2 inside the component once can analyze the assembly instructions and C functions in the assembly result text.
[0043] 4. The component analyzes all assembly instructions and C functions in the assembly result text.
[0044] The assembly result text has a fixed format, and the component code only needs to parse each line of text according to the fixed template. The fixed template includes function templates and assembly instruction templates. The function templates and assembly instruction templates are as follows.
[0045] Function template: "address <label>":" is a fixed format for the start position of a C function, address is a 32-bit hexadecimal value representing the start storage space of the function, label is the corresponding C function name, and the script can find all C functions and the start address of the function by identifying this template. The end address of the function can be determined by the start address of the next C function.
[0046] Assembly instruction template: "address:hex text" is a fixed format for a line of assembly instructions. Address is the hexadecimal value of a 32-bit address, representing the storage space where the assembly instruction is located. Hex is the hexadecimal value corresponding to the assembly instruction, and text is the corresponding assembly text (i.e., assembly content).
[0047] After reading the assembly result text, the component will parse each line from top to bottom, find out all the function names and the content of each line of assembly instructions, and store them in the function storage variable set and instruction storage variable set specified in the component according to a specific format. The function storage variable is a structure array with the format of {function name, start address, end address}. The instruction storage variable is a structure array with the format of {address, instruction content}. The start address and end address are the function storage address.
[0048] This step is to read the contents of the assembly result text in real time, namely the C functions and assembly instructions in the text, and store these two parts of the contents in the above two variables for use in the subsequent matching process.
[0049] 5. Match C functions and assembly instructions.
[0050] The matching process is implemented in the module of the SOC verification environment by using the CPU's PC pointer to compare with the function storage variables and instruction storage variables analyzed by the component in step 4 above.
[0051] The specific process is as follows: In the SOC verification environment, the RTL code of the CPU itself will be integrated for simulation. When the CPU is simulated, the PC pointer will first go to the storage space to obtain the instruction to be executed.
[0052] The process of matching C functions and assembly instructions is to use the PC pointer value to compare and judge the C functions and assembly instructions stored in the component in step 4 one by one.
[0053] First, search the component's function storage variable set. If the PC pointer value is between the start address and the end address of the function funcA, it means that the funcA function is matched, indicating that the current CPU is executing the funcA function. Save the 'funcA' string to the func_string variable.
[0054] Then search the instruction storage variables of the component. If the PC pointer value is equal to the address of a certain assembly instruction, save the content of the assembly instruction, the "text" string, into the asm_string variable.
[0055] This step is to obtain these two variables (func_string variable, asm_string variable) by comparing the real-time PC pointer value with the above function storage variable and instruction storage variable.
[0056] String variables include func_string variables and asm_string variables.
[0057] The code of the above matching process is the analysis result of the component in calling step 4. It is written in Verilog language inside the top-level module of the verification environment. The PC pointer refers to a variable inside the RTL of the CPU. The func_string variable and asm_string variable are defined in the module of the verification environment.
[0058] 6. Repeat step 5 until the simulation ends.
[0059] During the entire simulation phase, the PC pointer will keep changing until the simulation ends. Each time the PC pointer changes, step 5 needs to be executed and the execution result needs to be updated in the func_string and asm_string variables.
[0060] 7. Pull out specific signals in verdi.
[0061] At the end of the simulation, use verdi to open the simulation waveform, that is, use verdi to call the two variables (func_string variable and asm_string variable) in the above step 5 for display.
[0062] Specifically: You only need to pull out the func_string and asm_string variables in the SOC verification environment like the wire / reg type variables in other modules to get the running results of the C function and assembly instructions. By looking at func_string / asm_string, you can know the CPU C code execution process.
[0063] This embodiment uses an automated script analysis method to replace manual analysis of assembly code and C code functions, avoiding the defect of low SOC chip verification efficiency caused by relying on manual analysis, verification, and positioning of assembly code and C code functions. It can automatically verify and locate assembly code and C code functions, thereby improving SOC chip verification efficiency.
[0064] This embodiment is an automated script written in sverilog and integrated into the SOC verification environment code. It can be saved into a waveform file by the vcs tool. After the simulation is completed, the assembly instructions and C functions will be pulled out and displayed by verdi like other internal signals of the chip, which can make it easier to locate and analyze problems and improve work efficiency.
[0065] Therefore, this embodiment can greatly reduce the difficulty and workload of debugging C language and assembly language in SOC, which is very helpful for improving the efficiency of SOC chip verification. This embodiment has been applied in the SOC verification environment, and after multiple project verifications, the method has significant effects.
[0066] Example 2
[0067] This embodiment provides a device for debugging assembly and C code in a chip verification environment, including:
[0068] A pointer value acquisition module is used to obtain the current PC pointer value during the SOC chip simulation process, wherein the current PC pointer value is the memory address of the instruction currently executed by the CPU in the SOC chip, and the currently executed instruction refers to the instruction in the machine file currently executed by the CPU;
[0069] A matching module is used to match the corresponding C function in the function storage variable set and the corresponding assembly instruction in the instruction storage variable set according to the current PC pointer value, wherein the function storage variable set includes several C functions in the assembly result file, each of the C function includes a function name and a function storage address, the instruction storage variable set includes several assembly instructions in the assembly result file, each of the assembly instruction includes an instruction storage address and instruction content, the function storage variable set and the instruction storage variable set are variable sets obtained by processing the assembly result file according to the component, the component is integrated into the SOC verification environment, the component is used to read the assembly result text, identify all the C functions and the assembly instructions in the assembly result text, and store all the identified C functions and the assembly instructions in the function storage variable set and the instruction storage variable set, and the assembly result file corresponds to the machine file.
[0070] The solution to the problem provided by the device is similar to the solution described in the method of the above-mentioned embodiment 1. Therefore, the device for debugging assembly and C code in a chip verification environment provided in this embodiment can refer to the limitation of the method for debugging assembly and C code in a chip verification environment in embodiment 1, which will not be repeated here.
[0071] Example 3
[0072] This embodiment provides a computer device, which may be a server or a terminal. Its internal structure diagram may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data in the method for debugging assembly and C code in the chip verification environment provided in Example 1. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the method for debugging assembly and C code in the chip verification environment provided in Example 1 is implemented.
[0073] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components. In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.
[0074] Example 4
[0075] This embodiment provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the method for debugging assembly and C code in a chip verification environment provided in Embodiment 1 is implemented.
[0076] Example 5
[0077] This embodiment provides a computer program product, including a computer program. When the computer program is executed by a processor, the method for debugging assembly and C code in a chip verification environment provided in Embodiment 1 is implemented.
[0078] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.
[0079] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).
[0080] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.
[0081] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0082] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.< / label>
Claims
1. A method for debugging assembly and C code in a chip verification environment, characterized in that: The method for debugging assembly and C code in the chip verification environment includes: Obtaining the current PC pointer value during the SOC chip simulation process, wherein the current PC pointer value is the memory address of the instruction currently executed by the CPU in the SOC chip, and the currently executed instruction refers to the instruction in the machine file currently executed by the CPU; According to the current PC pointer value, the corresponding C function is matched in the function storage variable set, and the corresponding assembly instruction is matched in the instruction storage variable set, wherein the function storage variable set includes several C functions in the assembly result file, each of the C function includes a function name and a function storage address, the instruction storage variable set includes several assembly instructions in the assembly result file, each of the assembly instruction includes an instruction storage address and instruction content, the function storage variable set and the instruction storage variable set are variable sets obtained by processing the assembly result file according to the component, the component is integrated into the SOC verification environment, the component is used to read the assembly result text, identify all the C functions and the assembly instructions in the assembly result text, and store all the identified C functions and the assembly instructions in the function storage variable set and the instruction storage variable set, and the assembly result file corresponds to the machine file.
2. The method for debugging assembly and C code in a chip verification environment according to claim 1, characterized in that: After executing the step of "matching the corresponding C function in the function storage variable set and matching the corresponding assembly instruction in the instruction storage variable set according to the current PC pointer value", the method for debugging assembly and C code in the chip verification environment further includes: Save the C function and the assembly instruction that all PC pointer values match to into a string variable; The string variable is read through an EDA simulation tool and displayed in a waveform file, wherein the waveform file is used to record signal changes during the SOC chip simulation process.
3. The method for debugging assembly and C code in a chip verification environment according to claim 1, characterized in that: The specific process of identifying all the C functions and the assembly instructions in the assembly result text includes: The C function and the assembly instruction in the assembly result text are identified according to the correspondence between the function template and the assembly instruction template, wherein the function template consists of a function name and a start address, the end address of the C function is the start address of the next C function adjacent to it, the assembly instruction template consists of an instruction storage address, an instruction value and an instruction content, and the instruction refers to the hexadecimal value corresponding to the assembly instruction.
4. The method for debugging assembly and C code in a chip verification environment according to claim 2, characterized in that: The C function and the assembly instruction that all PC pointer values match are saved into a string variable, specifically including: The function name in the matched C function and the instruction content in the assembly instruction are saved in a string variable.
5. The method for debugging assembly and C code in a chip verification environment according to claim 1, characterized in that: The component is a class code written in SystemVerilog language.
6. The method for debugging assembly and C code in a chip verification environment according to claim 2, characterized in that: The string variable is a string variable of sverilog type.
7. A device for debugging assembly and C code in a chip verification environment, characterized in that: The device for debugging assembly and C code in the chip verification environment includes: A pointer value acquisition module is used to obtain the current PC pointer value during the SOC chip simulation process, wherein the current PC pointer value is the memory address of the instruction currently executed by the CPU in the SOC chip, and the currently executed instruction refers to the instruction in the machine file currently executed by the CPU; A matching module is used to match the corresponding C function in the function storage variable set and the corresponding assembly instruction in the instruction storage variable set according to the current PC pointer value, wherein the function storage variable set includes several C functions in the assembly result file, each of the C function includes a function name and a function storage address, the instruction storage variable set includes several assembly instructions in the assembly result file, each of the assembly instruction includes an instruction storage address and instruction content, the function storage variable set and the instruction storage variable set are variable sets obtained by processing the assembly result file according to the component, the component is integrated into the SOC verification environment, the component is used to read the assembly result text, identify all the C functions and the assembly instructions in the assembly result text, and store all the identified C functions and the assembly instructions in the function storage variable set and the instruction storage variable set, and the assembly result file corresponds to the machine file.
8. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method for debugging assembly and C code in a chip verification environment as described in any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for debugging assembly and C code in a chip verification environment described in any one of claims 1 to 6 is implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for debugging assembly and C code in a chip verification environment described in any one of claims 1 to 6 is implemented.