A chip pin cross-domain configuration method and chip

Abstract

The present invention provides a chip pin cross-domain configuration method and chip, the method is applied to a chip with multiple hardware domains, the multiple hardware domains include a first domain and at least one second domain, the chip has multiple chip pins, each of the chip pins has a different type of registers, the method includes: the first domain determines the function to be detected and the execution domain of the function to be detected according to the target chip pin to be detected, the execution domain is any second domain of the function to be detected that uses the target chip pin; the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can apply the target chip pin to execute the function to be detected; the execution domain configures the specified type of register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of system on chip, and in particular to a chip pin cross-domain configuration method and a chip. Background Art

[0002] When chip manufacturers test newly manufactured chips, they include multiple stages of testing, such as using large-scale ATE test tools to test the functions of each pin of each chip.

[0003] After passing the test, the chip is mounted on a specific motherboard with various peripherals for further testing and debugging. Typically, during this stage, the chip is tested with an operating system, such as Linux or Android. Therefore, testers must configure the chip during the compilation phase, assigning specific pins to specific functions. They then create test firmware, burn it to the machine, and conduct testing.

[0004] However, for multi-core heterogeneous systems and systems with multiple hardware domains, the functions of the pins corresponding to each domain in the chip need to be configured, then burned accordingly, and then tested. The overall process is cumbersome and complicated. Summary of the Invention

[0005] To solve the above technical problems, an embodiment of the present invention provides a chip pin cross-domain configuration method, which is applied to a chip having multiple hardware domains, wherein the multiple hardware domains include a first domain and at least one second domain, and the chip has multiple chip pins, each of which has a different type of register. The method includes:

[0006] The first domain determines a function to be detected and an execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0007] The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0008] The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0009] In one embodiment, the different types of registers include permission configuration registers and function control registers. The permission configuration registers are used to configure the permissions for different second domains to use the chip pins, and the function control registers are used to configure the functions of the chip pins.

[0010] In one embodiment, the first domain configures different types of registers of the target chip pins based on the execution domain, including:

[0011] The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

[0012] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected, including:

[0013] The first domain determines the functional configuration information of the target chip pin according to the function to be detected;

[0014] The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

[0015] In one embodiment, the method further comprises:

[0016] The first domain determines the chip pins involved in the execution of the function to be detected;

[0017] The chip pins involved in the first domain are all determined as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

[0018] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including:

[0019] The first domain configures the permission configuration register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins;

[0020] The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected;

[0021] The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that the plurality of target chip pins are configured to cooperate in executing the function to be detected.

[0022] In one embodiment, the method further comprises:

[0023] The first domain records multiple target chip pins that participate in and cooperate in executing the function to be detected, so as to determine that the function detection of each of the target chip pins is completed;

[0024] When the detection of one function of the target chip pin is completed, the first domain switches another function of the target chip pin to the function to be detected, and detects the new function to be detected;

[0025] When the detection of various functions of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs various function detection on the new target chip pin.

[0026] In one embodiment, the execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including:

[0027] The execution domain determines a register of a specified type to be configured according to the function to be detected;

[0028] The execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs an execution result;

[0029] The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

[0030] In one embodiment, the method further comprises:

[0031] After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain to the execution domain by configuring different types of registers of the target chip pins.

[0032] Another embodiment of the present invention also provides a chip having multiple hardware domains, the multiple hardware domains including a first domain and at least one second domain, the chip having multiple chip pins, each of the chip pins having a different type of register, wherein:

[0033] The first domain determines a function to be detected and an execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0034] The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0035] The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0036] Based on the disclosure of the above embodiments, it can be known that the beneficial effects of the embodiments of the present invention include enabling multi-core heterogeneous, multi-hardware domain chips to be configured without human participation. Only relevant instructions need to be input, and the chip can automatically determine the pins that need to be functionally configured in response to the instructions, and perform relevant functional configuration on the pins, or configure the pins to be used in different hardware domains. The overall configuration process is simple and fast, providing a more efficient configuration method for chip testing and subsequent use, and laying the foundation for test efficiency and operation efficiency.

[0037] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0038] The technical solution of the present application is further described in detail below through the accompanying drawings and examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 The figure is a flow chart of a chip pin cross-domain configuration method in an embodiment of the present invention.

[0041] Figure 2 Schematic diagram of the application flow of the chip pin cross-domain configuration method in an embodiment of the present invention.

[0042] Figure 3 2 is a schematic diagram of the application flow of a chip pin cross-domain configuration method in another embodiment of the present invention.

[0043] Figure 4 Schematic diagram of the chip structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but are not intended to limit the present invention.

[0045] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope of the present disclosure will occur to those skilled in the art.

[0046] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0047] These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0048] It should also be understood that although the invention has been described with reference to certain specific examples, those skilled in the art will be able to realize many other equivalent forms of the invention that have the characteristics recited in the claims and are therefore within the scope of protection defined thereby.

[0049] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0050] Specific embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant detail. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but rather serve merely as a basis and representative basis for the claims to teach those skilled in the art to variously employ the present disclosure with substantially any suitable detailed structure.

[0051] This description may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," each of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] like Figure 1As shown, an embodiment of the present invention provides a chip pin cross-domain configuration method, which is applied to a chip with multiple hardware domains. For example, the method of this embodiment is applicable to, but not limited to, any chip with multiple hardware domains, such as a digital signal processing chip, a microcontroller chip, a field programmable gate array (FPGA) chip, etc. wherein the multiple hardware domains include a first domain and at least one second domain. For example, the chip includes multiple different processor cores, and the processor cores in the chip and their corresponding hardware resources form corresponding domains, the domains including a first domain and multiple second domains, each processor core running an operating system, such as FreeRTOS, Android, Linux, OS, etc. Inter-core communication can be performed between the first domain and the second domain. Specifically, the chip of the embodiment of the present application can be a SOC, or a chip including an SOC. The chip includes multiple processor cores, and the processor cores and their corresponding hardware resources can form corresponding domains, wherein the formed domains can include one or more processor cores, for example, one domain can have one or more processor cores. The domains include a first domain and multiple second domains, the first domain can be a security domain, and the second domain can be an application domain or other functional domain. There is a communication link between the first domain and the second domain, which enables inter-core communication, so that the first domain and the second domain can interact with each other and share functions in a secure and high-speed transmission environment.

[0054] Furthermore, the chip has a plurality of chip pins, each of the chip pins has a different type of register, and the method includes:

[0055] S1: The first domain determines a function to be detected and an execution domain of the function to be detected according to a pin of a target chip to be detected, wherein the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0056] Exemplarily, a pin function mapping table is stored in a non-volatile memory inside the chip in advance, and the first domain needs to determine the function to be detected of the target chip pin to be detected and the execution domain of the function to be detected when responding to the input instruction. For example, the first domain can first read the pin function mapping table stored in the non-volatile memory inside the chip, and then determine the configuration parameters and application requirements of the current system, such as the detection requirements, which can be obtained through instructions input by the user, or determined according to the application started by the current system, such as a test program, or other non-test programs, such as an application started by the chip during subsequent normal use. After determining the system configuration parameters and application requirements, the first domain can combine the determined information with the mapping table to perform a comprehensive analysis, and then determine the function to be detected corresponding to the target chip pin to be detected. To determine the execution domain, it can be determined based on the domain information indicated in the input instruction, or based on the preset test sequence, or based on the function to be tested of the pin, as well as the communication links and function sharing rules between hardware domains to determine the second domain that executes the function to be tested, that is, determine the second domain that can currently execute the pin function test, and the second domain can be a domain that is currently idle and supports function testing.

[0057] S2: The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0058] In this embodiment, the first domain can configure the first type of registers of the target chip pins based on the type of function to be detected, such as data transmission or interrupt triggering, including but not limited to configuring the pin's operating mode, transmission rate, and transmitted data type. Furthermore, other types of registers can be initialized and configured based on the electrical characteristics of the execution domain and the communication protocol supported during data transmission to ensure correct data storage and transmission. Of course, the specific registers involved and the specific configurations performed are not fixed and can be flexibly changed based on actual circumstances.

[0059] S3: The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0060] The execution domain in this embodiment instructs and controls the target chip pin to execute the function to be tested by configuring within a specified type of register. For example, the execution domain writes specific test data to a specified type of register of the target chip pin, such as a status register, and reads the value of this register to determine whether the target chip pin has executed the function to be tested as expected. In other words, when the target chip pin executes a specific function, it needs to configure data in the various registers corresponding to the function, thereby enabling the target chip pin to execute the corresponding function.

[0061] In this embodiment, the first domain is a security domain, which has the function configuration of chip pins, the right to configure usage permissions, and the right to access any second domain. The second domain is the various functional domains in the chip. The number of pins of the chip is not fixed, and it can have any number of chip pins. Different chip pins can support one or more different functions. The addition or modification of pin functions can be implemented through the first domain, such as updating the relevant function mapping table and configuration parameters. This method can make the method of this embodiment have good adaptability and a wide range of applications.

[0062] Furthermore, the different types of registers described in this embodiment include permission configuration registers and function control registers. The permission configuration registers are used to configure the permissions granted to different second domains to use the chip pins, such as configuring the second domain A to have the permission to use the chip pins. The function control registers are used to configure the functions that the chip pins must have, and the functions may be, but are not limited to, receiving specified data, transmitting specified data, etc. The function control registers include, but are not limited to, control registers, which are used to set the working mode of the pin, such as input mode, output mode, bidirectional mode, etc. The different types of registers may also include, but are not limited to, status registers, which are used to feedback the current electrical state of the pin, such as high level state, low level state, open circuit state, etc.; and data registers, which are used to temporarily store data transmitted through the pin, etc.

[0063] When the execution domain detects whether the target chip pin can execute the function to be detected, the execution domain can write specific test data to a specified type of register, such as a status register, that is, configure the status register, and then read the value in the register that represents whether the target chip pin responds to the data write operation and executes the corresponding function to determine whether the target chip pin has executed the function to be detected as expected. If the read value is consistent with the preset standard value, it is determined that the pin can execute the function to be detected on the execution domain. On the contrary, if the read value does not match the preset standard value, it is determined that the pin cannot execute the function to be detected on the execution domain, and the chip is an abnormal chip.

[0064] Based on the method of this embodiment, the user does not need to perform many operations. He only needs to input corresponding instructions to control the first domain to implement operations such as function modification and function addition of chip pins, and switching of specific execution domains. Moreover, when the user inputs a specified test instruction, the first domain can control the target chip pins to perform tests of different functions and corresponding to different execution domains in sequence. The intermediate process does not require user participation, which significantly improves test efficiency, simplifies user operations, and provides convenience for the functional configuration of chip pins when the chip is used normally in the future.

[0065] In one embodiment, the first domain configures different types of registers of the target chip pins based on the execution domain, including:

[0066] S4: The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

[0067] For example, when the second domain A completes the function test of the target chip pin, the data in the permission configuration register of the target chip pin is updated and rewritten to cancel the permission of the second domain A and grant the second domain B the permission to use the target chip pin.

[0068] like Figure 2 As shown, the first domain is the security domain. After the system is powered on, the processor cores of each domain start up and run their respective operating systems. After the startup is completed, the first domain modifies the data in the permission configuration class register of the target chip pin pin1, and configures pin1 to be a resource of the secure domain. At the same time, it notifies the secure domain as the execution domain to perform the functional detection operation of pin1.

[0069] The execution domain can be determined based on preset configuration information, such as preset detection configuration information, or based on the instructions input by the user to indicate detection, or based on the function of the target chip pin to be detected, the configuration parameters of the processor core, etc., to ensure that the selected execution domain can transmit data to the target chip pin, has the ability to perform functional detection of the target chip pin, and can realize functional detection of the target chip pin.

[0070] When determining the target chip pin, the method includes:

[0071] S5: The first domain determines the chip pins involved in the execution of the function to be detected;

[0072] S6: The first domain determines all the chip pins involved as the target chip pins, and the plurality of target chip pins are used to cooperate in implementing the execution of the function to be detected.

[0073] Because each chip pin has multiple different functions and can be configured as a variety of different functions, the functions supported by different chip pins may not be exactly the same. For example, two chip pins may support different functions. When determining the target chip pin, the first domain first determines the functions supported by each chip pin and then determines the target chip pin based on the supported functions and the function to be tested.

[0074] Furthermore, the first domain configures different types of registers of the target chip pin based on the function to be detected, including:

[0075] S7: The first domain determines the functional configuration information of the pin of the target chip according to the function to be detected;

[0076] S8: The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to perform the function to be detected.

[0077] For example, if the first domain determines that the function to be detected is an input or output function, it can configure the function of the target chip pin accordingly, including specifically configuring it as an input or output function. The first domain can then configure the function control registers of the target chip pin, such as the function control register, based on this determined function configuration information to configure the target chip pin to have the input or output function.

[0078] Combine Figure 2 As shown, the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including:

[0079] S9: The first domain configures the permission configuration register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins;

[0080] S10: The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected;

[0081] S11: The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that multiple target chip pins are configured to cooperate in executing the function to be detected.

[0082] Exemplarily, when switching the execution domain, the first domain configures the permission configuration class register of the target chip pin according to the execution domain, and adds the information of the specified execution domain so that the execution domain has the right to use the target chip pin. Then, the first domain determines the function that the target chip pin needs to have based on the function to be detected that needs to be executed, and then determines the function configuration information of the target chip pin accordingly, and configures the function control register of the target chip pin based on the information. Since the chip pins involved are not unique when executing a certain function to be detected, usually multiple chip pins cooperate to perform the task to be detected, such as data input and output. Therefore, when the first domain determines the target chip pin, it determines multiple chip pins that can cooperate to perform the task to be detected. After that, each chip pin determined as the target chip pin is executed. The domain configuration and function configuration are performed, so that it is triggered to perform the corresponding function for the next test.

[0083] In order to avoid repeated testing of a certain function on some chip pins in the future, the first domain can record the target chip pins that have completed a certain function to be tested, so that when it is the turn of the chip pin to perform the test of the function to be tested in the future, it can be skipped directly to avoid repeated testing and waste of testing resources.

[0084] Specifically, the method further includes:

[0085] S12: The first domain records multiple target chip pins that participate in and cooperate in executing the function to be tested, so as to determine that the function test of each of the target chip pins is completed;

[0086] S13: When the detection of one function of the target chip pin is completed, the first domain switches another function of the target chip pin to the function to be detected, and detects the new function to be detected;

[0087] S14: When the detection of various functions of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs various function detection on the new target chip pin.

[0088] For example, when the user instructs the first domain to perform a functional test on all chip pins, the first domain records multiple target chip pins that participate in cooperating to execute the first function to be tested. After completing the first functional test of the target chip pins, the first domain can automatically configure the current target chip pins for the next function to be tested. The specific configuration method is as above, including deleting the existing function configuration information in the register and writing new function configuration information. The switching method for the execution domain is similar, which also involves deleting the existing execution domain configuration information in the register and writing new execution domain configuration information. The switching of the above functions and execution domains are all automatically determined and executed by the first domain without user participation, and have strong automation performance.

[0089] For example, Figure 2 As shown, the first domain modifies the function of pin1 to a normal output port function, and at the same time configures its execution domain to the AP1 domain corresponding to the AP1 core. After the function test is completed, pin1 is modified to the uart function, and the execution domain remains unchanged. After the function test is completed, the first domain modifies the function of pin1 to the spi function and continues to test. After all functions of the pin1 are tested, the target chip pin can be switched to the next chip pin, and the function test can be continued in the same execution domain.

[0090] Furthermore, the execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including:

[0091] S15: The execution domain determines a register of a specified type to be configured according to the function to be detected;

[0092] S16: the execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs the execution result;

[0093] S17: The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

[0094] Continue to combine Figure 2As shown, in this embodiment, after completing the configuration of the chip pin's function and usage permissions, the first domain will send a notification to the execution domain to inform it to perform the relevant configuration of the function to be tested and execute the function to be tested. For example, the status register in pin1 is set to a high level, and then it is determined whether it is a high level when the oscilloscope tests pin1. If so, it indicates that pin1 functions normally when it is a normal output port, otherwise it is abnormal. Alternatively, a specified type register in pin1 is configured with a uart waveform, and then it is determined whether the uart waveform is received when the oscilloscope tests pin1. If so, it indicates that pin1 functions normally when executing the uart function, otherwise it is abnormal. Alternatively, a specified register in pin1 is configured with a spi waveform, such as running a spi test program to continuously configure the spi waveform in the register, and then using an oscilloscope to test whether pin1 has a spi waveform. If so, it indicates that pin1 can execute the spi function, otherwise it is abnormal, indicating that pin1 cannot execute the spi function.

[0095] Furthermore, when performing cross-domain detection, the method further includes:

[0096] S18: After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain as the execution domain by configuring different types of registers of the target chip pins.

[0097] like Figure 3 As shown, for example, pin1 is modified to be a resource of the secure domain, that is, the permissions are configured to the secure domain, making the secure domain an execution domain. After completing the configuration of the relevant permission registers, the first domain sends a notification to the secure domain to inform it that it is an execution domain. Then the first domain configures the function to be detected of pin1 and notifies the execution domain to start the function detection. When the execution domain is to be changed, such as changing the current secure domain to the AP1 domain, the first domain uses the information of the AP1 domain to update the configuration information in the permission class register in pin1 to switch the usage permission of pin1 to the AP1 domain, and then notifies the AP1 domain to inform it that it is an execution domain. Then the first domain can choose whether to configure and update the function to be detected of pin1 as needed, that is, whether to change the function to be detected. If so, the function control register of pin1 is configured to change the function to be detected, and the AP1 domain is notified to start the detection of the new function to be detected. If the function to be detected does not need to be changed, the AP1 domain can be directly notified to execute the current function to be detected.

[0098] Based on the contents of the above embodiments, it can be seen that the method provided in this embodiment can enable multi-core heterogeneous, multi-hardware domain chips to be configured without human participation. Only relevant instructions need to be input, and the chip can respond to the instruction and automatically determine the chip pins that need to be functionally configured, and perform relevant functional configuration on the pins, or configure the pins for use in different hardware domains. The overall configuration process is simple and fast, providing a more efficient configuration method for chip testing and subsequent use, and laying the foundation for testing efficiency and operation efficiency.

[0099] like Figure 4 As shown, another embodiment of the present invention also provides a chip having multiple hardware domains, the multiple hardware domains including a first domain and at least one second domain, the chip having multiple chip pins, each of the chip pins having a different type of register, wherein:

[0100] The first domain determines a function to be detected and an execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0101] The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0102] The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0103] In one embodiment, the different types of registers include permission configuration registers and function control registers. The permission configuration registers are used to configure the permissions for different second domains to use the chip pins, and the function control registers are used to configure the functions of the chip pins.

[0104] In one embodiment, the first domain configures different types of registers of the target chip pins based on the execution domain, including:

[0105] The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

[0106] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected, including:

[0107] The first domain determines the functional configuration information of the target chip pin according to the function to be detected;

[0108] The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

[0109] In one embodiment, the first domain is further used for:

[0110] The first domain determines the chip pins involved in the execution of the function to be detected;

[0111] The chip pins involved in the first domain are all determined as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

[0112] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including:

[0113] The first domain configures the permission configuration register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins;

[0114] The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected;

[0115] The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that the plurality of target chip pins are configured to cooperate in executing the function to be detected.

[0116] In one embodiment, the first domain is further used for:

[0117] The first domain records multiple target chip pins that participate in and cooperate in executing the function to be detected, so as to determine that the function detection of each of the target chip pins is completed;

[0118] When the detection of one function of the target chip pin is completed, the first domain switches another function of the target chip pin to the function to be detected, and detects the new function to be detected;

[0119] When the detection of various functions of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs various function detection on the new target chip pin.

[0120] In one embodiment, the execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including:

[0121] The execution domain determines a register of a specified type to be configured according to the function to be detected;

[0122] The execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs an execution result;

[0123] The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

[0124] In one embodiment, the first domain is further used for:

[0125] After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain to the execution domain by configuring different types of registers of the target chip pins.

[0126] Furthermore, an embodiment of the present invention further provides a storage medium storing a computer program that, when executed by a processor comprising the chip, implements the chip pin cross-domain configuration method described above. It should be understood that each solution in this embodiment has the corresponding technical effects of the above method embodiments and will not be further described here.

[0127] Furthermore, an embodiment of the present invention also provides a computer program product, which is tangibly stored on a computer-readable medium and includes computer-readable instructions, which, when executed, enable at least one processor including the chip to perform a chip pin cross-domain configuration method such as the one in the embodiment described above.

[0128] It should be noted that the computer storage medium of the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable media may, for example, be, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage medium, a magnetic storage medium, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. In the present invention, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program configured for use by or in conjunction with an instruction execution system, system, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, antenna, optical cable, RF, or any suitable combination thereof.

[0129] In addition, it will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0130] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1a process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or boxes.

[0131] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction system that is implemented in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0132] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0133] The above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention. The scope of protection of the present invention is defined by the claims. Those skilled in the art may make various modifications or equivalent substitutions to the present invention within the spirit and scope of protection of the present invention, and such modifications or equivalent substitutions shall also be deemed to fall within the scope of protection of the present invention.

Claims

1. A chip pin cross-domain configuration method, applied to a chip having multiple hardware domains, wherein the multiple hardware domains include a first domain and at least one second domain, the chip having multiple chip pins, each of which has a different type of register, the method comprising: The first domain determines a function to be detected and an execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip; The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected; The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

2. The chip pin cross-domain configuration method according to claim 1, characterized in that: The different types of registers include permission configuration registers and function control registers. The permission configuration registers are used to configure the permissions granted to different second domains to use the chip pins, and the function control registers are used to configure the functions of the chip pins.

3. The chip pin cross-domain configuration method according to claim 2, characterized in that: The first domain configures different types of registers of the target chip pins based on the execution domain, including: The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

4. The chip pin cross-domain configuration method according to claim 2, characterized in that: The first domain configures different types of registers of the target chip pin based on the function to be detected, including: The first domain determines the functional configuration information of the target chip pin according to the function to be detected; The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

5. The chip pin cross-domain configuration method according to claim 2, characterized in that: The method further comprises: The first domain determines the chip pins involved in the execution of the function to be detected; The chip pins involved in the first domain are all determined as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

6. The chip pin cross-domain configuration method according to claim 5, characterized in that: The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including: The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins; The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected; The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that the plurality of target chip pins are configured to cooperate in executing the function to be detected.

7. The chip pin cross-domain configuration method according to claim 6, characterized in that: The method further comprises: The first domain records multiple target chip pins that participate in and cooperate in executing the function to be detected, so as to determine that the function detection of each of the target chip pins is completed; When the detection of one function of the target chip pin is completed, the first domain switches another function of the target chip pin to the function to be detected, and detects the new function to be detected; When the detection of various functions of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs various function detection on the new target chip pin.

8. The chip pin cross-domain configuration method according to claim 1, characterized in that: The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including: The execution domain determines a register of a specified type to be configured according to the function to be detected; The execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs an execution result; The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

9. The chip pin cross-domain configuration method according to claim 1, characterized in that: The method further comprises: After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain to the execution domain by configuring different types of registers of the target chip pins.

10. A chip having multiple hardware domains, the multiple hardware domains including a first domain and at least one second domain, the chip having multiple chip pins, each of the chip pins having a different type of register, wherein: The first domain determines a function to be detected and an execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip; The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected; The execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

Images