Sub-pixel and display device

Abstract

The invention relates to a sub-pixel and a display device. The sub-pixel may include: a first transistor configured to generate a driving current; a first capacitor including a first electrode connected to the first electrode of the first transistor, and a second electrode; a second capacitor including a first electrode connected to the control electrode of the first transistor and a second electrode connected to the second electrode of the first capacitor; a second transistor configured to supply a data voltage to a second electrode of the first capacitor in response to a write gate signal; and a light emitting element configured to receive the driving current and emit light.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0134666, filed on October 10, 2023, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to sub-pixels and display devices including the sub-pixels. Background Art

[0004] Typically, a display device may include a display panel, a gate driver, a data driver, and a drive controller. The display panel may include a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels electrically connected to the gate lines and the data lines. The gate driver may provide a gate signal to the gate lines. The data driver may provide a data voltage to the data lines. The drive controller may control the gate driver and the data driver.

[0005] Recently, display devices that provide virtual reality (VR) or augmented reality (AR) have become increasingly prominent. Therefore, a display device with a small surface area and a high pixel per inch (ppi) is required.

[0006] In order to achieve a small surface area and a high ppi, a display device can be designed so that components are integrated in a minimized surface area. However, during the design process, the integration of some components in a small surface area is limited by the minimum width required to meet the design rules.

[0007] Therefore, there is an increasing demand to minimize the transistors forming the sub-pixels and to integrate the transistors in a minimum surface area. Summary of the invention

[0008] Various embodiments of the present disclosure are directed to a sub-pixel capable of minimizing voltage distribution due to a capacitor when writing a data voltage.

[0009] Various embodiments of the present disclosure relate to a display device including a sub-pixel.

[0010] An embodiment of the present disclosure may provide a sub-pixel, which includes: a first transistor configured to generate a driving current; a first capacitor including a first electrode connected to the first electrode of the first transistor, and a second electrode; a second capacitor including a first electrode connected to the control electrode of the first transistor and a second electrode connected to the second electrode of the first capacitor; a second transistor configured to provide a data voltage to the second electrode of the first capacitor in response to a write gate signal; and a light-emitting element configured to receive the driving current and emit light.

[0011] In an embodiment, the subpixel may further include: a third transistor configured to connect the first electrode of the first transistor to the second electrode of the first capacitor in response to a reference gate signal; and a fourth transistor configured to provide a reference voltage to the control electrode of the first transistor in response to the reference gate signal.

[0012] In an embodiment, the sub-pixel may further include: a fifth transistor configured to provide an initialization voltage to the first electrode of the light emitting element in response to the initialization gate signal.

[0013] In an embodiment, each of the reference gate signal and the initialization gate signal may have an enable level during the initialization period. The reference gate signal may have an enable level during the compensation period after the initialization period in a frame. Each of the initialization gate signal and the write gate signal may have an enable level during the address period after the compensation period in a frame. The initialization gate signal may have an enable level during the emission initialization period after the address period in a frame.

[0014] In an embodiment, the sub-pixel may further include: a sixth transistor configured to provide a first power voltage to the first transistor in response to the emission signal.

[0015] In an embodiment, each of the reference gate signal and the initialization gate signal may have an enable level during the initialization period. Each of the reference gate signal and the emission signal may have an enable level during the compensation period after the initialization period in a frame. Each of the initialization gate signal and the write gate signal may have an enable level during the addressing period after the compensation period in a frame. The initialization gate signal may have an enable level during the emission initialization period after the addressing period in a frame.

[0016] In an embodiment, the sub-pixel may further include: a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to an emission bias signal.

[0017] In an embodiment, the sub-pixel may further include: an eighth transistor configured to provide a reference voltage to the first electrode of the first transistor in response to the write gate signal.

[0018] In an embodiment, each of the reference gate signal and the initialization gate signal may have an enable level during the initialization period. Each of the reference gate signal and the emission signal may have an enable level during the compensation period after the initialization period in a frame. The write gate signal may have an enable level during the address period after the compensation period in a frame. The initialization gate signal may have an enable level during the emission initialization period after the address period in a frame.

[0019] In an embodiment, the sub-pixel may further include: a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to an emission bias signal.

[0020] In an embodiment, the sub-pixel may further include: a ninth transistor configured to provide a first power voltage to the first transistor in response to a reference gate signal.

[0021] In an embodiment, the initialization gate signal may have an enable level during the first compensation initialization period. The reference gate signal may have an enable level during the second compensation initialization period. Each of the initialization gate signal and the write gate signal may have an enable level during an address period after the first compensation initialization period and the second compensation initialization period in one frame. The initialization gate signal may have an enable level during an emission initialization period after the address period in one frame.

[0022] In an embodiment, the first compensation initialization period and the second compensation initialization period may be alternately arranged.

[0023] In an embodiment, the subpixel may further include: a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to a previous emission signal.

[0024] In an embodiment, the sub-pixel may further include: an eighth transistor configured to provide a reference voltage to the first electrode of the first transistor in response to the write gate signal.

[0025] In an embodiment, the initialization gate signal may have an enable level during the first compensation initialization period. The reference gate signal may have an enable level during the second compensation initialization period. The write gate signal may have an enable level during the address period after the first compensation initialization period and the second compensation initialization period in one frame. The initialization gate signal may have an enable level during the emission initialization period after the address period in one frame.

[0026] In an embodiment, the subpixel may further include: a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to a previous emission signal.

[0027] In an embodiment, the subpixel may further include: a sixth transistor configured to provide a 1-1th power voltage to the first transistor in response to the emission signal; and a ninth transistor configured to provide a 1-2th power voltage to the first transistor in response to the reference gate signal.

[0028] In an embodiment, the sub-pixel may further include: an eighth transistor configured to provide a reference voltage to the first electrode of the first transistor in response to the write gate signal.

[0029] In an embodiment, the sub-pixel may further include: a fifth transistor configured to provide an initialization voltage to the first electrode of the first transistor in response to an initialization gate signal; a sixth transistor configured to provide a first power voltage to the first transistor in response to an emission signal; and a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light-emitting element in response to an emission bias signal.

[0030] In an embodiment, each of the reference gate signal and the initialization gate signal may have an enable level during the initialization period. Each of the reference gate signal and the emission signal may have an enable level during the compensation period after the initialization period in a frame. Each of the initialization gate signal, the write gate signal, and the emission bias signal may have an enable level during the address period after the compensation period in a frame. Each of the initialization gate signal and the emission bias signal may have an enable level during the emission initialization period after the address period in a frame.

[0031] In an embodiment, the sub-pixel may further include: an eighth transistor configured to provide a reference voltage to the first electrode of the first transistor in response to the write gate signal.

[0032] In an embodiment, each of the reference gate signal and the initialization gate signal may have an enable level during the initialization period. Each of the reference gate signal and the emission signal may have an enable level during the compensation period after the initialization period in a frame. The write gate signal may have an enable level during the address period after the compensation period in a frame. Each of the initialization gate signal and the emission bias signal may have an enable level during the emission initialization period after the address period in a frame.

[0033] In an embodiment, the sub-pixel may further include: a fifth transistor configured to provide an initialization voltage to the first electrode of the first transistor in response to an initialization gate signal; a sixth transistor configured to provide a first power voltage to the first transistor in response to an emission signal; a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light-emitting element in response to a previous emission signal; and a ninth transistor configured to provide a first power voltage to the first transistor in response to a reference gate signal.

[0034] In an embodiment, the initialization gate signal may have an enable level during the first compensation initialization period. The reference gate signal may have an enable level during the second compensation initialization period. Each of the initialization gate signal, the write gate signal, and the previous emission signal may have an enable level during an address period after the first compensation initialization period and the second compensation initialization period in one frame. Each of the initialization gate signal and the previous emission signal may have an enable level during an emission initialization period after the address period in one frame.

[0035] In an embodiment, the sub-pixel may further include: an eighth transistor configured to provide a reference voltage to the first electrode of the first transistor in response to the write gate signal.

[0036] In an embodiment, the initialization gate signal may have an enable level during the first compensation initialization period. The reference gate signal may have an enable level during the second compensation initialization period. The write gate signal may have an enable level during the address period after the first compensation initialization period and the second compensation initialization period in one frame. Each of the initialization gate signal and the previous emission signal may have an enable level during the emission initialization period after the address period in one frame.

[0037] An embodiment of the present disclosure may provide a display device, the display device comprising: a display panel including sub-pixels; and a display panel driver configured to drive the display panel. The sub-pixels may include: a first transistor configured to generate a driving current; a first capacitor including a first electrode connected to a first electrode of the first transistor, and a second electrode; a second capacitor including a first electrode connected to a control electrode of the first transistor and a second electrode connected to a second electrode of the first capacitor; a second transistor configured to provide a data voltage to the second electrode of the first capacitor in response to a write gate signal; and a light-emitting element configured to receive the driving current and emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0039] Figure 2 It is shown Figure 1 A circuit diagram of an example of a sub-pixel of a display device.

[0040] Figure 3 It is shown in Figure 1 1 is a timing diagram of an example of driving subpixels during a non-emission period in a display device.

[0041] Figure 4 It is shown in Figure 11 is a timing diagram of an example of driving subpixels during an emission period in a display device.

[0042] Figure 5 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0043] Figure 6 It is shown Figure 5 A circuit diagram of an example of a sub-pixel of a display device.

[0044] Figure 7 Is shown driving Figure 6 A timing diagram of an example of a sub-pixel in a display device.

[0045] Figure 8 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0046] Fig. 9 Is shown driving Figure 8 A timing diagram of an example of a sub-pixel in a display device.

[0047] Fig.10 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0048] Fig.11 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0049] Fig.12 Is shown driving Fig.11 A timing diagram of an example of a sub-pixel in a display device.

[0050] Fig.13 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0051] Fig.14 Is shown driving Fig.13 A timing diagram of an example of a sub-pixel in a display device.

[0052] Fig.15 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0053] Fig.16 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0054] Fig.17 It is shown in Fig.16 1 is a timing diagram of an example of driving subpixels during a non-emission period in a display device.

[0055] Fig.18 It is shown in Fig.161 is a timing diagram of an example of driving subpixels during an emission period in a display device.

[0056] Fig.19 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0057] Fig. 20 It is shown in Fig.19 1 is a timing diagram of an example of driving subpixels during a non-emission period in a display device.

[0058] Fig.21 It is shown in Fig.19 1 is a timing diagram of an example of driving subpixels during an emission period in a display device.

[0059] Fig. 22 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0060] Fig.23 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0061] Fig.24 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0062] Fig.25 Is shown driving Fig.24 A timing diagram of an example of a sub-pixel in a display device.

[0063] Fig.26 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0064] Fig. 27 Is shown driving Fig.26 A timing diagram of an example of a sub-pixel in a display device.

[0065] Fig.28 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0066] Fig.29 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure.

[0067] Fig.30 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0068] Fig.31 It is shown Fig.30 FIG. 5 is a diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0069] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the following description, only the parts required for understanding the operation according to the present disclosure will be described, and the description of other parts will be omitted so as not to make the main points of the present disclosure unclear. Therefore, the present disclosure is not limited to the embodiments set forth herein, but can be implemented in other types. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the technical spirit of the present disclosure will be fully conveyed to those skilled in the art.

[0070] It will be understood that when an element is referred to as "coupled" or "connected" to another element, the element can be directly coupled or connected to the other element, or there may be an intermediate element between the element and the other element. The terms used herein are only for the purpose of describing a specific embodiment, and are not intended to be restrictive. In this specification, unless the context clearly indicates otherwise, when an element is referred to as "including" or "comprising" a component, the element does not exclude another component, but may also include other components. "At least one (kind / person) of X, Y and Z" and "at least one (kind / person) selected from the group consisting of X, Y and Z" can be understood as any combination of only X, only Y, only Z or two or more of X, Y and Z (for example, XYZ, XY, YZ and XZ). As used herein, the term "and / or" can include any combination and all combinations of one or more related listed items.

[0071] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0072] For descriptive purposes, spatially relative terms such as "under", "below", "below", "down", "above", "on", "above (throughout), "higher than", and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element or feature to another element (or elements) or another feature (or features) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "below" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the term "under" can cover both "above" and "under" orientations. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0073] Various embodiments will be described with reference to the figures showing idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes of the regions shown, but are to include deviations in shapes resulting, for example, from manufacturing. As such, the shapes shown in the drawings may not illustrate the actual shapes of regions of the device, and as such, are not intended to be limiting.

[0074] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0075] Reference Figure 1 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, and a data driver 400. In an embodiment, the driving controller 200 and the data driver 400 may be integrated into a single chip.

[0076] The display panel 100 may include a display area DA formed to display an image and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 300 may be installed in the non-display area NDA.

[0077] The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, and a plurality of sub-pixels SP electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction DR1. The data lines DL may extend in a second direction DR2 crossing the first direction DR1.

[0078] The drive controller 200 may receive input image data IMG and an input control signal CONT from a main processor (e.g., a graphics processing unit (GPU)). For example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may also include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may include a vertical synchronization signal and a horizontal synchronization signal.

[0079] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0080] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0081] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0082] The driving controller 200 may receive input image data IMG and an input control signal CONT and generate a data signal DATA. The driving controller 200 may output the data signal DATA to the data driver 400.

[0083] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0084] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200. The data driver 400 may generate a data voltage by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0085] Figure 2 It is shown Figure 1 1 is a circuit diagram of an example of a sub-pixel SP of a display device. Figure 3 It is shown in Figure 1 The sub-pixel SP is driven during the non-emission period in the display device (see Figure 2 ) example. Figure 4 It is shown in Figure 1 The sub-pixel SP is driven during the emission period in the display device (see Figure 2 ) example.

[0086] Reference Figure 2, the sub-pixel SP may include a first transistor T1 (e.g., a driving transistor), a first capacitor C1, a second capacitor C2, a second transistor T2, and a light emitting element EE. The first transistor T1 may generate a driving current. The first capacitor C1 may include a first electrode connected to the first electrode of the first transistor T1, and a second electrode. The second capacitor C2 may include a first electrode connected to the control electrode of the first transistor T1 and a second electrode connected to the second electrode of the first capacitor C1. The second transistor T2 may provide a data voltage VDATA to the second electrode of the first capacitor C1 in response to a write gate signal GW. The light emitting element EE may receive the driving current and emit light. The sub-pixel SP may include a third transistor T3 and a fourth transistor T4, the third transistor T3 being configured to connect the first electrode of the first transistor T1 to the second electrode of the first capacitor C1 in response to a reference gate signal GR, and the fourth transistor T4 being configured to provide a reference voltage VREF to the control electrode of the first transistor T1 in response to the reference gate signal GR. The sub-pixel SP may also include a fifth transistor T5 configured to provide an initialization voltage VINT to the first electrode of the light emitting element EE in response to an initialization gate signal GI.

[0087] For example, the first transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode configured to receive a first power voltage ELVDD (e.g., a high power voltage). The second transistor T2 may include a control electrode configured to receive a write gate signal GW, a first electrode configured to receive a data voltage VDATA, and a second electrode connected to a third node N3. The third transistor T3 may include a control electrode configured to receive a reference gate signal GR, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The fourth transistor T4 may include a control electrode configured to receive a reference gate signal GR, a first electrode configured to receive a reference voltage VREF, and a second electrode connected to the first node N1. The fifth transistor T5 may include a control electrode configured to receive an initialization gate signal GI, a first electrode configured to receive an initialization voltage VINT, and a second electrode connected to the second node N2. The first capacitor C1 may include a first electrode connected to the second node N2 and a second electrode connected to the third node N3. The second capacitor C2 may include a first electrode connected to the first node N1 and a second electrode connected to the third node N3. The light emitting element EE may include a first electrode (eg, an anode electrode) connected to the second node N2 and a second electrode configured to receive a second power voltage ELVSS (eg, a low power voltage).

[0088] In an embodiment, the first transistor T1 may further include a back gate electrode connected to the second node N2. However, the present disclosure is not limited to the foregoing examples.

[0089] Each of the first transistor T1 to the fifth transistor T5 can be implemented using an N-channel metal oxide semiconductor (NMOS) transistor. In this case, the low voltage level can be a disable level, and the high voltage level can be an enable level. For example, if the signal applied to the control electrode of the NMOS transistor has a low voltage level, the NMOS transistor can be turned off. For example, if the signal applied to the control electrode of the NMOS transistor has a high voltage level, the NMOS transistor can be turned on.

[0090] However, the present disclosure is not limited to the foregoing examples. For example, each of the first transistor T1 to the fifth transistor T5 can be implemented using a P-channel metal oxide semiconductor (PMOS) transistor. In this case, the low voltage level can be an enable level, and the high voltage level can be a disable level. For example, if the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor can be turned on. For example, if the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor can be turned off. In other words, the enable level and the disable level can be determined based on the type of transistor.

[0091] Reference Figures 2 to 4 , one frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP.

[0092] The non-emission period NEP may include an initialization period IP, a compensation period CP, and an address period AP. The emission period EP may include an emission initialization period EIP.

[0093] For example, in the initialization period IP, each of the reference gate signal GR and the initialization gate signal GI may have an enable level, and the third transistor T3 to the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VINT. In other words, the first capacitor C1 and the second capacitor C2 may be initialized. Here, VREF represents the reference voltage VREF (or the value of the reference voltage VREF), and VINT represents the initialization voltage VINT (or the value of the initialization voltage VINT), and this remains unchanged below.

[0094] For example, in one frame, during the compensation period CP after the initialization period IP, the reference gate signal GR may have an enable level, and the third transistor T3 and the fourth transistor T4 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since the voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP to be described below. Here, VTH represents the threshold voltage (VTH) of the first transistor T1 (or the value of the threshold voltage (VTH) of the first transistor T1), and this remains unchanged below.

[0095] For example, in one frame, during the address period AP after the compensation period CP, each of the initialization gate signal GI and the write gate signal GW may have an enable level, and the second transistor T2 and the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VINT, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2. Here, VDATA represents the data voltage VDATA (or the value of the data voltage VDATA), and this remains unchanged below.

[0096] For example, during the emission period EP, the first transistor T1 may generate a driving current corresponding to a gate-source voltage (ie, a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VINT+VTH.

[0097] In the case of writing a reduced data voltage (e.g., (1-α)×VDATA, where α is a real number less than 1 and greater than 0), a higher data voltage needs to be written to emit light with the same brightness. As the data voltage VDATA increases, the power consumption of the display device may also increase. However, in the sub-pixel SP according to an embodiment of the present disclosure, the unchanged data voltage VDATA is written instead of the reduced data voltage. Therefore, the range of the data voltage VDATA applied to the sub-pixel SP can be reduced, and the power consumption of the display device including the sub-pixel SP can be reduced.

[0098] For example, in one frame, during the emission initialization period EIP after the address period AP, the initialization gate signal GI may have an enable level and the fifth transistor T5 may be turned on. In other words, the voltage of the second node N2 may be initialized.

[0099] Figure 5is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0100] The configuration of the display device according to the present embodiment is similar to that of the present embodiment except for the emission driver 500 and the sub-pixel SP. Figure 1 The configurations of the display devices are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0101] Reference Figure 5 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a data driver 400, and an emission driver 500. In an embodiment, the driving controller 200 and the data driver 400 may be integrated into a single chip.

[0102] The display panel 100 may include a display area DA formed to display an image and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 300 and the emission driver 500 may be installed in the non-display area NDA.

[0103] The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, and a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction DR1. The data lines DL may extend in a second direction DR2 crossing the first direction DR1.

[0104] The drive controller 200 may receive input image data IMG and an input control signal CONT from a main processor (e.g., a graphics processing unit (GPU)). For example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may also include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may include a vertical synchronization signal and a horizontal synchronization signal.

[0105] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0106] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0107] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0108] The driving controller 200 may receive input image data IMG and an input control signal CONT and generate a data signal DATA. The driving controller 200 may output the data signal DATA to the data driver 400.

[0109] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT, and output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0110] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0111] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200. The data driver 400 may generate a data voltage by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0112] The emission driver 500 may generate emission signals for driving the emission lines EL in response to the third control signal CONT3 received from the driving controller 200. The emission driver 500 may output the emission signals to the emission lines EL. For example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.

[0113] In an embodiment, the transmit driver 500 may generate Figure 8 The emission bias signal EMB for driving the emission line EL is used in Figure 8 The emission bias signal EMB in is output to the emission line EL.

[0114] Figure 6 It is shown Figure 5 1 is a circuit diagram of an example of a sub-pixel SP of a display device. Figure 7 Is shown driving Figure 6 1 is a timing diagram of an example of a sub-pixel SP in a display device of FIG.

[0115] Except for the sixth transistor T6, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Figure 2 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0116] Reference Figure 6 , the sub-pixel SP may further include a sixth transistor T6 configured to provide the first power voltage ELVDD to the first transistor T1 in response to the emission signal EM.

[0117] For example, the first transistor T1 may include a second electrode connected to the second electrode of the sixth transistor T6. The sixth transistor T6 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive the first power voltage ELVDD, and a second electrode connected to the second electrode of the first transistor T1.

[0118] The sixth transistor T6 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. The sixth transistor T6 may be implemented using a PMOS transistor.

[0119] Reference Figure 6 and Figure 7 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include an initialization period IP, a compensation period CP, an address period AP, and an emission initialization period EIP.

[0120] For example, in the initialization period IP, each of the reference gate signal GR and the initialization gate signal GI may have an enable level, and the third transistor T3 to the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VINT. In other words, the first capacitor C1 and the second capacitor C2 may be initialized.

[0121] For example, in one frame, during the compensation period CP after the initialization period IP, each of the reference gate signal GR and the emission signal EM may have an enable level, and the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since the voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0122] For example, in one frame, during the address period AP after the compensation period CP, each of the initialization gate signal GI and the write gate signal GW may have an enable level, and the second transistor T2 and the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VINT, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0123] For example, in one frame, during the emission initialization period EIP after the address period AP, the initialization gate signal GI may have an enable level and the fifth transistor T5 may be turned on. In other words, the voltage of the second node N2 may be initialized.

[0124] For example, during the emission period EP, the emission signal EM may have an enable level, and the sixth transistor T6 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VINT+VTH.

[0125] Figure 8 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig. 9 Is shown driving Figure 8 1 is a timing diagram of an example of a sub-pixel SP in a display device of FIG.

[0126] The configuration of the sub-pixel SP according to the present embodiment is similar to that of the embodiment except for the fifth transistor T5 and the seventh transistor T7. Figure 6 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0127] Reference Figure 8The subpixel SP may further include a fifth transistor T5 and a seventh transistor T7, the fifth transistor T5 being configured to provide an initialization voltage VINT to the first electrode of the first transistor T1 in response to an initialization gate signal GI, and the seventh transistor T7 being configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to an emission bias signal EMB.

[0128] For example, the fifth transistor T5 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the second node N2. The seventh transistor T7 may include a control electrode configured to receive the emission bias signal EMB, a first electrode connected to the second node N2, and a second electrode connected to the first electrode of the light emitting element EE.

[0129] Each of the fifth transistor T5 and the seventh transistor T7 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. For example, each of the fifth transistor T5 and the seventh transistor T7 may be implemented using a PMOS transistor.

[0130] Reference Figures 8 to 9 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include an initialization period IP, a compensation period CP, an address period AP, and an emission initialization period EIP.

[0131] For example, in the initialization period IP, each of the reference gate signal GR and the initialization gate signal GI may have an enable level, and the third transistor T3 to the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VINT. In other words, the first capacitor C1 and the second capacitor C2 may be initialized.

[0132] For example, in one frame, during the compensation period CP after the initialization period IP, each of the reference gate signal GR and the emission signal EM may have an enable level, and the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since the voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0133] For example, in one frame, during the address period AP after the compensation period CP, each of the initialization gate signal GI, the write gate signal GW, and the emission bias signal EMB may have an enable level, and the second transistor T2, the fifth transistor T5, and the seventh transistor T7 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VINT, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0134] For example, in one frame, during the emission initialization period EIP after the address period AP, each of the initialization gate signal GI and the emission bias signal EMB may have an enable level, and the fifth transistor T5 and the seventh transistor T7 may be turned on. In other words, the voltage of the second node N2 and the first electrode of the light emitting element EE may be initialized.

[0135] For example, during the emission period EP, each of the emission signal EM and the emission bias signal EMB may have an enable level, and the sixth transistor T6 and the seventh transistor T7 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VINT+VTH.

[0136] Fig.10 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure.

[0137] Except for the seventh transistor T7, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Figure 6 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0138] Reference Fig.10 , the sub-pixel SP may further include a seventh transistor T7 configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to the emission bias signal EMB. Fig.10 The display device in the Fig. 9 The sub-pixel SP is driven in substantially the same manner as in FIG. 4 ; therefore, redundant description will be omitted.

[0139] Fig.11 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig.12 Is shown driving Fig.11 1 is a timing diagram of an example of a sub-pixel SP in a display device of FIG.

[0140] Except for the eighth transistor T8, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Figure 6 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0141] Reference Fig.11 The sub-pixel SP may further include an eighth transistor T8 configured to provide a reference voltage VREF to the first electrode of the first transistor T1 in response to the write gate signal GW.

[0142] For example, the eighth transistor T8 may include a control electrode configured to receive the write gate signal GW, a first electrode configured to receive the reference voltage VREF, and a second electrode connected to the second node N2.

[0143] The eighth transistor T8 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. The eighth transistor T8 may be implemented using a PMOS transistor.

[0144] Reference Figure 11 to Figure 12 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include an initialization period IP, a compensation period CP, an address period AP, and an emission initialization period EIP.

[0145] For example, in the initialization period IP, each of the reference gate signal GR and the initialization gate signal GI may have an enable level, and the third transistor T3 to the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VINT. In other words, the first capacitor C1 and the second capacitor C2 may be initialized.

[0146] For example, in one frame, during the compensation period CP after the initialization period IP, each of the reference gate signal GR and the emission signal EM may have an enable level, and the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since the voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0147] For example, in one frame, during the address period AP after the compensation period CP, the write gate signal GW may have an enable level, and the second transistor T2 and the eighth transistor T8 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VREF, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0148] For example, in one frame, during the emission initialization period EIP after the address period AP, the initialization gate signal GI may have an enable level and the fifth transistor T5 may be turned on. In other words, the voltage of the second node N2 may be initialized.

[0149] For example, during the emission period EP, the emission signal EM may have an enable level, and the sixth transistor T6 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VREF+VTH. Setting a voltage value for the reference voltage VREF may be easier than setting a voltage value for the initialization voltage VINT. Therefore, the range of the data voltage VDATA may be adjusted by adjusting the reference voltage VREF. Therefore, the power consumption of the display device may be reduced.

[0150] Fig.13 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig.14 Is shown driving Fig.13 1 is a timing diagram of an example of a sub-pixel SP in a display device of FIG.

[0151] The configuration of the sub-pixel SP according to the present embodiment is similar to that of the embodiment except for the fifth transistor T5 and the seventh transistor T7. Fig.11 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0152] Reference Fig.13 The subpixel SP may further include a fifth transistor T5 and a seventh transistor T7, the fifth transistor T5 being configured to provide an initialization voltage VINT to the first electrode of the first transistor T1 in response to an initialization gate signal GI, and the seventh transistor T7 being configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to an emission bias signal EMB.

[0153] For example, the fifth transistor T5 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the second node N2. The seventh transistor T7 may include a control electrode configured to receive the emission bias signal EMB, a first electrode connected to the second node N2, and a second electrode connected to the first electrode of the light emitting element EE.

[0154] Each of the fifth transistor T5 and the seventh transistor T7 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. For example, each of the fifth transistor T5 and the seventh transistor T7 may be implemented using a PMOS transistor.

[0155] Reference Figure 13 to Figure 14 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include an initialization period IP, a compensation period CP, an address period AP, and an emission initialization period EIP.

[0156] For example, in the initialization period IP, each of the reference gate signal GR and the initialization gate signal GI may have an enable level, and the third transistor T3 to the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VINT. In other words, the first capacitor C1 and the second capacitor C2 may be initialized.

[0157] For example, in one frame, during the compensation period CP after the initialization period IP, each of the reference gate signal GR and the emission signal EM may have an enable level, and the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since the voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0158] For example, in one frame, during the address period AP after the compensation period CP, the write gate signal GW may have an enable level, and the second transistor T2 and the eighth transistor T8 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VREF, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0159] For example, in one frame, during the emission initialization period EIP after the address period AP, each of the initialization gate signal GI and the emission bias signal EMB may have an enable level, and the fifth transistor T5 and the seventh transistor T7 may be turned on. In other words, the voltage of the second node N2 and the first electrode of the light emitting element EE may be initialized.

[0160] For example, during the emission period EP, each of the emission signal EM and the emission bias signal EMB may have an enable level, and the sixth transistor T6 and the seventh transistor T7 may be turned on. The first transistor T1 may generate a driving current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VREF+VTH.

[0161] Fig.15 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure.

[0162] Except for the seventh transistor T7, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Fig.11 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0163] Reference Fig.15 , the sub-pixel SP may further include a seventh transistor T7 configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to the emission bias signal EMB. Fig.15 The display device in the Fig.14 The sub-pixel SP is driven in substantially the same manner as in FIG. 4 ; therefore, redundant description will be omitted.

[0164] Fig.16 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig.17 It is shown in Fig.16 1 is a timing diagram of an example of driving a sub-pixel SP during a non-emission period in a display device of FIG. Fig.18 It is shown in Fig.16 1 is a timing diagram of an example of driving a sub-pixel SP during an emission period in a display device.

[0165] Except for the ninth transistor T9, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Figure 8 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0166] Reference Fig.16, the sub-pixel SP may further include a ninth transistor T9 configured to provide the first power voltage ELVDD to the first transistor T1 in response to the reference gate signal GR.

[0167] For example, the second electrode of the first transistor T1 may be connected to the fourth node N4. The ninth transistor T9 may include a control electrode configured to receive the reference gate signal GR, a first electrode configured to receive the first power voltage ELVDD, and a second electrode connected to the fourth node N4. The second electrode of the sixth transistor T6 may be connected to the fourth node N4.

[0168] For example, the fifth transistor T5 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the second node N2. The seventh transistor T7 may include a control electrode configured to receive the emission bias signal EMB, a first electrode connected to the second node N2, and a second electrode connected to the first electrode of the light emitting element EE.

[0169] The ninth transistor T9 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. The ninth transistor T9 may be implemented using a PMOS transistor.

[0170] Reference Figures 16 to 18 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include a first compensation initialization period ICP1, a second compensation initialization period ICP2 and an address period AP. The emission period EP may include an emission initialization period EIP.

[0171] In an embodiment, the first compensation initialization period ICP1 and the second compensation initialization period ICP2 may be arranged alternately. The second compensation initialization period ICP2 may be positioned immediately before the address period AP. In the present embodiment, the case where the first compensation initialization period ICP1 and the second compensation initialization period ICP2 are repeated twice has been shown, but the present disclosure is not limited thereto.

[0172] For example, during the first compensation initialization period ICP1, the initialization gate signal GI may have an enable level, and the fifth transistor T5 may be turned on. Therefore, the voltage of the second node N2 may be VINT.

[0173] For example, during the second compensation initialization period ICP2, the reference gate signal GR may have an enable level, and the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since a voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0174] For example, in one frame, during the address period AP after the first compensation initialization period ICP1 and the second compensation initialization period ICP2, each of the initialization gate signal GI and the write gate signal GW may have an enable level, and the second transistor T2 and the fifth transistor T5 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VINT, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0175] For example, in one frame, during the emission initialization period EIP after the address period AP, the initialization gate signal GI may have an enable level and the fifth transistor T5 may be turned on. In other words, the voltage of the second node N2 may be initialized.

[0176] For example, during the emission period EP, the emission signal EM may periodically have an enable level and a disable level. When the emission signal EM has the enable level, the sixth transistor T6 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VINT+VTH.

[0177] Fig.19 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig. 20 It is shown in Fig.19 1 is a timing diagram of an example of driving a sub-pixel SP during a non-emission period in a display device of FIG. Fig.21 It is shown in Fig.19 1 is a timing diagram of an example of driving a sub-pixel SP during an emission period in a display device.

[0178] The configuration of the sub-pixel SP according to the present embodiment is similar to that of the embodiment except for the fifth transistor T5 and the seventh transistor T7. Fig.16The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0179] Reference Fig.19 The subpixel SP may further include a fifth transistor T5 and a seventh transistor T7, the fifth transistor T5 being configured to provide an initialization voltage VINT to the first electrode of the first transistor T1 in response to the initialization gate signal GI, and the seventh transistor T7 being configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to the previous emission signal EM[n-1].

[0180] Fig.19 The sub-pixel SP may be a sub-pixel SP provided in an n-th pixel row (where n is a positive integer). The previous emission signal EM[n-1] may be an emission signal of the sixth transistor T6 applied to the sub-pixel SP provided in the n-1-th pixel row. In the present embodiment, the n-1-th pixel row has been shown, but the present disclosure is not limited thereto.

[0181] Thus, the previous transmission signal EM[n-1] can be used to replace Figure 8 The transmit bias signal EMB in the Figure 5 As a result, dead space can be reduced.

[0182] For example, the fifth transistor T5 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the second node N2. The seventh transistor T7 may include a control electrode configured to receive the previous emission signal EM[n-1], a first electrode connected to the second node N2, and a second electrode connected to the first electrode of the light emitting element EE.

[0183] Each of the fifth transistor T5 and the seventh transistor T7 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. For example, each of the fifth transistor T5 and the seventh transistor T7 may be implemented using a PMOS transistor.

[0184] Reference Figures 19 to 21 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include a first compensation initialization period ICP1, a second compensation initialization period ICP2 and an address period AP. The emission period EP may include an emission initialization period EIP.

[0185] In an embodiment, the first compensation initialization period ICP1 and the second compensation initialization period ICP2 may be arranged alternately. The second compensation initialization period ICP2 may be positioned immediately before the address period AP. In the present embodiment, the case where the first compensation initialization period ICP1 and the second compensation initialization period ICP2 are repeated twice has been shown, but the present disclosure is not limited thereto.

[0186] For example, during the first compensation initialization period ICP1, the initialization gate signal GI may have an enable level, and the fifth transistor T5 may be turned on. Therefore, the voltage of the second node N2 may be VINT.

[0187] For example, during the second compensation initialization period ICP2, the reference gate signal GR may have an enable level, and the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since a voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0188] For example, in one frame, during the address period AP after the first compensation initialization period ICP1 and the second compensation initialization period ICP2, each of the initialization gate signal GI, the write gate signal GW, and the previous emission signal EM[n-1] may have an enable level, and the second transistor T2, the fifth transistor T5, and the seventh transistor T7 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VINT, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0189] For example, in one frame, during the emission initialization period EIP after the address period AP, each of the initialization gate signal GI and the previous emission signal EM[n-1] may have an enable level, and the fifth transistor T5 and the seventh transistor T7 may be turned on. In other words, the voltage of the second node N2 and the first electrode of the light emitting element EE may be initialized.

[0190] For example, during the emission period EP, the emission signal EM[n] and the previous emission signal EM[n-1] may periodically have an enable level and a disable level. When the emission signal EM[n] and the previous emission signal EM[n-1] have an enable level, the sixth transistor T6 and the seventh transistor T7 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VINT+VTH.

[0191] Fig. 22 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure.

[0192] Except for the seventh transistor T7, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Fig.19 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0193] Reference Fig. 22 The subpixel SP may further include a seventh transistor T7 configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to the previous emission signal EM[n-1]. Fig. 22 The display device in the Fig. 20 and Fig.21 The sub-pixel SP is driven in substantially the same manner as in FIG. 4 ; therefore, redundant description will be omitted.

[0194] Fig.23 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure.

[0195] The configuration of the sub-pixel SP according to the present embodiment is the same as that of the first embodiment except for the first-first power voltage ELVDD1 and the first-second power voltage ELVDD2. Fig.16 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0196] Reference Fig.23 The subpixel SP may include a sixth transistor T6 and a ninth transistor T9, the sixth transistor T6 being configured to provide a 1-1st power voltage ELVDD1 to the first transistor T1 in response to the emission signal EM, and the ninth transistor T9 being configured to provide a 1-2nd power voltage ELVDD2 to the first transistor T1 in response to the reference gate signal GR.

[0197] For example, the sixth transistor T6 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive the 1-1th power voltage ELVDD1, and a second electrode connected to the fourth node N4. The ninth transistor T9 may include a control electrode configured to receive the reference gate signal GR, a first electrode configured to receive the 1-2nd power voltage ELVDD2, and a second electrode connected to the fourth node N4.

[0198] In an embodiment, the 1-1th power voltage ELVDD1 and the 1-2th power voltage ELVDD2 may be applied to the display panel through different lines. For example, the 1-1th power voltage ELVDD1 may be used to emit light, and the 1-2nd power voltage ELVDD2 may be used to compensate for a threshold voltage.

[0199] However, the voltage values ​​of the 1-1st power voltage ELVDD1 and the 1-2nd power voltage ELVDD2 do not necessarily have to be different from each other. Fig.16 The division of the first power voltage ELVDD into the 1-1th power voltage ELVDD1 and the 1-2nd power voltage ELVDD2 may minimize the influence between the sub-pixels SP.

[0200] Will Fig.16 The first power voltage ELVDD in the embodiment is divided into a 1-1 power voltage ELVDD1 and a 1-2 power voltage ELVDD2, which can also be applied to Fig.19 and Fig. 22 sub-pixel SP.

[0201] Fig.23 The display device in the Fig.17 The sub-pixel SP is driven in substantially the same manner as in FIG. 4 ; therefore, redundant description will be omitted.

[0202] Fig.24 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig.25 Is shown driving Fig.24 1 is a timing diagram of an example of a sub-pixel SP in a display device of FIG.

[0203] Except for the eighth transistor T8, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Fig.16 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0204] Reference Fig.24 The sub-pixel SP may further include an eighth transistor T8 configured to provide a reference voltage VREF to the first electrode of the first transistor T1 in response to the write gate signal GW.

[0205] For example, the eighth transistor T8 may include a control electrode configured to receive the write gate signal GW, a first electrode configured to receive the reference voltage VREF, and a second electrode connected to the second node N2.

[0206] The eighth transistor T8 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. The eighth transistor T8 may be implemented using a PMOS transistor.

[0207] Reference Figure 24 to Figure 25 , a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include a first compensation initialization period ICP1, a second compensation initialization period ICP2, an address period AP, and an emission initialization period EIP.

[0208] In an embodiment, the first compensation initialization period ICP1 and the second compensation initialization period ICP2 may be arranged alternately. The second compensation initialization period ICP2 may be positioned immediately before the address period AP. In the present embodiment, the case where the first compensation initialization period ICP1 and the second compensation initialization period ICP2 are repeated twice has been shown, but the present disclosure is not limited thereto.

[0209] For example, during the first compensation initialization period ICP1, the initialization gate signal GI may have an enable level, and the fifth transistor T5 may be turned on. Therefore, the voltage of the second node N2 may be VINT.

[0210] For example, during the second compensation initialization period ICP2, the reference gate signal GR may have an enable level, and the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since a voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0211] For example, in one frame, during the address period AP after the first compensation initialization period ICP1 and the second compensation initialization period ICP2, the write gate signal GW may have an enable level, and the second transistor T2 and the eighth transistor T8 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VREF, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0212] For example, in one frame, during the emission initialization period EIP after the address period AP, the initialization gate signal GI may have an enable level and the fifth transistor T5 may be turned on. In other words, the voltage of the second node N2 may be initialized.

[0213] For example, during the emission period EP, the emission signal EM may have an enable level and the sixth transistor T6 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VREF+VTH.

[0214] Fig.26 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure. Fig. 27 Is shown driving Fig.26 1 is a timing diagram of an example of a sub-pixel SP in a display device of FIG.

[0215] The configuration of the sub-pixel SP according to the present embodiment is similar to that of the embodiment except for the fifth transistor T5 and the seventh transistor T7. Fig.24 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0216] Reference Fig.26 The subpixel SP may further include a fifth transistor T5 and a seventh transistor T7, the fifth transistor T5 being configured to provide an initialization voltage VINT to the first electrode of the first transistor T1 in response to the initialization gate signal GI, and the seventh transistor T7 being configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to the previous emission signal EM[n-1].

[0217] For example, the fifth transistor T5 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the second node N2. The seventh transistor T7 may include a control electrode configured to receive the previous emission signal EM[n-1], a first electrode connected to the second node N2, and a second electrode connected to the first electrode of the light emitting element EE.

[0218] Each of the fifth transistor T5 and the seventh transistor T7 may be implemented using an NMOS transistor. However, the present disclosure is not limited to the foregoing example. For example, each of the fifth transistor T5 and the seventh transistor T7 may be implemented using a PMOS transistor.

[0219] Reference Fig.26 and Fig. 27, a frame may include a non-emission period NEP and an emission period EP. For example, the light emitting element EE may emit light during the emission period EP. The non-emission period NEP may include a first compensation initialization period ICP1, a second compensation initialization period ICP2, an address period AP, and an emission initialization period EIP.

[0220] In an embodiment, the first compensation initialization period ICP1 and the second compensation initialization period ICP2 may be arranged alternately. The second compensation initialization period ICP2 may be positioned immediately before the address period AP. In the present embodiment, the case where the first compensation initialization period ICP1 and the second compensation initialization period ICP2 are repeated twice has been shown, but the present disclosure is not limited thereto.

[0221] For example, during the first compensation initialization period ICP1, the initialization gate signal GI may have an enable level, and the fifth transistor T5 may be turned on. Therefore, the voltage of the second node N2 may be VINT.

[0222] For example, during the second compensation initialization period ICP2, the reference gate signal GR may have an enable level, and the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be turned on. Therefore, the voltage of the first node N1 may be VREF, and the voltage of each of the second node N2 and the third node N3 may be VREF-VTH. In other words, since a voltage corresponding to VREF-VTH is stored in the first capacitor C1 and the second capacitor C2, the threshold voltage of the first transistor T1 may be compensated during the emission period EP.

[0223] For example, in one frame, during the address period AP after the first compensation initialization period ICP1 and the second compensation initialization period ICP2, the write gate signal GW may have an enable level, and the second transistor T2 and the eighth transistor T8 may be turned on. Therefore, the voltage of the first node N1 may be VDATA+VTH, the voltage of the second node N2 may be VREF, and the voltage of the third node N3 may be VDATA. In other words, the data voltage VDATA may be written to the first capacitor C1 and the second capacitor C2.

[0224] For example, in one frame, during the emission initialization period EIP after the address period AP, each of the initialization gate signal GI and the previous emission signal EM[n-1] may have an enable level, and the fifth transistor T5 and the seventh transistor T7 may be turned on. In other words, the voltage of the second node N2 and the first electrode of the light emitting element EE may be initialized.

[0225] For example, during the emission period EP, each of the emission signal EM[n] and the previous emission signal EM[n-1] may have an enable level, and the sixth transistor T6 and the seventh transistor T7 may be turned on. The first transistor T1 may generate a drive current corresponding to a gate-source voltage (i.e., a voltage between the first node N1 and the second node N2). The gate-source voltage of the first transistor T1 may be VDATA-VREF+VTH.

[0226] Fig.28 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure.

[0227] Except for the seventh transistor T7, the configuration of the sub-pixel SP according to the present embodiment is the same as that of the Fig.24 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0228] Reference Fig.28 The subpixel SP may further include a seventh transistor T7 configured to connect the first electrode of the first transistor T1 to the first electrode of the light emitting element EE in response to the previous emission signal EM[n-1]. Fig.28 The display device in the Fig. 27 The sub-pixel SP is driven in substantially the same manner as in FIG. 4 ; therefore, redundant description will be omitted.

[0229] Fig.29 is a circuit diagram showing a sub-pixel SP of a display device according to an embodiment of the present disclosure.

[0230] The configuration of the sub-pixel SP according to the present embodiment is the same as that of the first embodiment except for the first-first power voltage ELVDD1 and the first-second power voltage ELVDD2. Fig.24 The configurations of the sub-pixels SP are substantially the same; therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted.

[0231] Reference Fig.29 The subpixel SP may include a sixth transistor T6 and a ninth transistor T9, the sixth transistor T6 being configured to provide a 1-1st power voltage ELVDD1 to the first transistor T1 in response to the emission signal EM, and the ninth transistor T9 being configured to provide a 1-2nd power voltage ELVDD2 to the first transistor T1 in response to the reference gate signal GR.

[0232] For example, the sixth transistor T6 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive the 1-1th power voltage ELVDD1, and a second electrode connected to the fourth node N4. The ninth transistor T9 may include a control electrode configured to receive the reference gate signal GR, a first electrode configured to receive the 1-2nd power voltage ELVDD2, and a second electrode connected to the fourth node N4.

[0233] In an embodiment, the 1-1th power voltage ELVDD1 and the 1-2th power voltage ELVDD2 may be applied to the display panel through different lines. For example, the 1-1th power voltage ELVDD1 may be used to emit light, and the 1-2nd power voltage ELVDD2 may be used to compensate for a threshold voltage.

[0234] However, the voltage values ​​of the 1-1st power voltage ELVDD1 and the 1-2nd power voltage ELVDD2 do not necessarily have to be different from each other. Fig.24 The division of the first power voltage ELVDD into the 1-1th power voltage ELVDD1 and the 1-2nd power voltage ELVDD2 may minimize the influence between the sub-pixels SP.

[0235] Will Fig.24 The first power voltage ELVDD in the embodiment is divided into a 1-1 power voltage ELVDD1 and a 1-2 power voltage ELVDD2, which can also be applied to Fig.26 and Fig.28 sub-pixel SP.

[0236] Fig.29 The display device in the Fig.25 The sub-pixel SP is driven in substantially the same manner as in FIG. 4 ; therefore, redundant description will be omitted.

[0237] Fig.30 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Fig.31 It is shown Fig.30 The electronic device 1000 is implemented as an example of a smart phone.

[0238] Reference Figure 30 to Figure 31 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The electronic device 1000 may also include various ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, or other systems. Fig.31As shown in , the electronic device 1000 can be implemented as a smart phone. However, the foregoing examples are illustrative, and the electronic device 1000 is not limited to the foregoing examples. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a navigation device for a vehicle, a computer monitor, a laptop computer, and a head-mounted display device, etc.

[0239] The processor 1010 may perform specific calculations or tasks. In an embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, and a data bus, etc. In an embodiment, the processor 1010 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0240] The memory device 1020 may store data required to perform operations of the electronic device 1000. For example, the memory device 1020 may include a nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device) and / or a volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0241] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a compact disk read only memory (CD-ROM), or the like.

[0242] The I / O device 1040 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer. In an embodiment, the display device 1060 may be included in the I / O device 1040 .

[0243] The power supply 1050 may supply power required to perform operations of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0244] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. Here, the display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but is not limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0245] In the sub-pixel according to an embodiment of the present disclosure, an unchanged data voltage may be written instead of a reduced data voltage (e.g., (1-α)×VDATA, where α is a real number less than 1 and greater than 0). Therefore, the range of the data voltage to be applied to the sub-pixel may be reduced, and the power consumption of the display device including the sub-pixel may be reduced.

[0246] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications are possible without departing from the spirit and scope of the present disclosure.

[0247] The present disclosure can be applied to display devices and electronic devices including display devices. For example, the present disclosure can be applied to digital televisions (TVs), 3D TVs, cellular phones, smart phones, tablet computers, virtual reality (VR) devices, PCs, home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, and navigation devices, etc.

[0248] While embodiments have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure as claimed in the accompanying claims.

Claims

1. A sub-pixel, wherein: The sub-pixel comprises: A first transistor configured to generate a driving current; a first capacitor including a first electrode connected to the first electrode of the first transistor, and a second electrode; a second capacitor including a first electrode connected to the control electrode of the first transistor and a second electrode connected to the second electrode of the first capacitor; a second transistor configured to provide a data voltage to the second electrode of the first capacitor in response to a write gate signal; and The light emitting element is configured to receive the driving current and emit light.

2. The sub-pixel according to claim 1, wherein: The sub-pixel further includes: a third transistor configured to connect the first electrode of the first transistor to the second electrode of the first capacitor in response to a reference gate signal; and A fourth transistor is configured to provide a reference voltage to the control electrode of the first transistor in response to the reference gate signal.

3. The sub-pixel according to claim 2, wherein: The sub-pixel further includes a fifth transistor configured to provide an initialization voltage to the first electrode of the light emitting element in response to an initialization gate signal.

4. The sub-pixel according to claim 3, in, Each of the reference gate signal and the initialization gate signal has an enable level during an initialization period, wherein the reference gate signal has the enable level during a compensation period after the initialization period in a frame, wherein each of the initialization gate signal and the write gate signal has the enable level during an address period after the compensation period in the one frame, and The initialization gate signal has the enable level during an emission initialization period after the address period in the frame.

5. The sub-pixel according to claim 3, wherein: The sub-pixel further includes a sixth transistor configured to provide a first power voltage to the first transistor in response to an emission signal.

6. The sub-pixel according to claim 5, in, Each of the reference gate signal and the initialization gate signal has an enable level during an initialization period, wherein each of the reference gate signal and the emission signal has the enable level during a compensation period after the initialization period in one frame, wherein each of the initialization gate signal and the write gate signal has the enable level during an address period after the compensation period in the one frame, and The initialization gate signal has the enable level during an emission initialization period after the address period in the frame.

7. The sub-pixel according to claim 5, wherein: The subpixel further includes a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to an emission bias signal.

8. The sub-pixel according to claim 5, wherein: The subpixel further includes an eighth transistor configured to provide the reference voltage to the first electrode of the first transistor in response to the write gate signal.

9. The sub-pixel according to claim 8, in, Each of the reference gate signal and the initialization gate signal has an enable level during an initialization period, wherein each of the reference gate signal and the emission signal has the enable level during a compensation period after the initialization period in one frame, wherein the write gate signal has the enable level during the address period after the compensation period in the frame, and The initialization gate signal has the enable level during an emission initialization period after the address period in the frame.

10. The sub-pixel according to claim 8, wherein: The subpixel further includes a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to an emission bias signal.

11. The sub-pixel according to claim 5, wherein: The sub-pixel further includes a ninth transistor configured to provide the first power voltage to the first transistor in response to the reference gate signal.

12. The sub-pixel according to claim 11, in, The initialization gate signal has an enable level during the first compensation initialization period, wherein the reference gate signal has the enable level during the second compensation initialization period, wherein each of the initialization gate signal and the write gate signal has the enable level during an addressing period after the first compensation initialization period and the second compensation initialization period in one frame, and The initialization gate signal has the enable level during an emission initialization period after the address period in the frame.

13. The sub-pixel according to claim 12, wherein: The first compensation initialization period and the second compensation initialization period are alternately arranged.

14. The sub-pixel according to claim 11, wherein: The subpixel further includes a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to a previous emission signal.

15. The sub-pixel according to claim 11, wherein: The subpixel further includes an eighth transistor configured to provide the reference voltage to the first electrode of the first transistor in response to the write gate signal.

16. The sub-pixel according to claim 15, in, The initialization gate signal has an enable level during the first compensation initialization period, wherein the reference gate signal has the enable level during the second compensation initialization period, wherein the write gate signal has the enable level during the addressing period after the first compensation initialization period and the second compensation initialization period in one frame, and The initialization gate signal has the enable level during an emission initialization period after the address period in the frame.

17. The sub-pixel according to claim 15, wherein: The subpixel further includes a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to a previous emission signal.

18. The sub-pixel according to claim 3, wherein: The sub-pixel further includes: a sixth transistor configured to provide a 1-1th power voltage to the first transistor in response to a transmission signal; and A ninth transistor is configured to provide a 1-2nd power voltage to the first transistor in response to the reference gate signal.

19. The sub-pixel according to claim 18, wherein: The subpixel further includes an eighth transistor configured to provide the reference voltage to the first electrode of the first transistor in response to the write gate signal.

20. The sub-pixel according to claim 2, wherein: The sub-pixel further includes: a fifth transistor configured to provide an initialization voltage to the first electrode of the first transistor in response to an initialization gate signal; a sixth transistor configured to provide a first power voltage to the first transistor in response to a transmission signal; and A seventh transistor is configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to an emission bias signal.

21. The sub-pixel according to claim 20, in, Each of the reference gate signal and the initialization gate signal has an enable level during an initialization period, wherein each of the reference gate signal and the emission signal has the enable level during a compensation period after the initialization period in one frame, wherein each of the initialization gate signal, the write gate signal, and the emission bias signal has the enable level during an address period after the compensation period in the one frame, and Wherein, each of the initialization gate signal and the emission bias signal has the enable level during an emission initialization period after the address period in the one frame.

22. The sub-pixel according to claim 20, wherein: The subpixel further includes an eighth transistor configured to provide the reference voltage to the first electrode of the first transistor in response to the write gate signal.

23. The sub-pixel according to claim 22, in, Each of the reference gate signal and the initialization gate signal has an enable level during an initialization period, wherein each of the reference gate signal and the emission signal has the enable level during a compensation period after the initialization period in one frame, wherein the write gate signal has the enable level during the address period after the compensation period in the frame, and Wherein, each of the initialization gate signal and the emission bias signal has the enable level during an emission initialization period after the address period in the one frame.

24. The sub-pixel according to claim 2, wherein: The sub-pixel further includes: a fifth transistor configured to provide an initialization voltage to the first electrode of the first transistor in response to an initialization gate signal; a sixth transistor configured to provide a first power voltage to the first transistor in response to a transmission signal; a seventh transistor configured to connect the first electrode of the first transistor to the first electrode of the light emitting element in response to a previous emission signal; and A ninth transistor is configured to provide the first power voltage to the first transistor in response to the reference gate signal.

25. The sub-pixel according to claim 24, in, The initialization gate signal has an enable level during the first compensation initialization period, wherein the reference gate signal has the enable level during the second compensation initialization period, wherein each of the initialization gate signal, the write gate signal, and the previous emission signal has the enable level during an addressing period after the first compensation initialization period and the second compensation initialization period in one frame, and Wherein, each of the initialization gate signal and the previous emission signal has the enable level during an emission initialization period after the address period in the one frame.

26. The sub-pixel according to claim 24, wherein: The subpixel further includes an eighth transistor configured to provide the reference voltage to the first electrode of the first transistor in response to the write gate signal.

27. The sub-pixel according to claim 26, in, The initialization gate signal has an enable level during the first compensation initialization period, wherein the reference gate signal has the enable level during the second compensation initialization period, wherein the write gate signal has the enable level during the addressing period after the first compensation initialization period and the second compensation initialization period in one frame, and Wherein, each of the initialization gate signal and the previous emission signal has the enable level during an emission initialization period after the address period in the one frame.

28. A display device, wherein: The display device comprises: A display panel including sub-pixels; and A display panel driver is configured to drive the display panel. Wherein, the sub-pixel comprises: A first transistor configured to generate a driving current; a first capacitor including a first electrode connected to the first electrode of the first transistor, and a second electrode; a second capacitor including a first electrode connected to the control electrode of the first transistor and a second electrode connected to the second electrode of the first capacitor; a second transistor configured to provide a data voltage to the second electrode of the first capacitor in response to a write gate signal; and The light emitting element is configured to receive the driving current and emit light.

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