Display panel, driving method thereof and display device

Abstract

The invention discloses a display panel, a driving method thereof and a display device. The display panel includes: a driving circuit; the driving circuit comprises multiple stages of shift register units; at least part of the shift register units in the multiple stages of shift register units are first-class shift register units; the first type shift register unit comprises an input module, an output module, a signal input end, a first clock end, a first level end, a signal output end, a reduction module and a reduction signal end; the first type of shift register units comprise at least one stage of first shift register unit and at least one stage of second shift register unit; the reduction signal of the second shift register unit at least comprises a first effective pulse, and the reduction signal of the first shift register unit is an invalid level at least in the time period of the first effective pulse; the starting time of the first effective pulse is before the starting time of the starting effective pulse of the first clock signal of the at least one first shift register unit. The scheme can improve the output noise problem.

Description

Technical Field

[0001] The embodiments of the present invention relate to display technology, and more particularly to a display panel and a driving method thereof, and a display device. Background Art

[0002] Display panels are widely used in electronic devices such as smart phones, tablet personal computers, and car navigation systems, and have become indispensable equipment for people's lives and work. With the development of display technology, people have higher and higher requirements for the display quality of display panels.

[0003] The display panel includes a driving circuit and a plurality of pixels arranged in an array. The gate driving signal provided by the driving circuit can scan each pixel row by row, so that the data signal can be written into each pixel one by one to control the display luminescence brightness of each pixel, thereby controlling the display panel to present the corresponding display picture.

[0004] However, under the influence of the structure of the driving circuit and the signal received by the driving circuit, noise exists at the signal output end of the driving circuit, thereby affecting the accuracy of the gate driving signal output by the driving circuit, and further affecting the display effect of the display panel. Summary of the invention

[0005] The present invention provides a display panel and a driving method thereof and a display device, so as to improve the noise problem of the signal output end of each level of shift register unit in a driving circuit and improve the accuracy of the gate driving signal output by each level of shift register unit.

[0006] In a first aspect, the present invention provides a display panel, the display panel comprising: a driving circuit; the driving circuit comprising a multi-stage shift register unit; the shift register unit at least comprising an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal and a signal output terminal;

[0007] In the shift register unit, the input module is electrically connected to the signal input terminal and the output module respectively, and the input module and the output module are electrically connected to a first node; the output module is electrically connected to the first node, the first clock terminal and the signal output terminal respectively; the first clock terminal receives a first clock signal; the first level terminal receives a first level signal;

[0008] At least part of the shift register units are first-type shift register units; the first-type shift register units further include a restoration module and a restoration signal terminal; in the first-type shift register units, the restoration module is electrically connected to the restoration signal terminal and the first level terminal respectively, and the restoration module is also electrically connected to the first node and / or the signal output terminal; the restoration signal terminal receives a restoration signal;

[0009] The signal output end of the shift register unit of the i-th stage is electrically connected to the signal input end of the shift register unit of the i+N-th stage; i and N are both positive integers;

[0010] The multiple levels of the first type of shift register units include at least one level of first shift register unit and at least one level of second shift register unit;

[0011] The restoration signal of the second shift register unit includes at least a first valid pulse, and at least in the time period of the first valid pulse of the restoration signal of the second shift register unit, the restoration signal of the first shift register unit is at an invalid level; the starting time of the first valid pulse is before the starting time of the starting valid pulse of the first clock signal of at least one level of the first shift register unit.

[0012] In a second aspect, the present invention further provides a display panel, the display panel comprising: a driving circuit, a first restoration signal line and a second restoration signal line;

[0013] The driving circuit comprises a multi-stage shift register unit, wherein the shift register unit comprises an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal and a signal output terminal;

[0014] In the shift register unit, the input module is electrically connected to the signal input terminal and the output module respectively, and the input module and the output module are electrically connected to a first node; the output module is electrically connected to the first node, the first clock terminal and the signal output terminal respectively; the first level terminal receives a first level signal; the first clock terminal receives a first clock signal;

[0015] At least part of the shift register units are first-type shift register units; the first-type shift register units further include a restoration module and a restoration signal terminal; in the first-type shift register units, the restoration module is electrically connected to the restoration signal terminal and the first level terminal respectively, and the restoration module is also electrically connected to the first node and / or the signal output terminal; the restoration signal terminal receives a restoration signal;

[0016] The multi-stage first-type shift register unit includes at least one stage of first shift register unit and at least one stage of second shift register unit, the restoration signal end of the first shift register unit is electrically connected to the first restoration signal line, and the restoration signal end of the second shift register unit is electrically connected to the second restoration signal line;

[0017] Wherein, the first restoration signal line and the second restoration signal line are insulated from each other.

[0018] In a third aspect, the present invention further provides a method for driving a display panel, the display panel comprising: a driving circuit; the driving circuit comprising a multi-stage shift register unit; the driving circuit receiving a start control signal, a restoration signal and a clock signal; the working process of the display panel comprises a frame period;

[0019] The driving method comprises: within the frame period, the start control signal comprises a start control pulse, the restoration signal comprises a first valid pulse, and the clock signal comprises a start valid pulse;

[0020] The first effective pulse is the same as the start control pulse;

[0021] The starting time of the start effective pulse is later than the starting time of the start control pulse.

[0022] In a fourth aspect, the present invention further provides a display device, which includes: the above-mentioned display panel.

[0023] The technical solution of the present invention is that in a first type of shift register unit, an input module and a restoration module are used to jointly control the signal of the first node, so that the signal of the first node is combined with the first clock signal to jointly control the gate drive signal provided by the output module to the signal output end, and at the same time, the output module and the restoration module are used to jointly control the gate drive signal output by the signal output end to ensure that the signal output end can accurately output the gate drive signal; in addition, the multi-stage first type shift register unit includes at least one first shift register unit and at least one second shift register unit, by keeping the restoration signal of the restoration signal end of the first shift register unit at an invalid level, and the restoration signal of the restoration signal end of the second shift register unit includes at least a first valid pulse, and the starting time of the first valid pulse is set to be located before the starting time of the starting valid pulse of the first clock signal of at least one first shift register unit, so that the restoration signal in the first shift register unit The module can, under the control of the invalid level of the restoration signal, not affect the signal of the first node and the signal output end in the first shift register unit, ensuring that when the first shift register unit receives the valid pulse of the first clock signal, it can control its signal output end to accurately output the valid level of the gate drive signal; before the first shift register unit receives the starting valid pulse of the first clock signal, the restoration module in the second shift register unit can, under the control of the first valid pulse of the restoration signal received by it and the first level signal of the first level end, pull down the signal of the first node and the signal output end, so as to improve the interference of the first clock signal jump received by the first shift register unit on the signal of the first node in the second shift register unit and the gate drive signal outputted by the signal output end, reduce the noise of the signal output end of the second shift register unit, and improve the accuracy of the gate drive signal outputted by the second shift register unit, thereby facilitating the improvement of the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of a display panel in the related art;

[0025] Figure 2 It is a driving timing diagram of a shift register unit in the related art;

[0026] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0027] Figure 4 is a structural schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0028] Figure 5 is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0029] Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0030] Figure 7 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0031] Figure 8 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0032] Fig. 9 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0033] Fig.10 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0034] Fig.11 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0035] Fig.12 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0036] Fig.13 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0037] Fig.14 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0038] Fig.15 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0039] Fig.16is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0040] Fig.17 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0041] Fig.18 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0042] Fig.19 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0043] Fig. 20 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0044] Fig.21 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0045] Fig. 22 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0046] Fig.23 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0047] Fig.24 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0048] Fig.25 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention;

[0049] Fig.26 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0050] Fig. 27 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0051] Fig.28 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0052] Fig.29 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0053] Fig.30 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0054] Fig.31 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0055] Fig.32 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0056] Fig.33 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0057] Fig.34 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0058] Fig.35 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0059] Fig.36 is a driving timing diagram of a shift register unit provided by an embodiment of the present invention;

[0060] Fig.37 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0061] Fig.38 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0062] Fig.39 is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0063] Fig.40 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0064] Fig.41 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0065] Fig.42 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0066] Fig.43 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0067] Fig.44 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0068] Fig.45 is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0069] Fig.46 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0070] Fig.47It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings. In the case where the technical features do not conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0072] It should be noted that the “electrical connection” mentioned in the present application can be understood as direct electrical connection or indirect electrical connection. For example, device A is electrically connected to device B, which can be understood as device A is directly electrically connected to device B, or device A is electrically connected to device B via device C.

[0073] Figure 1 is a schematic diagram of the structure of a display panel of the related technology, such as Figure 1 As shown, in the related art, the display panel 001 may include a display area AA′ and a non-display area NA′ at least partially surrounding the display area AA′, a plurality of pixels 020 arranged in an array may be provided in the display area AA′, and a driving circuit 010 is provided in the non-display area NA′. The driving circuit 010 may include a cascade of multi-stage shift register units ASG′ (ASGi′, ASGi+1′, ASGi+2′, ASGi+3′, ASGi+4′, ASGi+5′, ASGi+6′, ASGi+7′), the shift register unit ASG′ at least includes a signal input terminal IN′, a first clock terminal CLK′, a first level terminal VGL′ and a signal output terminal OUT′, and the signal output terminals of each shift register unit ASG′ are respectively electrically connected to each row of pixels 020 to provide gate driving signals for each row of pixels 020. In the same shift register unit ASG′, the input signal Vin′ of the signal input terminal IN′, the first clock signal CK′ of the first clock terminal CLK′, and the first level signal Vgl′ of the first level terminal VGL′ can control the gate drive signal Gout′ output by the signal output terminal OUT′. For example, after the input signal Vin′ becomes a valid level, when the first clock signal CK′ becomes a valid level for the first time, the signal output terminal OUT′ can be controlled to output the valid level of the gate drive signal Gout′; otherwise, the signal output terminal OUT′ outputs the invalid level of the gate drive signal Gout′.

[0074] Among them, the gate drive signal Goutx' output by the x-th shift register unit ASGx' can be used as the input signal Viny' of the y-th shift register unit ASGy', that is, the signal output terminal OUT' of the x-th shift register unit ASGx' is electrically connected to the signal input terminal IN' of the y-th shift register unit ASGy', for example, the signal output terminal OUT' of the i-th shift register unit ASGi' is electrically connected to the signal input terminal IN' of the i+1-th shift register unit ASGi+1', and the i+1-th shift register unit ASGi+1' is electrically connected to the signal output terminal OUT' of the i-th shift register unit ASGi'. The signal output terminal OUT' of the first shift register unit ASGi+1' is electrically connected to the signal input terminal IN' of the i+2-th shift register unit ASGi+2', and so on, the signal output terminal of the previous shift register unit is electrically connected to the signal input terminal of the next shift register unit, so that the next shift register unit can control the gate drive signal Gout' output by the next shift register unit according to the gate drive signal Gout' output by the previous shift register unit, and the first clock signal CK' and the first level signal Vgl' received by it. The signal input terminal IN of the first shift register unit ASG1' can receive the start control signal, so that the first shift register unit ASG1' can output the corresponding gate drive signal Gout1' under the control of the start control signal STV'.

[0075] Before each shift register unit in the control driving circuit outputs the effective level of the gate driving signal Gout′, a start control pulse of the start control signal STV′ can be provided to the signal input terminal IN′ of the first-stage shift register unit ASG1′ to charge the node in the first-stage shift register unit ASG1′; when the signal of the node in the first-stage shift register unit ASG1′ becomes a valid level, the effective level of the first clock signal CK′ can be provided to the first-stage shift register unit ASG1′, so that the first-stage shift register unit ASG1′ can output the effective level of the gate driving signal Gout1′.

[0076] However, when the first clock signal CK′ of the first-stage shift register unit ASG1′ first jumps to the valid level, the corresponding signals have not been written into the nodes of the other stages of the shift register units ASG′, and because there is a parasitic capacitance between the clock signal line transmitting the first clock signal CK′ and the other stages of the shift register units ASG′, at least part of the shift register units ASG′ are affected by the jump of the first clock signal CK′ received by the first-stage shift register unit ASG1′, and output the gate drive signal Gout′ with the same jump trend as the first clock signal CK′ (e.g. Figure 2As shown), that is, the gate drive signal Gout′ includes noise pulses, as shown by the pulses in the dotted box in the figure, and the noise interference is particularly large at the rising and falling edges of the first clock signal CK′, so that the partial shift register unit ASG′ cannot accurately output the gate drive signal, thereby failing to accurately scan each pixel 020 in the display area AA′ row by row, thereby affecting the display effect of the display panel 001.

[0077] To solve the above technical problems, an embodiment of the present invention provides a display panel, which includes: a driving circuit; the driving circuit includes a multi-stage shift register unit; the shift register unit at least includes an input module, an output module, a signal input end, a first clock end, a first level end and a signal output end; in the shift register unit, the input module is electrically connected to the signal input end and the output module, respectively, and the input module and the output module are electrically connected to the first node; the output module is electrically connected to the first node, the first clock end and the signal output end, respectively; the first level end receives a first level signal; and the first clock end receives a first clock signal.

[0078] At least some of the shift register units are first-type shift register units; the first-type shift register units also include a restoration module and a restoration signal terminal; in the first-type shift register units, the restoration module is electrically connected to the restoration signal terminal, the first node and the signal output terminal respectively; the restoration signal terminal receives the restoration signal; the signal output terminal of the i-th shift register unit is electrically connected to the signal input terminal of the i+N-th shift register unit; i and N are both positive integers; the multi-stage first-type shift register units include at least one first shift register unit and at least one second shift register unit; the restoration signal of the first shift register unit is an invalid level; the restoration signal of the second shift register unit includes at least a first valid pulse; the starting time of the first valid pulse is before the starting time of the starting valid pulse of the first clock signal of at least one first shift register unit.

[0079] By adopting the above technical scheme, in the first type of shift register unit, the signal of the first node is controlled by the input module and the restoration module, so that the signal of the first node is combined with the first clock signal to jointly control the gate drive signal provided by the output module to the signal output end, and at the same time, the gate drive signal output by the signal output end is controlled by the output module and the restoration module to ensure that the signal output end can accurately output the gate drive signal; in addition, the multi-stage first type shift register unit includes at least one first shift register unit and at least one second shift register unit, by making the restoration signal of the restoration signal end of the first shift register unit remain at an invalid level, and the restoration signal of the restoration signal end of the second shift register unit includes at least a first valid pulse, and the starting time of the first valid pulse is set to be located before the starting time of the starting valid pulse of the first clock signal of at least one first shift register unit, so that the restoration signal in the first shift register unit The module can, under the control of the invalid level of the restoration signal, not affect the signal of the first node and the signal output end in the first shift register unit, ensuring that when the first shift register unit receives the valid pulse of the first clock signal, it can control its signal output end to accurately output the valid level of the gate drive signal; before the first shift register unit receives the starting valid pulse of the first clock signal, the restoration module in the second shift register unit can, under the control of the first valid pulse of the restoration signal received by it and the first level signal of the first level end, pull down the signal of the first node and the signal output end, so as to improve the interference of the first clock signal jump received by the first shift register unit on the signal of the first node in the second shift register unit and the gate drive signal outputted by the signal output end, reduce the noise of the signal output end of the second shift register unit, and improve the accuracy of the gate drive signal outputted by the second shift register unit, thereby facilitating the improvement of the display effect of the display panel.

[0080] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0081] The display panel provided by the embodiment of the present invention includes, but is not limited to, a liquid crystal display panel (LCD), an organic light emitting display panel (OLED), or a micro light emitting diode display panel (Micro LED).

[0082] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 4 is a schematic diagram of a structure of a shift register unit provided by an embodiment of the present invention, and is combined with reference to Figure 3 and Figure 4The display panel 100 includes a driving circuit 10, and the driving circuit 10 includes a plurality of cascaded shift register units ASG; the shift register unit ASG at least includes an input module 110, an output module 120, a signal input terminal IN, a first clock terminal CLK, a first level terminal VGL and a signal output terminal OUT; in the shift register unit ASG, the input module 110 is electrically connected to the signal input terminal IN and the output module 120, respectively, and the input module 110 and the output module 120 are electrically connected to the first node PU; the output module 120 is electrically connected to the first node PU, the first clock terminal CLK and the signal output terminal OUT, respectively; wherein the first clock terminal CLK receives a first clock signal CK, and the first level terminal VGL receives a first level signal Vgl.

[0083] In an exemplary embodiment, the input module 110 can control the signal of the first node PU according to the input signal Vin of the signal input terminal IN. For example, when the input signal Vin of the signal input terminal IN is at a valid level, the input module 110 can control the signal of the first node PU to be at a valid level; when the input signal Vin of the signal input terminal IN is at an invalid level, the input module 110 no longer inputs a signal to the first node PU, that is, the potential of the first node PU at this time is not affected by the input module 110. The output module 120 can control the conduction path between the first clock terminal CLK and the signal output terminal OUT under the control of the signal of the first node PU, so as to control the time when the signal output terminal OUT outputs the first clock signal CK as the gate drive signal Gout. For example, when the signal of the first node PU is at a valid level, the output module 120 can be in a conductive state, and a conductive path is formed between the first clock terminal CLK and the signal output terminal OUT, so that the first clock signal CK of the first clock terminal CLK can be transmitted to the signal output terminal OUT, so that the gate drive signal Gout output by the signal output terminal OUT is consistent with the first clock signal CLK; conversely, when the signal of the first node PU is at an invalid level, the output module 120 is in a closed state, so that the first clock terminal CLK and the signal output terminal OUT cannot be conductive, and the first clock signal CK cannot be transmitted to the signal output terminal OUT.

[0084] Continue to refer Figure 3 and Figure 4, at least part of the shift register units ASG are first-type shift register units ASGa; the first-type shift register unit ASGa may further include a restoration module 130 and a restoration signal terminal REST; in the first-type shift register unit ASGa, the restoration module 130 is electrically connected to the restoration signal terminal REST and the first level terminal VGL, respectively, and the restoration module 130 may also be electrically connected to the first node PU and / or the signal output terminal OUT; the restoration signal terminal REST receives the restoration signal Vrest; the restoration module 130 can control the first node PU according to the restoration signal Vrest and the first level signal Vgl. The restoration module 130 can transmit the first level signal Vgl to the first node PU and the signal output terminal OUT, and the signal of the first node PU and the gate drive signal Gout of the signal output terminal OUT can be consistent with the first level signal Vgl; when the restoration signal Vrest is an invalid level, the restoration module 130 cannot transmit the first level signal Vgl to the first node PU, that is, the potential of the first node PU at this time is not affected by the restoration module 130. In this way, in the first type shift register unit ASGa, the restoration module 130 and the input module 110 jointly control the signal of the first node PU to ensure that the signal of the first node PU can accurately control the output module 120 to be turned on or off. At the same time, the output module 120 and the restoration module 130 are used to jointly control the gate drive signal Gout outputted from the signal output terminal OUT, which is conducive to improving the output accuracy of the gate drive signal Gout.

[0085] Among them, in the first type of shift register unit ASGa in the embodiment of the present invention, the restoration module 130 can be electrically connected only to the first node PU, or the restoration module 130 can be electrically connected only to the signal output terminal OUT, or the restoration module 130 can be electrically connected to the first node PU and the signal output terminal OUT at the same time. Under the premise that the accuracy of the gate drive signal Gout output by the shift register unit can be improved, the embodiment of the present invention does not make specific limitations on this. For the convenience of description, under the premise that there are no special limitations, the embodiments of the present invention take the case where the restoration module 130 is electrically connected to the first node PU and the signal output terminal OUT at the same time as an example to exemplarily illustrate the technical solution of the embodiments of the present invention.

[0086] It can be understood that at least some of the shift register units ASG are first-type shift register units ASGa, that is, some of the shift register units ASG are first-type shift register units ASGa or all of the shift register units ASG are first-type shift register units ASGa. The specific design can be based on actual needs, and the embodiment of the present invention does not make specific limitations on this. For the convenience of description, without special limitations, the embodiment of the present invention takes all the shift register units ASG as the first-type shift register units ASGa as an example to illustrate the technical solution of the embodiment of the present invention.

[0087] It can also be understood that the first clock signal CK can alternate between a valid level and an invalid level, and one of the valid level and the invalid level can be a high level and the other can be a low level, which can be specifically designed according to actual needs; the first level signal Vgl can be a continuous high level or a low level. When the first level signal Vgl is transmitted to the first node PU, the signal of the first node PU can control the output module 120 to be in a closed state. Therefore, the first level signal Vgl is an invalid level for controlling the output module 120 to be in a closed state, which can be designed according to the specific structure of the output module 120; the restoration signal Vrest can include a valid level and / or an invalid level. The effective level of the restoration signal Vrest can be a high level and the invalid level can be a low level, or the effective level of the restoration signal Vrest can be a low level and the invalid level can be a high level. Under the premise that the effective level of the restoration signal Vrest can control the restoration module 130 to be in a conductive state and the invalid level can control the restoration module 130 to be in a closed state, the embodiment of the present invention does not make specific limitations on this. When the transistor in the shift register unit is an N-type transistor, the effective level is a high level, the high level controls the N-type transistor to be turned on, the invalid level is a low level, the low level controls the N-type transistor to be turned off (or cut off), when the transistor in the shift register unit is a P-type transistor, the effective level is a low level, the low level controls the P-type transistor to be turned on, the invalid level is a high level, the high level controls the P-type transistor to be turned off (or cut off). For the convenience of description, without special limitations, the embodiments of the present invention take the transistor in the shift register unit as an N-type transistor, the effective level is a high level, and the invalid level is a low level as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0088] Continue to refer Figure 3, the signal output terminal OUT of the i-th shift register unit ASGi is electrically connected to the signal input terminal IN of the i+N-th shift register unit ASGi+1, so that the gate drive signal Gout output by the signal output terminal OUT of the i-th shift register unit ASGi can be used as the input signal Vin received by the signal input terminal IN of the i+N-th shift register unit ASGi+N, so that the i+N-th shift register unit ASGi+N can output the corresponding gate drive signal Gouti+N under the control of the gate drive signal Gouti output by the i-th shift register unit ASGi, ensuring that the effective level of the gate drive signal Gout output by each level of the shift register unit ASG can be shifted in sequence. Wherein, i and N are both positive integers, that is, i can be any integer such as 1, 2, 3, ..., and the value of N can be any integer among 1, 2, 3, ...

[0089] For example, Figure 5 is a driving timing diagram of a display panel provided by an embodiment of the present invention, combined with reference Figure 3 and Figure 5 When N is equal to 1, the signal output terminal OUT of the i-th shift register unit ASGi can be electrically connected to the signal input terminal IN of the i+1-th shift register unit ASGi+1, and the signal output terminal OUT of the i+1-th shift register unit ASGi+1 can be electrically connected to the signal input terminal IN of the i+2-th shift register unit ASGi+2, and so on. The signal output terminal OUT of the previous shift register unit ASG can be electrically connected to the signal input terminal of the next shift register unit ASG, so that the gate of the previous shift register unit ASG output The driving signal Gout can be combined with the first clock signal CK, the restoration signal Vrest and the first level signal Vgl received by the next-stage shift register unit ASG to jointly control the gate driving signal Gout output by the next-stage shift register unit ASG, thereby ensuring that the effective level of the gate driving signal Gout (Gouti, Gouti+1, Gouti+2, Gouti+3, Gouti+4, Gouti+5, Gouti+6, Gouti+7) output by each stage of the shift register unit ASG can be shifted sequentially.

[0090] It should be noted that the above is only an exemplary description of the cascade mode of the shift register units at each level when N is equal to 1. In the embodiment of the present invention, the cascade mode of the shift register units is not limited to this. The value of N can be any positive integer and can be designed according to actual needs. The embodiment of the present invention does not make any specific limitation on this.

[0091] Exemplary, reference Figure 6 and Figure 7As shown, when N is equal to 4, the signal output terminal OUT of the i-th shift register unit ASGi can be electrically connected to the signal input terminal of the i+4-th shift register unit ASGi+4, the signal output terminal OUT of the i+1-th shift register unit ASGi+1 can be electrically connected to the signal input terminal of the i+5-th shift register unit ASGi+5, the signal output terminal OUT of the i+2-th shift register unit ASGi+2 can be electrically connected to the signal input terminal of the i+6-th shift register unit ASGi+6, the signal output terminal OUT of the i+3-th shift register unit ASGi+3 can be electrically connected to the signal input terminal of the i+7-th shift register unit ASGi+7 The signal input end is electrically connected; in this way, the gate drive signal Gouti output by the i-th shift register unit ASGi is combined with the first clock signal CK and the first level signal Vgl received by the i+4-th shift register unit ASGi+4 to control the i+4-th shift register unit ASGi+4 to output the gate drive signal Gouti+4, so as to ensure that the effective level starting time of the gate drive signal Gout (Gouti, Gouti+1, Gouti+2, Gouti+3, Gouti+4, Gouti+5, Gouti+6, Gouti+7) output by each level of shift register unit can be shifted in sequence.

[0092] For the convenience of description, without any special limitation, the embodiments of the present invention all take N equal to 4 as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0093] The signal output terminal OUT of the shift register unit ASGi can be understood as the gate drive signal output terminal, and the gate drive signal output terminal OUT is electrically connected to the gate signal line 31 and the signal input terminal IN of the shift register unit ASGi+N, respectively. Alternatively, the signal output terminal OUT of the shift register unit ASGi can be understood as the cascade signal output terminal OUT, that is, the shift register unit ASGi includes the cascade signal output terminal OUT and the gate drive signal output terminal, the cascade signal output terminal OUT of the shift register unit ASGi is electrically connected to the signal input terminal IN of the shift register unit ASGi+N, and the gate drive signal output terminal of the shift register unit ASGi is electrically connected to the gate signal line 31.

[0094] In an optional embodiment, in conjunction with reference Figure 2 , Figure 6 and Figure 7The multi-stage first-type shift register unit ASGa includes at least one first shift register unit ASG01 and at least one second shift register unit ASG02; the restoration signal Vrest2 of the second shift register unit ASG02 includes at least a first valid pulse, and at least in the period of the first valid pulse of the restoration signal Vrest2 of the second shift register unit ASG02, the restoration signal Vrest1 of the first shift register unit ASG01 is an invalid level; the starting time T1 of the first valid pulse is located before the starting time T2 of the starting valid pulse of the first clock signal CK of at least one first shift register unit ASG01.

[0095] During the operation of the display panel, the display screen will be refreshed at a certain refresh frequency. The time from the start time of the previous screen refresh to the start time of the next screen refresh is the time required for the display panel to display a frame of the screen, that is, the frame period. For example, within the frame period, the drive circuit of the display panel sequentially provides gate drive signals to each gate signal line, and cooperates with the data signal line to write data signals to the pixels row by row. Within the frame period, the first clock signal can include multiple valid pulses, that is, the first clock signal includes multiple valid level times, and the starting valid pulse of the first clock signal is the first valid level time of the first clock signal within the frame period. The multiple valid pulses of the first clock signal can be set periodically.

[0096] It can also be understood that the multi-stage first-type shift register unit ASGa includes at least one stage of first shift register unit ASG01, that is, the multi-stage first-type shift register unit ASGa may include one or more stages of first shift register unit ASG01; similarly, the multi-stage first-type shift register unit ASGa also includes at least one stage of second shift register unit ASG02, that is, the plurality of first-type shift register units ASGa may include one or more stages of second shift register unit ASG02. ​​In an exemplary embodiment, as Figure 3 As shown, the i-th shift register unit ASGi may be the first shift register unit ASG01, and the i+1-th shift register unit ASGi+1 to the i+7-th shift register unit are all second shift register units ASG02. ​​In another exemplary embodiment, as Figure 6 As shown, the i-th shift register unit ASGi to the i+3-th shift register unit ASGi+3 may be the first shift register unit ASG01, and the i+4-th shift register unit ASGi+4 to the i+7-th shift register unit may be the second shift register unit ASG02.

[0097] For example, Figure 6 As an example, the display panel shown in FIG. Figure 2 , Figure 6 and Figure 7Since the signal output terminal Gout of the i-th shift register unit ASGi is electrically connected to the signal input terminal IN of the i+4-th shift register unit ASGi+4, when the signal of the first node PU is at a valid level and the first clock signal CK1 is a valid pulse in the i-th shift register unit ASGi, the signal output terminal OUT of the i-th shift register unit ASGi can output the valid level of the gate drive signal Gouti; when the i+4-th shift register unit ASGi+4 receives the valid level of the gate drive signal Gouti output by the i-th shift register unit ASGi, its input module 110 can be controlled to charge its first node PU, and the first clock signal CK5 received by the i+4-th shift register unit ASGi+4 becomes a valid pulse, so that the signal output terminal OUT of the i+4-th shift register unit ASGi+4 outputs the valid level of the gate drive signal Gouti+4.

[0098] Referring to the structural schematic diagram of each shift register unit, the shift register unit may further include a pull-down module 140 and a pull-down control module 150. The pull-down module 140 may control the signal of the first node PU according to the signal of the second node PD and the first level signal Vgl of the first level end VGL. The pull-down control module 150 may control the signal of the second node PD according to the signal of the first node PU and the first level signal Vgl of the first level end VGL. The first node PU and the second node PD are mutually constrained. If a restoration module is not provided in the first-class shift register unit ASGa, before the first clock signal CK1 of the i-th-stage shift register unit ASGi becomes a valid pulse for the first time, the second node PD of each level of the first-class shift register unit ASG is not at a valid level; when the first clock signal CK1 of the i-th-stage shift register unit ASGi becomes a valid pulse for the first time, the first node PU of each level of the first-class shift register unit ASG is disturbed by the starting valid pulse of the first clock signal CK1 and is not at an invalid level; before the shift register unit normally outputs the gate drive signal, the starting valid pulse of the first clock signal CK1 that enters is likely to bring about a larger noise output, causing a reliability risk of the gate drive signal output by the drive circuit.

[0099] It can be understood that the i+1th level shift register unit ASGi+1, the i+2th level shift register unit ASGi+2 and the i+3th level shift register unit ASGi+3 have a similar working process to the i-level shift register unit ASGi, and the i+5th level shift register unit ASGi+5, the i+6th level shift register unit ASGi+6 and the i+7th level shift register unit ASGi+7 have similar problems to the i+4th level shift register unit ASGi+4. The similarities can be found in the above description and will not be repeated here.

[0100] Continue to refer Figure 2 , Figure 6 and Figure 7 In the embodiment of the present invention, a restoration module 130 and a restoration signal terminal REST are further provided in the first type shift register unit ASGa. The restoration module 130 can control the signal of the first node PU under the control of the restoration signal Vrest of the restoration signal terminal REST and the first level signal Vgl of the first level terminal VGL.

[0101] For the first shift register unit ASG01 in the first type of shift register unit ASGa, for example, the i-th shift register unit ASGi, the i+1-th shift register unit ASGi+1, the i+2-th shift register unit ASGi+2, and the i+3-th shift register unit ASGi+3, the restoration signal Vrest1 of the restoration signal terminal REST is an invalid level, and the restoration signal terminal REST controls the restoration module 130 to be in a closed state, and the restoration module 130 cannot transmit the first level signal Vgl of the first level terminal VGL to the first node PU and / or the signal output terminal OUT, so that the signal of the first node PU can be kept consistent with the signal provided by the input module 110. The output module 120 of the first shift register unit ASG01 can be turned on under the control of the signal provided to the first node PU by its input module 110, and the first clock signal CK received by its first clock terminal CLK is provided to the signal output terminal OUT, so that the gate drive signal Gout output by the signal output terminal OUT can be consistent with the first clock signal CK, that is, when the first clock signal CK of the first clock terminal CLK is a valid pulse, the signal output terminal OUT can output the valid level of the gate drive signal Gout, and when the first clock signal CK of the first clock terminal CLK is an invalid pulse, the signal output terminal OUT can output the invalid level of the gate drive signal Gout.

[0102] In the case where the restoration module 130 of the first shift register unit ASG01 is electrically connected to the first node PU, if the restoration signal Vrest1 received by the first shift register unit ASG01 contains a valid pulse, the input module 110 of the first shift register unit ASG01 provides a valid level to the first node PU to charge the first node PU. At the same time, the restoration module 130 of the first shift register unit ASG01 provides an invalid level (the first level signal Vgl of the first level end VGL) to the first node PU under the control of the valid pulse to discharge the first node PU, causing the first shift register unit ASG01 to fail to operate normally.

[0103] In the case where the restoration module 130 of the first shift register unit ASG01 is electrically connected to the signal output terminal OUT, if the restoration signal Vrest1 received by the first shift register unit ASG contains a valid pulse, the output module 120 of the first shift register unit ASG01 transmits the first clock signal CK of the first clock terminal CLK to the signal output terminal OUT, and the restoration module 130 of the first shift register unit ASG01 provides an invalid level (the first level signal Vgl of the first level terminal VGL) to the signal output terminal OUT under the control of the valid pulse. When the signal output terminal OUT simultaneously receives the valid level of the first clock signal CK and the first level signal Vgl, the signal output terminal OUT cannot output the signal normally.

[0104] For the second shift register unit ASG02 in the first type of shift register unit ASGa, for example, the i+4th shift register unit ASGi+4, the i+5th shift register unit ASGi+5, the i+6th shift register unit ASGi+6, and the i+7th shift register unit ASGi+7, the restoration signal Vrest2 of the restoration signal terminal REST includes a first valid pulse, and the starting time T1 of the first valid pulse is located before the starting valid pulse of the first clock signal CK received by at least one first shift register unit ASG01 , for example, before the start valid pulse of any one of the first clock signal CK1 received by the i-th shift register unit ASGi, the first clock signal CK2 received by the i+1-th shift register unit ASGi+1, the first clock signal CK3 received by the i+2-th shift register unit ASGi+2, and the first clock signal CK4 received by the i+3-th shift register unit ASGi+3, so that before the first clock signal CK received by the first shift register unit ASG01 jumps to the valid level for the first time, the second shift register unit ASG02 The first valid pulse of the restoration signal Vrest2 received by the restoration signal terminal REST can control the restoration module 130 to be turned on, so that the restoration module 130 can provide the first level signal Vgl of the first level terminal VGL to the first node PU and / or the signal output terminal OUT, so that the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT can be consistent with the first level signal Vgl, ensuring that the signal of the first node PU can accurately control the output module 120 to be in a closed state, and the gate drive signal OUT output by the signal output terminal OUT can be maintained at an invalid level, so that the situation where the first node PU of the second shift register unit ASG02 is not at an invalid level due to the influence of the starting valid pulse of the first clock signal CK of the first shift register unit ASG01 will no longer occur, and / or, the signal output terminal OUT outputs the first level signal Vgl, so that the situation where there is output noise at the signal output terminal OUT is improved, and the accuracy and reliability of the gate drive signal Gout output by the signal output terminal OUT of each second shift register unit ASG02 are improved.

[0105] The first effective pulse refers to the period of time during which the restoration signal of the second shift register unit ASG02 maintains the effective level, the starting time of the first effective pulse refers to the time when the restoration signal is converted from the invalid level to the effective level, and the ending time of the first effective pulse refers to the time when the restoration signal is converted from the effective level to the invalid level. The starting time and ending time of the pulse of other signals can be explained in the same way.

[0106] The first shift register unit ASG01 and the second shift register unit ASG02 both include a restoration module 130, and the restoration signal received by the restoration module 130 of the first shift register unit ASG01 is an invalid level, and the restoration signal received by the restoration module 130 of the second shift register unit ASG02 includes a first valid pulse. Although the restoration module 130 of the first shift register unit ASG01 does not provide the first level signal Vgl to the first node PU and / or the signal output terminal, it is still retained in the first shift register unit ASG01, so that the first shift register unit ASG01 can be restored. The leakage condition of the first node PU (or the signal output terminal OUT) of the bit register unit ASG01 is basically the same as the leakage condition of the first node PU (or the signal output terminal OUT) of the second shift register unit ASG02, and the internal capacitance of the first shift register unit ASG01 is basically the same as the internal capacitance of the second shift register unit ASG02, so that the working performance of the first shift register unit ASG01 is similar to or the same as the working performance of the second shift register unit ASG02, thereby improving the consistency of the gate drive signal output by the drive circuit.

[0107] On the basis of the above embodiment, the display panel 100 may further include a plurality of gate signal lines 31 and a plurality of pixels 20 arranged in an array, and the pixel 20 may include at least one switching transistor. The specific structure of the pixel 20 may be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. Among them, at least part of the pixels 20 located in the same row may be electrically connected to the same gate signal line 31, and the signal output terminals OUT of the shift register units ASG at various levels in the driving circuit 10 may be electrically connected to each gate signal line 31 respectively to control the transistors in the pixel 20 to be turned on or off, so that the corresponding display signal (such as a data signal) can be written into the pixel 20, and the display luminous brightness of the pixel 20 is controlled, so that the display panel 100 can present the corresponding display screen. In this way, by improving the accuracy and reliability of the gate drive signal output by the shift register units ASG at various levels, the writing accuracy of the display signal of each pixel 20 can be improved, which is conducive to improving the display effect of the display panel 100.

[0108] It can be understood that when the switch transistor in the pixel 20 is an N-type transistor, the effective level of the gate drive signal Gout output by the signal output terminal OUT of the shift register unit ASG is a high level; and when the transistor in the pixel 20 is a P-type transistor, the effective level of the gate drive signal Gout output by the signal output terminal OUT of the shift register unit ASG is a low level. For the convenience of description, without special limitations, the embodiments of the present invention take the effective level of the gate drive signal Gout as a high level and the invalid level of the gate drive signal Gout as a low level as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0109] It should be noted that the above only illustrates the case where the restoration signal Vrest1 received by the first shift register unit ASG01 is different from the restoration signal Vref2 received by the second shift register unit ASG02. ​​On the premise of being able to realize the core invention point of the embodiment of the present invention, the restoration signal Vrest1 received by the first shift register unit ASG01 and the restoration signal Vref2 received by the second shift register unit ASG02 can be designed according to actual needs, and the embodiment of the present invention does not make any specific limitation on this.

[0110] In other optional embodiments, continue to refer to Figure 2 , Figure 6 and Figure 7 When the multi-stage first-type shift register unit includes at least one first shift register unit ASG01 and at least one second shift register unit ASG02, the display panel 100 may further include a first restoration signal line 41 and a second restoration signal line 42, the restoration signal end REST of the first shift register unit ASG01 may be electrically connected to the first restoration signal line 41, and the restoration signal end REST of the second shift register unit ASG02 may be electrically connected to the second restoration signal line 42; wherein the first restoration signal line 41 and the second restoration signal line 42 are insulated from each other.

[0111] It can be understood that the first restoration signal line 41 and the second restoration signal line 42 are insulated from each other, so that the restoration signals Vrest transmitted by the first restoration signal line 41 and the second restoration signal line 42 do not interfere with each other. The restoration signal Vrest transmitted by the first restoration signal line 41 is the same as or different from the restoration signal Vrest transmitted by the second restoration signal line 42, and can be designed according to actual needs.

[0112] As a feasible embodiment, when the display panel 100 is required to have a higher display effect, the restoration signal Vrest1 transmitted by the first restoration signal line 41 may include an invalid level, which can control the restoration module 130 in the first shift register unit ASG01 to be in a closed state, thereby preventing the first level signal Vgl of the first level end VGL from being transmitted to the first node PU and the signal output end OUT, thereby affecting the conduction time of the output module 120 in the first shift register unit ASG01 and the accuracy of the gate drive signal Gout output by the signal output end OUT, thereby ensuring that the first shift register unit ASG01 accurately outputs the gate drive signal Gout. The restoration signal Vrest2 transmitted by the second restoration signal line 42 may include a first effective pulse, which may control the restoration module 130 in the second shift register unit ASG02 to be in a conducting state before the second shift register unit ASG02 outputs the effective level of the gate drive signal Gout, so that the first level signal Vgl of the first level terminal VGL can be transmitted to the first node PU and / or the signal output terminal OUT, ensuring that the signal of the first node PU can control the output module 120 to be in a closed state, and the gate drive signal Gout output by the control signal output terminal OUT is consistent with the first level signal Vgl, so as to prevent the accuracy of the gate drive signal Gout output by the signal output terminal OUT of the second shift register unit ASG02 from being affected by the uncontrollable state of the output module 120 and the first jump of the first clock signal CK received by the first shift register unit ASG01. In this way, by making the first restoration signal line 41 and the second restoration signal line 42 transmit different restoration signals Vrest, the accuracy of the gate drive signal Gout output by each level of the shift register unit ASG can be improved.

[0113] As another possible embodiment, refer to Figure 2 , Figure 6 and Figure 8, the restoration signal Vrest1 transmitted by the first restoration signal line 41 and the restoration signal Vrest2 transmitted by the second restoration signal line 42 may both include a first valid pulse, and the termination time T1 of the first valid pulse may be located before the start time T2 of the start valid pulse of the first clock signal CK received by each shift register unit ASG, so that before each shift register unit ASG receives the valid pulse of the first clock signal CK, the restoration module 130 in each shift register unit ASG can be controlled to be in a conductive state through the restoration signal Vrest, so that the first level signal Vgl of the first level end VGL can be transmitted to the first node PU and / or the signal output end OUT, ensuring that the signal of the first node PU can control the output module 120 to be in a closed state, and the signal of the control signal output end OUT can be consistent with the first level signal Vgl, so as to prevent the accuracy of the gate drive signal Gout outputted by the signal output end OUT of each shift register unit ASG from being affected by the uncontrollable state of the output module 120 and the first jump of the first clock signal CK of the first shift register unit ASG01. In this way, by making the first restoration signal line 41 and the second restoration signal line 42 transmit the same restoration signal Vrest, and the restoration signal Vrest includes the first effective pulse, the accuracy of the gate driving signal Gout output by each stage of the shift register unit ASG can be improved.

[0114] As other possible embodiments, refer to Figure 2 , Figure 6 and Fig. 9 When the display panel is in standby mode or has a lower refresh frequency, the restoration signal Vrest1 transmitted by the first restoration signal line 41 and the restoration signal Vrest2 transmitted by the second restoration signal line 42 can both be invalid levels to reduce the power consumption caused by the level conversion of the first restoration signal line 41 and the second restoration signal line 42, thereby facilitating low power consumption of the display panel 100.

[0115] It should be noted that the above description only exemplarily illustrates the restoration signal transmitted by the first restoration signal line and the second restoration signal line. On the premise that the gate drive signal output by each level of shift register unit can be ensured to have a high accuracy, the embodiment of the present invention does not specifically limit the restoration signal transmitted by the first restoration signal line and the restoration signal transmitted by the second restoration signal line.

[0116] Based on the above embodiment, optionally, Fig.10 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.10As shown, the display panel 100 may further include a first level signal line 51, and the first level end VGL of at least one first shift register unit ASG01 and the first level end VGL of at least one second shift register unit ASG02 are electrically connected to the first level signal line 51, so that the first level signal transmitted by the first level signal line 51 can be provided to the first level end VGL of each level of the first shift register unit ASG01 and the first level end VGL of each level of the second shift register unit ASG02.

[0117] Continue to refer Fig.10 , the first restoration signal line 41 can be electrically connected to the first level signal line 51, so that the restoration signal Vrest1 can be the same signal as the first level signal Vgl, that is, the restoration signal Vrest1 transmitted by the first restoration signal line 41 can be the same invalid level as the first level signal Vgl, that is, the first level signal VGL can be multiplexed as the restoration signal Vrest1 of the first shift register unit ASG01. At this time, the first restoration signal line 41 and the first level signal line 51 can be electrically connected to the same signal terminal to receive the same signal through the signal terminal, thereby facilitating the reduction of the number of signal terminals provided in the display panel 100 and simplifying the structure of the display panel 100; at the same time, because the driving chip providing the signal to the display panel 100 includes output terminals electrically connected to the signal terminals in the display panel 100 in a one-to-one correspondence, when the data of the signal terminals in the display panel 100 is reduced, the output terminals in the driving chip can also be reduced accordingly, thereby simplifying the structure of the driving chip, reducing the cost of the driving chip, and further reducing the driving cost of the display panel 100.

[0118] It should be noted that the above description is only an example of the case where the display panel includes the first restoration signal line 41, the second restoration signal line 42 and the first level signal line 51 at the same time. In the embodiment of the present invention, when the first level signal VGL is multiplexed as the restoration signal Vrest of the first shift register unit ASG, the first level signal line 51 can also be multiplexed as the first restoration signal line 42. Under the premise of being able to realize the core invention of the embodiment of the present invention, the embodiment of the present invention does not specifically limit the arrangement of the signal lines in the display panel.

[0119] In an alternative embodiment, Fig.11 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.11As shown, the display panel 100 may include a first level signal line 51 and a restoration signal line 40 that are insulated from each other; the first level end VGL of at least one first shift register unit ASG01 and the first level end VGL of at least one second shift register unit ASG02 are both electrically connected to the first level signal line 51; the restoration signal end REST of at least one first shift register unit ASG01 is electrically connected to the first level signal line 51; and the restoration signal end REST of at least one second shift register unit ASG02 is electrically connected to the restoration signal line 40.

[0120] With such arrangement, the first level end VGL of the first shift register unit ASG01, the first level end VGL of the second shift register unit ASG02, and the restoration signal end REST of the first shift register unit ASG01 can all receive the first level signal Vgl transmitted by the first level signal line 51, so that the restoration module of the first shift register unit ASG01 can be in a closed state under the control of the first level signal Vgl received by its first level end VGL and the restoration signal end REST, thereby ensuring that the first shift register unit ASG01 can accurately output the gate drive signal Gout; the restoration signal end REST of the second shift register unit ASG02 can receive the restoration signal Vrest2 transmitted by the restoration signal line 40, so that the restoration module of the second shift register unit ASG02 can be turned on or off under the control of the first level signal Vgl received by its first level end VGL and the restoration signal Vrest2 received by its restoration signal end REST, thereby improving the accuracy of the gate drive signal Gout output by the second shift register unit ASG02 while improving the output noise of the second shift register unit ASG02.

[0121] In addition, when the first level end VGL of at least one first shift register unit ASG01, the restoration signal end REST of at least one first shift register unit ASG01, and the first level end VGL of at least one second shift register unit ASG02 are all electrically connected to the first level signal line 51, there is no need to set a signal line that is separately electrically connected to the restoration signal end REST of at least one first shift register unit ASG01, which is beneficial to reducing the number of signal lines set in the display panel 100 and simplifying the structure of the display panel 100; and when the first level signal line 51 and the restoration signal line 40 are both located in the non-display area NA of the display panel 100, it is beneficial to reduce the size of the non-display area NA of the display panel 100, which is beneficial to the narrow frame of the display panel 100.

[0122] Optional, Fig.12 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.12As shown, when the shift register units ASG of each level are arranged in sequence along the first direction Y, the first level signal line 51 may include a first portion 511 and a second portion 512 both extending along the first direction Y and electrically connected to each other; the first portion 511 and the second portion 512 are arranged along the second direction X; the second direction X intersects with the first direction Y, and the second direction X is parallel to the plane where the display panel 100 is located; the restoration signal line 40 extends along the first direction Y, and the restoration signal line 40 and the first portion 511 are arranged along the second direction X; in the second direction X, the first portion 511 and the second portion 512 overlap with at least one level of the first shift register unit ASG01, and the first portion 511 and the restoration signal line 40 overlap with at least one level of the second shift register unit ASG02.

[0123] Specifically, in the second direction X, at least one level of the first shift register unit ASG01 and the first part 511 and the second part 512 of the first level signal line 51 electrically connected thereto overlap, so that the parasitic capacitance formed between the first shift register unit ASG01 and the first level signal line 51 includes the parasitic capacitance formed by the first shift register unit ASG01 and the first part 511, and the parasitic capacitance formed by the first shift register unit ASG01 and the second part 512; at the same time, in the second direction X, the first part 511 and the restoration signal line 40 overlap with at least one level of the second shift register unit ASG02, so that the second shift register unit ASG02 can simultaneously form a parasitic capacitance with the restoration signal line 40 and the first part 511. In this way, the parasitic capacitance formed by the first shift register unit ASG01 and the first level signal line 51 can be consistent with the parasitic capacitance formed by the second shift register unit ASG02 and the first level signal line 51 and the restoration signal line 40, so that the impedance of the first shift register unit ASG01 and the second shift register unit ASG02 are consistent, which is beneficial to improve the consistency of the effective level of the gate drive signal output by the first shift register unit ASG01 and the second shift register unit ASG02, and further helps to improve the display uniformity of the display panel 100.

[0124] In an optional embodiment, continue to refer to Fig.12When the first level signal line 51 includes a first part 511 and a second part 512, the restoration signal terminal REST of the first shift register unit ASG01 can be electrically connected to the second part 512, and the first level terminal VGL of the first shift register unit ASG01 and the first level terminal VGL of the second shift register unit ASG02 can both be electrically connected to the first part 511, so that the first level terminal VGL and the restoration signal terminal REST of the first shift register unit ASG01 are respectively electrically connected to different parts of the first level signal line 51, ensuring that the first shift register unit ASG01 and the second shift register unit ASG02 have a similar connection method, further improving the consistency of the gate drive signals output by the first shift register unit ASG01 and the second shift register unit ASG02.

[0125] Based on the above embodiment, optionally, continue to refer to Fig.12 , in the first direction Y, the second portion 512 overlaps the restoration signal line 40 .

[0126] Specifically, when each first-type shift register unit ASG has the same structure, by making the second part 512 overlap with the restoration signal line 40 in the first direction Y, it can be ensured that the connection method between the restoration signal terminal REST of the first shift register unit ASG01 and the second part 512 can be consistent with the connection method between the restoration signal terminal REST of the second shift register unit ASG02 and the restoration signal line 40, so that the impedance of the first shift register unit ASG01 and the second shift register unit ASG02 can be consistent, thereby improving the consistency of the gate drive signals output by the first shift register unit ASG01 and the second shift register unit ASG02.

[0127] In an implementation of the technical feature including that the second portion 512 overlaps with the restoration signal line 40 in the first direction Y, the second portion 512 and the restoration signal line 40 can be located on a side of the shift register unit (including a thin film transistor and a capacitor) away from the display area (including pixels), or the second portion 512 and the restoration signal line 40 are located in a circuit layout area of ​​the shift register unit, that is, passing through the shift register unit.

[0128] Based on the above embodiment, optionally, continue to refer to Fig.12 The first level signal line 51 further includes a connecting portion 513, which connects the first portion 511 and the second portion 512; in the second direction X, the connecting portion 513 does not overlap with each level of the shift register unit ASG.

[0129] Specifically, the connection portion 513 may extend along the second direction X, and the connection portion 513 is respectively connected to the first connection portion 511 and the first end of the first connection portion 511 and the first end of the second connection portion 512, and the first end of the first connection portion 511 and the first end of the second connection portion 512 may be located on a side of the first shift register unit ASG01 away from the second shift register unit ASG02. ​​By making the connection portion 513 not overlap with the shift register units ASG at all levels in the second direction X, it is possible to prevent the impedance of the shift register unit ASG from being inconsistent due to the connection portion 513 only overlapping with part of the shift register units ASG, thereby ensuring the consistency of the gate drive signals output by the shift register units ASG at all levels, thereby improving the display uniformity of the display panel.

[0130] It should be noted that the above is only an illustrative description of the connection relationship between the restoration signal terminal of the first shift register unit and the second shift register unit and the signal line. Under the premise that the core invention point of the embodiment of the present invention can be realized, the connection relationship between the first shift register unit and the second shift register unit and the signal line is not limited to this, and can be designed according to actual needs. For the convenience of description, under the premise that there are no special limitations, the embodiments of the present invention take the restoration signal terminal of the first shift register unit electrically connected to the first level signal line, and the restoration signal terminal of the second shift register unit electrically connected to the restoration signal line as an example to exemplarily illustrate the technical solution of the embodiments of the present invention.

[0131] Based on the above embodiment, optionally, Fig.13 is another driving timing diagram of a display panel provided by an embodiment of the present invention, and is combined with reference to Figure 2 , Fig.12 and Fig.13 , the first effective pulse overlaps with the start effective pulse of the first clock signal CK (CK1, CK2, CK3, CK4) of at least one first shift register unit ASG01, that is, the end time T3 of the first effective pulse is located after the start time of the start effective pulse of the first clock signal CK (CK1, CK2, CK3, CK4) of at least one shift register unit ASG01, and is located before the end time of the start effective pulse of the first clock signal CK (CK1, CK2, CK3, CK4) of at least one shift register unit ASG01.

[0132] Specifically, taking the termination time T3 of the first effective pulse being located after the start time of the start effective pulse of the first clock signal CK1 of the i-th shift register unit ASGi, the first clock signal CK2 of the i+1-th shift register unit ASGi+1, and the first clock signal CK3 of the i+2-th shift register unit ASGi+2 as an example, since the i-th shift register unit ASGi, the i+1-th shift register unit ASGi+1, and the i+2-th shift register unit ASGi+2 are all first shift register units ASG01, Therefore, the restoration module 130 of the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2) will continue to be in a closed state, so that when the first clock signal CK (CK1, CK2, CK3) of the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2) is at an effective level, the first effective pulse will not affect the effective level of the gate drive signal Gout (Gouti, Gouti+1, Gouti+2) output by the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2). In the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7), the restoration module 130 can continue to be in a conductive state during the time period when the restoration signal Vrest2 is the first effective pulse, so that the restoration module 130 will continue to provide the first level signal Vgl to its first node PU and the signal output terminal OUT.Thus, when the first clock signal CK (CK1, CK2, CK3) received by the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2) changes from an invalid level to a valid level, the restoration module 130 of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7) continues to provide the first level signal Vgl to its first node PU and the signal output terminal OUT, so that the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7) +4, ASGi+5, ASGi+6, ASGi+7) will not change with the jump of the first clock signal CK (CK1, CK2, CK3) received by the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2), ensuring that the signal output terminal OUT of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7) can output the gate drive signal Gout (Gouti+4, Gouti+5, The invalid level of the first clock signal CK (CK1, CK2, CK3) received by the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2) is improved by the invalid level of the first clock signal CK (CK1, CK2, CK3) received by the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2), and the rising edge (the signal change process from low level to high level) of the starting valid pulse of the first clock signal CK (CK1, CK2, CK3) received by the first shift register unit ASG01 (ASGi, ASGi+1, ASGi+2) is located in the period where the first valid pulse is located, 2, CK3) causes the rising edge of the starting valid pulse to have an output noise problem at the signal output terminal OUT of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7), thereby improving the accuracy of the gate drive signal Gout (Gouti+4, Gouti+5, Gouti+6, Gouti+7) output by the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7).

[0133] Optional, Fig.14 is another driving timing diagram of a display panel provided by an embodiment of the present invention, and is combined with reference to Figure 2 , Fig.12 and Fig.14 , the time period of the start valid pulse of the first clock signal CK of at least one first shift register unit ASG01 is located within the time period of the first valid pulse, that is, the start time T2 of the start valid pulse of the first clock signal CK of at least one first shift register unit ASG01 is located after the start time T1 of the first valid pulse, and the end time T3 of the start valid pulse of the first clock signal CK is the same as or before the end time T3 of the first valid pulse.

[0134] Exemplarily, the time period where the starting valid pulse of the first clock signal CK1 of the i-th shift register unit ASGi is located in the time period where the first valid pulse is located (T1-T3). At this time, when the starting valid pulse of the first clock signal CK1 of the i-th shift register unit ASGi jumps from the invalid level to the valid level, and from the valid level to the invalid level, because the first valid pulse can control the restoration module of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7) to be in the on state, the gate drive signal Gout (Gouti+4, Gouti+5, Gouti+6) output by the signal output terminal OUT of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7) is turned on. , Gouti+7) will not change with the jump of the starting valid pulse of the first clock signal CK1 of the i-th shift register unit ASGi, thereby improving the problem of output noise at the signal output terminal OUT of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7) caused by the rising edge and falling edge (the change process from the valid level to the invalid level) of the starting valid pulse of the first clock signal CK1 of the i-th shift register unit ASGi, thereby improving the accuracy of the gate drive signal Gout (Gouti+4, Gouti+5, Gouti+6, Gouti+7) output by the signal output terminal OUT of the second shift register unit ASG02 (ASGi+4, ASGi+5, ASGi+6, ASGi+7).

[0135] It should be noted that the above description is only an example of an example in which the time period in which the starting valid pulse of the first clock signal CK1 of the i-th shift register unit ASGi is located within the time period in which the first valid pulse is located. In the embodiment of the present invention, there may be one or more stages of the first shift register units in which the time period in which the starting valid pulse of the first clock signal is located is within the time period in which the first valid pulse is located. Under the premise that the core invention point of the embodiment of the present invention can be achieved, the embodiment of the present invention does not make any specific limitation on this.

[0136] It can be understood that the above only exemplarily illustrates the technical solution of the embodiment of the present invention by taking the i-th level shift register unit ASGi to the i+3-th level shift register unit ASGi+3 as the first shift register unit ASG01 as an example, and the specific number and distribution method of the first shift register unit ASG01 in the embodiment of the present invention can be designed according to actual needs, and the embodiment of the present invention does not make any specific limitation on this.

[0137] Optionally, the first-level first-type shift register unit to the L-th-level first-type shift register unit are first shift register units; the starting time of the first valid pulse is before the starting time of the starting valid pulse of the first clock signal received by the first-level first-type shift register unit; L is a positive integer.

[0138] For example, Fig.15 is a partial structural diagram of a display panel provided by an embodiment of the present invention, Fig.16 is another driving timing diagram of a display panel provided by an embodiment of the present invention, and is combined with reference to Fig.15 and Fig.16 When all the shift registers in the driving circuit are first-class shift registers, the first-class shift registers to the L-th-class shift registers are first shift registers, which can be understood as the first-class shift registers ASG1 to the L-th-class shift registers ASGL being first shift registers. In order to shift the effective levels of the gate drive signals Gout (Gout1, ..., GoutL) output by the first-class shift registers ASG1 to the L-th-class shift registers ASGL in sequence, the effective pulses of the first clock signals CK (CK1, ..., CKL) received by the first-class shift registers ASG1 to the L-th-class shift registers ASGL are shifted in sequence. At this time, the starting time of the starting effective pulse of the first clock signal CK1 received by the first-class shift registers ASG1 is located before the starting time of the starting effective pulse of the first clock signal CK1 received by the other shift registers ASG in each level. When the starting time T1 of the first effective pulse is before the starting time T2 of the starting effective pulse of the first clock signal CK1 received by the first-level first-type shift register unit ASG1, the starting time T1 of the first effective pulse can be before the starting time of the starting effective pulse of the first clock signal CK received by the first-type shift register unit ASG01 at each level, thereby improving the situation in which the starting effective pulse of the first clock signal CK received by each first shift register unit ASG01 jumps from an invalid level to a valid level, thereby affecting the output noise of the signal output terminal OUT of each level of the second shift register unit ASG02, which is beneficial to improve the accuracy of the gate drive signal Gout output by the second shift register unit ASG02 at each level.

[0139] It is understandable that L can be any positive integer and can be designed according to actual needs. The embodiment of the present invention does not specifically limit this. In an optional embodiment, L can be greater than or equal to N. In this case, at least the first-stage shift register unit to the N-th-stage shift register unit are the first shift register unit. Fig.15 and Fig.16As shown, when N is equal to 4, at least the first-stage shift register unit ASG1 to the fourth-stage shift register unit ASG4 are the first shift register unit ASG01, that is, the restoration signal Vrest1 received by the restoration signal end REST of the first-stage shift register unit ASG1 to the fourth-stage shift register unit ASG4 is an invalid level, so as to ensure that the shift register units of each stage in the first-stage shift register unit ASG1 to the fourth-stage shift register unit ASG4 can output the effective level of the gate drive signal Gout (Gout1, Gout2, Gout3, Gout4) in sequence; at the same time, since the starting time T1 of the first effective pulse is located at the first-stage shift register unit Before the starting time of the starting valid pulse of the first clock signal CK (CK1, CK2, CK3, CK4) received by each shift register unit in the unit ASG1 to the fourth shift register unit ASG4, therefore, it is possible to improve the influence of the first clock signal CK received by the first-stage shift register unit ASG1 to the fourth-stage shift register unit ASG4 on the output noise of the signal output terminal OUT received by the second shift register unit ASG02 (ASG5, ASG6, ASG7, ASG8, ...) of each stage, thereby helping to improve the accuracy of the gate drive signal Gout output by the shift register unit ASG of each stage.

[0140] Based on the above embodiment, optionally, continue to refer to Fig.15 and Fig.16 In the multi-stage shift register unit ASG, every 2*N-stage shift register unit ASG is a shift register unit group. For example, when N is equal to 4, the first-stage shift register unit ASG1 to the eighth-stage shift register unit ASG8 are a shift register unit group. The display panel also includes 2*N clock signal lines 60. For example, the display panel includes a first clock signal line 61, a second clock signal line 62, a third clock signal line 63, a fourth clock signal line 64, a fifth clock signal line 65, a sixth clock signal line 66, a seventh clock signal line 67 and an eighth clock signal line 68.

[0141] The first clock terminal CLK of each shift register unit ASG in the same shift register unit group is connected to each clock signal line 60, for example, the first clock terminal CLK of the first-stage shift register unit ASG1 is connected to the first clock signal line 61, the first clock terminal CLK of the second-stage shift register unit ASG21 is connected to the second clock signal line 62, the first clock terminal CLK of the third-stage shift register unit ASG3 is connected to the third clock signal line 63, the first clock terminal CLK of the fourth-stage shift register unit ASG4 is connected to the fourth clock signal line 64, and the first clock terminal CLK of the fifth-stage shift register unit ASG5 is connected to the fifth clock signal line 65. , the first clock terminal CLK of the sixth-stage shift register unit ASG6 is connected to the sixth clock signal line 66, the first clock terminal CLK of the seventh-stage shift register unit ASG7 is connected to the seventh clock signal line 67, and the first clock terminal CLK of the eighth-stage shift register unit ASG8 is connected to the eighth clock signal line 68, so that the shift register units ASG (ASG1, ASG2, ASG3, ASG4, ASG5, ASG6, ASG7, ASG8) of each stage in the same shift register unit group can respectively receive different first clock signals CK (CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8).

[0142] The clock cycle Tck duration of the clock signal CK provided by each clock signal line 60 is 2*N*H, wherein H is the duration of one clock unit; the duration Tck1 of the valid pulse of the first clock signal CK is N*H; within one clock cycle Tck, the starting time of the valid pulse of the clock signal CK provided by each clock signal line 60 is shifted by 1H in sequence, that is, the starting time of the valid pulse of the first clock signal CK received by each level of shift register ASG in the same shift register group is shifted in sequence.

[0143] Specifically, since the gate drive signal Gouti output by the i-th shift register unit ASGi is used as the input signal Vini+N of the i+N-th shift register unit ASGi+N, for example, the gate drive signal Gout1 output by the first-stage shift register unit ASG1 is the input signal Vin5 of the fifth-stage shift register unit ASG5, the input module 110 of the fifth-stage shift register unit ASG5 can charge the first node PU under the control of the received input signal Vin5; and when charging the first node PU of the fifth-stage shift register unit ASG5, the input module 110 of the fifth-stage shift register unit ASG5 can charge the first node PU. During the charging process, the first clock signal CK5 received by its output module 120 is at an invalid level, and in the time period Tck2 when the first clock signal CK1 of the first-stage shift register unit ASG1 is at an invalid level, the first clock signal CK5 of the fifth-stage shift register unit ASG5 can be at a valid level, so as to prevent the signal of the first node PU from being unstable during the charging process of the first node PU, thereby affecting the conduction characteristics of the output module 120 of the fifth-stage shift register unit ASG5, and affecting the accuracy of the effective level of the gate drive signal Gout5 output by the fifth-stage shift register unit ASG5. In this way, the effective pulse time of the first clock signal CK5 received by the fifth-level shift register ASG5 does not overlap with the effective pulse time of the first clock signal CK1 received by the first-level shift register ASG1, and similar requirements are applied to the first clock signal CK2 received by the second-level shift register ASG2 and the sixth-level shift register ASG6, the first clock signal CK3 of the third-level shift register ASG3 and the seventh-level shift register ASG7, and the first clock signal CK4 of the fourth-level shift register ASG4 and the clock signal received by the eighth-level shift register ASG8.

[0144] At the same time, since the output module 120 in the shift register unit ASG can transmit the first clock signal CK to its signal output terminal OUT when the signal at its first node PU is at a valid level, the gate drive signal Gout output by the signal output terminal OUT can be consistent with the first clock signal CK received by it, that is, when the first clock signal CK is at a valid level, the gate drive signal Gout output by its signal output terminal Gout is also at a valid level. In this way, by shifting the effective pulse start time of the first clock signal CK received by each level of the shift register unit ASG in the same shift register unit group by 1H in sequence, it can be ensured that the effective pulse time of the gate drive signal Gout output by each level of the shift register unit ASG in the same shift register unit group is shifted by 1H in sequence. For example, the effective pulse starting time of the first clock signal CK (CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8) received by the first-stage shift register ASG1 to the eighth-stage shift register ASG8 is shifted by 1H in sequence, so that the effective level starting time of the gate drive signal Gout (Gout1, Gout2, Gout3, Gout4, Gout5, Gout6, Gout7, Gout8) output by each of the first-stage shift register ASG1 to the eighth-stage shift register ASG8 can be shifted by 1H in sequence.

[0145] It can be understood that, since the display panel can also include a plurality of pixels and a plurality of gate signal lines arranged in an array, and the pixels in the same row can be electrically connected to the same gate signal line, it is necessary to control the shift register units at various levels to provide gate drive signals to the gate signal lines within a frame period, and scan the pixels in each row in turn, so that the display signals (such as data signals) of the pixels in each row can be written in time division. At this time, by shifting the effective pulses of the gate drive signals output by the shift register units at various levels in the driving circuit in turn by 1H, the effective pulses of the gate drive signals corresponding to the pixels in two adjacent rows contain 3Hs overlapping each other, and the gate drive signal in the latter is delayed by 1H than the gate drive signal in the former, so that the row of pixels corresponding to the gate drive signal in the latter can have a pre-charging time of 3H with the data signal corresponding to the pixel corresponding to the former gate drive signal, and contains a charging time of 1H with the data signal corresponding to the pixel in the current row, which can ensure that the time for writing the display signal of each row of pixels is 1H, thereby ensuring the charging time and writing accuracy of the display signal of the pixel.

[0146] In addition, when the starting time T1 of the first effective pulse is before the starting time T2 of the starting effective pulse of the first clock signal CK1 of the first-stage shift register unit ASG1, the starting time T1 of the first effective pulse can be before the starting time of the starting effective pulse of the first clock signal CK of each stage of the shift register unit ASG, thereby improving the output noise of the signal output terminal OUT of each second shift register unit ASG02 caused by the first jump of the first clock signal CK of each stage of the shift register unit ASG to the effective level, thereby ensuring the accuracy of the gate drive signal Gout output by each stage of the shift register unit ASG01.

[0147] Based on the above embodiment, optionally, Fig.17: is a partial structural schematic diagram of another display panel provided by an embodiment of the present invention. When every 2*N stages of shift register units ASG form a shift register unit group, and the stages of shift register units ASG in the same shift register unit group are electrically connected to the clock signal lines 60 respectively, the first clock terminal CLK of the i-th stage shift register unit ASGi and the first clock terminal CLK of the i+2*N-th stage shift register unit ASGi+2*N are connected to the same clock signal line 60. For example, taking N as 4 as an example, the first clock terminal CLK of the first stage shift register unit ASG1 and the first clock terminal CLK of the ninth stage shift register unit ASG9 are both connected to the first clock signal line 61, the first clock terminal CLK of the second stage shift register unit ASG2 and the first clock terminal CLK of the tenth stage shift register unit ASG10 are both connected to the second clock signal line 62, and the first clock terminal CLK of the third stage shift register unit ASG3 and the first clock terminal CLK of the eleventh stage shift register unit ASG11 are both connected to the second clock signal line 63. The first clock terminal CLK is connected to the third clock signal line 63, the first clock terminal CLK of the fourth-stage shift register ASG4 and the first clock terminal CLK of the twelfth-stage shift register ASG12 are connected to the fourth clock signal line 64, the first clock terminal CLK of the fifth-stage shift register ASG5 and the first clock terminal CLK of the thirteenth-stage shift register ASG13 are connected to the fifth clock signal line 65, the first clock terminal CLK of the sixth-stage shift register ASG6 and the first clock terminal CLK of the fourteenth-stage shift register ASG14 are connected to the sixth clock signal line 66, the first clock terminal CLK of the seventh-stage shift register ASG7 and the first clock terminal CLK of the fifteenth-stage shift register ASG15 are connected to the seventh clock signal line 67, and the first clock terminal CLK of the eighth-stage shift register ASG8 and the first clock terminal CLK of the sixteenth-stage shift register ASG16 are connected to the eighth clock signal line 68. Such arrangement can help reduce the number of clock signal lines 60 while ensuring that the effective pulses of the gate drive signal Gout output by each level of shift register unit ASG are shifted in sequence, thereby helping to simplify the structure of the display panel and further help to narrow the frame of the display panel.

[0148] Based on the above embodiment, optionally, Fig.18 is another driving timing diagram of a display panel provided by an embodiment of the present invention, such as Fig.18 As shown, the operation process of the display panel may include a frame period TD, and the frame period TD includes a first effective pulse.

[0149] Among them, within the frame period TD, the first clock signal CK alternates between the effective level and the invalid level, so that the effective level of the gate drive signal Gout output by each level of the shift register unit ASG can be shifted in sequence; after the last level of the shift register unit ASG outputs the effective level of the gate drive signal Gout, the first clock signal CK can be maintained at the invalid level to reduce the power consumption caused by the repeated jumps of the first clock signal CK, which is beneficial to the low power consumption of the display panel; after entering the next frame period TD, the first clock signal CK can be alternately changed between the effective level and the invalid level again, so that the effective level of the gate drive signal Gout output by each level of the shift register unit ASG in the frame period TD can be shifted in sequence. In this way, in the starting time period of each frame period TD, there will be a starting effective pulse of the first clock signal CK, and at the starting time T2 of the starting effective pulse, the first clock signal CK will jump from the invalid level to the effective level, thereby causing output noise at the signal output terminal OUT of each level of the shift register unit ASG.

[0150] In this embodiment, by making each frame period TD include the first valid pulse, that is, in each frame period TD, the restoration signal Vrest2 received by the second shift register unit ASG02 includes the first valid pulse, so that in each frame period TD, before the start time T2 of the start valid pulse of the first clock signal CK, the signal of the first node PU and the signal output terminal OUT of each second shift register unit ASG02 is pulled down to be consistent with the first level signal, thereby improving the output noise of each stage of the second shift register unit ASG02 and improving the accuracy of the gate drive signal output by each stage of the second shift register unit ASG02.

[0151] Based on the above embodiment, optionally, refer to Fig.17 and Fig.18The display panel may further include: a start signal line 70; the start signal line 70 is used to transmit a start control signal STV; the signal input terminals IN of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN are all electrically connected to the start signal line 70, so that the start control signal STV transmitted by the start signal line 70 can be provided to the signal input terminals IN of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN, respectively, and the input modules 110 in the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN can respectively charge their first nodes PU. The signal of the first node PU can control its respective output module 120 to transmit its respective received first clock signal CK (CK1, ..., CKN) to its respective signal output terminal OUT, and because the valid pulses of the first clock signal CK (CK1, ..., CKN) received by the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN are shifted in sequence, the effective level of the gate drive signal Gout (Gout1, ..., GoutN) output by the signal output terminal OUT of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN can be shifted in sequence.

[0152] It can be understood that, since the effective pulse of the start control signal STV can control the input modules of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN to charge their first nodes PU, so that the effective levels of the gate drive signals Gout (Gout1, ..., GoutN) outputted from the signal output terminals OUT of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN can be shifted in sequence, and the N+1-stage shift register unit ASGN+1 electrically connected to the signal output terminals OUT of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN respectively The N+Nth shift register unit ASGN+N can receive the effective level of the gate drive signal Gout (Gout1, ..., GoutN) output from the signal output terminal OUT of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN, and can charge their respective first nodes PU in sequence. The N+1th-stage shift register unit ASGN+1 to the N+Nth-stage shift register unit ASGN+N can output the effective level of the gate drive Gout in sequence, and so on. The gate drive signal Gout (GoutN+1, ..., Gout N+N) output by each stage of the shift register unit ASG can be shifted in sequence, so that each row of pixels can be scanned row by row. Therefore, at the beginning of each frame period, an effective pulse of the start signal can be provided to the start signal line 70, so that the effective level of the gate drive signal Gout can be output in sequence from the first-stage shift register unit ASG1 to the last-stage shift register unit.

[0153] Optional, continue to refer to Fig.17 and Fig.18 The starting time T4 of the valid pulse of the start control signal STV is located before the starting time of the starting valid pulse of the first clock signal CK1 received by the first-stage shift register unit ASG1, and the ending time T5 of the valid pulse of the start control signal STV is located before the ending time T6 of the starting valid pulse of the first clock signal CK1 received by the first-stage shift register unit ASG1.

[0154] Specifically, by making the starting time T4 of the effective pulse of the start control signal STV be located before the starting time of the starting effective pulse of the first clock signal CK1 received by the first-stage shift register ASG1, before the starting time of the starting effective pulse of the first clock signal CK1 received by the first-stage shift register ASG1, the effective pulse of the start control signal STV can respectively control the input modules 110 in the first-stage shift register ASG1 to the N-th stage shift register ASGN to charge their first nodes PU respectively, so that when the first-stage shift register ASG1 receives the starting effective pulse of the first clock signal CK1, the signals of the first nodes PU of the first-stage shift register ASG1 to the N-th stage shift register ASGN can meet the conduction requirements of their respective output modules 120, so that the first-stage shift register ASG1 to the N-th stage shift register ASGN can accurately output the effective level of the gate drive signal Gout (Gout1, ..., GoutN).

[0155] At the same time, by making the termination time T5 of the effective pulse of the start control signal STV before the termination time T6 of the start effective pulse of the first clock signal CK1 received by the first-stage shift register unit ASG1, the input module 110 of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN can be controlled to stop charging the first node PU thereof before the termination time T6 of the start effective pulse of the first clock signal CK1 received by the first-stage shift register unit ASG1, and the potential of the first node PU of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN can remain unchanged when no other signal is written. In this way, it is possible to prevent the effective pulse time of the start control signal STV from being too long, thereby affecting the accuracy of the gate drive signal Gou1t output by the first-stage shift register unit ASG1, thereby ensuring that the shift register units ASG at all levels accurately output the gate drive signal Gout.

[0156] It can be understood that since the signal output terminal OUT of the first-stage shift register unit ASG1 is electrically connected to the signal input terminal IN of the N+1-stage shift register unit ASGN+1, in order to ensure that the N+1-stage shift register unit ASGN+1 stably outputs the effective level of the gate drive signal GoutN+1, the first clock signal CKN+1 received by the N+1-stage shift register unit ASGN+1 can be maintained at an invalid level when the signal output terminal OUT of the first-stage shift register unit ASG1 outputs the effective level of the gate drive signal Gout1, that is, the start time of the start effective pulse of the first clock signal CKN+1 of the N+1-stage shift register unit ASGN+1 can be located after the end time of the start effective pulse of the first clock signal CK1 of the first-stage shift register unit ASG1, or can be the same time as the end time of the start effective pulse of the first clock signal CK1 of the first-stage shift register unit ASG1. In this way, the end time T5 of the effective pulse of the start control signal STV should be before the start time of the start effective pulse of the first clock signal CKN+1 of the N+1-th level shift register unit ASGN+1, so as to ensure that the N+1-th level shift register unit ASGN+1 accurately outputs the effective level of the gate drive signal.

[0157] Optional, continue to refer to Fig.17 and Fig.18 When the clock cycle length of the first clock signal CK is 2*N*H, the duration of the valid pulse of the first clock signal CK is N*H, and H is a clock unit length, the time interval between the starting time T4 of the valid pulse of the start control signal STV and the starting time T2 of the starting valid pulse of the first clock signal CK received by the first-stage shift register unit ASG1 is greater than or equal to N*H.

[0158] Among them, when the signal input terminals IN of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN are all electrically connected to the start signal line 70, the start signal line 70 needs to provide the start control signal STV to the signal input terminals IN of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN respectively, so that the start control signal STV transmitted by the start signal line 70 needs a certain load capacity, and there will be a certain voltage drop during the transmission of the start control signal STV.Since the valid pulses of the first clock signal CK received by the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN are shifted in sequence, and the signal input terminals IN of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN receive the same start control signal STV, before the start time of the valid pulses of the first clock signal CK of the shift register units ASG1-N at each stage, the charging time of the first node PU of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN is successively reduced, compared with the second-stage shift register unit ASG2 to the N-stage shift register unit ASGN. The charging time of the first node PU of the first-stage shift register unit ASG1 is the shortest. Since the input signal received by the signal input terminal IN of each stage shift register unit ASG is shifted in sequence starting from the N+1-th stage shift register unit ASGN+1, and the first clock signal CK received by the first clock signal CLK of each stage shift register unit ASG is shifted in sequence, therefore, starting from the N+1-th stage shift register unit ASGN+1, the charging time of the first node PU of each stage shift register unit is the same before the effective pulse of its first clock signal CK starts, and the charging time is N*H. To ensure the The basic charging time of the first node PU of the first-stage shift register unit ASG1 ensures that the gate signal output performance of the first-stage shift register unit ASG1 is consistent with the performance of the other-stage shift register units ASG. It is necessary to set the time interval between the starting time T4 of the effective pulse of the start control signal STV and the starting time T2 of the starting effective pulse of the first clock signal CK received by the first-stage shift register unit ASG1 to be greater than or equal to N*H, so that the start signal line 70 can start to transmit the effective level of the start control signal STV within at least N*H time before the starting time T2 of the starting effective pulse of the first clock signal CK. In order to control the input modules IN of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN to charge their respective first nodes PU, sufficient time is reserved, so that when the first clock signals CK (CK1, ..., CKN) of the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN jump to valid pulses, the signal of the first node PU can accurately control the output module 120 to be in the on state, thereby ensuring the accuracy of the gate drive signals Gout (Gout1, ..., GoutN) output by the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN.

[0159] It can be understood that, under the premise that the time interval between the starting time T4 of the effective pulse of the start control signal STV and the starting time T2 of the starting effective pulse of the first clock signal CK received by the first-stage shift register unit ASG1 is greater than or equal to N*H, the longer the time interval between the starting time T4 of the effective pulse of the start control signal STV and the starting time T2 of the starting effective pulse of the first clock signal CK received by the first-stage shift register unit ASG1, the longer the time for charging the first node PU of the first-stage shift register unit ASG1 to the N-th stage shift register unit ASGN, and the stronger the ability of the output module 120 of the first-stage shift register unit ASG1 to the N-th stage shift register unit ASGN to transmit the first clock signal CK (CK1, ..., CKN) to its respective signal output terminal OUT. Therefore, within the driving capability of the display panel, the time interval between the starting moment T4 of the valid pulse of the driving control signal STV and the starting moment T2 of the starting valid pulse of the first clock signal CK received by the first-stage shift register unit ASG1 can be controlled to be as long as possible. The design can be made according to actual needs, and the embodiment of the present invention does not make any specific limitation to this.

[0160] Based on the above embodiment, optionally, continue to refer to Fig.17 and Fig.18 The starting time T1 of the first effective pulse and the starting time T4 of the effective pulse of the start control signal STV are the same time.

[0161] Among them, the starting time T1 of the first effective pulse and the starting time T4 of the effective pulse of the start control signal STV are the same time, which can be understood as: the driving chip used to drive the display panel for display starts to provide the first effective pulse and the effective pulse of the start control signal STV at the same time, or, when the restoration signal line 40 used to transmit the second shift register unit ASG02 receives the first effective pulse, the start signal line 70 starts to transmit the effective pulse of the start control signal STV. In this way, by making the starting time T1 of the first effective pulse and the starting time T4 of the effective pulse of the start control signal STV the same time, the driving chip can simultaneously provide the first effective pulse and the effective pulse of the start control signal, so that when the start control signal STV received by the first-stage shift register unit ASG1 to the N-th-stage shift register unit ASGN jumps from an invalid level to a valid level, the restoration module 130 in each second shift register unit ASG01 can be controlled by the first effective pulse to control its respective signal output terminal OUT and the signal of the first node PU to remain at an invalid level, thereby improving the influence of the start control signal STV on the accuracy of the gate drive signal Gout outputted from the signal output terminal OUT of each second shift register unit ASG01, thereby facilitating improving the display effect of the display panel.

[0162] Optional, continue to combine references Fig.17 and Fig.18 The termination time T3 of the first effective pulse and the termination time T5 of the effective pulse of the start control signal STV are the same time.

[0163] Among them, the termination time T3 of the first effective pulse and the termination time T5 of the effective pulse of the start control signal STV are the same time, which can be understood as: the driving chip used to drive the display panel for display stops providing the first effective pulse and the effective pulse of the start control signal STV at the same time, or, when the restoration signal line 40 used to transmit the second shift register unit ASG02 receives the restoration signal Vrest2 and starts to change from the effective level to the invalid level, the start signal line 70 transmitting the start control signal STV also starts to change from the effective level to the invalid level. By setting the termination time T3 of the first effective pulse to be the same as the termination time T5 of the effective pulse of the start control signal STV, the start control signal STV can stop controlling the input module 110 in the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN to charge its first node PU, so that when the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN outputs the effective level of the gate drive signal Gout under the control of the stable first node PU signal, it is ensured that the input module 110 of each second shift register unit ASG02 can charge its first node PU under the control of the received input signal Vin, and ensure that the first node PU in each second shift register unit ASG02 has a longer charging time, thereby improving the accuracy of the first node PU signal in each second shift register unit ASG02, thereby improving the accuracy of the gate drive signal Gout output by each second shift register unit ASG02.

[0164] It can be understood that the above description is merely an example of taking the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN as the first shift register unit ASG01 to exemplify the technical solution of the embodiment of the present invention. When the time of the first effective pulse overlaps with the starting effective pulse of the first clock signal CK of at least some of the shift register units ASG in the first-stage shift register unit ASG1 to the N-stage shift register unit ASGN, the effective level of the gate drive signal Gout output by the part of the shift register unit ASG overlaps with the first effective pulse. If the shift register unit ASG electrically connected to the signal output terminal OUT of the part of the shift register unit ASG is the second shift register unit ASG02, the input module 110 of the part of the second shift register unit ASG02 will provide the effective level to the first node PU, and the restoration module 130 will also provide the first level signal Vgl to the first node PU, so that the first node PU cannot be charged, thereby affecting the accuracy of the gate drive signal Gout output by the part of the second shift register unit ASG02.

[0165] In an optional implementation, Fig.19 is a partial structural diagram of another display panel provided by an embodiment of the present invention, combined with reference Fig.18 and Fig.19 , the time of the first effective pulse overlaps with the effective pulse time of the first clock signal CK (CK1, ..., CKM) of the first-stage shift register ASG1 to the M-th-stage shift register ASGM, and the time of the first effective pulse does not overlap with the effective pulse time of the first clock signal CKM+1 of the M+1-th-stage shift register ASGM+1; M≤N, and M is a positive integer; at this time, the first-stage shift register ASG1 to the M+N-th-stage shift register ASGM+N can all be the first shift register ASG01.

[0166] Exemplarily, taking the overlap of the time of the first effective pulse with the effective pulse time of the first clock signal CK (CK1, CK2, CK3) of the first-stage shift register unit ASG1 to the third-stage shift register unit ASG3 as an example, in the time period when the first-stage shift register unit ASG1 to the third-stage shift register unit ASG3 output the effective level of the gate drive signal Gout (Gout1, Gout2, Gout3), the restoration signal Vrest2 of the second shift register unit ASG02 is at an effective level; at this time, if the fifth-stage shift register unit ASG5 to the seventh-stage shift register unit ASG7 are the second shift register unit ASG02, the fifth-stage shift register unit ASG03 will be The charging time of the first node PU in ASG5 is shortened to 1*H, the charging time of the first node PU in the sixth-level shift register unit ASG6 is shortened to 2*H, the charging time of the first node PU in the seventh-level shift register unit ASG7 is shortened to 3*H, and the charging time of the first node PU in the eighth-level shift register unit ASG8 is 4*H. In this way, the charging time of the first node PU in the fifth-level shift register unit ASG5 to the seventh-level shift register unit ASG7 is shorter than the charging time of the first node PU in the eighth-level shift register unit ASG8, and thus the first node PU in the fifth-level shift register unit ASG5 to the seventh-level shift register unit ASG7 cannot be accurately charged.

[0167] In this embodiment, by making the first-stage shift register unit ASG1 to the M+N-th stage shift register unit ASGM+N all be the first shift register unit ASG01, that is, the first-stage shift register unit ASG1 to the seventh-stage shift register unit ASG7 are all the first shift register unit ASG01, it can be ensured that the restoration signal Vrest1 received by the restoration signal end REST of the first-stage shift register unit ASG1 to the seventh-stage shift register unit ASG7 is an invalid level, so that within the time when the first-stage shift register unit ASG1 outputs the effective level of the gate drive signal Gout1, the input module 110 in the fifth-stage shift register unit ASG5 can continue to charge its first node PU, and in the second-stage shift register unit ASG2 During the time when the effective level of the gate drive signal Gout2 is output, the input module 110 in the sixth-level shift register unit ASG6 can continuously charge its first node PU, and during the time when the third-level shift register unit ASG3 outputs the effective level of the gate drive signal Gout3, the input module 110 in the seventh-level shift register unit ASG7 can continuously charge its first node PU, so as to ensure that the first node PU in the fifth-level shift register unit ASG5 to the seventh-level shift register unit ASG7 has a sufficiently long charging time, thereby improving the accuracy of the gate drive signal Gout (Gout5, Gout6, Gout7) output by the fifth-level shift register unit ASG5 to the seventh-level shift register unit ASG7.

[0168] It can be understood that the above description only exemplarily illustrates the distribution of the first shift register unit ASG01 and the second shift register unit ASG02 in the first type of shift register unit by taking the termination time T3 of the first effective pulse and the termination time T5 of the effective pulse of the start control signal STV as the same time. In other embodiments of the present invention, the termination time T3 of the first effective pulse may also be located after the termination time T5 of the effective pulse of the start control signal STV.

[0169] In an alternative embodiment, reference Fig.19 and Fig. 20, the termination time T3 of the first valid pulse is later than the termination time T5 of the start control signal STV, that is, when the start control signal STV jumps from the valid level to the invalid level, the restoration signal Vrest2 received by the restoration signal terminal REST of the second shift register unit ASG02 can continue to maintain the valid level, so that the first node PU and the signal output terminal OUT of each second shift register unit ASG02 can continue to maintain the invalid level, so as to prevent the gate drive signal Gout output by the signal output terminal OUT of each second shift register unit ASG02 from being affected by the start control signal STV jumping from the valid level to the invalid level, so that the signal output terminal OUT of each second shift register unit ASG02 has output noise, thereby improving the accuracy of the gate drive signal Gout output by each second shift register unit ASG02.

[0170] Optional, continue to refer to Fig.19 and Fig. 20 The time period from the end time T6 of the start effective pulse of the first clock signal CK1 received by the first-stage shift register unit ASG1 to the start time T7 of the next effective pulse thereof is the first time period; the end time T3 of the first effective pulse is within the first time period.

[0171] Among them, the next valid pulse of the starting valid pulse of the first clock signal CK1 can be understood as the time period in which the first clock signal CK1 becomes the valid level for the second time within a frame period, that is, the second valid pulse of the first clock signal CK1. The termination time T3 of the first valid pulse is within the first time period, which can be understood as: the termination time T3 of the first valid pulse can be the same as the termination time T6 of the starting valid pulse of the first clock signal CK1 or the starting time T7 of the second valid pulse of the first clock signal CK1, or the termination time T3 of the first valid pulse is between the termination time T6 of the starting valid pulse of the first clock signal CK1 and the starting time T7 of the second valid pulse. It can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0172] In the present embodiment, by making the termination time T3 of the first effective pulse within the first time period, on the premise that when the first clock signal CK (CK1, CK2, CK3, CK4) received by the first-stage shift register unit ASG1 to the N-th stage shift register unit ASGN jumps from an invalid level to a valid level, the gate drive signal Gout outputted by the signal output terminal OUT of each second shift register unit ASG02 will not change accordingly, at least when the first clock signal CK1 of the first-stage shift register unit ASG1 jumps from a valid level to an invalid level, the gate drive signal Gout outputted by the signal output terminal OUT of each second shift register unit ASG02 will not change accordingly.

[0173] It can be understood that the relationship between the termination time T3 of the first valid pulse and the start time and termination time of the start valid pulse of the first clock signal CK received by each stage of the shift register unit ASG can determine the influence of the start valid pulse jump of the first clock signal CK received by each stage of the shift register unit ASG on the output noise of the signal output terminal OUT of each second shift register unit ASG02. On the premise that each stage of the shift register unit ASG can accurately output the gate driving signal Gout, the embodiments of the present invention do not make specific limitations on this.

[0174] It can also be understood that when the termination time T3 of the first valid pulse is within the first time period, the first valid pulse will overlap with the first clock signal CK whose start time of the start valid pulse is before the termination time T3 of the first valid pulse, so that the valid level of the gate driving signal Gout output by each stage of the shift register unit ASG receiving this part of the first clock signal CK will also overlap with the first valid pulse, resulting in insufficient charging time of the first node PU of the shift register unit ASG electrically connected to the signal output terminal of this part of the shift register unit ASG.

[0175] Based on the above embodiments, optionally, Fig.21 is a schematic diagram of a partial structure of another display panel provided by the embodiments of the present invention. With reference to Fig. 20 and Fig.21 , the time of the first valid pulse overlaps with the valid pulse time of the first clock signal CK (CK1,..., CKP) of the first-stage shift register unit ASG1 to the P-stage shift register unit ASGP, and the time of the first valid pulse does not overlap with the valid pulse time of the first clock signal CKP+1 of the (P + 1)-stage shift register unit ASGP+1; N < P ≤ 2N, and P is a positive integer; at this time, the first-stage shift register unit ASG1 to the (P + N)-stage shift register unit ASGP+N are all the first shift register unit ASG01.

[0176] For example, taking the overlap of the first effective pulse time with the effective pulse time of the first clock signal CK (CK1, CK2, ..., CK7) of the first-stage shift register unit ASG1 to the seventh-stage shift register unit ASG7 as an example, in the time period when the first-stage shift register unit ASG1 to the seventh-stage shift register unit ASG7 output the effective level of the gate drive signal Gout (Gout1, Gout2, ..., Gout7), the restoration signal Vrest2 of the second shift register unit ASG02 is at an effective level; at this time, if the restoration signal Vrest2 of the second shift register unit ASG02 is at an effective level with the fifth-stage shift register unit ASG5 to the seventh-stage shift register unit ASG7, the restoration signal Vrest2 of the second shift register unit ASG02 is at an effective level. If the ninth-stage shift register unit ASG9 to the eleventh-stage shift register unit ASG11 electrically connected to the signal output terminal OUT of the unit ASG7 is the second shift register unit ASG02, the charging time of the first node PU in the ninth-stage shift register unit ASG9 to the eleventh-stage shift register unit ASG11 will be shortened to 1*H, 2*H, and 3*H respectively, while the charging time of the first node PU in the twelfth-stage shift register unit ASG12 will be 4*H. In this way, the first node PU in the ninth-stage shift register unit ASG9 to the eleventh-stage shift register unit ASG11 cannot be accurately charged.

[0177] In this embodiment, by making the first-stage shift register unit ASG1 to the P+N-stage shift register unit ASGP+N all the first shift register unit ASG01, that is, the first-stage shift register unit ASG1 to the eleventh-stage shift register unit ASG11 are all the first shift register unit ASG01, it can be ensured that the restoration signal Vrest1 received by the restoration signal end REST of the first-stage shift register unit ASG1 to the eleventh-stage shift register unit ASG11 is an invalid level, so that within the time when the first-stage shift register unit ASG1 to the fourth-stage shift register unit ASG4 output the effective level of the gate drive signal Gout1, the fifth-stage shift register unit ASG4 can be accurately shifted. The first node PU in the unit ASG5 to the eighth-level shift register unit ASG8 is charged, and the first node PU in the ninth-level shift register unit ASG9 to the twelfth-level shift register unit ASG12 can be accurately charged within the time when the fifth-level shift register unit ASG5 to the eighth-level shift register unit ASG8 output the effective level of the gate drive signal Gout2; in this way, it can ensure that the charging time of the first node PU of each level of shift register unit ASG is 4*H, ensure the charging consistency and accuracy of the first node PU of each level of shift register unit ASG, and thereby improve the accuracy of the gate drive signal Gout output by the shift register unit ASG at each level.

[0178] It should be noted that the above description is only an exemplary description of the distribution of the first shift register unit in the driving circuit, and in the embodiment of the present invention, the other shift register units except the first shift register unit in the first type of shift register unit of the driving circuit can be the second shift register unit, which can be specifically designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this. For the convenience of description, under the premise of no special limitations, the embodiment of the present invention takes the first-level to N-th level first-level shift register units as the first shift register unit, and the other first-level shift register units as the second shift register unit as an example to exemplify the technical solution of the embodiment of the present invention.

[0179] Optional, Fig. 22 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig. 22 As shown, when the display panel 100 further includes a plurality of pixels 20 arranged in an array, a plurality of gate signal lines 31 and a start signal line 70, and the gate signal line 31 is electrically connected to the pixel 20, the signal input terminal IN of the first shift register unit ASG01 can be electrically connected to the start signal line 70, and the first shift register unit ASG01 is not configured to provide a gate drive signal Gout to the gate signal line 31. At this time, each second shift register unit ASG02 can be electrically connected to each gate signal line 31, so that each second shift register unit ASG02 can provide a gate drive signal Gout to each gate signal line 31, respectively.

[0180] Among them, the first shift register unit ASG01 can output the corresponding gate drive signal Gout under the control of the start control signal STV transmitted by the start signal 70 and the first clock signal CK received by it, and use the gate drive signal Gout as the input signal Vin of the second shift register unit ASG02 cascaded with it, so that the second shift register unit ASG02 can output the corresponding gate drive signal Gout under the control of the input signal Vin, the first clock signal CK, the restoration signal Vrest2 and the first level signal Vgl received by it.

[0181] At the same time, due to the difference between the signal received by the first shift register unit ASG01 and the signal received by the second shift register unit ASG02, there is a certain difference in the impedance of the first shift register unit ASG01 and the second shift register unit ASG02, which leads to a certain difference in the gate drive signal Gout output by the first shift register unit ASG01 and the second shift register unit ASG02. ​​By making each second shift register unit ASG01 electrically connected to each gate signal line 31, while the first shift register unit ASG01 is not electrically connected to the gate signal line 31, it can be ensured that the gate drive signal Gout received by each pixel 20 in the display panel 100 remains consistent, thereby improving the display uniformity of the display panel 100.

[0182] In other optional embodiments, Fig.23 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.23 As shown, when the display panel 100 includes a plurality of pixels 20 and a plurality of gate signal lines 31 arranged in an array, and the gate signal lines 31 are electrically connected to the pixels 20, the first shift register unit ASG01 provides a gate drive signal to the gate signal line 31, so that each pixel 20 electrically connected to the first shift register unit ASG01 through the gate signal line 31 can write a display signal under the control of the gate drive signal output by the first shift register unit ASG01. At this time, the first shift register unit ASG01 is not a virtual shift register unit, and a virtual shift register unit may not be provided in the driving circuit 10 or other virtual shift register units may be additionally provided. The specific design may be based on actual needs, and the embodiment of the present invention does not specifically limit this.

[0183] Based on the above embodiment, optionally, Fig.24 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.25 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present invention, and is combined with reference to Fig.24 and Fig.25 The shift register unit ASG also includes a second-type shift register unit ASGb; the second-type shift register unit ASGb is not provided with a restoration module and a restoration signal terminal; in addition, when the display panel 100 also includes a start signal line 70, the signal input terminal IN of the second-type shift register unit ASGb can be electrically connected to the start signal line 70.

[0184] Specifically, since the second type shift register unit ASGb is not provided with a restoration module and a restoration signal terminal, it is not necessary to provide the restoration signal Vrest to the second type shift register unit ASGb, and compared with the first type shift register unit ASGa, the second type shift register unit ASGb has a simpler structure, so that the second type shift register unit ASGb has a smaller size, thereby simplifying the structure of the driving circuit 10, which is beneficial to the narrow frame of the display panel. At the same time, since the signal input terminal IN of the second type shift register unit ASGb is electrically connected to the start signal line 70, the input module 110 in the second type shift register unit ASGb can charge its first node PU under the control of the start control signal STV transmitted by the start signal line 70, so that the signal of its first node PU can control its output module 120 to transmit the first clock signal CK to its signal output terminal OUT, so that the second type shift register unit ASGb can output the corresponding gate drive signal Gout.

[0185] In addition, the signal output terminal OUT of each second-type shift register unit ASGb can also be electrically connected to the signal input terminal IN of some first-type shift register units ASGa, so that these first-type shift register units ASGa can output the corresponding gate drive signal under the control of the gate drive signal Gout output by the second-type shift register unit ASGb cascaded with it.

[0186] Among them, since the restoration module is not set in the second-type shift register unit ASGb, there may be a difference between the gate drive signal Gout output by the second-type shift register unit ASGb and the first-type shift register unit ASGa. Therefore, the second-type shift register unit ASGb may not be electrically connected to the gate signal line 31, and the gate signal line 31 may be electrically connected to each first-type shift register unit ASGa, respectively, so as to improve the consistency of the gate drive signal Gout transmitted by each gate signal line 31, thereby improving the display uniformity of the display panel 100. At this time, the second-type shift register unit ASGb can exist in the driving circuit 10 as a virtual shift register unit.

[0187] It should be noted that the above is only an exemplary description of the setting method of the virtual shift register unit in the driving circuit. Under the premise that the core invention point of the embodiment of the present invention can be achieved, the embodiment of the present invention does not make specific limitations on this. For the convenience of description, under the premise that there is no special limitation, the embodiment of the present invention takes the driving circuit without additionally setting the virtual shift register unit as an example to exemplify the technical solution of the embodiment of the present invention.

[0188] It can be understood that in the embodiment of the present invention, the i-th shift register unit ASGi is cascaded with the i+N-th shift register unit ASGi+N, and N can be any positive integer, that is, N can be equal to 1 or greater than 1. When N is greater than 1, the first-stage shift register unit ASG1 to the N-th-stage shift register unit ASGN can all be electrically connected to the same start signal line or different start signal lines, and can be designed according to actual needs.

[0189] Optional, Fig.26 is a partial structural diagram of another display panel provided by an embodiment of the present invention, Fig. 27 is another driving timing diagram of a display panel provided by an embodiment of the present invention, and is combined with reference to Fig.26 and Fig. 27 The display panel also includes M start signal lines 70, which are used to transmit the start control signal STV; the effective pulse start time of the start control signal STV transmitted by each start signal line 70 is shifted in sequence; 2≤M≤N, M is a positive integer; each shift register unit ASG in the first-stage shift register unit ASG1 to the N-th-stage shift register unit ASGN is electrically connected to each start signal line 70, and each start signal line 70 is electrically connected to at least one stage of shift register unit ASG.

[0190] Among them, when M is greater than 1 and less than or equal to N, M can be any positive integer of 2-N and can be designed according to actual needs. The embodiment of the present invention does not make specific limitations on this.

[0191] For example, the display panel includes two start signal lines 70, and N is equal to 4, that is, the first start signal line 701 and the second start signal line 702, the signal input terminal IN of the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 can be electrically connected to the first start signal line 701, and the signal input terminal IN of the third-stage shift register unit ASG3 and the fourth-stage shift register unit ASG4 can be electrically connected to the second start signal line 702. At this time, the input module 110 of the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 can be electrically connected to the first start signal line 701. Under the control of a first start control signal STV1 transmitted by a start signal line 701, its first node PU is charged, and the input module 110 of the third-level shift register unit ASG3 and the fourth-level shift register unit ASG4 can charge its first node PU under the control of a second start control signal STV2 transmitted by a second start signal line 702; in this way, each start signal line 70 is only electrically connected to two stages of shift register units ASG, which is beneficial to reducing the load on each start signal line 70 and improving the accuracy of the start control signal received by each level of shift register unit ASG. At the same time, the effective pulse starting time T41 of the first start control signal STV1 transmitted by the first start signal line 701 and the effective pulse starting time T42 of the second start control signal STV2 transmitted by the second start signal line 702 are shifted sequentially, so that under the premise of ensuring that the gate drive signal Gout output by each level of shift register unit ASG is shifted sequentially, the charging time of the first-level shift register unit ASG1 and the second-level shift register unit ASG2 controlled by the first start control signal STV1 can be consistent with the charging time of the third-level shift register unit ASG3 and the fourth-level shift register unit ASG4 controlled by the second start control signal STV2, which is beneficial to improve the accuracy of the gate drive signal Gout output by each level of shift register unit ASG.

[0192] Optional, continue to refer to Fig.26 and Fig. 27 , the M start signal lines 70 include at least one first start signal line 701; the effective pulse start time T41 of the start control signal STV1 transmitted by the first start signal line 701 is located before the effective pulse start time T42 of the start control signal STV2 transmitted by other start signal lines (for example, the second start signal line 702); the shift register units ASG at all levels electrically connected to at least the first start signal line 701 are the first shift register units ASG01.

[0193] Exemplarily, taking N equal to 4, and the display panel includes a first start signal line 701 and a second start signal line 702 as an example, when the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 electrically connected to the first start signal line 701 are set to the first shift register unit ASG01, and the third-stage shift register unit ASG3 and the fourth-stage shift register unit ASG4 electrically connected to the second start signal line 702 are set to the second shift register unit ASG02, so that the restoration signal end REST of the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 receives the invalid level of the restoration signal Vrest1, so that under the control of the invalid level of the restoration signal Vrest1, the restoration module 130 in the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 will not affect the charging of the first node PU by its input module 110, ensuring that the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 can accurately output the gate drive signal Gout (Gout1, Gout2); and the first valid pulse of the restoration signal Vrest2 received by the restoration signal terminal REST of the third-stage shift register unit ASG3 and the fourth-stage shift register unit ASG4 can be controlled to be kept at an invalid level at the signal output terminal OUT of the third-stage shift register unit ASG3 and the fourth-stage shift register unit ASG4 before the starting time of the starting valid pulse of the first clock signal CK (CK1, CK2) received by the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2, thereby improving the influence of the first jump of the first clock signal CK (CK1, CK2) received by the first-stage shift register unit ASG1 and the second-stage shift register unit ASG2 on the output noise of the signal output terminal OUT of the third-stage shift register unit ASG3 and the fourth-stage shift register unit ASG4, thereby facilitating improving the accuracy of the gate drive signals output by the shift register units ASG at each level.

[0194] It should be noted that the above is only an exemplary description of the structure, connection relationship, and working process of the shift register units at various levels, and under the premise of being able to achieve the core invention of the embodiment of the present invention, the structure, connection relationship, and working process of the shift register units at various levels are not limited to this, and can be designed according to actual needs. The typical structure of the shift register unit will be exemplarily described below.

[0195] Based on the above embodiment, optionally, Fig.28 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present invention, such as Fig.28As shown, the shift register unit ASG may also include a pull-down module 140 and a pull-down control module 150; in the same shift register unit ASG, the pull-down control module 150 is electrically connected to at least the first node PU, the second node PD and the first level end VGL respectively; the pull-down module 140 is electrically connected to the first level end VGL, the second node PD, the first node PU and the signal output end OUT respectively.

[0196] Among them, the pull-down control module 150 can at least control the signal of the second node PD according to the signal of the first node PU and the first level signal Vgl of the first level end VGL. For example, when the signal of the first node PU is at a valid level, the signal of the second node PD can be controlled to be an invalid level consistent with the first level signal Vgl; conversely, the pull-down control module 150 can control the signal of the second node PD to be a valid level.

[0197] The pull-down module 140 can at least control the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT according to the signal of the second node PD and the first level signal Vgl of the first level terminal VGL. For example, when the signal of the second node PD is at a valid level, the pull-down module 140 can control the first level signal Vgl of the first level terminal VGL to be transmitted to the first node PU and the signal output terminal OUT respectively, so as to pull down the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT respectively, so that the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT are both at invalid levels; and when the signal of the second node PD is at an invalid level, the pull-down module 140 no longer pulls down the signal of the first node PU and the gate drive signal Gout of the signal output terminal OUT. At this time, the signal of the first node PU can be controlled by the signal provided by the input module 110, and the gate drive signal Gout of the signal output terminal OUT is controlled by the signal provided by the output module 120.

[0198] In this embodiment, by setting a pull-down control module 150 and a pull-down module 140 in the shift register unit ASG, and using the pull-down control module 150 to control the signal of the second node PD, the pull-down module 140 can pull down the signal of the first node PU and the signal output terminal OUT under the control of the signal of the second node PD, thereby achieving control of the time when the signal of the first node PU is an invalid level, and controlling the time when the signal output terminal OUT outputs the invalid level of the gate drive signal Gout, thereby ensuring the accuracy of the gate drive signal Gout output by the shift register unit ASG.

[0199] Optional, continue to refer to Fig.28The shift register unit may further include a first signal terminal SIG1, a second signal terminal SIG2 and a third signal terminal SIG3, and the pull-down control module 150 is also electrically connected to the first signal terminal SIG, the second signal terminal SIG2 and the third signal terminal SIG3 respectively. At this time, the pull-down control module 150 can control the signal of the second node PD according to the signal of the first node PU, the first signal Vsig1 of the first signal terminal SIG1, the second signal Vsig2 of the second signal terminal SIG2, the third signal Vsig3 of the third signal terminal SIG3, and the first level signal Vgl of the first level terminal VGL. For example, when the first signal Vsig1, the second signal Vsig2 and the third signal Vsig3 are at a valid level, the pull-down control module 150 can transmit the third signal Vsig3 to the second node PD under the control of the first signal Vsig1 and the second signal Vsig2, so that the signal of the second node PD is at a valid level. At this time, the signal of the first node PU can be at an invalid level; conversely, when the first node PU is at a valid level, the pull-down control module 150 can transmit the first level signal Vgl to the second node PD, so that the signal of the second node PD is at an invalid level. In this way, by setting the pull-down control module 150 in the shift register unit ASG, the signal of the first node PU can be inverted with the signal of the second node PD.

[0200] As a feasible embodiment, Fig.29 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.29 As shown, the pull-down control module includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4; the first electrode of the first transistor M1 is connected to the first signal terminal SIG1, the second electrode of the first transistor M1 is connected to the gate of the second transistor M2, and the gate of the first transistor M1 is connected to the second signal terminal SIG2; the first electrode of the second transistor M1 is connected to the third signal terminal SIG3, and the second electrode of the second transistor M2 is connected to the second node PD; the gates of the third transistor M3 and the fourth transistor M4 are both electrically connected to the first node PU; the first electrode of the third transistor M3 and the first electrode of the fourth transistor M4 are both electrically connected to the first level terminal VGL; the second electrode of the third transistor M3 is electrically connected to the second node PD, and the second electrode of the fourth transistor M4 is electrically connected to the gate of the second transistor M2.

[0201] Among them, the first transistor M1 can be turned on or off under the control of the second signal Vsig2 of the second signal terminal SIG2, and when the first transistor M1 is turned on, the first signal Vsig1 of the first signal terminal SIG1 can be transmitted to the gate of the second transistor M2 to control the second transistor M2 to be turned on or off; the third transistor M3 and the fourth transistor M4 can be turned on or off under the control of the signal of the first node PU.

[0202] Exemplarily, when the signal of the first node PU is at an invalid level, and the first signal Vsig1, the second signal Vsig2, and the third signal Vsig3 are all at valid levels, the third transistor M3 and the fourth transistor M4 are in a closed state, and the first transistor M1 can be turned on under the control of the second signal Vsig2 to provide the first signal Vsig1 to the gate of the second transistor M2, so that the second transistor M2 is turned on, and the second transistor M2 can transmit the third signal Vsig3 of the third signal terminal SIG3 to the second node PD, so that the signal of the second node PD can be consistent with the third signal Vsig3, that is, the signal of the second node PD is at a valid level; and in the first node When the signal at the point PU is at a valid level, the signal at the first node PU can control the third transistor M3 and the fourth transistor M4 to turn on, so that the fourth transistor M4 can transmit the first level signal Vgl of the first level end VGL to the gate of the second transistor M2. At this time, regardless of whether the first transistor M1 transmits the first signal Vsig1 to the second transistor M2, the voltage difference between the gate of the second transistor M2 and its first electrode cannot meet its turn-on condition, so that the second transistor M2 is in a closed state. At the same time, the third transistor M3 can transmit the first level signal Vgl of the first level end VGL to the second node PD, so that the signal of the second node PD is an invalid level. In this way, by setting the pull-down control module 150 in the shift register unit ASG, the signal of the first node PU can be inverted with the signal of the second node PD.

[0203] It can be understood that the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 can be P-type transistors or N-type transistors, and can be specifically designed according to actual needs. Wherein, when the transistor is an N-type transistor, the signal received by its gate is a high level, or the voltage difference between its gate signal and its first pole signal is greater than or equal to its threshold voltage, the transistor can be in a conducting state, that is, the effective level of controlling the transistor to be turned on is a high level, and the effective level of controlling the transistor to be turned off is a low level; when the transistor is a P-type transistor, the signal received by its gate is a low level, or the voltage difference between its gate signal and its first pole signal is less than or equal to its threshold voltage, the transistor can be in a conducting state, that is, the effective level of controlling the transistor to be turned on is a low level, and the effective level of controlling the transistor to be turned off is a high level. Therefore, based on the type of each transistor, providing a corresponding signal to the shift register unit can enable the shift register unit to implement a corresponding working process. For the convenience of description, without special limitations, the embodiments of the present invention take the transistor in the shift register unit as an N-type transistor as an example to exemplarily illustrate the technical solution of the embodiments of the present invention.

[0204] It should be noted that the above only exemplarily describes the first signal Vsig1, the second signal Vsig2 and the third signal Vsig3. In the embodiment of the present invention, the first signal Vsig1, the second signal Vsig2 and the third signal Vsig3 may be the same or different and may be designed according to actual needs. The embodiment of the present invention does not make any specific limitation on this.

[0205] In an alternative embodiment, Fig.30 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.30 As shown, the shift register unit ASG also includes a second level terminal VGH, and the second level terminal VGH is used to receive a second level signal Vgh; in the same shift register unit ASG, the pull-down control module 150 is also electrically connected to the second level terminal VGH, so that the pull-down control module 150 can control the signal of the second node PD according to the signal of the first node PU, the first level signal Vgl of the first level terminal VGL, and the second level signal Vgh of the second level terminal VGH. For example, when the signal of the first node PU is an invalid level, the pull-down control module 150 can transmit the second level signal Vgh of the second level terminal VGH to the second node PD, so that the signal of the second node PD is a valid level; and when the signal of the first node PU is a valid level, the pull-down control module 150 can transmit the first level signal Vgl of the first level terminal VGL to the second node PD, so that the signal of the second node PD is an invalid level. In this way, by setting the pull-down control module 150 in the shift register unit ASG, the signal of the first node PU can be inverted with the signal of the second node PD.

[0206] The second level signal Vgh of the second level terminal VGH may have a polarity opposite to that of the first level signal Vgl of the first level terminal VGL, that is, when the first level signal Vgl is at a low level, the second level signal Vgh may be at a high level, or when the first level signal Vgl is at a high level, the second level signal Vgh may be at a low level, which may be specifically designed according to actual needs, and the embodiments of the present invention do not specifically limit this. For ease of description, without special limitations, the embodiments of the present invention are all based on the first level signal Vgl being at a low level and the second level signal Vgh being at a high level as an example to exemplarily illustrate the embodiments of the present invention.

[0207] It can be understood that when the shift register unit includes a first signal terminal SIG, a second signal terminal SIG2 and a third signal terminal SIG3, and the first signal Vsig1 of the first signal terminal SIG, the second signal Vsig2 of the second signal terminal SIG2 and the third signal Vsig3 of the third signal terminal SIG3 are the same signal, the first signal terminal SIG, the second signal terminal SIG2 and the third signal terminal SIG3 can all be electrically connected to the second level terminal VGH. At this time, the first signal Vsig1, the second signal Vsig2 and the third signal Vsig3 are all second level signals VGH.

[0208] In an exemplary embodiment, Fig.31 As shown, the shift register unit ASG also includes a second level terminal VGH, and the second level terminal VGH is used to receive the second level signal Vgh, the first signal terminal SIG1, the second signal terminal SIG2 and the third signal terminal SIG3 can be electrically connected to the second level terminal VGH, that is, the first electrode of the first transistor M1, the gate of the first transistor M1, and the first electrode of the second transistor M2 are electrically connected to the second level terminal VGH. At this time, the first transistor M1 can be continuously in a conductive state under the control of the second level signal Vgh, and when the signal at the first node PU is at an invalid level, the second transistor M2 can transmit the second level signal Vgh from the first transistor M1 to the gate of the second transistor M2. is in a conducting state under the control of, so that the second level signal Vgh can be transmitted to the second node PD, so that the signal of the second node PD is a valid level; when the signal at the first node PU is a valid level, the fourth transistor M4 transmits the first level signal Vgl to the gate of the second transistor M2, so that the gate signal of the second transistor M2 is pulled down to a level less than the second level signal Vgh, and the voltage difference between the gate signal of the second transistor M2 and its first pole signal is less than the threshold voltage of the second transistor M2, so that the second transistor M2 is in a closed state, and at the same time, the third transistor M3 can transmit the first level signal Vgl to the second node PD, so that the signal of the second node PD is an invalid level.

[0209] In this embodiment, the first signal terminal SIG, the second signal terminal SIG2 and the third signal terminal SIG3 are all electrically connected to the second level terminal VGH, so that the first signal terminal SIG, the second signal terminal SIG2 and the third signal terminal SIG3 receive the same signal, which is beneficial to reducing the number of signals provided to the shift register unit and reducing the number of signal lines used to transmit signals, thereby helping to simplify the structure of the display panel. When the shift register unit is set in the non-display area of ​​the display panel, it is beneficial to have a narrow frame of the display panel.

[0210] In another alternative embodiment, Fig.32is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.32 As shown, the shift register unit ASG may further include a second clock terminal CLB; the second clock terminal CLB is used to receive a second clock signal CKB; in the same shift register unit ASG, the pull-down control module 150 is also electrically connected to the second clock terminal CLB, so that the pull-down control module 150 can control the signal of the second node PD according to the signal of the first node PU, the first level signal Vgl of the first level terminal VGL, the second level signal Vgh of the second level terminal VGH, and the second clock signal CKB of the second clock terminal CLB. For example, when the signal of the first node PU is an invalid level and the second clock signal CKB is an effective level, the pull-down control module 150 can transmit the second level signal Vgh of the second level terminal VGH to the second node PD, so that the signal of the second node PD is an effective level; and when the signal of the first node PU is an effective level, the pull-down control module 150 can transmit the first level signal Vgl of the first level terminal VGL to the second node PD, so that the signal of the second node PD is an invalid level. In this way, by setting the pull-down control module 150 in the shift register unit ASG, the signal of the first node PU can be inverted with the signal of the second node PD.

[0211] Among them, the second clock signal CKB of the second clock terminal CLB can be the same as or different from the first clock signal CK of the first clock terminal CLK, and can be specifically designed according to actual needs. In an optional embodiment, the second clock signal CKB of the second clock terminal CLB can be the same as the first clock signal CK of the first clock terminal CLK. In this case, the first clock terminal CLK can be electrically connected to the second clock terminal CLB, so that the first clock terminal CLK and the second clock terminal CLB receive the same clock signal, which is beneficial to reduce the number of signals provided to the shift register unit ASG, reduce the number of clock signal lines used to transmit clock signals, and thus help simplify the structure of the display panel, and help narrow the border of the display panel. In other optional embodiments, the second clock signal CKB of the second clock terminal CLB can be different from the first clock signal CK of the first clock terminal CLK, for example, the first clock signal CK of the first clock terminal CLK is inverted with the second clock signal CKB of the second clock terminal CLB, that is, when the first clock signal CK is at a valid level, the second clock signal CK is at an invalid level, and when the first clock signal CK is at an invalid level, the second clock signal CK is at a valid level. On the premise that the signals at the first node PU and the second node PD can be controlled to be inverted by the pull-down control module 150 , the embodiment of the present invention does not specifically limit the first clock signal CK and the second clock signal CKB.

[0212] In an exemplary embodiment, Fig.33As shown, when the shift register unit ASG includes the second level terminal VGH and the second clock terminal CLB at the same time, and the second level terminal VGH is used to receive the second level signal, and the second clock terminal CLB is used to receive the second clock signal CKB, the second signal terminal SIG2 can be electrically connected to the second clock terminal CLB, and the first signal terminal SIG1 and the third signal terminal SIG3 can be electrically connected to the second level terminal VGH, that is, the gate of the first transistor M1 can be electrically connected to the second clock terminal CLB, and the first electrode of the first transistor M1 and the first electrode of the second transistor M2 can be electrically connected to the second level terminal VGH. At this time, the first transistor M1 can be turned on or off under the control of the second clock signal CKB, and when the second clock signal CKB is at a valid level and the signal of the first node PU is at an invalid level, The first transistor M1 can transmit the second level signal Vgh to the gate of the second transistor M2 to control the conduction of the second transistor M2, so that the second level signal Vgh can be transmitted to the second node PD, and the signal of the second node PD is a valid level; when the signal at the first node PU is a valid level, the fourth transistor M4 will transmit the first level signal Vgl to the gate of the second transistor M2, so that the gate signal of the second transistor M2 is pulled down to less than the second level signal Vgh, and the voltage difference between the gate signal of the second transistor M2 and its first pole signal will be less than the threshold voltage of the second transistor M2, so that the second transistor M2 is in a closed state, and at the same time, the third transistor M3 can transmit the first level signal Vgl to the second node PD, so that the signal of the second node PD is an invalid level.

[0213] It can be understood that, since the second clock signal CLB can alternate between the effective level and the ineffective level at a certain period, that is, the signal received by the gate of the first transistor M1 is not a fixed signal, and when the second clock signal CLB is at the effective level, the first transistor M1 is in the on state, and when the second clock signal CLB is at the ineffective level, the first transistor M1 is in the off state, so that the first transistor M1 can be prevented from being on for a long time, causing the first transistor M1 to have a hysteresis phenomenon and affecting the characteristic curve of the first transistor M1. When the characteristic curve of the first transistor M1 changes, the threshold of the first transistor M1 will drift, so that the first transistor M1 cannot accurately transmit the first signal Vsig1 of the first signal terminal SIG1 to the gate of the second transistor M2, and thus cannot accurately control the second transistor M2 to be turned on or off, thereby affecting the accuracy of the signal of the second node PD. In this embodiment, by electrically connecting the gate of the first transistor M1 to the second clock terminal CLB, the hysteresis phenomenon of the first transistor M1 is improved, so as to ensure that the second transistor M2 is accurately turned on or off, and ensure that the second transistor M2 accurately provides the third signal Vsig3 of the third signal terminal SIG3 to the second node PD, so that the signal of the second node PD can accurately control the pull-down module 140 to be turned on or off, and then can accurately control the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT, which is beneficial to improving the signal output accuracy of the shift register unit ASG.

[0214] It should be noted that the above only exemplifies the connection method between the first transistor M1 and the second transistor M2 of the shift register unit ASG and the second clock terminal CLB and the second level terminal VGH. In the embodiment of the present invention, the connection method of the first transistor M1 and the second transistor M2 is not limited to this. On the premise that the shift register unit ASG includes the second clock terminal CLB and the second signal terminal SIG2 is electrically connected to the second clock terminal CLB to improve the threshold drift phenomenon of the first transistor M1, the connection relationship between the first signal terminal SIG1 and the third signal terminal SIG3 can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0215] In an optional embodiment, continue to refer to Fig.30, when the shift register unit ASG includes a second clock terminal CLB, and the second clock terminal CLB is used to receive a second clock signal CKB, in the same shift register unit ASG, the pull-down control module 150 is also electrically connected to the second clock terminal CKB. At this time, the pull-down control module 150 can control the signal of the second node PD according to the second clock signal CKB of the second clock terminal CLB, the signal of the first node PU and the first level signal Vgl of the first level terminal VGL. For example, when the second clock signal CKB of the second clock terminal CLB is at a valid level and the signal of the first node PU is at an invalid level, the pull-down control module 150 can control the signal of the second node PD to be at the same valid level as the second clock terminal CKB; conversely, when the signal of the first node PU is at a valid level, the pull-down control module 150 can control the signal of the second node PD to be consistent with the first level signal Vgl, that is, the signal of the second node PD is at an invalid level.

[0216] Among them, when the pull-down control module 150 is electrically connected to the second clock terminal CLB, the first level terminal VGL, the first node PU and the second node PD respectively, the pull-down control module 150 does not need to be electrically connected to the second level terminal VGH, and can also realize the control of the signal of the second node PD. At this time, the second level terminal VGH may not be set in the shift register unit ASG, which is beneficial to simplify the structure of the shift register unit ASG and reduce the number of signals provided to the shift register unit ASG, which is beneficial to reduce the driving cost of the driving circuit.

[0217] In an exemplary embodiment, in conjunction with reference Fig.30 and Fig.31 The first signal terminal SIG1, the second signal terminal SIG2 and the third signal terminal SIG3 are all electrically connected to the second clock terminal CLB.

[0218] Among them, since the signal of the second clock terminal CLB alternates between the effective level and the ineffective level, the first transistor M1 can be controlled to alternate between the on state and the off state, so as to prevent the hysteresis phenomenon caused by the long-term conduction of the first transistor M1; at the same time, when the first signal terminal SIG1, the second signal terminal SIG2 and the third signal terminal SIG3 are all electrically connected to the second clock terminal CLB, the first transistor M1 can be turned on only when the second clock signal CKB is at the effective level, and the signal transmitted to the gate of the second transistor M2 is also the effective level of the second clock signal CKB. The effective level of the second clock signal CKB can control the second transistor M2 to be turned on, so that the second transistor M2 can transmit the effective level of the second clock signal CKB to the second node PD, so that the signal of the second node PD is at the effective level; and when the second clock signal CKB at the second clock terminal CLB is at the ineffective level, both the first transistor M1 and the second transistor M2 cannot be turned on, so that the second node PD can maintain the signal written in the previous stage, so as to ensure the accuracy of the signal of the second node PD. In this way, by electrically connecting the first signal terminal SIG1, the second signal terminal SIG2 and the third signal terminal SIG3 to the second clock terminal CLB, the accuracy of the signal at the second node PD can be ensured while simplifying the structure of the shift register unit ASG and improving the hysteresis phenomenon of the first transistor M1, which is beneficial to improving the accuracy of the gate drive signal Gout output by the shift register unit ASG.

[0219] Based on the above embodiment, optionally, refer to Fig.14 , Fig.16 and Fig.18In any of the figures, the pull-down module 140 may include a ninth transistor M9 and a tenth transistor M10, a gate of the ninth transistor M9 and a gate of the tenth transistor M10 are both electrically connected to the second node PD, a first electrode of the ninth transistor M9 and a first electrode of the tenth transistor M10 are both electrically connected to the first level terminal VGL, a second stage of the ninth transistor M9 is electrically connected to the first node PU, and a second stage of the tenth transistor M10 is electrically connected to the signal output terminal OUT. In this way, the signal of the second node PD can simultaneously control the ninth transistor M9 and the tenth transistor M10 to be turned on or off. When the signal of the second node PD controls the ninth transistor M9 and the tenth transistor M10 to be turned on, the ninth transistor M9 can transmit the first level signal Vgl of the first level end VGL to the first node PU, so that the signal of the first node PU is consistent with the first level signal Vgl, that is, the signal of the first node PU is an invalid level. At the same time, the tenth transistor M10 can transmit the first level signal Vgl of the first level end VGL to the signal output end OUT, so that the gate drive signal Gout output by the signal output end OUT can be consistent with the first level signal Vgl, that is, the signal output end OUT outputs the invalid level of the gate drive signal Gout.

[0220] Based on the above embodiment, optionally, refer to Fig.14 , Fig.16 and Fig.18 In any of the figures, the input module 110 includes a fifth transistor M5, a first electrode and a gate of the fifth transistor M5 are electrically connected to the signal input terminal IN and electrically connected to the second level terminal VGH, and a second electrode of the fifth transistor M5 is electrically connected to the first node PU, so that the fifth transistor M5 can be turned on or off under the control of the input signal Vin received by the signal input terminal IN, and when the input signal Vin of the signal input terminal IN is at a valid level, the fifth transistor M5 can transmit the valid level of the input signal Vin to the first node PU, and control the signal of the first node PU to be a valid level.

[0221] In other optional embodiments, Fig.34 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.34As shown, when the shift register unit ASG further includes a second level terminal VGH, and the second level terminal VGH is used to provide a second level signal Vgh, the input module 110 includes a fifth transistor M5, at which time the first electrode of the fifth transistor M5 is electrically connected to the second level terminal VGH, the second electrode of the fifth transistor M5 is electrically connected to the first node PU, and the gate of the fifth transistor M5 is electrically connected to the signal input terminal IN. At this time, when the input signal Vin of the signal input terminal IN controls the fifth transistor M5 to be turned on, the fifth transistor M5 can transmit the second level signal Vgh to the first node PU, so that the signal of the first node PU can be consistent with the second level signal Vgh, that is, the signal of the first node PU can be a valid level.

[0222] It should be noted that the above exemplary embodiments respectively describe that the first electrode of the fifth transistor M5 is electrically connected to the signal input terminal IN and the second level terminal VGH. The specific connection method of the fifth transistor M5 can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. For the convenience of description, without special limitations, the embodiments of the present invention take the gate and the first electrode of the fifth transistor M5 as being electrically connected to the signal input terminal IN, and the gate of the first transistor M1, the first electrode of the first transistor M1, and the first electrode of the second transistor M2 as being electrically connected to the second clock terminal CLB as an example to exemplify the technical solution of the embodiment of the present invention.

[0223] Optionally, based on the above embodiment, Fig.35 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.35 As shown, the shift register unit ASG may further include a voltage-stabilizing transistor M51 and a voltage-stabilizing control terminal VGH1. The voltage-stabilizing transistor M51 may be electrically connected between the input module 110 and the first node PU, that is, when the input module 110 includes a fifth transistor M5, the first electrode of the voltage-stabilizing transistor M51 may be electrically connected to the second electrode of the fifth transistor M5, the second electrode of the voltage-stabilizing transistor M51 may be electrically connected to the first node PU, and the gate of the voltage-stabilizing transistor M51 may be electrically connected to the voltage-stabilizing control terminal VGH1.

[0224] Among them, the voltage-stabilizing transistor M51 can stabilize the signal of the second pole of the fifth transistor M5 and the first node PU. When the second pole of the fifth transistor M5 and the signal of the first node PU are both within the set range, the voltage-stabilizing transistor M51 can be in an on state, and the signal of the second pole of the fifth transistor M5 can be transmitted to the first node PU through the voltage-stabilizing transistor M51. At this time, the output module 120 can be electrically connected to the second pole of the fifth transistor M5 through the voltage-stabilizing transistor M51, so that the output module 120 can receive the signal of the first node PU that is the same as the signal of the second pole of the fifth transistor M5; and when the voltage of the signal of the second pole of the fifth transistor M5 and / or the signal of the first node PU is too high or too low, the voltage-stabilizing transistor M51 can be in an off state to prevent the signal of the first node PU from affecting the signal of the second pole of the fifth transistor M5, or the signal of the second pole of the fifth transistor M5 from affecting the signal of the first node PU. In this way, by setting the voltage-stabilizing transistor M51 in the shift register unit ASG, the second electrode of the fifth transistor M5 and the first node PU can be isolated, ensuring that the signals of the second electrode of the fifth transistor M5 and the first node PU are relatively stable, and preventing the accuracy of the gate drive signal Gout output by the shift register unit ASG from being affected by signal fluctuations of the second electrode of the fifth transistor M5 and / or signal fluctuations of the first node PU, thereby helping to improve the working stability of the shift register unit ASG, and further helping to improve the display effect of the display panel.

[0225] In an optional embodiment, when the shift register unit ASG includes a second level terminal VGH, the voltage regulation control terminal VGH1 can reuse the second level terminal VGH to reduce the number of signal terminals in the shift register unit ASG, simplify the structure of the shift register unit ASG, reduce the number of signals provided to the shift register unit ASG, and reduce the control cost of the shift register unit ASG.

[0226] Based on the above embodiment, optionally, continue to refer to Fig.35The restoration module 130 includes a sixth transistor M6 and / or a seventh transistor M7, a first electrode of the sixth transistor M6 is electrically connected to the first level end VGL, a second electrode of the sixth transistor M6 is electrically connected to the first node PU, and a gate of the sixth transistor M6 is electrically connected to the restoration signal end REST; a first electrode of the seventh transistor M7 is electrically connected to the first level end VGL, a second electrode of the seventh transistor M7 is electrically connected to the signal output end OUT, and a gate of the seventh transistor M7 is electrically connected to the restoration signal end REST. In this way, the restoration signal Vrest of the restoration signal terminal REST can control the sixth transistor M6 and the seventh transistor M7 to be turned on or off, and when the restoration signal Vrest controls the sixth transistor M6 and the seventh transistor M7 to be turned on, the sixth transistor M6 can transmit the first level signal Vgl to the first node PU, and the seventh transistor M7 can transmit the first level signal Vgl to the signal output terminal OUT, so that the first node PU is an invalid level, and the signal output terminal OUT continues to output the invalid level of the gate drive signal Gout; and when the restoration signal Vrest controls the sixth transistor M6 and the seventh transistor M7 to be turned off, the sixth transistor M6 cannot transmit the first level signal Vgl to the first node PU, and the seventh transistor M7 cannot transmit the first level signal Vgl to the signal output terminal OUT, so that the signal of the first node PU can be controlled by the signal provided by the input module 110, and the gate drive signal Gout output by the signal output terminal OUT can be controlled by the signal provided by the output module 120.

[0227] It can be understood that in the embodiment of the present invention, the restoration module 130 of the shift register unit ASG may only include the sixth transistor M6, or the restoration module 130 may only include the seventh transistor M7, or the restoration module 130 may also include the sixth transistor M6 and the seventh transistor M7 at the same time. The specific design can be based on actual needs, and the embodiment of the present invention does not make any specific limitation on this.

[0228] Optionally, the output module 120 may include an eighth transistor M8, a gate of the eighth transistor M8 may be electrically connected to the first node PU, a first electrode of the eighth transistor M8 may be electrically connected to the first clock terminal CLK, and a second electrode of the eighth transistor M8 may be electrically connected to the signal output terminal OUT, so that the eighth transistor M8 can be turned on or off under the control of the signal of the first node PU, and when the eighth transistor M8 is turned on, the first clock signal CK of the first clock terminal CLK can be transmitted to the signal output terminal OUT, so that the gate drive signal Gout output by the signal output terminal OUT can be consistent with the first clock signal CK.

[0229] On the basis of the above embodiment, optionally, the shift register unit ASG may further include a bootstrap capacitor C0 for driving the signal of the first node PU to change when the gate driving signal Gout changes.

[0230] Exemplarily, the bootstrap capacitor C0 is electrically connected between the first node PU and the signal output terminal OUT. When the first node PU is at a valid level, the output module 120 is turned on, and the first clock signal CK can be transmitted to the signal output terminal OUT; when the first clock signal CK changes from an invalid level to a valid level, the gate drive signal Gout output by the signal output terminal OUT also changes from an invalid level to a valid level, so that the signal at one end of the bootstrap capacitor C0 is raised. Affected by the coupling effect of the bootstrap capacitor C0, the signal at the other end of the bootstrap capacitor C0 will also be raised, that is, the signal of the first node PU will also be raised, so that the voltage of the first node PU is higher than the voltage of the first clock terminal CLK and the signal output terminal OUT, which is beneficial to the full opening of the output module 120. In this way, the opening degree of the output module 120 can be increased, and the output capacity of the output module 120 can be improved.

[0231] Based on the above embodiment, optionally, continue to refer to Fig.35 The shift register unit ASG also includes a first reset module 161 and a first reset signal terminal REF1; in the same shift register unit ASG, the first reset module 161 is electrically connected to the first reset signal terminal REF1, the first level terminal VGL and the first node PU respectively; the first reset signal terminal REF1 is used to receive the first reset signal Vref1; at least part of the time of the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the first reset signal Vref1.

[0232] Specifically, the first reset module 161 can control the signal of the first node PU according to the first reset signal Vref1 of the first reset signal terminal REF1 and the first level signal Vgl of the first level terminal VGL. For example, when the first reset signal Vref1 is at a valid level, the first reset module 161 can transmit the first level signal Vgl to the first node PU, so that the signal of the first node PU is consistent with the first level signal Vgl. When the first reset signal Vref1 is at an invalid level, the first reset module 161 cannot transmit the first level signal Vgl to the first node PU, so that the signal of the first node PU can be controlled by the signal provided by the input module 110 or the restoration module 130. At the same time, since the output module 120 can be controlled to provide the first clock signal CK to the signal output terminal OUT when the signal at the first node PU is at a valid level, so that the signal output terminal OUT can output a valid pulse of the gate drive signal Gout, therefore, by ensuring that at least part of the time of the valid pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the valid pulse time of the first reset signal Vref1, it can be ensured that at least part of the time of the valid pulse of the gate drive signal Gout output by the signal output terminal OUT, the first reset module 161 will not transmit the first level signal Vgl to the first node PU, thereby avoiding the situation where the conduction state of the output module 120 is affected by the change of the signal at the first node PU, so that the output module 120 cannot accurately transmit the first clock signal CK to the signal output terminal OUT, thereby ensuring the accuracy of the gate drive signal Gout output by the signal output terminal OUT.

[0233] In an optional embodiment, the first reset module 161 may include an eleventh transistor M11, a gate of the eleventh transistor M11 is electrically connected to the first reset signal terminal REF1, a first electrode of the eleventh transistor M11 is electrically connected to the first level terminal VGL, and a second electrode of the eleventh transistor M11 is electrically connected to the first node PU, so that the first reset signal Vref1 of the first reset signal terminal REF1 can control the eleventh transistor M11 to be turned on or off, and when the first reset signal Vref1 controls the eleventh transistor M11 to be turned on, the eleventh transistor M11 can transmit the first level signal Vgl to the first node PU to reset the first node PU.

[0234] It can be understood that at least part of the time of the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the first reset signal Vref1, that is, the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the first reset signal Vref1, or, part of the time of the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the first reset signal Vref1. The specific design can be made according to actual needs. The embodiment of the present invention does not make specific limitations on this. For the sake of convenience of description, without special limitations, the embodiments of the present invention take the example that the effective pulse time of the gate drive signal Gout of the same shift register unit ASG does not overlap with the effective pulse time of the first reset signal Vref1 as an example to exemplarily illustrate the working process of the shift register unit in the embodiment of the present invention.

[0235] In an exemplary embodiment, the working process of the second shift register unit in the first type of shift register unit is taken as an example, and combined with reference Fig.35 and Fig.36 In the T00 stage, the first valid pulse of the restoration signal Vrest of the restoration signal terminal REST can control the sixth transistor M6 and the seventh transistor M7 to be in the on state, so that the first level signal Vgl of the first level terminal VGL can be transmitted to the first node PU and the signal output terminal OUT respectively, so that the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT are kept at an invalid level, preventing the start valid pulse jump of the first clock signal received by the first shift register unit from affecting the signal of the first node PU of the shift register unit ASG and the gate drive signal Gout output by the signal output terminal OUT. At this time, because the first node PU is at an invalid level, the eighth transistor M8 is in a closed state, and the first clock signal CK cannot be transmitted to the signal output terminal OUT, so that the signal output terminal OUT outputs the invalid level of the gate drive signal Gout.

[0236] After the T00 stage and before the T10 stage, when the second clock signal CKB becomes a valid level, the first transistor M1 and the second transistor M2 can be controlled to be in a turned-on state, so that the valid level of the second clock signal CKB can be transmitted to the second node PD, so that the signal of the second node PD becomes a valid level; the valid level of the second node PD will control the ninth transistor M9 and the tenth transistor M10 to be in a turned-on state, so that the first level signal Vgl is transmitted to the first node PU and the signal output terminal OUT through the ninth transistor M9 and the tenth transistor M10 respectively, so as to control the first node PU to remain at an invalid level, and the signal output terminal OUT outputs the invalid level of the gate drive signal Gout.

[0237] In the T10 stage, the first clock signal CK is at an invalid level, the second clock signal CKB is at an effective level, the input signal Vin is at an effective level, the fifth transistor M5 is in a conducting state, the input signal Vin is transmitted to the first node PU, and the first node PU becomes at an effective level. At this time, the third transistor M3, the fourth transistor M4 and the eighth transistor M8 are all in a conducting state, and the fourth transistor M4 transmits the first level signal Vgl to the gate of the second transistor M2, so that the voltage difference between the gate voltage of the second transistor M2 and the effective level of the first clock signal CKB of its first stage cannot meet the conduction condition of the second transistor M2, and the second transistor M2 is in a closed state, and the second transistor M2 no longer provides the second node PD. The effective level of the clock signal CKB; the third crystal M3 transmits the first level signal Vgl to the second node PD, so that the signal of the second node PD becomes an invalid level; under the invalid level control of the second node PD, the ninth transistor M9 and the tenth transistor M10 are in a closed state, and the first level signal Vgl cannot be transmitted to the first node PU and the signal output terminal OUT; the eighth transistor M8 can transmit the first clock signal CK to the signal output terminal OUT, so that the gate drive signal Gout output by the signal output terminal OUT is consistent with the first clock signal CK, and because the first clock signal CK is an invalid level in this stage, the gate drive signal Gout output by the signal output terminal OUT continues to remain at an invalid level.

[0238] In the T20 stage, the input signal becomes an invalid level, and the input transistor M5 is in a closed state; the first clock signal CK is a valid level, and the second clock signal CKB is an invalid level. Under the premise that no new signal is written to the gates of the transistors in the shift register unit ASG, the signal of the second node PD can be maintained at an invalid level, and the signal of the first node PU can also be maintained at a valid level. The eighth transistor M8 continues to remain in the on state, and the eighth transistor M8 transmits the valid level of the first clock signal CK to the signal output terminal OUT, so that the signal output terminal OUT outputs the valid level of the gate drive signal Gout; at the same time, when the gate drive signal Gout outputted from the signal output terminal OUT jumps from an invalid level to a valid level, the signal of the first node PU will change due to the coupling effect of the bootstrap capacitor C0, so that the first node PU has a higher level, and the signal of the first node PU can make the eighth transistor M8 have a higher degree of conduction, so that the eighth transistor M8 can accurately transmit the first clock signal CK to the signal output terminal OUT.

[0239] In the T30 stage, the input signal Vin continues to maintain an invalid level, and the fifth transistor M05 continues to remain in a closed state; the second clock signal CKB and the first reset signal Vref1 both become valid levels, the eleventh transistor M11 is turned on under the control of the first reset signal Vref1, and the first transistor M1 is turned on under the control of the second clock signal CKB, so that the eleventh transistor M11 can reset the signal of the first node PU to an invalid level, the third transistor M3, the fourth transistor M4 and the eighth transistor M8 are all in a closed state, and the gate signal of the second transistor M2 is controlled by the second clock signal CKB transmitted by the first transistor M1, so that the second transistor M2 is in a turned-on state. At this time, the second clock signal CKB can be transmitted to the second node PD through the second transistor M2, so that the signal of the second node PD becomes a valid level, and the ninth transistor M9 and the tenth transistor M10 are turned on under the control of the valid level of the second node PD, so that the signal of the first node PU and the gate drive signal Gout both become invalid levels.

[0240] In the T40 stage, the input signal Vin continues to maintain an invalid level, the second clock signal CKB becomes an invalid level, the first clock signal CK is a valid level, and under the premise that no new signal is written, the signal of the second node PD can be maintained at a valid level, the signal of the first node PU is maintained at an invalid level, the eighth transistor M8 is turned off, the ninth transistor M9 and the tenth transistor M10 are continuously in the on state, and the gate drive signal Gout is maintained at an invalid level.

[0241] After stage T40, since the signal of the first node PU continues to maintain an inactive level, the eighth transistor M8 is in a turned-off state, and the signal output terminal OUT continues to output the inactive level of the gate driving signal Gout until the next frame period arrives.

[0242] In an alternative embodiment, Fig.37 is a partial structural diagram of another display panel provided by an embodiment of the present invention, such as Fig.37 As shown, when the first clock signal CK and the second clock signal CKB received by the same shift register unit ASG are inverted, the second clock terminal CLB of the i-th shift register unit ASGi and the first clock terminal CLK of the i+N-th shift register unit ASGi+N can be electrically connected to the same clock signal line. For example, when N is equal to 4, the second clock terminal CLB of the fifth-level shift register unit ASG5 and the first clock terminal CLK of the eighth-level shift register unit ASG8 can both be electrically connected to the fifth clock signal line 65. In this way, there is no need to separately set a clock signal line for transmitting the second clock signal CKB, which is beneficial to reduce the number of signal lines set in the display panel, simplify the structure of the display panel, and facilitate a narrow frame of the display panel.

[0243] It can be understood that, in the same shift register unit ASG, the first reset signal Vref1 of the first reset signal terminal REF1 can control the first reset module 161 to reset the first node PU, and after the first node PU is reset, the output module 120 will not be able to output the first clock signal CK to the signal output terminal OUT. Therefore, in order to ensure that the effective pulse of the first clock signal CK is completely transmitted to the signal output terminal OUT, so that the effective level time of the gate drive signal Gout output by the shift register unit ASG is long enough, the effective pulse of the first reset signal Vref1 can be set to be after the effective level of the gate drive signal Gout.

[0244] In an optional embodiment, in conjunction with reference Fig.35 and Fig.37 , the first reset signal terminal REF1 of the i-th stage shift register unit ASGi is electrically connected to the signal output terminal OUT of the j-th stage shift register unit ASGj; j>i, and i and j are both positive integers; wherein, j=i+N.

[0245] It can be understood that the gate drive signal Gout output by each level of shift register ASG in the driving circuit 10 is shifted in sequence, and when the gate drive signal Gout output by the i-th level shift register ASGi is used as the input signal Vini+N of the i+N-th level shift register ASGi+N, the effective level time of the gate drive signal Gouti+N output by the signal output terminal OUT of the i+N-th level shift register ASGi+N will be after the input signal Vin it receives, that is, the effective level time of the gate drive signal Gouti+N output by the signal output terminal OUT of the i+N-th level shift register ASGi+N is after the effective level time of the gate drive signal Gout output by the i-th level shift register ASGi. In this way, by making j=i+N, the gate drive signal Gouti+N outputted by the signal output terminal OUT of the i+N-th shift register unit ASGi+N can be used as the first reset signal Vref1i of the first reset signal terminal REF1 of the i-th shift register unit ASGi, so that after the i-th shift register unit ASGi outputs the effective level of the gate drive signal Gout, the effective level of the gate drive signal Gouti+N outputted by the i+N-th shift register unit ASGi+N is used to control the first reset module REF1 in the i-th shift register unit ASGi to reset its first node PU, so that its first node PU becomes an invalid level, thereby controlling its output module 120 to stop transmitting the first clock signal CK to its signal output terminal OUT, and the signal output terminal OUT of the i-th shift register unit ASGi can continuously output the invalid level of the gate drive signal Gout. In this way, under the premise of ensuring the accuracy of the gate drive signal output by the shift register unit ASG, there is no need to reset the first node PU in each level of the shift register unit ASG, and an additional first reset signal Vref1 is provided for each level of the shift register unit, which is beneficial to reducing the number of signals provided to the driving circuit 10 and reducing the control cost of the driving circuit 10.

[0246] In other optional embodiments, Fig.38 is a partial structural diagram of another display panel provided by an embodiment of the present invention, combined with reference Fig.35 and Fig.38As shown, when the first reset signal terminal REF1 of the i-th shift register unit ASGi is electrically connected to the signal output terminal OUT of the j-th shift register unit ASGj, the value of j can also be i+N+1, that is, the signal output terminal gate drive signal Gouti+N+1 output by the i+N+1-th shift register unit ASGi+N+1 can control the first reset module 161 in the i-th shift register unit ASGi to reset the first node PU of the i-th shift register unit ASGi. Compared with using the i+N-th shift register unit ASGi+N to provide a signal to the first reset signal terminal REF1 of the i-th shift register unit ASGi, using the i+N+1-th shift register unit ASGi+N+1 to provide a signal to the first reset signal terminal REF1 of the i-th shift register unit ASGi can increase the duty cycle, which is friendly to the charging of the first node PU of the i-th shift register unit ASGi.

[0247] It should be noted that the above is only an illustrative example of the technical solution of the embodiment of the present invention using j=i+N or i+N+1 as an example. In the same shift register unit, under the premise that the effective level of the first reset signal Vref1 received by the first reset signal terminal REF1 is later than the effective level of the gate drive signal Gout output by its signal output terminal OUT, the embodiment of the present invention does not make any specific limitation on this.

[0248] Based on the above embodiment, optionally, Fig.39 is a partial structural diagram of another display panel provided by an embodiment of the present invention, combined with reference Fig.35 and Fig.39As shown, when the display panel 100 further includes a plurality of gate signal lines 31, a plurality of pixels 20, and a first reset signal line 80, and the gate signal lines 31 are electrically connected to the pixels 20, the second shift register unit includes a driving shift register unit and a virtual shift register unit. The driving shift register unit provides a gate driving signal Gout to the gate signal lines 31, and the virtual shift register unit does not provide a gate driving signal Gout to the gate signal lines 31. If the driving shift register unit and the virtual shift register unit further include a first reset module 161 and a first reset signal terminal REF1, and in the same shift register unit, the first reset module 161 is respectively electrically connected to the first reset signal terminal REF1, the first level terminal VGL, and the first node PU, then when the i-th stage shift register unit is a driving shift register unit and the p-th stage shift register unit is a virtual shift register unit, the first reset signal terminal REF1 of the i-th stage shift register unit ASGi can be electrically connected to the signal output terminal OUT of the j-th stage shift register unit ASGj, and the first reset signal terminal REF1 of the p-th stage shift register unit ASGp is electrically connected to the first reset signal line 80. Wherein, i, j, and p are all positive integers, and i + N ≤ j < i + 2N; the first reset signal line 80 provides a reset valid pulse, and the reset valid pulse is the same as the first valid pulse.

[0249] Exemplarily, Fig.40 is another driving timing diagram of a display panel provided by an embodiment of the present invention. With reference to Fig.35 、 Fig.39 and Fig.40 , taking j = i + N and the driving circuit 10 including S-stage shift register units as an example, the (S - 7)-th stage shift register unit ASGS - 7 to the (S - 4)-th stage shift register unit ASGS - 4 are all driving shift register units in the second shift register unit, and the (S - 3)-th stage shift register unit ASGS - 3 to the S-th stage shift register unit ASGS are all virtual shift register units in the second shift register unit. At this time, the signal output terminals OUT of the shift register units ASG in the (S - 7)-th stage shift register unit ASGS - 7 to the (S - 4)-th stage shift register unit ASGS - 4 can be respectively electrically connected to the respective gate signal lines 31 to respectively provide a gate driving signal Gout to the respective gate signal lines 31. The signal output terminals OUT of the shift register units ASG in the (S - 3)-th stage shift register unit ASGS - 3 to the S-th stage shift register unit ASGS are not electrically connected to the gate signal lines 31, so that the shift register units ASG in the (S - 3)-th stage shift register unit ASGS - 3 to the S-th stage shift register unit ASGS do not need to provide a gate driving signal Gout to the gate signal lines 31.

[0250] At the same time, since the first reset signal terminal REF1 of the i-th level shift register unit ASGi can be electrically connected to the signal output terminal OUT of the j-th level shift register unit ASGj, that is, the signal output terminal OUT of the S-3-th level shift register unit ASGS-3 is electrically connected to the first reset signal terminal REF1 of the S-7-th level shift register unit ASGS-7, the gate drive signal GoutS-3 output by the S-3-th level shift register unit ASGS-3 can be used as the first reset signal Vref1 of the S-7-th level shift register unit ASGS-7 to control the first reset module 161 of the S-7-th level shift register unit ASGS-7 to reset its first node PU. The other levels of shift register units from the S-7-th level shift register unit ASGS-7 to the S-th level shift register unit ASGS have similar connection relationships. In this way, by using the gate drive signal output by the virtual shift register unit to control the first reset module in the driving shift register unit to reset its first node, it is possible to ensure that the last N stages of driving shift register units can be accurately reset and accurately output gate drive signals, thereby improving the accuracy of the gate drive signals output by each stage of the shift register unit.

[0251] In addition, the first reset signal terminal REF1 of the S-3-th shift register unit ASGS-3 to the S-th shift register unit ASGS is electrically connected to the first reset signal line 80, so that the shift register units at each level in the S-3-th shift register unit ASGS-3 to the S-th shift register unit ASGS can reset their respective first nodes PU under the control of the reset pulse signal transmitted by the first reset signal line 80; and, since the reset pulse signal transmitted by the first reset signal line 80 is the same as the first valid pulse, that is, the effective level starting time of the reset pulse signal is the same as the starting time T1 of the first valid pulse, and the effective pulse ending time of the reset pulse signal is the same as the ending time T3 of the first valid pulse, so that when the first reset module 161 resets the first node PU, the restoration module 130 can respectively restore the signals of the first node PU and the signal output terminal OUT, so that the signal of the first node PU and the gate drive signal Gout output by the signal output terminal OUT are both maintained at an invalid level, ensuring that the shift register units at each level can accurately output the gate drive signal.

[0252] Optionally, based on the above embodiment, Fig.41 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.41As shown, the shift register unit ASG also includes a second reset module 162 and a second reset signal terminal REF2; in the same shift register unit ASG, the second reset module 162 is electrically connected to the second reset signal terminal REF2, the first level terminal VGL and the signal output terminal OUT respectively; the second reset signal terminal REF2 is used to receive the second reset signal Vref2; at least part of the time of the effective pulse of the gate drive signal output by the signal output terminal OUT does not overlap with the effective pulse time of the second reset signal REF2.

[0253] Specifically, the second reset module 162 can control the gate drive signal Gout output by the signal output terminal OUT according to the second reset signal Vref2 of the second reset signal terminal REF2 and the first level signal Vgl of the first level terminal VGL. For example, when the second reset signal Vref2 is at a valid level, the second reset module 162 can transmit the first level signal Vgl to the signal output terminal OUT, so that the gate drive signal Gout output by the signal output terminal OUT is consistent with the first level signal Vgl. When the second reset signal Vref2 is at an invalid level, the second reset module 162 cannot transmit the first level signal Vgl to the signal output terminal OUT, so that the signal at the signal output terminal OUT can be controlled by the signal provided by the output module 120 or the restoration module 130.

[0254] At the same time, since the gate drive signal Gout is at an invalid level when it is consistent with the first level signal Vgl, in order to prevent the accuracy of the gate drive signal Gout output from the signal output terminal OUT from being affected by the second reset module 162 transmitting the first level signal Vgl to the signal output terminal OUT during the effective level time of the gate drive signal Gout output from the signal output terminal OUT, at least part of the time of the effective pulse of the gate drive signal Gout output from the signal output terminal OUT can be set not to overlap with the effective pulse time of the second reset signal Vref2, thereby ensuring the accuracy of the gate drive signal Gout output from the signal output terminal OUT.

[0255] In an optional embodiment, continue to refer to Fig.41The second reset module 162 may include a twelfth transistor M12, a gate of the twelfth transistor M12 is electrically connected to the second reset signal terminal REF2, a first electrode of the twelfth transistor M12 is electrically connected to the first level terminal VGL, and a second electrode of the twelfth transistor M12 is electrically connected to the signal output terminal OUT, so that the second reset signal Vref2 of the second reset signal terminal REF2 can control the twelfth transistor M12 to be turned on or off, and when the second reset signal Vref2 controls the twelfth transistor M12 to be turned on, the eleventh transistor M11 can transmit the first level signal Vgl to the signal output terminal OUT to reset the signal output terminal OUT.

[0256] It can be understood that at least part of the time of the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the second reset signal Vref2, that is, the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the second reset signal Vref2, or, part of the time of the effective pulse of the gate drive signal Gout output by the signal output terminal OUT does not overlap with the effective pulse time of the second reset signal Vref2. The specific design can be based on actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0257] In an optional embodiment, continue to refer to Fig.41 , the first reset signal terminal REF1 is multiplexed as the second reset signal terminal REF2, and the first reset signal terminal REF1 and the second reset signal terminal REF2 can be electrically connected to the same reset signal line. At this time, the first reset module 161 and the second reset module 162 receive the same reset signal Vref, so that when the first reset module 161 resets the first node PU, the second reset module 162 also resets the signal output terminal OUT. In this way, there is no need to additionally set the second reset signal terminal REF2, nor is there any need to additionally provide the second reset signal Vref2, which is conducive to simplifying the structure of the shift register unit ASG, and reducing the number of signals provided to the shift register unit ASG, thereby helping to reduce the control cost of the shift register unit ASG.

[0258] Based on the above embodiment, optionally, Fig.42 is a structural diagram of another shift register unit provided by an embodiment of the present invention, Fig.43 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, and Fig.42 and Fig.43The shift register unit ASG also includes a third reset module 163 and a third reset signal terminal REF3. The third reset module 163 is electrically connected to the third reset signal terminal REF3, the third level terminal VGL1, and the second side signal output terminal respectively. The signal output terminal OUT of the shift register unit ASG is the first side signal output terminal.

[0259] Among them, the third reset module 163 can control the signal of the second side signal output end according to the third reset signal Vref3 of the third reset signal end REF3 and the third level signal Vgl1 of the third level end VGL1. For example, when the third reset signal Vref3 is at a valid level, the third reset module 163 can transmit the third level signal Vgl1 to the second side signal output end to reset the second side signal output end; conversely, when the third reset signal Vref3 is at an invalid level, the third reset module 163 stops resetting the second side signal output end.

[0260] In an exemplary embodiment, the third reset module 163 may include a thirteenth transistor M13, a gate of the thirteenth transistor M13 may be electrically connected to the third reset signal terminal REF3, a first electrode of the thirteenth transistor M13 may be electrically connected to the third level terminal VGL1, and a second electrode of the thirteenth transistor M13 may be electrically connected to the second side signal output terminal, so that the third reset signal Vref3 of the third reset signal terminal REF3 can control the thirteenth transistor M13 to be turned on or off, and when the thirteenth transistor M13 is turned on, the third level signal Vgl1 of the third level terminal VGL1 can be transmitted to the second side signal output terminal to reset the second side signal output terminal.

[0261] Continue to refer Fig.42 and Fig.43 The display panel 100 also includes a plurality of gate signal lines 31 and a plurality of pixels 20, the gate signal lines 31 are electrically connected to the pixels 20, and the gate signal lines 31 are electrically connected to the first side signal output terminal OUT and the second side signal output terminal respectively; along the extension direction of the gate signal lines 31, the output module 120 of the shift register unit ASG and the third reset module 163 are respectively located on the opposite sides of the gate signal lines 31.

[0262] Among them, since the gate signal line 31 is electrically connected to the first side signal output terminal OUT and the second side signal output terminal respectively, that is, the first side signal output terminal OUT is electrically connected to the second side signal output terminal through the gate signal line 31, the signals of the first side signal output terminal OUT and the second side signal output terminal are kept consistent, ensuring that the gate signal line 31 can stably transmit the corresponding gate drive signal. Among them, the output module 120 can transmit the first clock signal CK to the first side signal output terminal OUT under the control of the signal of the first node PU, so that the gate drive signal Gout output by the first side signal output terminal OUT can be consistent with the first clock signal CK; and the third reset module 163 can transmit the third level signal Vgl1 to the second side signal output terminal under the control of the third reset signal Vref3 to reset the second side signal output terminal. In this way, when the output module 120 transmits the invalid level of the first clock signal CK, the third reset signal Vref3 can control the third reset module 163 to transmit the third level signal Vgl1 to the second side signal output terminal to reset the second side signal output terminal, so that the first side signal output terminal OUT and the second side signal output terminal at both ends of the gate signal line 31 can simultaneously receive the invalid level of the gate drive signal Gout, thereby realizing a rapid reset of the gate drive signal Gout transmitted on the gate signal line 31, so that the gate drive signal Gout uploaded on the gate signal line 31 can quickly become an invalid level.

[0263] In addition, when the shift register unit ASG also includes a second reset module 162 and a second reset signal terminal REF2, the signal output terminal OUT of the i+N-th shift register unit ASG i+N can be electrically connected to the second reset signal terminal REF2 of the i-th shift register unit ASGi, so that the gate drive signal Gouti+N output by the i+N-th shift register unit ASG i+N can be used as the second reset signal Vref2 of the i-th shift register unit ASGi, so as to control the second reset module 162 in the i-th shift register unit ASGi to reset its first side signal output terminal OUT, that is, to reset the gate drive signal Gout transmitted on the gate signal line 31; at this time, by setting a third reset module 163 at the second side signal output terminal of the shift register unit ASG, the third reset module 163 is used to reset the gate drive signal Gout transmitted by the gate signal line 31 away from the first side signal output terminal OUT of the gate signal line 31, which can help reduce the i+N-th shift register unit ASG The amount of loading on the clock signal line that is electrically connected to i+N.

[0264] It can be understood that when the third reset module 163 transmits the third level signal Vgl1 of the third level terminal VGL1 to the second side signal output terminal, the second side signal output terminal can be reset, and the third level signal Vgl1 can be consistent with the invalid level of the gate driving signal Gout transmitted by the gate signal line 31. Among them, the third level signal Vgl1 of the third level terminal VGL1 can be the same as or different from the first level signal Vgl of the first level terminal VgL, which can be specifically designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0265] It should be noted that the above only exemplifies that the driving circuit 10 is located in the non-display area NA on one side of the display area AA. In the embodiment of the present invention, the specific arrangement of the driving circuit 10 can be designed according to actual needs. For example, the driving circuit 10 can also be located in the display area AA. In this case, a narrow frame of the display panel can be achieved. In other optional embodiments, the driving circuit can also be distributed in the non-display areas NA on the opposite sides of the display area AA, so that the non-display areas NA on the opposite sides of the display area AA are of comparable size, which is beneficial to the aesthetics of the display panel 100.

[0266] For example, Fig.44 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.44 As shown, the driving circuit may include a first driving circuit 101 and a second driving circuit 102, and the first driving circuit 101 and the second driving circuit 102 are respectively located in non-display areas NA on two opposite sides of the display area AA, that is, the first driving circuit 101 is located in the first non-display area NA1, and the second driving circuit 102 is located in the second non-display area NA2. In this way, by setting the first driving circuit 101 in the first non-display area NA1 and setting the second driving circuit 102 in the second non-display area NA2, the sizes of the first non-display area NA1 and the second non-display area NA2 can be kept consistent, that is, the frame sizes on the opposite sides of the display area AA of the display panel 100 are kept consistent, which is beneficial to improving the display uniformity of the display panel 100.

[0267] In addition, when the shift register unit ASG includes a third reset module 163, the third reset module 163 of each shift register unit ASG in the first driving circuit 101 can be located in the second non-display area NA2, and the third reset module 163 of each shift register unit ASG in the second driving circuit 102 can be located in the first non-display area NA1. At this time, the third level signal terminal VGL1 of each shift register unit ASG in the first driving circuit 101 can be electrically connected to the same first level signal line as the first level terminal VGL of each shift register unit ASG in the second driving circuit 102, and the third level signal terminal VGL1 of each shift register unit ASG in the second driving circuit 102 can be electrically connected to the same first level signal line as the first level terminal VGL of each shift register unit ASG in the first driving circuit 101. In this way, the number of signal lines set in the non-display area NA can be reduced, which is beneficial to reducing the size of the non-display area NA, and at the same time, the number of signals provided to each driving circuit is reduced, which is beneficial to reducing the control cost of the driving circuit.

[0268] Based on the above embodiment, optionally, Fig.45 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Fig.45 As shown, the shift register unit ASG further includes a noise reduction module 170; in the same shift register unit ASG, the noise reduction module 170 is electrically connected to the signal input terminal IN, the first level terminal VGL and the second node PD respectively.

[0269] The noise reduction module 170 can control the signal of the second node PD according to the input signal Vin of the signal input terminal IN and the first level signal VGL of the first level terminal VGL. For example, when the input signal Vin of the signal input terminal IN is at a valid level, the noise reduction module 170 can control the first level signal VGL to be transmitted to the second node PD to control the signal of the second node PD to be at an invalid level; conversely, when the input signal Vin of the signal input terminal IN is at an invalid level, the noise reduction module 170 can stop transmitting the first level signal VGL to the second node PD, so that the signal of the second node PD can be controlled by the pull-down control module 150. In this way, by setting the noise reduction module 170, when the input signal Vin is at a valid level, the second node PD can be controlled to be at an invalid level, that is, the pull-down module 140 can be controlled to stop working, so that the signal of the first node PU is not easily affected by the signal of the second node PD, thereby improving the competitiveness of the first node PU.

[0270] In an exemplary embodiment, continue to refer to Fig.45The noise reduction module 170 may include a fourteenth transistor M14, a gate of which may be electrically connected to the signal input terminal IN, a first electrode of the fourteenth transistor M14 may be electrically connected to the first level terminal VGL, and a second electrode of the fourteenth transistor M14 may be electrically connected to the second node PD, so that an input signal Vin of the signal input terminal IN may control the fourteenth transistor M14 to be turned on or off, and when the fourteenth transistor M14 is turned on, the first level signal Vgl may pass through to the second node PD to ensure that the second node PD remains at an invalid level during a time period when the first node PU is at a valid level.

[0271] Based on the above embodiment, optionally, Fig.46 is another driving timing diagram of a display panel provided by an embodiment of the present invention, and is combined with reference to Figures 44 to 46 The restoration signal Vrest2 received by the second shift register unit also includes a second effective pulse; the working process of the display panel 100 includes a frame period, and the frame period includes a first effective pulse and a second effective pulse; the starting time T8 of the second effective pulse is located after the end time of the effective pulse of the gate drive signal Gout output by each level of the shift register unit ASG.

[0272] Among them, when the restoration module 130 of the second shift register unit transmits the first level signal VGL to the first node PU and the signal output terminal OUT under the control of the first valid pulse of the restoration signal Vrest2 it receives, the output noise of the signal output terminal OUT of the second shift register unit can be reduced; and after the gate drive signal Gout is output by each level of shift register unit ASG, the restoration module 130 of the second shift register unit transmits the first level signal VGL to the first node PU and the signal output terminal OUT again under the control of the second valid pulse of the restoration signal Vrest2 it receives, so that the first node PU and the signal output terminal OUT can both be maintained at an invalid level to prepare for the arrival of the next frame cycle.

[0273] The time length of the first effective pulse may be the same as or different from the time length of the second effective pulse, and may be designed according to actual needs, which is not specifically limited in the embodiment of the present invention. Figures 44 to 46 The time length of the first effective pulse can be greater than or equal to the time length of the second effective pulse. In this way, it can be ensured that the first effective pulse has a sufficiently long time to control the restoration module 130 to transmit the first electrical level VGL to the first node PU and the signal output terminal OUT, and the second effective pulse can have a relatively short time length to reduce the occupation time of the second effective pulse and ensure the display effect of the display panel 100.

[0274] Optionally, when the second shift register includes a virtual shift register, the starting time of the second effective pulse can be located after the ending time of the effective pulse of the gate drive signal Gout output by the virtual shift register, so as to ensure that each virtual shift register unit can accurately output the effective level of the gate drive signal Gout, so that the effective level of the gate drive signal Gout output by the virtual shift register unit can accurately control the first reset module 161 in the driving shift register unit to accurately reset its first node PU, thereby facilitating improving the accuracy of the gate drive signal Gout output by each level of shift register unit ASG.

[0275] Based on the same inventive concept, an embodiment of the present invention also provides a method for driving a display panel, which is used to drive the display panel provided by an embodiment of the present invention, and the display panel may include: a driving circuit; the driving circuit includes a multi-stage shift register unit; the driving circuit receives a start control signal, a restore signal and a clock signal; the working process of the display panel includes a frame period; the driving method includes: within the frame period, the start control signal includes a start control pulse, the restore signal includes a first valid pulse, and the clock signal includes a start valid pulse; the first valid pulse is the same as the start control pulse; the start time of the start valid pulse is later than the start time of the start control pulse.

[0276] Among them, by making the start control pulse of the start control signal received by the driving circuit the same as the first effective pulse of the restoration signal, the first effective pulse of the restoration signal can be provided to the driving circuit while providing the start control pulse of the start control signal to the driving circuit. The output noise of the signal output end of the shift register unit of each stage in the driving circuit can be reduced by the first effective pulse of the restoration signal, thereby improving the accuracy of the gate drive signal output by the shift register unit of each stage, which is beneficial to improving the display effect of the display panel.

[0277] It can be understood that the driving method of the display panel provided in the embodiment of the present invention is used to drive the display panel provided in the embodiment of the present invention. Therefore, the driving method of the display panel has relevant steps for controlling the display panel provided in the embodiment of the present invention to perform display, and can implement the same technical principles as the display panel provided in the embodiment of the present invention. The similarities can be referred to the above description and will not be repeated here.

[0278] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention. Therefore, the display device has the technical features of the display panel provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by the embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0279] For example, Fig.47 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.47 As shown, the display device 200 includes a display panel 100. The display device 200 provided in the embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0280] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit; the driving circuit comprises a multi-stage shift register unit; the shift register unit comprises at least an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal and a signal output terminal; In the shift register unit, the input module is electrically connected to the signal input terminal and the output module respectively, and the input module and the output module are electrically connected to a first node; the output module is electrically connected to the first node, the first clock terminal and the signal output terminal respectively; the first clock terminal receives a first clock signal; the first level terminal receives a first level signal; At least part of the shift register units are first-type shift register units; the first-type shift register units further include a restoration module and a restoration signal terminal; in the first-type shift register units, the restoration module is electrically connected to the restoration signal terminal and the first level terminal respectively, and the restoration module is also electrically connected to the first node and / or the signal output terminal; the restoration signal terminal receives a restoration signal; The signal output end of the shift register unit of the i-th stage is electrically connected to the signal input end of the shift register unit of the i+N-th stage; i and N are both positive integers; The multiple levels of the first type of shift register units include at least one level of first shift register unit and at least one level of second shift register unit; The restoration signal of the second shift register unit includes at least a first valid pulse, and at least in the time period of the first valid pulse of the restoration signal of the second shift register unit, the restoration signal of the first shift register unit is at an invalid level; the starting time of the first valid pulse is before the starting time of the starting valid pulse of the first clock signal of at least one level of the first shift register unit.

2. The display panel according to claim 1, characterized in that: The first valid pulse overlaps with a start valid pulse of the first clock signal of at least one stage of the first shift register unit.

3. The display panel according to claim 2, characterized in that: The time period of the start valid pulse of the first clock signal of at least one stage of the first shift register unit is located within the time period of the first valid pulse.

4. The display panel according to claim 1, characterized in that: The first-level first-type shift register unit to the L-th-level first-type shift register unit are the first shift register units; the starting time of the first valid pulse is before the starting time of the starting valid pulse of the first clock signal received by the first-level first-type shift register unit; L is a positive integer.

5. The display panel according to claim 1, characterized in that: Every 2*N levels of shift register units in the multiple levels of shift register units constitute a shift register unit group; The display panel further includes 2*N clock signal lines, and the first clock end of each shift register unit in the same shift register unit group is respectively connected to each of the clock signal lines; The clock cycle length of the clock signal provided by each of the clock signal lines is 2*N*H, where H is the length of a clock unit, and the length of the valid pulse of the first clock signal is N*H; within one clock cycle, the starting time of the valid pulse of the clock signal provided by each of the clock signal lines is shifted by 1H in sequence.

6. The display panel according to claim 1, characterized in that: The operation process of the display panel includes a frame period, and the frame period includes the first effective pulse.

7. The display panel according to claim 1, characterized in that: Also includes: Start signal line; the start signal line is used to transmit a start control signal; The signal input ends of the first-stage to the Nth-stage shift register units are all electrically connected to the start signal line.

8. The display panel according to claim 7, characterized in that: The starting moment of the effective pulse of the start control signal is before the starting moment of the starting effective pulse of the first clock signal received by the first-stage shift register unit, and the ending moment of the effective pulse of the start control signal is before the ending moment of the starting effective pulse of the first clock signal received by the first-stage shift register unit.

9. The display panel according to claim 7 or 8, characterized in that: The clock period duration of the first clock signal is 2*N*H, and the duration of the effective pulse of the first clock signal is N*H; where H is the duration of one clock unit; The time interval between the starting moment of the effective pulse of the start control signal and the starting moment of the starting effective pulse of the first clock signal received by the first-stage shift register unit is greater than or equal to N*H.

10. The display panel according to claim 7, characterized in that: The starting moment of the first effective pulse is the same as the starting moment of the effective pulse of the start control signal.

11. The display panel according to claim 7, characterized in that: The ending moment of the first effective pulse is the same as the ending moment of the effective pulse of the start control signal.

12. The display panel according to claim 7, characterized in that: The ending moment of the first effective pulse is later than the ending moment of the start control signal.

13. The display panel according to claim 12, characterized in that: The time period from the ending moment of the starting effective pulse of the first clock signal received by the first-stage shift register unit to the starting moment of its next effective pulse is the first time period; the ending moment of the first effective pulse is within the first time period.

14. The display panel according to claim 1, characterized in that: At least the first-stage to the Nth-stage shift register units are the first shift register unit.

15. The display panel according to claim 1, characterized in that: The time of the first effective pulse overlaps with the time of the effective pulse of the first clock signal of the first-stage to the Mth-stage shift register units, and the time of the first effective pulse does not overlap with the time of the effective pulse of the first clock signal of the (M + 1)th-stage shift register unit; M ≤ N, and M is a positive integer; The first-stage to the (M + N)th-stage shift register units are all the first shift register unit.

16. The display panel according to claim 1, characterized in that: The time of the first effective pulse overlaps with the time of the effective pulse of the first clock signal of the first-stage to the Pth-stage shift register units, and the time of the first effective pulse does not overlap with the time of the effective pulse of the first clock signal of the (P + 1)th-stage shift register unit; N < P ≤ 2N, P is a positive integer; The first-stage to the (P + N)th-stage shift register units are all the first shift register unit.

17. The display panel according to claim 1, characterized in that: The first-level signal is multiplexed as the restoration signal of the first shift register unit.

18. The display panel according to claim 17, characterized in that: It further includes: A first-level signal line and a restoration signal line that are insulated from each other; The first-level terminals of at least one stage of the first shift register unit and the first-level terminals of at least one stage of the second shift register unit are all electrically connected to the first-level signal line; The restoration signal terminal of at least one stage of the first shift register unit is electrically connected to the first-level signal line; The restoration signal terminal of at least one stage of the second shift register unit is electrically connected to the restoration signal line.

19. The display panel according to claim 18, characterized in that: The shift register units of each stage are arranged in sequence along a first direction; The first level signal line comprises a first portion and a second portion both extending along the first direction and electrically connected to each other; the first portion and the second portion are arranged along a second direction; the second direction intersects the first direction, and the second direction is parallel to the plane where the display panel is located; The restoration signal line extends along the first direction, and the restoration signal line and the first portion are arranged along the second direction; In the second direction, the first portion and the second portion overlap with at least one stage of the first shift register unit, and the first portion and the restoration signal line overlap with at least one stage of the second shift register unit.

20. The display panel according to claim 19, characterized in that: In the first direction, the second portion overlaps the restoration signal line.

21. The display panel according to claim 19, characterized in that: The first level signal line further includes a connecting portion, the connecting portion connecting the first portion and the second portion; In the second direction, the connecting portion does not overlap with each level of the shift register units.

22. The display panel according to claim 1, characterized in that: The shift register unit also includes a pull-down module and a pull-down control module; In the same shift register unit, the pull-down control module is electrically connected to at least the first node, the second node and the first level end respectively; the pull-down module is electrically connected to the first level end, the second node, the first node and the signal output end respectively.

23. The display panel according to claim 22, characterized in that: The shift register unit further includes a second level end, the second level end is used to receive a second level signal, and in the same shift register unit, the pull-down control module is also electrically connected to the second level end; and / or, The shift register unit also includes a second clock terminal; the second clock terminal is used to receive a second clock signal. In the same shift register unit, the pull-down control module is also electrically connected to the second clock terminal.

24. The display panel according to claim 22, characterized in that: The pull-down control module includes a first transistor, a second transistor, a third transistor and a fourth transistor; The first electrode of the first transistor is connected to the first signal terminal, the second electrode of the first transistor is connected to the gate of the second transistor, and the gate of the first transistor is connected to the second signal terminal; A first electrode of the second transistor is connected to the third signal terminal, and a second electrode of the second transistor is connected to the second node; The gates of the third transistor and the fourth transistor are both electrically connected to the first node; the first electrode of the third transistor and the first electrode of the fourth transistor are both electrically connected to the first level end; the second electrode of the third transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the gate of the second transistor.

25. The display panel according to claim 24, characterized in that: The shift register unit also includes a second clock terminal, and the second signal terminal is electrically connected to the second clock terminal; the second clock terminal is used to receive a second clock signal.

26. The display panel according to claim 25, characterized in that: The first signal terminal and the third signal terminal are both electrically connected to the second clock terminal; or, The shift register unit further includes a second level end, the second level end is used to receive a second level signal, and the first signal end and the third signal end are both electrically connected to the second level end.

27. The display panel according to claim 25, characterized in that: In the same shift register unit, the clock signal at the second clock end is the same as or inversely related to the clock signal at the first clock end.

28. The display panel according to claim 24, characterized in that: The shift register unit further includes a second level end, the second level end is used to receive a second level signal, and the first signal end, the second signal end and the third signal end are all electrically connected to the second level end.

29. The display panel according to claim 22, characterized in that: The shift register unit also includes a noise reduction module; In the same shift register unit, the noise reduction module is electrically connected to the signal input end, the first level end and the second node respectively.

30. The display panel according to claim 1, characterized in that: The shift register unit further includes a second level terminal, and the second level terminal is used to provide a second level signal; The input module includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the second level end, a second electrode of the fifth transistor is electrically connected to the first node, and a gate of the fifth transistor is electrically connected to the signal input end.

31. The display panel according to claim 1, characterized in that: The restoration module comprises: a sixth transistor, wherein a first electrode of the sixth transistor is electrically connected to the first level end, a second electrode of the sixth transistor is electrically connected to the first node, and a gate of the sixth transistor is electrically connected to the restoration signal end; and / or, A seventh transistor, wherein a first electrode of the seventh transistor is electrically connected to the first level end, a second electrode of the seventh transistor is electrically connected to the signal output end, and a gate of the seventh transistor is electrically connected to the restoration signal end.

32. The display panel according to claim 1, characterized in that: The shift register unit also includes a first reset module and a first reset signal terminal; In the same shift register unit, the first reset module is electrically connected to the first reset signal end, the first level end and the first node respectively; the first reset signal end is used to receive a first reset signal; at least part of the time of the effective pulse of the gate drive signal output by the signal output end does not overlap with the effective pulse time of the first reset signal.

33. The display panel according to claim 32, characterized in that: The first reset signal terminal of the i-th shift register unit is electrically connected to the signal output terminal of the j-th shift register unit; j>i, and i and j are both positive integers; Among them, j=i+N, or j=i+N+1.

34. The display panel according to claim 32, characterized in that: The shift register unit also includes a second reset module and a second reset signal terminal; In the same shift register unit, the second reset module is electrically connected to the second reset signal end, the first level end and the signal output end respectively; the second reset signal end is used to receive a second reset signal; at least part of the time of the effective pulse of the gate drive signal output by the signal output end does not overlap with the effective pulse time of the second reset signal.

35. The display panel according to claim 34, characterized in that: The first reset signal terminal is multiplexed as the second reset signal terminal.

36. The display panel according to claim 1, characterized in that: The shift register unit further includes a third reset module and a third reset signal terminal, the third reset module is electrically connected to the third reset signal terminal, the third level terminal and the second side signal output terminal respectively, and the signal output terminal of the shift register unit is the first side signal output terminal; The display panel further comprises a plurality of gate signal lines and a plurality of pixels, wherein the gate signal lines are electrically connected to the pixels, and the gate signal lines are electrically connected to the first side signal output terminal and the second side signal output terminal respectively; Along the extending direction of the gate signal line, the output module and the third reset module of the shift register unit are respectively located at two opposite sides of the gate signal line.

37. The display panel according to claim 1, characterized in that: The display panel further comprises a plurality of gate signal lines, a plurality of pixels and a first reset signal line, wherein the gate signal lines are electrically connected to the pixels; The second shift register unit includes a driving shift register unit and a dummy shift register unit, the driving shift register unit provides a gate driving signal to the gate signal line, and the dummy shift register unit does not provide a gate driving signal to the gate signal line; The driving shift register unit and the dummy shift register unit further include a first reset module and a first reset signal terminal; In the same shift register unit, the first reset module is electrically connected to the first reset signal terminal, the first level terminal and the first node respectively; The i-th shift register unit is the driving shift register unit, and the first reset signal terminal of the i-th shift register unit is electrically connected to the signal output terminal of the j-th shift register unit; wherein i and j are both positive integers, i+N≤j <i+2N; The p-th shift register unit is the virtual shift register unit, and the first reset signal terminal of the p-th shift register unit is electrically connected to the first reset signal line; p is a positive integer; The first reset signal line provides a reset valid pulse, and the reset valid pulse is the same as the first valid pulse.

38. The display panel according to claim 1, characterized in that: The restored signal received by the second shift register unit further includes a second valid pulse; The working process of the display panel includes a frame period, and the frame period includes the first effective pulse and the second effective pulse; The starting time of the second effective pulse is located after the ending time of the effective pulse of the gate driving signal output by the shift register units of each stage.

39. The display panel according to claim 38, characterized in that: The time length of the first effective pulse is greater than or equal to the time length of the second effective pulse.

40. The display panel according to claim 38, characterized in that The second shift register includes a virtual shift register, and the starting time of the second effective pulse is located after the ending time of the effective pulse of the gate driving signal output by the virtual shift register.

41. The display panel according to claim 1, characterized in that: Also includes: A plurality of pixels and a plurality of gate signal lines arranged in an array, wherein the gate signal lines are electrically connected to the pixels; The first type shift register unit provides a gate driving signal to the gate signal line.

42. The display panel according to claim 41, characterized in that The shift register unit further includes a second type of shift register unit; the second type of shift register unit is not provided with the restoration module and the restoration signal terminal; The display panel further includes a start signal line, and the signal input end of the second-type shift register unit is electrically connected to the start signal line.

43. The display panel according to claim 1, characterized in that: Also includes: A plurality of pixels, a plurality of gate signal lines and a start signal line arranged in an array; The gate signal line is electrically connected to the pixel; The signal input terminal of the first shift register unit is electrically connected to the start signal line, and the first shift register unit is not configured to provide a gate driving signal to the gate signal line.

44. The display panel according to claim 1, characterized in that: Also includes: M start signal lines; the start signal lines are used to transmit start control signals; The starting time of the effective pulse of the start control signal transmitted by each of the start signal lines is shifted in sequence; 2≤M≤N, M is a positive integer; Each of the shift register units from the first stage to the Nth stage is electrically connected to each of the start signal lines, and each of the start signal lines is electrically connected to at least one stage of the shift register unit.

45. The display panel according to claim 44, characterized in that: The M start signal lines include at least one first start signal line; The effective pulse start time of the start control signal transmitted by the first start signal line is located before the effective pulse start time of the start control signal transmitted by other start signal lines; At least one of the shift register units electrically connected to the first start signal line is the first shift register unit.

46. ​​A display panel, characterized in that: include: A driving circuit, a first restoration signal line and a second restoration signal line; The driving circuit comprises a multi-stage shift register unit, wherein the shift register unit comprises an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal and a signal output terminal; In the shift register unit, the input module is electrically connected to the signal input terminal and the output module respectively, and the input module and the output module are electrically connected to a first node; the output module is electrically connected to the first node, the first clock terminal and the signal output terminal respectively; the first level terminal receives a first level signal; The first clock end receives a first clock signal; At least part of the shift register units are first-type shift register units; the first-type shift register units further include a restoration module and a restoration signal terminal; in the first-type shift register units, the restoration module is electrically connected to the restoration signal terminal and the first level terminal respectively, and the restoration module is also electrically connected to the first node and / or the signal output terminal; the restoration signal terminal receives a restoration signal; The multi-stage first-type shift register unit includes at least one stage of first shift register unit and at least one stage of second shift register unit, the restoration signal end of the first shift register unit is electrically connected to the first restoration signal line, and the restoration signal end of the second shift register unit is electrically connected to the second restoration signal line; Wherein, the first restoration signal line and the second restoration signal line are insulated from each other.

47. The display panel according to claim 46, characterized in that: Also includes: a first level signal line, the first level end of at least one stage of the first shift register unit and the first level end of at least one stage of the second shift register unit are both electrically connected to the first level signal line; The first restoration signal line is electrically connected to the first level signal line.

48. A method for driving a display panel, characterized in that: The display panel comprises: a driving circuit; the driving circuit comprises a multi-stage shift register unit; the driving circuit receives a start control signal, a restoration signal and a clock signal; the working process of the display panel comprises a frame cycle; The driving method comprises: within the frame period, the start control signal comprises a start control pulse, the restoration signal comprises a first valid pulse, and the clock signal comprises a start valid pulse; The first effective pulse is the same as the start control pulse; The starting time of the start effective pulse is later than the starting time of the start control pulse.

49. A display device, characterized in that: include: A display panel as described in any one of claims 1 to 47.

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