Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The output end of an enabling output module of a shifting register included in a first scanning driving circuit is electrically connected with the first end of a first scanning line; the input end of the compensation module in the first compensation module group is electrically connected with the first non-enable signal line, and the output end of the compensation module is electrically connected with the second end of the first scanning line; in the shift register and the compensation module which are electrically connected with the same first scanning line, the compensation module is used for being started in a switching period when an enable output module included in the shift register is switched from an output enable signal to an output non-enable signal. According to the technical scheme provided by the embodiment of the invention, the problems that the non-enable signals received by the first end and the second end of the first scanning line are different due to voltage drop and the non-enable signals received by the second end of the first scanning line are delayed can be effectively solved; and transistors electrically connected to different positions of the first scanning line can be turned off in time, so that the problem of abnormal display is effectively relieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, users generally prefer display devices with high screen-to-body ratio. Therefore, narrow-frame display has become an important research direction in the field of display technology. In the display panel of the display device, the reduction of the width of the frame area is largely limited by the scan drive circuit. In order to achieve a narrow frame, the scan line in the display panel adopts unilateral drive, that is, one end of the scan line is electrically connected to the shift register and the other end is not electrically connected to the shift register. However, unilateral drive will cause the display panel to have poor display uniformity. Summary of the invention

[0003] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising a first scan line, a first scan drive circuit and a first compensation module group; the first scan drive circuit comprises a multi-stage cascaded shift register, the shift register comprises an enable output module, and the output end of the enable output module of the shift register included in the first scan drive circuit is electrically connected to the first end of the first scan line; the first compensation module group comprises a plurality of compensation modules, the input end of the compensation module is electrically connected to the first non-enable signal line and the output end is electrically connected to the second end of the first scan line; wherein, in the shift register included in the first scan drive circuit and the compensation module included in the first compensation module group that are electrically connected to the same first scan line, the compensation module is used to be turned on during the switching period of the shift register; the switching period is the period when the enable output module switches from outputting an enable signal to outputting a non-enable signal.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0006] The technical solution provided in the embodiment of the present application can not only effectively solve the problem that the non-enable signals received by the first end and the second end of the first scan line have different voltage drops and that the non-enable signals received by the second end of the first scan line have delays, but also enable the transistors electrically connected at different positions of the first scan line to be turned off in time, thereby effectively alleviating the problem of display abnormalities. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0008] Figure 1 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0009] Figure 2 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0010] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application;

[0011] Figure 4 A schematic diagram of the connection between a shift register and a compensation module and a first scan line provided in an embodiment of the present application;

[0012] Figure 5 for Figure 4 A corresponding working timing diagram;

[0013] Figure 6 A schematic diagram of a pixel circuit related to an embodiment of the present application;

[0014] Figure 7 for Figure 6 An existing working timing diagram corresponding to the pixel circuit shown;

[0015] Figure 8 for Figure 6 A working timing diagram corresponding to the pixel circuit shown;

[0016] Fig. 9 for Figure 6 An equivalent circuit diagram of a corresponding pixel circuit;

[0017] Fig.10 A schematic diagram of the connection between a shift register and a compensation module and a first scan line provided in an embodiment of the present application;

[0018] Fig.11 for Fig.10 A corresponding working timing diagram;

[0019] Fig.12 for Fig.10 Another corresponding working timing diagram;

[0020] Fig.13 An equivalent circuit diagram of a compensation module provided in an embodiment of the present application;

[0021] Fig.14 An equivalent circuit diagram of a shift register and a compensation module provided in an embodiment of the present application;

[0022] Fig.15 for Fig.14 A corresponding working timing diagram;

[0023] Fig.16 A schematic diagram of a display panel provided in an embodiment of the present application;

[0024] Fig.17 A schematic diagram of a display panel provided in an embodiment of the present application;

[0025] Fig.18 A schematic diagram of a display panel provided in an embodiment of the present application;

[0026] Fig.19 A schematic diagram of a display panel provided in an embodiment of the present application;

[0027] Fig. 20 for Fig.19 A corresponding working timing diagram;

[0028] Fig.21 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0029] Fig. 22 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0030] Fig.23 A schematic diagram of a display panel provided in an embodiment of the present application;

[0031] Fig.24 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0032] Fig.25 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0033] Fig.26 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0034] Fig. 27 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0035] Fig.28 A schematic diagram of a display panel provided in an embodiment of the present application;

[0036] Fig.29 A schematic diagram of the structure of different transistors in a display panel provided in an embodiment of the present application;

[0037] Fig.30 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0039] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0040] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0041] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0042] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0043] It should be understood that although the terms first, second, etc. may be used to describe transistors, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish transistors, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first transistor may also be referred to as the second transistor, and similarly, the second transistor may also be referred to as the first transistor. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0044] Figure 1 A partial schematic diagram of a display panel provided in an embodiment of the present application, Figure 2 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0045] like Figure 1 and Figure 2 As shown, the display panel 01 includes a plurality of pixels 10 and a plurality of scan lines 20. Figure 1 As shown, the pixel 10 may include a pixel circuit 11, and the scan line 20 is electrically connected to the pixel circuit 11 in the same row to drive the pixel circuit 11 row by row. Figure 2 As shown, the pixel 10 may further include a pixel electrode 12 and a pixel switch 13 electrically connected to the pixel electrode 12, and the scanning line 20 is electrically connected to the pixel switches 13 in the same row to drive the pixel switches 13 to work row by row. Figure 1 The display panel 01 including the pixel circuit 11 shown can also be applied to Figure 2 The display panel 01 shown includes a pixel electrode 12 and a pixel switch 13. Figure 1 The display panel 01 shown may be an organic light emitting diode (OLED) display panel, a micro light emitting diode (Micro-LED) display panel, a sub-millimeter light emitting diode (Mini-LED) display panel, etc. Figure 2 The display panel 01 shown may be a liquid crystal display panel (LCD) or the like.

[0046] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application.

[0047] Combination Figure 3 and Figure 1 , Figure 2 The display panel 01 includes a first scan driving circuit 30 and a first compensation module group 40. The first scan driving circuit 30 includes a multi-stage cascaded shift register 300, and the output ends of the multi-stage shift register 300 included in the first scan driving circuit 30 are electrically connected to different first scan lines 21 respectively, and the first compensation module group 40 includes a plurality of compensation modules 400, and the output ends of the plurality of compensation modules 400 included in the first compensation module group 40 are electrically connected to different first scan lines 21 respectively.

[0048] For the sake of clarity, Figure 3 Only part of the structure of the display panel 01 is shown in the figure. In actual products, the structure of the display panel 01 is not limited to Figure 3 The structure shown in .

[0049] Please continue to refer to Figure 3, the output end of the shift register 300 included in the first scan driving circuit 30 is electrically connected to the first end of the first scan line 21, and the output end of the compensation module 400 included in the first compensation module group 40 is electrically connected to the second end of the first scan line 21. Wherein, at least part of the first scan lines 21 are electrically connected to the shift register 300 included in the first scan driving circuit 30 and the compensation module 400 included in the first compensation module group 40 at the same time, that is, at least part of the first scan lines 21 have a first end electrically connected to the shift register 300 included in the first scan driving circuit 30 and a second end electrically connected to the compensation module 400 included in the first compensation module group 40. For example, all the first scan lines 21 are electrically connected to the shift register 300 included in the first scan driving circuit 30 and the compensation module 400 included in the first compensation module group 40 at the same time.

[0050] The first scan line 21 may be a scan line 20 of the same type among the plurality of scan lines 20 included in the display panel 01. For example, please refer to Figure 1 When the display panel 01 includes a pixel circuit 11 and the pixel circuit 11 includes a plurality of transistors, the transistors electrically connected to different first scan lines 21 are transistors with the same function in the pixel circuit 11. For example, please refer to Figure 2 When the display panel 01 includes a switching transistor connected between the pixel electrode 12 and the data line DL, the transistors electrically connected to different first scan lines 21 may all be switching transistors.

[0051] Figure 4 A schematic diagram of the connection between a shift register and a compensation module and a first scan line provided in an embodiment of the present application.

[0052] like Figure 4 As shown, the shift register 300 includes an enable output module 31, which is at least used to output an enable signal to the scan line 20 electrically connected thereto, and the enable signal output by the enable output module 31 can control the transistor electrically connected thereto through the scan line 20 to turn on. The output end of the enable output module 31 of the shift register 300 included in the first scan drive circuit 30 is electrically connected to the first end of the first scan line 21, wherein the output end of the enable output module 31 can also be used as the output end of the shift register 300. Unless otherwise specified, the following is taken as an example that the enable signal output by the shift register 300 included in the first scan drive circuit 30 is a high level.

[0053] For ease of description, the shift register 300 included in the first scan driving circuit 30 is referred to as a first shift register 301, and the enable output module 31 of the shift register 300 included in the first scan driving circuit 30 is referred to as a first enable output module 311. The first enable output module 311 in this embodiment is at least used to output an enable signal to the first scan line 21, so that the first scan line 21 can control the transistor electrically connected thereto to turn on when transmitting the enable signal.

[0054] Figure 5 for Figure 4 A corresponding working timing diagram.

[0055] refer to Figure 5 , the working process of the shift register 300 may include an enabling phase T1 and a non-enabling phase T2, and the enabling output module 31 of the shift register 300 outputs an enabling signal in the enabling phase T1. Figure 5 As shown, the output terminal OUT1 of the first enable output module 311 transmits the enable signal to the first scan line 21 through the first end of the first scan line 21 in the enable phase T1 of the shift register 300 to which it belongs. Figure 5 and Figure 4 , out1 represents the signal of the output terminal OUT1 of the first enable output module 311 , and out1 represents the high level of the enable signal in the enable phase T1 .

[0056] When the first enable output module 311 finishes outputting the enable signal, it means that the enable phase T1 of the first shift register 301 to which the first enable output module 311 belongs ends. At this time, if the first enable output module 311 is immediately turned off, the charge on the first scan line 21 to which it is electrically connected cannot be effectively released, resulting in the transistor to which the first scan line 21 is electrically connected cannot be effectively turned off, and the transistor will mischarge the signal.

[0057] Therefore, after the first enable output module 311 of the first shift register 301 finishes outputting the enable signal, the first enable output module 311 will not be turned off immediately but will remain on, so that the charge on the first scan line 21 can be released. At this time, the first enable output module 311 switches from outputting the enable signal to outputting the disable signal, so that the first scan line 21 can transmit a relatively accurate signal in the disable phase T2 after the enable phase T1 of the shift register 300 ends, thereby accurately controlling the on / off state of the transistor electrically connected to the first scan line 21. That is, Figure 5As shown, the initial period when the first shift register 301 ends the enabling phase T1 and enters the non-enabling phase T2 is the switching period T20, and the switching period T20 is the period when the enabling output module 31 switches from outputting the enabling signal to outputting the non-enabling signal; that is, the first enabling output module 311 switches from outputting the enabling signal to outputting the non-enabling signal in the initial period when the first shift register 301 ends the enabling phase T1 and enters the non-enabling phase T2. For example, Figure 5 As shown, out1 finally outputs a low level representing a non-enable signal in the non-enable phase T2, and out1 switches from a high level to a low level in the switching period T20 of the non-enable phase T2. In addition, the first shift register 301 electrically connected to the first scan line 21 switches from outputting an enable signal to outputting a non-enable phase in the switching period T20, so that the signal on the first scan line 21 does not immediately switch from a transmission enable signal to a transmission non-enable signal, and correspondingly, the transistor electrically connected to the first scan line 21 also switches from on to off in the switching period T20 of the first shift register 301 and does not immediately turn off.

[0058] like Figure 4 As shown, the input end of the compensation module 400 included in the first compensation module group 40 is electrically connected to the first non-enable signal line VGL1 and the output end is electrically connected to the second end of the first scan line 21, wherein the first non-enable signal line VGL1 is used to transmit the non-enable signal. Unless otherwise specified, the following description is made by taking the enable signal as a high level and the non-enable signal as a low level as an example.

[0059] It should be noted that, in actual products, when the transistor electrically connected and controlled by the first scan line 21 is an N-channel transistor, the enable signal is a high level and the disable signal is a low level; in actual products, when the transistor electrically connected and controlled by the first scan line 21 is a P-channel transistor, the enable signal is a low level and the disable signal is a high level.

[0060] For ease of description, the compensation module 400 included in the first compensation module group 40 is referred to as the first compensation module 401. When the first compensation module 401 is turned on, it can transmit the non-enable signal transmitted on the first non-enable signal line VGL1 to the first scan line 21 electrically connected to it through the second end of the first scan line 21. Figure 5 and Figure 4 , ctr1 represents the potential signal of the control terminal CTR1 of the first compensation module 401. Unless otherwise specified, the following description is based on the example that the first compensation module 401 is turned on when ctr1 is at a high level. It should be noted that in actual products, the first compensation module 401 can also be turned on when ctr1 is at a low level.

[0061] In the embodiment of the present application, the compensation module 400 included in the shift register 300 and the first compensation module group 40 electrically connected to the same first scan line 21 is used to start the shift register 300 during the switching period T20. Figure 5 and Figure 4 When the first shift register 301 electrically connected to the first scan line 21 ends the enabling phase T1 and enters the switching period T20 of the non-enabling phase T2, the first compensation module 401 electrically connected to the first scan line 21 is turned on, that is, in the process of the potential of the first end of the first scan line 21 switching from the potential corresponding to the enabling signal to the potential corresponding to the non-enabling signal, the potential of the second end of the first scan line 21 also switches from the potential corresponding to the enabling signal to the potential corresponding to the non-enabling signal.

[0062] In the prior art, when one end (called the near end) of the scan line 20 is electrically connected to the shift register 300 and the other end (called the far end) is suspended, the near end of the scan line 20 obtains a signal from the shift register 300, and the signal may have voltage drop and delay problems when transmitted in the scan line 20. When the shift register 300 switches from outputting an enable signal to outputting a disable signal, the far end of the scan line 20 has a certain difference in potential of the received disable signal relative to the near end, and receives the disable signal later.

[0063] In the embodiment of the present application, the first end (corresponding to the proximal end) of the first scan line 21 is electrically connected to the shift register 300 and the second end (corresponding to the distal end) is electrically connected to the compensation module 400. When the shift register 300 outputs a non-enable signal to the first end of the first scan line 21, the compensation module 400 also outputs a non-enable signal to the second end of the first scan line 21. Then, both the first end and the second end of the first scan line 21 can receive the non-enable signal nearby, effectively solving the problem of difference in voltage drop between the non-enable signals received by the first end and the second end of the first scan line 21, and effectively solving the problem of delay in the non-enable signal received by the second end of the first scan line 21.

[0064] In addition, when one end (called the near end) of the scan line 20 is electrically connected to the shift register 300 and the other end (called the far end) is suspended, among the transistors electrically connected to the scan line 20, the turn-off time of the transistor near the far end is not timely enough relative to the turn-off time of the transistor near the near end. On the one hand, the delay in the transmission of the non-enable signal on the scan line 20 causes the turn-off start time of the transistor near the far end to be later than the turn-off start time of the transistor near the near end; on the other hand, the voltage drop when the non-enable signal is transmitted on the scan line 20 causes the turn-off time of the transistor near the far end to be longer than the turn-off time of the transistor near the near end. If the transistor is not turned off in time, it may cause the transistor to write an inaccurate signal to the node electrically connected to its output end, thereby causing display abnormality.

[0065] Based on this problem, the embodiment of the present application provides a corresponding solution, that is, in the shift register 300 included in the first scan driving circuit 30 electrically connected to the same first scan line 21 and the compensation module 400 included in the first compensation module group 40, the compensation module 400 is used to be turned on in the switching period T20 of the shift register 300, that is, in the process of switching the potential of the first end of the first scan line 21 from the potential corresponding to the enable signal to the potential corresponding to the non-enable signal, the potential of the second end of the first scan line 21 is also switched from the potential corresponding to the enable signal to the potential corresponding to the non-enable signal. Therefore, the time duration of the transistor electrically connected near the first end of the first scan line 21 to be turned off is similar to the time duration of the transistor electrically connected near the second end to be turned off, and the time when the transistor electrically connected near the first end of the first scan line 21 is turned off is similar to the time when the transistor electrically connected near the second end is turned off. The technical solution provided in the embodiment of the present application can enable the transistors electrically connected at different positions of the first scan line 21 to be turned off in time, effectively alleviating the problem of display abnormality.

[0066] It should be noted that the embodiment of the present application takes the first scanning drive circuit 30, the shift register 300 included in the first scanning drive circuit 30 and the enable output module 31 included therein, the first compensation module group 40 and the compensation module 400 included therein, and the first scanning line 21 as examples to explain the inventive concept of the present application.

[0067] In addition, the display panel 01 may also include other scan drive circuits other than the first scan drive circuit 30, such as a second scan drive circuit and a third scan drive circuit. The second scan drive circuit and the third scan drive circuit may include a shift register 300 and the shift registers 300 may also include an enable output module 31. The display panel 01 may also include other compensation module groups other than the first compensation module group 40, such as a second compensation module group and a third compensation module group. The second compensation module group and the third compensation module group may include a compensation module 400. In addition, the display panel 01 may also include other scan lines 20 other than the first scan line 21, such as a second scan line and a third scan line. Other scan drive circuits other than the first scan drive circuit 30, other compensation modules other than the first compensation module group 40, and other scan lines 20 other than the first scan line 21 may also adopt the inventive concept of the present application, and the present application does not limit this.

[0068] like Figure 4 As shown, the shift register 300 may further include a non-enable output module 32 and a control module 33. The non-enable output module 32 is used to output a non-enable signal to the scan line 20 to which it is electrically connected, and the non-enable signal output by the non-enable output module 32 can control the transistor to which it is electrically connected to be turned off through the scan line 20. The control module 33 is used to control the opening and closing of the enable output module 31 and the non-enable output module 32 respectively.

[0069] Figure 6 A schematic diagram of a pixel circuit related to an embodiment of the present application.

[0070] In some embodiments of this application, please refer to Figure 6 , the display panel 01 includes a pixel circuit 11 and a data line DL. The pixel circuit 11 includes a driving transistor M0 and a data voltage writing module 111. The driving transistor M0 is used to generate a driving current. The data voltage writing module 111 is electrically connected to the driving transistor M0 and is used to write a data voltage to the driving transistor M0. The size of the driving current generated by the driving transistor M0 is mainly determined by the data voltage received by it. Figure 6 As shown, the input end of the data voltage writing module 111 is electrically connected to the data line DL and the data voltage writing module 111 is used to transmit the data voltage on the data line DL to the driving transistor M0. When the data voltage writing module 111 is turned on, the data voltage transmitted on the data line DL will be transmitted to one end of the driving transistor M0.

[0071] In these embodiments, the first scan line 21 is electrically connected to the control end of the data voltage writing module 111, and the opening and closing of the data voltage writing module 111 is controlled by the signal transmitted by the first scan line 21. The working process of the pixel circuit 11 includes a data voltage writing stage, and in the data voltage writing stage, the data voltage writing module 111 is turned on. Therefore, in the data voltage writing stage, when the data voltage writing module 111 needs to transmit the data voltage to the driving transistor M0, the first scan line 21 should transmit an enable signal to the control end of the data voltage writing module 111; in the non-data voltage writing stage, when the data voltage writing module 111 stops transmitting the data voltage to the driving transistor M0, the first scan line 21 should transmit a non-enable signal to the control end of the data voltage writing module 111. Specifically, the first scan line 21 can be electrically connected to the gate of at least one transistor in the data voltage writing module 111.

[0072] Figure 7 for Figure 6 An existing working timing diagram corresponding to the pixel circuit shown.

[0073] Combination Figure 6 and Figure 7 , g1 represents the signal of the gate of the transistor electrically connected to the first scan line 21 in the data voltage writing module 111; in addition, d1 represents the signal transmitted by the data line DL. It can be understood that the signal g1 is transmitted from the first scan line 21 to the gate of the transistor electrically connected to the first scan line 21 in the data voltage writing module 111; the signal d1 is transmitted to the first electrode of the transistor electrically connected to the first scan line 21 in the data voltage writing module 111. Figure 6 and Figure 7 When the pixel circuit 11 ends the data voltage writing stage Td, the transistor in the data voltage writing module 111 electrically connected to the first scan line 21 is not turned off immediately, but is gradually turned off in response to the switching process of the signal g1 from the enable signal to the non-enable signal; at this time, the signal d1 transmitted by the data line DL is also changed from the data voltage required by the pixel circuit 11 (for example Figure 7 high level shown) to other potentials (such as Figure 7 As shown in the low potential). Figure 7 As shown in FIG. 1 , when the switching process of the signal g1 from the enable signal to the disable signal takes a long time, the gate potential of the transistor electrically connected to the first scan line 21 in the data voltage writing module 111 changes from the enable signal to the disable signal for a long time, and at this time, there will be a problem of data voltage mischarging. Figure 7As shown, since the time it takes for the potential of the gate of the transistor electrically connected to the first scan line 21 in the data voltage writing module 111 to change from an enable signal to a non-enable signal is relatively long, the transistor will still be turned on when the signal d1 on the data line DL is no longer the required data voltage, and then the wrong voltage will be written into the driving transistor M0, resulting in mischarging of the data voltage.

[0074] In the prior art, if the first end of the first scan line 21 is electrically connected to the shift register 300 and the second end is left floating, the gate potential of the transistor electrically connected to the first end of the first scan line 21 changes from an enable signal to a non-enable signal, and the change characteristics of the signal output by the non-enable output module 32 in the switching period T20 are basically the same. Since the switching period T20 experienced by the signal of the non-enable output module 32 from the enable signal to the non-enable signal is short, the transistor electrically connected to the first scan line 21 included in the data voltage writing module 111 near the first end of the first scan line 21 can also be quickly turned off. However, due to the influence of voltage drop and delay, the reference Figure 7 , the gate potential of the transistor electrically connected to the second end of the first scan line 21 starts switching from the enable signal to the non-enable signal later and the time it takes to change from the enable signal to the non-enable signal is significantly increased, which leads to a significantly increased risk of data voltage mischarging in the pixel 10 electrically connected to the far end of the first scan line 21. And when the display panel 01 is a high-frequency display, the time of the data voltage writing stage Td is shorter, and the problem of data voltage mischarging is more obvious.

[0075] Figure 8 for Figure 6 A working timing diagram corresponding to the pixel circuit shown.

[0076] In this embodiment, the second end of the first scan line 21 is electrically connected to the compensation module 400 in the first compensation module group 40 and the compensation module 400 is turned on during the switching period T20 when the shift register 300 switches from outputting an enable signal to outputting a non-enable signal. Then, when the transistor electrically connected to the first scan line 21 in the data voltage writing module 111 near the first end of the first scan line 21 begins to turn off, the transistor electrically connected to the first scan line 21 in the data voltage writing module 111 near the second end of the second scan line 20 also basically begins to turn off; the time length experienced by the transistor electrically connected to the first scan line 21 in the data voltage writing module 111 near the first end of the first scan line 21 from turning on to turning off is basically the same as the time length experienced by the transistor electrically connected to the first scan line 21 in the data voltage writing module 111 near the second end of the first scan line 21 from turning on to turning off.

[0077] Figure 8This is a partial working sequence of a transistor electrically connected to the first scan line 21 in the data voltage writing module 111 near the second end of the first scan line 21 in the display panel 01 using the technical solution of the present application. Figure 8 and Figure 7 By adopting the technical solution of the present application, in the data voltage writing module 111 near the second end of the first scan line 21, the time for the signal g of the gate of the transistor electrically connected to the first scan line 21 to change from a high level to a low level is significantly shortened, and the time for the transistor to be turned on and off is significantly shortened, and the risk of these transistors being turned on by mistake is significantly reduced. Therefore, the problem of data voltage mischarging in the pixel circuit 11 near the second end of the first scan line 21 is effectively improved, thereby improving the display effect of the display panel 01.

[0078] In a technical solution corresponding to these embodiments, the data voltage writing module 111 includes an N-channel transistor, and the first scan line 21 is electrically connected to the gate of the N-channel transistor included in the data voltage writing module 111. Then the enable signal received and transmitted by the first scan line 21 is a high level and the disable signal is a low level, and the enable signal output by the shift register 300 is a high level and the disable signal is a low level.

[0079] Fig. 9 for Figure 6 An equivalent circuit diagram of a corresponding pixel circuit.

[0080] like Fig. 9As shown, the data voltage writing module 111 includes a data voltage writing transistor M01 and a threshold grabbing transistor M02, a first electrode of the data voltage writing transistor M01 is electrically connected to the data line DL, a second electrode of the data voltage writing transistor M01 is electrically connected to a first electrode of the driving transistor M0, a first electrode of the threshold grabbing transistor M02 is electrically connected to a second electrode of the driving transistor M0, a second electrode of the threshold grabbing transistor M02 is electrically connected to a gate of the driving transistor M0, and a gate of the threshold grabbing transistor M02 is electrically connected to a first scanning line 21. In the data voltage writing phase Td of the pixel circuit 11, the data voltage writing transistor M01 and the threshold grabbing transistor M02 are turned on, and the data voltage transmitted on the data line DL is written into the gate of the driving transistor M0 via the turned-on data voltage writing transistor M01, the threshold grabbing transistor M02 and the driving transistor M0. The first scan line 21 is electrically connected to the gate of the threshold grabbing transistor M02. In the data voltage writing phase Td of the pixel circuit 11, the first scan line 21 transmits an enable signal to control the threshold grabbing transistor M02 to turn on; in the non-data voltage writing phase of the pixel circuit 11, the first scan line 21 transmits a non-enable signal to control the threshold grabbing transistor M02 to turn off. In some embodiments, the threshold grabbing transistor M02 may be an N-channel transistor. When the threshold grabbing transistor M02 is an N-channel transistor, the problem of unsatisfactory light emitting brightness of the light emitting device caused by the change of the gate potential of the driving transistor M0 due to leakage current can be effectively improved.

[0081] like Fig. 9 As shown, the data voltage write transistor M01 may be a P-channel transistor, and the gate of the data voltage write transistor M01 and the gate of the threshold grab transistor M02 may be electrically connected to different scan lines 20. In some embodiments, the data voltage write transistor M01 may also be an N-channel transistor, and the gate of the data voltage write transistor M01 and the gate of the threshold grab transistor M02 may be electrically connected to the first scan line 21 at the same time.

[0082] like Fig. 9 As shown, the pixel circuit 11 may further include a first reset transistor M03, a second reset transistor M04, a power supply voltage writing transistor M05, a light emitting control transistor M06 and a storage capacitor Cst, and the storage capacitor Cst is electrically connected to the gate of the driving transistor M0.

[0083] The first electrode of the first reset transistor M03 is electrically connected to the reset signal line, the second electrode of the first reset transistor M03 is electrically connected to the gate of the driving transistor M0, the first electrode of the second reset transistor M04 is electrically connected to the reset signal line, and the second electrode of the second reset transistor M04 is electrically connected to the output end of the pixel circuit 11. The first reset transistor M03 and the second reset transistor M04 can be turned on in the reset phase of the pixel circuit 11, and reset the gate of the driving transistor M0 and the output end of the pixel circuit 11 respectively. In some embodiments, at least one of the gate of the first reset transistor M03 and the gate of the second reset transistor M04 can be electrically connected to the first scan line 21, and the first end of the first scan line 21 can be electrically connected to the first shift register 301, and the second end of the first scan line 21 can be electrically connected to the first compensation module 401, so as to improve the reset effect of the pixel circuit 11 near the first end and the second end of the first scan line 21.

[0084] The first electrode of the power supply voltage writing transistor M05 is electrically connected to the first power supply voltage line, the second electrode of the power supply voltage writing transistor M05 is electrically connected to the first electrode of the driving transistor M0, the first electrode of the light emitting control transistor M06 is electrically connected to the second electrode of the driving transistor M0, and the second electrode of the light emitting control transistor M06 can be electrically connected to the light emitting device as the output end of the pixel circuit 11, and the power supply voltage writing transistor M05 and the light emitting control transistor M06 can be turned on in the light emitting stage of the pixel circuit 11, and control the driving transistor M0 to generate a driving current. In some embodiments, at least one of the gate of the power supply voltage writing transistor M05 and the gate of the light emitting control transistor M06 can be electrically connected to the first scan line 21, and the first end of the first scan line 21 can be electrically connected to the first shift register 301, and the second end of the first scan line 21 can be electrically connected to the first compensation module 401, so as to improve the uniformity of the light emitting brightness of the pixel circuit 11 near the first end and the second end of the first scan line 21.

[0085] In addition, the output end of the light emitting control transistor M06 can be electrically connected to the light emitting device EL, and the light emitting device EL can be at least one of an organic light emitting diode (OLED), a micro light emitting diode (Micro-LED), a sub-millimeter light emitting diode (Mini-LED), etc.

[0086] It should be noted that Fig. 9 It is merely an illustration of a possible pixel circuit 11 involved in the embodiment of the present application. The pixel circuit 11 in an actual product may also be a pixel circuit 11 with other structures.

[0087] Fig.10 A schematic diagram of the connection between a shift register and a compensation module and a first scan line provided in an embodiment of the present application is shown in FIG. Fig.11 for Fig.10A corresponding working timing diagram.

[0088] In some embodiments of the present application, reference Fig.10 The display panel 01 further includes a first signal line SL1 and a first control line CL1.

[0089] The input end of the enable output module 31 of the shift register 300 included in the first scan driving circuit 30 is electrically connected to the first signal line SL1. The enable output module 31 is used to transmit the signal on the first signal line SL1 to the first scan line 21 when turned on. s1 represents the signal transmitted on the first signal line SL1. Fig.10 and Fig.11 The first signal line SL1 can transmit an enable signal in the enable phase T1 of the shift register 300 to which it is electrically connected, can switch from transmitting an enable signal to transmitting a non-enable signal in the switching period T20 in the non-enable phase T2 of the shift register 300 to which it is electrically connected, and can transmit a non-enable signal in another period after the switching period T20 in the non-enable phase T2 of the shift register 300 to which it is electrically connected.

[0090] The first control line CL1 is electrically connected to the control end of the compensation module 400 included in the first compensation module group 40. The effective level signal transmitted by the first control line CL1 controls the compensation module 400 to be turned on, and the ineffective level signal transmitted by the first control line CL1 controls the compensation module 400 to be turned off. Wherein, cl represents the signal transmitted on the first control line CL1. Unless otherwise specified, the following description is taken as an example that the effective level signal is a high level. When the first control line CL1 transmits a high level, the first compensation module 401 is turned on; when the first control line CL1 transmits a low level, the first compensation module 401 is turned off.

[0091] In the embodiment of the present application, in the first control line CL1 and the first signal line SL1 electrically connected to the shift register 300 included in the first scan driving circuit 30 and the compensation module 400 included in the first compensation module group 40 respectively connected to the same first scan line 21, in the switching period T20, the signal on the first control line CL1 is a valid level signal before the signal on the first signal line SL1 becomes a non-enable signal. For example, in combination Fig.10 and Fig.12In the first signal line SL1 and the first control line CL1 electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21, before the signal s1 on the first signal line SL1 changes to a low level during the switching period T20, the signal cl on the first control line CL1 is already at a high level. In this way, in the first shift register 301 and the first compensation module 401 electrically connected to the same first scan line 21, the first compensation module 401 is already turned on before the first shift register 301 ends the switching period T20.

[0092] In some implementations, in the first control line CL1 and the first signal line SL1 electrically connected to the shift register 300 included in the first scan driving circuit 30 and the compensation module 400 included in the first compensation module group 40 respectively connected to the same first scan line 21, in the switching period T20, the start time of the signal cl on the first control line CL1 switching from the non-valid level signal to the valid level signal is the same as the start time of the signal sl on the first signal line SL1 switching from the enable signal to the non-enable signal. For example, in combination Fig.10 and Fig.11 In the first signal line SL1 and the first control line CL1 electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21, in the switching period T20, the moment when the signal cl on the first control line CL1 starts to switch from a low level to a high level is the same as the moment when the signal sl on the first signal line SL1 starts to switch from a high level to a low level. In this way, in the first shift register 301 and the first compensation module 401 electrically connected to the same first scan line 21, the first compensation module 401 is already turned on before the first shift register 301 ends the switching period T20.

[0093] In this implementation, the signal transmitted by the first signal line SL1 and the signal transmitted by the first control line CL1 change at the same time, and the generation of the two signals is easy and reduces the computing power of the driving module.

[0094] Fig.12 for Fig.10 Another corresponding working timing diagram.

[0095] In some implementations, in the first control line CL1 and the first signal line SL1 electrically connected to the shift register 300 included in the first scan driving circuit 30 and the compensation module 400 included in the first compensation module group 40 respectively, which are electrically connected to the same first scan line 21, before the start of the switching period T20, the signal cl on the first control line CL1 starts to switch from a non-valid level signal to a valid level signal. The compensation module 400 may include a transistor. Considering the time required for the transistor to switch from off to on, the time when the signal cl on the first control line CL1 starts to switch from a non-valid level signal to a valid level is advanced to before the switching period T20, so as to ensure that when the potential of the first end of the first scan line 21 starts to change in the non-enable phase T2, the compensation module 400 electrically connected to the first scan line 21 has been turned on so that the potential of the second end of the first scan line 21 also starts to change. For example, in combination with Fig.10 and Fig.12 In the first signal line SL1 and the first control line CL1 respectively electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21, the moment when the signal cl on the first control line CL1 starts to switch from a low level to a high level is slightly earlier than the moment when the signal sl on the first signal line SL1 starts to switch from a low level to a high level in the switching period T20.

[0096] The time required for the transistor to switch from off to on, when the moment when the signal cl on the first control line CL1 starts to switch from a low level to a high level is slightly earlier than the moment when the signal sl on the first signal line SL1 starts to switch from a low level to a high level in the switching period T20, the first compensation module 401 can be turned on as early as possible in the switching period T20 of the corresponding first shift register 301, so as to ensure that the second end of the first scan line 21 can start to switch to the non-enable signal as early as possible in the switching period T20.

[0097] Fig.13 An equivalent circuit diagram of a compensation module provided in an embodiment of the present application.

[0098] In some embodiments of the present application, Fig.13 As shown, the compensation module 400 in the first compensation module group 40 includes a compensation transistor M00, which is an N-channel transistor, and the gate of the compensation transistor M00 is electrically connected to the first control line CL1. Since the N-channel transistor is turned on when its gate receives a high level and is turned off when it receives a low level, the high level transmitted by the first control line CL1 is a valid level signal and the low level transmitted by the first control line CL1 is a non-valid level signal.

[0099] In some implementations, the first scan line 21 is electrically connected to the gate of an N-channel transistor in the data voltage writing module 111. Since the N-channel transistor is turned on when its gate receives a high level and is turned off when it receives a low level, the high level transmitted by the first scan line 21 is an enable signal and the low level transmitted by the first scan line 21 is a disable signal. Correspondingly, the high level transmitted by the first signal line SL1 is an enable signal and the low level transmitted by the first signal line SL1 is a disable signal.

[0100] Among them, combined Fig.13 and Fig.11 and Fig.12 In the first control line CL1 and the first signal line SL1 respectively electrically connected to the shift register 300 included in the first scan driving circuit 30 and the compensation module 400 included in the first compensation module group 40 electrically connected to the same first scan line 21, in the switching period T20, the rising edge of the signal cl transmitted by the first control line CL1 and the falling edge of the signal sl transmitted by the first signal line SL1 at least partially overlap. That is, in the first signal line SL1 and the first control line CL1 respectively electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21, in the switching period T20, the rising edge of the signal cl transmitted by the first control line CL1 and the falling edge of the signal sl transmitted by the first signal line SL1 at least partially overlap. In this way, in the process of switching the potential of the first end of the first scan line 21 from the enable signal to the non-enable signal, the potential of the second end of the first scan line 21 is also switched from the enable signal to the non-enable signal.

[0101] Fig.14 An equivalent circuit diagram of a shift register and a compensation module provided in an embodiment of the present application, Fig.15 for Fig.14 A corresponding working timing diagram.

[0102] In some embodiments of the present application, Fig.14As shown, the enable output module 31 of the shift register 300 includes a first transistor M1, an input terminal of the first transistor M1 is electrically connected to the first signal line SL1, an output terminal of the first transistor M1 is electrically connected to the first terminal of the first scan line 21, and a gate of the first transistor M1 is electrically connected to the first node PU. The disable output module 32 of the shift register 300 includes a second transistor M2 and a third transistor M3, input terminals of the second transistor M2 and the third transistor M3 are both electrically connected to the second disable signal line VGL2, output terminals of the second transistor M2 and the third transistor M3 are electrically connected to the first terminal of the first scan line 21, a gate of the second transistor M2 is electrically connected to the second node PD, and a gate of the third transistor M3 is electrically connected to the second control line CL3. The control module 33 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a first capacitor C1, the input end of the fourth transistor M4 is electrically connected to the enable signal line VGH, the output end of the fourth transistor M4 is electrically connected to the first node PU, the gate of the fourth transistor M4 is electrically connected to the trigger end STV, the input end of the fifth transistor M5 is electrically connected to the second non-enable signal line VGL2, the output end of the fifth transistor M5 is electrically connected to the first node PU, the gate of the fifth transistor M5 is electrically connected to the output end of the next stage shift register 300 The sixth transistor M6 is electrically connected to the second non-enable signal line VGL2, the output end of the sixth transistor M6 is electrically connected to the first node PU, the gate of the sixth transistor M6 is electrically connected to the second node PD, the input end of the seventh transistor M7 is electrically connected to the second non-enable signal line VGL2, the output end of the seventh transistor M7 is electrically connected to the first node PU, the gate of the seventh transistor M7 is electrically connected to the third control line CL3, the first plate of the first capacitor C1 is electrically connected to the first node PU and the second plate is electrically connected to the output end of the first transistor M1. The control module 33 also includes an eighth transistor M8 and a ninth transistor M9 and a second capacitor C2, wherein the input terminal of the eighth transistor M8 is electrically connected to the second non-enable signal line VGL2, the output terminal of the eighth transistor M8 is electrically connected to the second node PD, the gate of the eighth transistor M8 is electrically connected to the first node PU, the input terminal of the ninth transistor M9 is electrically connected to the second non-enable signal line VGL2, the output terminal of the ninth transistor M9 is electrically connected to the first end of the first scan line 21, the gate of the ninth transistor M9 is electrically connected to the third control line CL3, the first electrode of the second capacitor C2 is electrically connected to the first signal line SL1, and the second electrode of the third transistor M3 is electrically connected to the second node PD. When the shift register 300 is the first stage shift register 300 in the scan drive circuit, the corresponding trigger terminal STV is the trigger signal line; when the shift register 300 is not the first stage shift register 300 in the scan drive circuit, the corresponding trigger terminal STV can be the output terminal of the previous stage shift register 300.

[0103] The compensation module 400 includes a compensation transistor M00 , whose input terminal is electrically connected to the first non-enable signal line VGL1 , whose output terminal is electrically connected to the second end of the first scan line 21 , and whose gate is electrically connected to the first control line CL1 .

[0104] Among them, Fig.14 As shown, the first transistor M1 to the ninth transistor M9 and the compensation transistor M00 can all be N-channel transistors. For the first transistor M1 to the ninth transistor M9 and the compensation transistor M00, the effective level signal that controls them to turn on is a high level signal and the ineffective level signal that controls them to turn off is a low level signal.

[0105] In addition, at least some of the first transistor M1 to the ninth transistor M9 and the compensation transistor M00 may also be P-channel transistors. Fig.14 The equivalent circuit diagram of the shift register 300 and the compensation module 400 is merely shown. The shift register 300 and the compensation module 400 may also be equivalent circuit diagrams of other forms. Fig.14 The shift register 300 shown may be an equivalent circuit diagram of the first shift register 301. Fig.14 The compensation module 400 shown may be an equivalent circuit diagram of the first compensation module 401 .

[0106] This embodiment uses Fig.14 The shift register 300 and compensation module 400 shown in the figure are used as an example for explanation. In addition, p1 represents the signal of the first node PU, p2 represents the signal of the second node PD, cl represents the signal on the first control line CL1, cl02 represents the signal on the second control line CL2, cl03 represents the signal on the third control line CL3, st represents the signal on the trigger end STV, sl represents the signal on the first signal line, out1 represents the signal outputted from the output end OUT1 of the current stage shift register 300, and out2 represents the signal outputted from the output end OUT2 of the next stage shift register 300. Fig.14 and Fig.15 The operation process of the first shift register 301 is described.

[0107] Combination Fig.14 and Fig.15 The shift register 300 includes a reset phase T00, a trigger phase T0, an enable phase T1, a disable phase T2, a shutdown phase T3 and a maintenance phase T4.

[0108] In the reset stage T00, the signal transmitted by the third control line CL3 is at a high level, then the seventh transistor M7 and the ninth transistor M9 are both turned on, and the potential of the first node PU is at a low level, and the potential of the first end of the first scan line 21 is also at a low level; in addition, the second node PD maintains a high level, so that the second transistor M2 and the sixth transistor M6 are turned on, but the low level potential of the first node PU and the low level potential of the output end OUT1 of the shift register 300 are not changed. It should be noted that all shift registers 300 in the first scan driving circuit 30 can enter the reset stage T00 at the same time.

[0109] In the triggering stage T0, the triggering terminal STV receives a high level, the fourth transistor M4 is turned on, and the turned-on fourth transistor M4 outputs a high level to the first node PU. Based on the high level of the first node PU, the first transistor M1 and the eighth transistor M8 are turned on. At this time, the first signal line SL1 transmits a low level signal so that the output terminal OUT1 of the shift register 300 maintains an output low level to the first end of the first scan line 21, and the turned-on eighth transistor M8 outputs a low level to the second node PD, thereby turning off the second transistor M2 and the sixth transistor M6. In addition, in the triggering stage T0, the first control line CL1 and the second control line CL2 can transmit a high level signal, the compensation transistor M00 and the third transistor M3 are turned on, so that the output terminal OUT1 of the shift register 300 maintains an output low level to the first end of the first scan line 21 and the compensation module outputs a low level to the second end of the first scan line 21.

[0110] In the enabling phase T1, the trigger terminal STV receives a low level to turn off the fourth transistor M4, and the first capacitor C1 maintains the first node PU at a high level, so the first transistor M1 and the eighth transistor M8 remain turned on, and the turned-on eighth transistor M8 maintains the second node PD at a stable low level. At this time, the signal s1 transmitted by the first signal line SL1 is switched to a high level, the output terminal of the turned-on first transistor M1 outputs a high level and further pulls up the potential of the first node PU through the coupling effect of the first capacitor C1, and the output terminal OUT1 of the shift register 300 outputs a high level to the first end of the first scan line 21.

[0111] In the non-enabling stage T2, the first node PU maintains a high level so that the first transistor M1 and the eighth transistor M8 maintain an on state, and the signal s1 transmitted on the first signal line SL1 is switched from a high level to a low level in this stage, and the signal output from the output end OUT1 of the shift register 300 to the first end of the first scan line 21 is switched from a high level to a low level. In addition, in order to avoid interference between different signals, the second control line CL2 starts to transmit a high level after a period of time from the start of the non-enabling stage T2. Therefore, in the initial stage of the non-enabling stage T2, it mainly depends on the turned-on first transistor M1 to release the charge on the first scan line 21 and to switch the signal on the first scan line 21 to a non-enabling signal in time. In the non-enabling stage T2, the first control line CL1 also transmits a high level to control the compensation transistor M00 to turn on and transmit a low level to the second end of the first scan line 21. In order to ensure that the second end of the first scan line 21 can be switched from a high level to a low level in time, before the end of the switching period T20 of the non-enabling stage T2, the signal cl on the first control line CL1 is already at a high level and the signal sl on the first signal line SL1 has not completely changed to a low level. The specific situation of the signal cl on the first control line CL1 and the signal sl on the first signal line SL1 in the switching period T20 can be as follows: Fig.11 and Fig.12 As shown, no further description is given here.

[0112] In the off phase T3, the output terminal OUT2 of the next stage shift register 300 outputs a high level signal to turn on the fifth transistor M5, and the turned-on fifth transistor M5 transmits a low level to the first node PU. In addition, the signal s1 transmitted on the first signal line SL1 is switched from a low level to a high level, and the potential of the first node PD becomes a high level through the coupling effect of the second capacitor C2, and the second transistor M2 and the sixth transistor M6 are turned on, thereby causing the output terminal OUT1 of the shift register 300 to output a low level to the first end of the first scan line 21.

[0113] The maintenance phase T4 includes a first maintenance phase T41 and a second maintenance phase T42 which are performed alternately. In the first maintenance phase T41, the second control line CL2 transmits a high level, so that the third transistor M3 is turned on, and the turned-on third transistor M3 causes the output terminal OUT1 of the shift register 300 to output a low level to the first end of the first scan line 21. In the second maintenance phase T42, the signal s1 transmitted on the first signal line SL1 is switched to a high level again, and the potential of the first node PD becomes a high level through the coupling effect of the second capacitor C2, and the second transistor M2 and the sixth transistor M6 are turned on, thereby causing the output terminal OUT1 of the shift register 300 to output a low level to the first end of the first scan line 21. The signal s1 transmitted on the first signal line SL1 and the signal cl02 transmitted on the second control line CL2 are both periodic pulse signals, so that the first maintenance phase T41 and the second maintenance phase T42 are performed alternately.

[0114] In some embodiments of the present application, Figure 3 As shown, the display panel 01 includes a display area AA, and the first compensation module group 40 and the first scan driving circuit 30 are located on opposite sides of the display area AA along a first direction X, wherein the first direction X is parallel to the extension direction of the first scan line 21. Figure 3 As shown, the first scan line 21 extends substantially along the row direction, and one of the first scan driving circuit 30 and the first compensation module group 40 is located on the left side of the display area AA and the other is located on the right side of the display area AA.

[0115] The first compensation module group 40 and the first scan driving circuit 30 are respectively located on opposite sides of the display area AA in a direction parallel to the extension direction of the first scan line 21. Then the shift register 300 in the first scan driving circuit 30 can be arranged adjacent to the first end of the first scan line 21, so that the output end of the first enable output module 311 is electrically connected to the first end of the first scan line 21; the compensation module 400 in the first compensation module group 40 can be arranged adjacent to the second end of the first scan line 21, so that the output end of the first compensation module 401 is electrically connected to the second end of the first scan line 21. Among them, the connection difficulty of the first shift register 301 and the first compensation module 401 and the first scan line 21 is small, and the wiring difficulty is small; and the transmission path of the signal output by the first shift register 301 to the first scan line is short, and the transmission path of the signal output by the first compensation module 401 to the first scan line 21 is short, which reduces signal delay and voltage drop.

[0116] In some implementations, all the first scan lines 21 are electrically connected to the shift register 300 in the first scan drive circuit 30. Figure 3 As shown, the shift registers 300 electrically connected to the first scan line 21 are all located on the same side of the display area AA, for example, Figure 3 As shown, the shift registers 300 electrically connected to the first scan lines 21 are all located on the left side of the display area AA.

[0117] In these implementations, the first compensation module 401 electrically connected to the first scan line 21 is also located on the same side of the display area AA. Figure 3 As shown, the compensation modules 400 electrically connected to the first scan lines 21 are all located on the right side of the display area AA.

[0118] Fig.16 A schematic diagram of a display panel provided in an embodiment of the present application.

[0119] In some possible implementations, such as Fig.16 As shown, the display panel 01 further includes a second scan driving circuit 30', which may include a plurality of cascaded shift registers 300. For ease of description, the shift register 300 included in the second scan driving circuit 30' is referred to as a second shift register 302.

[0120] refer to Fig.16 , the first ends of some of the first scan lines 21 are electrically connected to the output ends of the second shift register 302 and the first ends of some of the first scan lines 21 are electrically connected to the output ends of the first shift register 301, wherein the first scan driving circuit 30 and the second scan driving circuit 30' are respectively located on opposite sides of the display area AA in a direction parallel to the extending direction of the first scan lines 21. For example, Fig.16 As shown, the first scan driving circuit 30 and the second scan driving circuit 30' are respectively located at the left and right sides of the display area AA.

[0121] In these implementations, correspondingly, the display panel 01 may further include a second compensation module group 40', and the second compensation module group 40' includes a plurality of compensation modules 400. For ease of description, the compensation module 400 included in the second compensation module group 40' is referred to as a second compensation module 402. Then the second end of the first scan line 21 electrically connected to the second shift register 302 is electrically connected to the second compensation module 402, wherein the first compensation module group 40 and the second compensation module group 40' are respectively located on opposite sides of the display area AA in a direction parallel to the extension direction of the first scan line 21. For example, Fig.16 As shown, the first scan driving circuit 30 and the second compensation module group 40 ′ are located on the left side of the display area AA, and the second scan driving circuit 30 ′ and the first compensation module group 40 are located on the right side of the display area AA.

[0122] The shift register 300 in the second scan driving circuit 30 ′ may also include an enable output module 31 , which is referred to as a second enable output module. The output end of the second enable output module is electrically connected to the first scan line 21 .

[0123] like Fig.16 As shown, the first scan line 21 includes a first sub-scan line 211 and a second sub-scan line 212, that is, part of the first scan line 21 is the first sub-scan line 211 and part of the first scan line 21 is the second sub-scan line 212. The display panel 01 also includes a second compensation module group 40', the second scan drive circuit 30' includes a multi-stage cascaded shift register 300, and the second compensation module group 40' includes a plurality of compensation modules 400. For ease of description, the shift register 300 in the second scan drive circuit 30' is named a second shift register 302, and the compensation module 400 in the second compensation module group 40' is named a second compensation module 402. The first scan drive circuit 30 and the second compensation module group 40' are located on the same side of the display area AA, the second scan drive circuit 30' and the first compensation module group 40 are located on the same side of the display area AA, and the first scan drive circuit 30 and the second scan drive circuit 30' are located on opposite sides of the display area AA. For example, as Fig.16 As shown, the first scan driving circuit 30 and the second compensation module group 40' are located on the left side of the display area AA, and the second scan driving circuit 30' and the first compensation module 401 are located on the right side of the display area AA. The output end of the enabling output module 31 in the first scan driving circuit 30 is electrically connected to the first end of the first sub-scanning line 211, and the output end of the compensation module 400 in the first compensation module group 40 is electrically connected to the second end of the first sub-scanning line 211; the output end of the enabling output module 31 in the second scan driving circuit 30' is electrically connected to the first end of the second sub-scanning line 212, and the output end of the compensation module 400 in the first compensation module group 40 is electrically connected to the second end of the second sub-scanning line 212. That is, the output end of the first enable output module 311 is electrically connected to the first end of the first sub-scan line 211 and the output end of the first compensation module 401 is electrically connected to the second end of the first sub-scan line 211, the output end of the second enable output module 31 is electrically connected to the first end of the second sub-scan line 212 and the output end of the second compensation module 402 is electrically connected to the second end of the second sub-scan line 212.

[0124] Among them, the second shift register 302 and the first shift register 301 in these implementations are both used to provide an enable signal and a disable signal for the first scan line 21, and the second compensation module 402 and the first compensation module 401 are both used to switch the second end of the first scan line 21 from the enable signal to the disable signal in a timely manner. That is, in these implementations, the second shift register 302 and the second compensation module 402 can be designed based on the same inventive concept as the first shift register 301 and the first compensation module 401, and will not be repeated here.

[0125] In some implementations, the second shift register 302 in the second scan drive circuit 30' is not electrically connected to the first scan line 21, but is electrically connected to other types of scan lines. For example, the scan line electrically connected to the first shift register 301 in the first scan drive circuit 30 is electrically connected to the gate of the threshold capture transistor M02 in the pixel circuit 11, and the scan line electrically connected to the second shift register 302 in the second scan drive circuit 30' can be electrically connected to the gate of any one of the first reset transistor M03, the second reset transistor M04, the power supply voltage writing transistor M05, and the light emission control transistor M06.

[0126] Fig.17 A schematic diagram of a display panel provided in an embodiment of the present application.

[0127] In some embodiments of this application, please refer to Fig.17 , some compensation modules 400 in the first compensation module group 40 are electrically connected to different first control lines CL1. Fig.17 As shown, the number of first control lines CL1 electrically connected to all compensation modules in the first compensation module group 40 is 4, wherein one first control line CL1 among the four first control lines CL1 is electrically connected to the control end of the 1st, 5th, 9th, ... first compensation modules 401 in the first compensation module group 40, one first control line CL1 is electrically connected to the control end of the 2nd, 6th, 10th, ... first compensation modules 401 in the first compensation module group 40, one first control line CL1 is electrically connected to the control end of the 3rd, 7th, 11th, ... first compensation modules 401 in the first compensation module group 40, and one first control line CL1 is electrically connected to the control end of the 4th, 8th, 12th, ... first compensation modules 401 in the first compensation module group 40.

[0128] At least some of the compensation modules 400 in the first compensation module group 40 are electrically connected to different first control lines CL1, that is, the number of compensation modules 400 electrically connected to the first control line CL1 is reduced, so that the load of the first control line CL1 is smaller, and then the first control lines CL1 can control the compensation modules 400 electrically connected thereto to switch on and off as quickly as possible. That is, the time length for the second end of the first scan line 21 to switch from an enable signal to a non-enable signal can be made faster.

[0129] It can be understood that in order to reduce the number of wirings, one first control line CL1 needs to be electrically connected to the plurality of compensation modules 400 in the first compensation module group 40 .

[0130] Fig.18 A schematic diagram of a display panel provided in an embodiment of the present application.

[0131] In some embodiments of the present application, Fig.18 As shown, some shift registers 300 in the first scan driving circuit 30 are electrically connected to different first signal lines SL1. Fig.18 As shown, the number of first signal lines SL1 electrically connected to all shift registers 300 in the first scanning drive circuit 30 is 4, wherein one first signal line SL1 among the four first signal lines SL1 is electrically connected to the input ends of the first shift registers 301 of the 1st level, the 5th level, the 9th level, ... in the first shift register 301 group, one first signal line SL1 is electrically connected to the input ends of the first shift registers 301 of the 2nd level, the 6th level, the 10th level, ... in the first shift register 301 group, one first signal line SL1 is electrically connected to the input ends of the first shift registers 301 of the 3rd level, the 7th level, the 11th level, ... in the first shift register 301 group, and one first signal line SL1 is electrically connected to the input ends of the first shift registers 301 of the 4th level, the 8th level, the 12th level, ... in the first shift register 301 group.

[0132] The first signal lines SL1 electrically connected to at least some of the shift registers 300 in the first scan driving circuit 30 are different, that is, the number of shift registers 300 electrically connected to the first signal line SL1 is reduced, so that the load of the first signal is smaller, and thus the accuracy of the signals transmitted by these first signals when they are output by the first enable output module 311 on the first scan line 21 is improved.

[0133] It can be understood that in order to reduce the number of wirings, one first signal line SL1 needs to be electrically connected to a plurality of shift registers 300 in the first scan driving circuit 30 .

[0134] In addition, when the first scan line 21 is electrically connected to the control end of the data voltage writing module 111 in the pixel circuit 11, the first signal lines SL1 electrically connected to the adjacent shift registers 300 in the first scan driving circuit 30 are different, and the pre-charging of the data voltage can also be achieved. That is, for the adjacent two shift registers 300 in the first scan driving circuit 30, the upper shift register 300 outputs the enable signal transmitted by the first signal line SL1 electrically connected to it to control the pixel circuit 11 electrically connected to it to write the data voltage for a part of the time period, and the lower shift register 300 can also output the enable signal transmitted by the first signal line SL1 electrically connected to it to control the data voltage writing module 111 of the pixel circuit 11 electrically connected to it to turn on to achieve the pre-charging of the data voltage.

[0135] Fig.19 A schematic diagram of a display panel provided in an embodiment of the present application.

[0136] In some implementations, the number of first signal lines SL1 electrically connected to the first scan driving circuit 30 is equal to the number of first control lines CL1 electrically connected to the first compensation module group 40. Fig.19 As shown, the number of first control lines CL1 electrically connected to all compensation film blocks in the first compensation module group 40 is four, and the number of first signal lines SL1 electrically connected to all shift registers 300 in the first scan driving circuit 30 is four.

[0137] When a first signal line SL1 is electrically connected to the first enable output modules 311 included in the multiple shift registers 300 in the first scan drive circuit 30, in order to achieve that the first enable output modules 311 do not output enable signals at the same time, the first signal line SL1 should transmit a multi-pulse signal; when a first control line CL1 is electrically connected to the multiple compensation modules 400 in the first compensation module group 40, in order to achieve that the compensation modules 400 do not output valid level signals at the same time, the first signal line SL1 should transmit a multi-pulse signal.

[0138] When the enable signal and the effective level signal are both at a high level or a low level, the pulse signals of the first signal line SL1 and the first control line CL1 electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21 may be the same. When one of the enable signal and the effective level signal is at a high level and the other is at a low level, the pulse signals of the first signal line SL1 and the first control line CL1 electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21 may be opposite.

[0139] Fig. 20 for Fig.19 A corresponding working timing diagram.

[0140] In one implementation, reference Fig.19 and Fig. 20 , the enable signal and the effective level signal are both high level, and the pulse signals of the first signal line SL1 and the first control line CL1 electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21 can be the same. Fig.19 and Fig. 20 In the first enable output module 311 and the first compensation module 401 respectively connected at both ends of the first scan line 211, the input end of the first enable output module 311 is electrically connected to the first signal line SL11 and the control end of the first compensation module 401 is electrically connected to the first control line CL11, wherein the pulse signals sl1 and cl1 respectively transmitted by the first signal line SL11 and the first control line CL11 are the same; in the first enable output module 311 and the first compensation module 401 respectively connected at both ends of the first scan line 212, the input end of the first enable output module 311 is electrically connected to the first signal line SL12 and the control end of the first compensation module 401 is electrically connected to the first control line CL12, wherein the pulse signals sl2 and cl2 transmitted by the first signal line SL12 and the first control line CL12 are the same. The same; in the first enable output module 311 and the first compensation module 401 respectively connected at both ends of the first scan line 213, the input end of the first enable output module 311 is electrically connected to the first signal line SL13 and the control end of the first compensation module 401 is electrically connected to the first control line CL13, wherein the pulse signals sl3 and cl3 transmitted by the first signal line SL13 and the first control line CL13 are the same; in the first enable output module 311 and the first compensation module 401 respectively connected at both ends of the first scan line 214, the input end of the first enable output module 311 is electrically connected to the first signal line SL14 and the control end of the first compensation module 401 is electrically connected to the first control line CL14, wherein the pulse signals sl4 and cl4 transmitted by the first signal line SL14 and the first control line CL14 are the same.

[0141] In this implementation, the pulse signals of the first signal line SL1 and the first control line CL1 electrically connected to the first enable output module 311 and the first compensation module 401 electrically connected to the same first scan line 21 are the same, which can reduce the computing power of the driving module used to drive the display panel 01 to emit light.

[0142] Fig.21 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0143] In some embodiments of the present application, Fig.21As shown, among the first control line CL1 and the first non-enable signal line VGL1 electrically connected to the first compensation module group 40, the first control line CL1 and the first non-enable signal line VGL1 are located at two sides of the first compensation module 401. That is, the first control line CL1 and the first non-enable signal line VGL1 electrically connected to the first compensation module 401 are respectively located at two opposite sides of the first compensation module 401.

[0144] like Fig.21 As shown, by arranging the first control line CL1 and the first non-enable signal line VGL1 on opposite sides of the first compensation module group 40 , it is convenient to connect the first control line CL1 and the first non-enable signal line VGL1 with the compensation module 400 in the first compensation module group 40 .

[0145] In some possible implementations, such as Fig.21 As shown, the first non-enabling signal line VGL1 is located between the first compensation module group 40 and the display area AA and the first control line CL1 is located at a side of the first compensation module group 40 away from the display area AA.

[0146] Fig. 22 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0147] In some possible implementations, such as Fig. 22 As shown, the first control line CL1 is located between the first compensation module group 40 and the display area AA and the first non-enabling signal line VGL1 is located at a side of the first compensation module group 40 away from the display area AA.

[0148] Fig.23 A schematic diagram of a display panel provided in an embodiment of the present application.

[0149] In some embodiments of the present application, Fig.16 and Fig.23 As shown, the display panel 01 further includes a second scanning driving circuit 30', and the second scanning driving circuit 30' also includes a multi-stage cascaded shift register 300. Fig.16 As shown, the shift register 300 in the second scan driving circuit 30' can be electrically connected to the first scan line 21, and the shift register 300 in the second scan driving circuit 30' and the shift register 300 in the first scan driving circuit 30 are electrically connected to different first scan lines 21, which will not be described in detail. Fig.23As shown, the shift register 300 in the second scan driving circuit can be electrically connected to the second scan line 22 and used to provide an enable signal and / or a non-enable signal for the second scan line 22. The transistor electrically connected to the second scan line 22 is of a different type from the transistor electrically connected to the first scan line 21. For example, the transistor electrically connected to the second scan line 22 and the transistor electrically connected to the first scan line 21 are transistors respectively included in different modules in the pixel circuit 11.

[0150] For the convenience of description, the shift register 300 in the second scan driving circuit 30 ′ is referred to as a second shift register 302 .

[0151] Alternatively, if Fig.16 As shown, the two ends of the scan line 20 electrically connected to the second shift register 302 can be electrically connected to the second shift register 302 and the second compensation module 402 respectively. Fig.23 As shown, one end of the scan line 20 electrically connected to the second shift register 302 can be electrically connected to the second shift register 302 and the other end can be suspended.

[0152] In these embodiments, the display panel 01 includes a display area AA, the second scan driving circuit 30' and the first compensation module group 40 are located on the same side of the display area AA, and the first compensation module 401 and the first scan driving circuit 30 are located on opposite sides of the display area AA. Fig.16 and Fig.23 As shown, the second scan driving circuit 30 ′ and the first compensation module group 40 are located on the right side of the display area AA, and the first scan driving circuit 30 is located on the left side of the display area AA.

[0153] In some feasible solutions, such as Fig.16 and Fig.23 As shown, the first compensation module group 40 is located on the side of the second scan driving circuit 30' close to the display area AA. Since the structure of the compensation module 400 in the first compensation module group 40 is usually simple, the area it occupies in the display panel 01 is small. The first compensation module group 40 is arranged on the side of the adjacent scan driving circuit close to the display area AA. On the one hand, the connection difficulty between the compensation module 400 in the first compensation module group 40 and the first scan line 21 is relatively small, and on the other hand, the connection difficulty between the shift register 300 in the second scan driving circuit 30' and the first scan line 21 will not be excessively increased.

[0154] Fig.24 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0155] In some possible implementations, such as Fig.24As shown, the first control line CL1 is located on the side of the first compensation module group 40 away from the second scan driving circuit 30'. When the first compensation module 401 is located between the second scan driving circuit 30' and the display area AA, the first control line CL1 is located between the first compensation module group 40 and the display area AA. Wherein, the first control line CL1 is located on the side of the first compensation module group 40 away from the second scan driving circuit 30', which can alleviate the signal crosstalk problem between the pulse signal electrically connected to the first control line CL1 and the second scan driving circuit 30'.

[0156] In addition, if Fig.24 As shown, when the first control line CL1 and the first non-enable signal line VGL1 are located at opposite sides of the first compensation module group 40, the first non-enable signal line VGL1 is located between the first compensation module group 40 and the second scan driving circuit 30'. Therefore, the first non-enable signal line VGL1 is used to isolate the signal of the second scan driving circuit 30' and the signal of the first compensation module group 40, which can reduce the signal interference of the second scan driving circuit 30' on the compensation module 400 in the first compensation module group 40.

[0157] Fig.25 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0158] Among them, please refer to Fig.25 When the first non-enable signal line VGL1 is located between the first compensation module group 40 and the second scan drive circuit 30', the first non-enable signal line VGL1 can be electrically connected to the shift register 300 in the second scan drive circuit 30'. Then the first non-enable signal line VGL1 is not only electrically connected to the compensation module 400 in the first compensation module group 40, but also electrically connected to the shift register 300 in the second scan drive circuit 30', that is, the first compensation module group 40 and the second scan drive circuit 30' share at least part of the non-enable signal line. It is beneficial to reduce the number of non-enable signal lines, reduce the frame of the display panel 01, and reduce the difficulty of wiring.

[0159] Fig.26 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0160] In some possible implementations, such as Fig.26As shown, the first non-enable signal line VGL1 is located on the side of the first compensation module 401 close to the display area AA. When the first compensation module group 40 is located between the second scan drive circuit 30' and the display area AA, the first non-enable signal line VGL1 is located between the first compensation module group 40 and the display area AA. The first non-enable signal line VGL1 is located on the side of the first compensation module group 40 far away from the second scan drive circuit 30', which can alleviate the problem that the signal in the display area AA is affected by the peripheral signal.

[0161] In addition, if Fig.26 As shown, when the first control line CL1 and the first non-enable signal line VGL1 are located at opposite sides of the first compensation module group 40 , the first control line CL1 is located at a side of the first compensation module group 40 close to the second scan driving circuit 30 ′.

[0162] It should be noted that Fig.24 and Fig.26 Only a partial structure of the shift register 300 is shown.

[0163] Fig. 27 A partial schematic diagram of a display panel provided in an embodiment of the present application.

[0164] Among them, please refer to Fig. 27 When the first control line CL1 is located between the first compensation module group 40 and the second scan driving circuit 30', the first control line CL1 can be electrically connected to the enable output module 31 of the shift register 300 in the second scan driving circuit 30'. Then the first control line CL1 is not only electrically connected to the compensation module 400 in the first compensation module group 40, but also to the shift register 300 in the second scan driving circuit 30'. This is beneficial to reducing the number of signal lines, reducing the frame of the display panel 01, and reducing the wiring difficulty.

[0165] The first control line CL1 may be electrically connected to the input end of the enable output module 31 of the shift register 300 in the second scan driving circuit 30 ′, and the enable output module 31 of the shift register 300 in the second scan driving circuit 30 ′ may output the signal on the first control line CL1 in a partial period.

[0166] Fig.28 A schematic diagram of a display panel provided in an embodiment of the present application.

[0167] In one embodiment of the present application, please refer to Fig.28The display panel 01 further includes a second non-enable signal line VGL2, which is connected between the shift register 300 in the first scan drive circuit 30 and the non-enable signal terminal PIN, and provides a non-enable signal to the first shift register 301. In addition, the first non-enable signal line VGL1 is connected between the compensation module 400 included in the first compensation module group 40 and the non-enable signal terminal PIN, and provides a non-enable signal to the first compensation module 401. Fig.28 It is shown that the first non-enable signal line VGL1 and the second non-enable signal line VGL2 are electrically connected to different non-enable signal terminals PIN. In some cases, the first non-enable signal line VGL1 and the second non-enable signal line VGL2 are electrically connected to the same non-enable signal terminal PIN.

[0168] In addition, when the display panel 01 further includes a second scan drive circuit 30', the non-enable signal line from which the shift register 300 in the second scan drive circuit 30' obtains the non-enable signal can also be connected between the shift register 300 in the second scan drive circuit 30' and the non-enable signal terminal PIN, that is, the second scan drive circuit 30' and the first compensation module group 40 do not share the non-enable signal line. In this embodiment, the first compensation module 401 and the shift register 300 may not share the non-enable signal line from which the non-enable signal is obtained.

[0169] In this embodiment, if Fig.28 As shown, the width of the first non-enable signal line VGL1 is smaller than the width of the second non-enable signal line VGL2. Since the structure of the compensation module 400 is simpler than that of the shift register 300 in the scan drive circuit, the coupling capacitor in the compensation module 400 will be smaller than the coupling capacitor of the shift register 300. The width of the first non-enable signal line VGL1 is designed to be narrower, which is conducive to reducing the border width while satisfying the requirement that the potential of the second end of the first scan line 21 is switched from the potential corresponding to the enable signal to the potential corresponding to the non-enable signal.

[0170] Fig.29 A schematic diagram of the structure of different transistors in a display panel provided in an embodiment of the present application.

[0171] In one embodiment of the present application, Fig.14 and Fig.29 The enable output module 31 of the shift register 300 in the first scan driving circuit 30 includes a first transistor M1, and the compensation module 400 in the first compensation module group 40 includes a compensation transistor M00. Fig.29The width-to-length ratio of the channel CH1 of the first transistor M1 (the ratio of the width in the row direction to the width in the column direction) indicates the width-to-length ratio of the first transistor M1, and the width-to-length ratio of the channel CH0 of the compensation transistor M00 (the ratio of the width in the row direction to the width in the column direction) indicates the width-to-length ratio of the compensation transistor M00. The width-to-length ratio of the compensation transistor M00 in the first compensation module group 40 is smaller than the width-to-length ratio of the first transistor M1 in the first scan driving circuit 30.

[0172] The load of the compensation transistor M00 is smaller than that of the first transistor M1 , so its width-to-length ratio can be made smaller, which is beneficial to reducing the border width of the display panel and reducing the difficulty of designing the circuit in the border area of ​​the display panel.

[0173] also, Fig.29 The width-to-length ratio of the channel CH2 (the ratio of the width in the row direction to the width in the column direction) is used to illustrate the width-to-length ratio of other transistors included in the shift register 300 in the first scan driving circuit 30. The width-to-length ratio of the compensation transistor M00 included in the compensation module 400 in the first compensation module group 40 is greater than the width-to-length ratio of other transistors included in the shift register 300 in the first scan driving circuit 30. For example, in combination Fig.14 and Fig.29 The width-to-length ratio of the compensation transistor M00 included in the compensation module 400 in the first compensation module group 40 is greater than the width-to-length ratio of any one of the second transistor M2 to the ninth transistor M9 included in the shift register 300 in the first scan driving circuit 30 .

[0174] In the process of the first scan line 21 switching from transmitting an enable signal to transmitting a non-enable signal, the load of the compensation transistor M00 needs to load multiple first scan lines 21 relative to other crystals included in the shift register 300 in the first scan drive circuit 30. The width-to-length ratio of the compensation transistor M00 is designed to be relatively larger, so that the speed at which the second end of the first scan line 21 switches from an enable signal to a non-enable signal can be faster.

[0175] Fig.30 A schematic diagram of a display device provided in an embodiment of the present application.

[0176] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.30 As shown, the display device includes the above-mentioned display panel 01. Of course, Fig.30 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

Claims

1. A display panel, characterized in that: include; The first scan line; a first scan driving circuit, wherein the first scan driving circuit comprises a multi-stage cascaded shift register, wherein the shift register comprises an enable output module; an output end of the enable output module of the shift register included in the first scan driving circuit is electrically connected to a first end of the first scan line; A first compensation module group, wherein the first compensation module group includes a plurality of compensation modules; an input end of the compensation module is electrically connected to the first non-enable signal line and an output end of the compensation module is electrically connected to the second end of the first scan line; Among them, in the shift register included in the first scan driving circuit electrically connected to the same first scan line and the compensation module included in the first compensation module group, the compensation module is used to be turned on during the switching period of the shift register; the switching period is the period when the enable output module switches from outputting an enable signal to outputting a non-enable signal.

2. The display panel according to claim 1, characterized in that: The display panel includes a display area, and the first compensation module group and the first scan driving circuit are located at opposite sides of the display area along a first direction; the first direction is parallel to an extending direction of the first scan line.

3. The display panel according to claim 1, characterized in that: The display panel further includes a first signal line and a first control line; The input end of the enable output module of the shift register included in the first scan driving circuit is electrically connected to the first signal line, and the enable output module is used to transmit the signal on the first signal line to the first scan line when turned on; The first control line is electrically connected to a control end of the compensation module included in the first compensation module group, the effective level signal transmitted by the first control line controls the compensation module to be turned on, and the ineffective level signal transmitted by the first control line controls the compensation module to be turned off; Among them, in the first control line and the first signal line respectively electrically connected to the shift register included in the first scan driving circuit electrically connected to the same first scan line and the compensation module included in the first compensation module group, during the switching period, the signal on the first control line is a valid level signal before the signal on the first signal line becomes a non-enable signal.

4. The display panel according to claim 3, characterized in that: In the first control line and the first signal line respectively electrically connected to the shift register included in the first scan driving circuit electrically connected to the same first scan line and the compensation module included in the first compensation module group, during the switching period, the start time of the signal on the first control line switching from a non-valid level signal to a valid level signal is the same as the start time of the signal on the first signal line switching from an enable signal to a non-enable signal.

5. The display panel according to claim 3, characterized in that: In the first control line and the first signal line respectively electrically connected to the shift register included in the first scan driving circuit electrically connected to the same first scan line and the compensation module included in the first compensation module group, before the switching period starts, the signal on the first control line starts to switch from a non-valid level signal to a valid level signal.

6. The display panel according to claim 3, characterized in that: Some of the compensation modules in the first compensation module group are electrically connected to different first control lines.

7. The display panel according to claim 6, characterized in that: The number of the first signal lines electrically connected to the first scan driving circuit is equal to the number of the first control lines electrically connected to the first compensation module group.

8. The display panel according to claim 3, characterized in that: Among the first control lines and the first non-enable signal lines electrically connected to the first compensation module group, the first control lines and the first non-enable signal lines are located at two sides of the first compensation module.

9. The display panel according to claim 3, characterized in that: The display panel further includes a second scan driving circuit, wherein the second scan driving circuit includes a multi-stage cascaded shift register; The display panel includes a display area, the second scan driving circuit and the first compensation module group are located on the same side of the display area, and the first compensation module group and the first scan driving circuit are located on two opposite sides of the display area.

10. The display panel according to claim 9, characterized in that: The first compensation module group is located at a side of the second scan driving circuit close to the display area.

11. The display panel according to claim 9 or 10, characterized in that: The first control line is located at a side of the first compensation module group away from the second scan driving circuit.

12. The display panel according to claim 11, characterized in that: The first non-enable signal line is located between the first compensation module group and the second scan driving circuit, and the first non-enable signal line is electrically connected to the shift register in the second scan driving circuit.

13. The display panel according to claim 9 or 10, characterized in that: The first non-enable signal line is located at a side of the first compensation module group close to the display area.

14. The display panel according to claim 13, characterized in that: The first control line is located at a side of the first compensation module group close to the second scan driving circuit, and the first control line is electrically connected to the enable output module of the shift register in the second scan driving circuit.

15. The display panel according to claim 9, characterized in that: The first scan line includes a first sub-scan line and a second sub-scan line; the display panel further includes a second compensation module group, the second scan drive circuit includes a multi-stage cascaded shift register, and the second compensation module group includes a plurality of compensation modules; Wherein, the first scan driving circuit and the second compensation module group are located on the same side of the display area, the second scan driving circuit and the first compensation module are located on the same side of the display area, and the first scan driving circuit and the second scan driving circuit are located on opposite sides of the display area; The output end of the enable output module in the first scan drive circuit is electrically connected to the first end of the first sub-scan line, and the output end of the compensation module in the first compensation module group is electrically connected to the second end of the first sub-scan line; the output end of the enable output module in the second scan drive circuit is electrically connected to the first end of the second sub-scan line, and the output end of the compensation module in the first compensation module group is electrically connected to the second end of the second sub-scan line.

16. The display panel according to claim 1, characterized in that: The display panel also includes a second non-enable signal line, which is connected between the shift register in the first scan drive circuit and the non-enable signal terminal, and the first non-enable signal line is connected between the compensation module included in the first compensation module group and the non-enable signal terminal; the width of the first non-enable signal line is smaller than the width of the second non-enable signal line.

17. The display panel according to claim 1, characterized in that: The enable output module of the shift register in the first scanning driving circuit includes a first transistor; the compensation module in the first compensation module group includes a compensation transistor; the width-to-length ratio of the compensation transistor in the first compensation module group is smaller than the width-to-length ratio of the first transistor in the first scanning driving circuit and larger than the width-to-length ratio of other transistors included in the shift register in the first scanning driving circuit.

18. The display panel according to claim 1, characterized in that: The display panel further includes a pixel circuit and a data line, the pixel circuit includes a driving transistor and a data voltage writing module, the input end of the data voltage writing module is electrically connected to the data line and the data voltage writing module is used to transmit the data voltage transmitted on the data line to the driving transistor; The first scan line is electrically connected to a control end of the data voltage writing module.

19. The display panel according to claim 18, characterized in that: The data voltage writing module includes an N-channel transistor, and the first scan line is electrically connected to a gate of the N-channel transistor included in the data voltage writing module.

20. The display panel according to claim 19, characterized in that: The compensation module in the first compensation module group includes a compensation transistor, the compensation transistor is an N-channel transistor, and a gate of the compensation transistor is electrically connected to the first control line; Among them, in the first control line and the first signal line to which the shift register included in the first scan driving circuit electrically connected to the same first scan line and the compensation module included in the first compensation module group are respectively electrically connected, during the switching period, the rising edge of the signal transmitted by the first control line and the falling edge of the signal transmitted by the first signal line at least partially overlap.

21. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-20.

Images