Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate comprises a gate drive circuit and a detection signal line, the gate drive circuit comprises a shifting register set and a virtual register, the shifting register set comprises N shifting registers arranged in a cascade mode, the virtual register is cascaded to the Nth-stage shifting register, and N is a positive integer greater than or equal to 1; the detection signal line is electrically connected to the output end of the virtual register. In the embodiment of the invention, the last row of shift registers can be isolated from the detection signal line by virtue of the virtual register, so that the load influence of the detection signal line on the last row of shift registers at the output end is reduced, and the load difference of the last row of shift registers relative to other rows of shift registers at the output end is reduced; therefore, the display difference of the last row or rows of light-emitting elements relative to other rows of light-emitting elements is reduced, and the display uniformity of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of science and technology, the field of display panels has also achieved tremendous progress and diversified development. On this basis, people's requirements for display panels are also increasing day by day. How to improve the reliability of display panels while meeting performance requirements has become one of the research directions of manufacturers. Summary of the invention

[0003] The embodiments of the present application provide an array substrate, a display panel and a display device, which can improve the reliability of the display panel.

[0004] In the first aspect, an embodiment of the present application provides an array substrate, the array substrate includes a gate drive circuit and a detection signal line, the gate drive circuit includes a shift register group and a virtual register, the shift register group includes N shift registers arranged in cascade, the virtual register is cascaded to the Nth stage shift register, and the detection signal line is electrically connected to the output end of the virtual register.

[0005] In a second aspect, an embodiment of the present application provides a display panel, which includes an array substrate and a light-emitting element in any of the aforementioned embodiments.

[0006] In a third aspect, an embodiment of the present application provides a display device, which includes a display panel in any of the aforementioned embodiments.

[0007] The embodiment of the present application provides an array substrate, a display panel and a display device, in which a virtual register is added, and the virtual register is cascaded to the Nth shift register, that is, the virtual register is cascaded to the last row shift register. On this basis, the detection signal line is not electrically connected to the output end of the last row shift register, but is electrically connected to the output end of the virtual register. In this way, the last row shift register can be isolated from the detection signal line by means of the virtual register, thereby reducing the load influence of the detection signal line on the last row shift register at the output end, reducing the load difference of the last row shift register relative to other rows of shift registers at the output end, thereby reducing the display difference of the last row or several rows of light-emitting elements relative to other rows of light-emitting elements, and improving the display uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 is a structural schematic diagram of a local circuit in an array substrate provided in an embodiment of the present application;

[0010] Figure 2 It is a simplified structural schematic diagram of a local circuit in an array substrate provided in an embodiment of the present application;

[0011] Figure 3a and Figure 3b It is a simplified circuit diagram of two pixel circuits in the array substrate provided in an embodiment of the present application;

[0012] Figure 4 This is a simplified structural diagram of a local circuit in another array substrate provided in an embodiment of the present application;

[0013] Figure 5 This is a simplified structural diagram of a local circuit in another array substrate provided in an embodiment of the present application;

[0014] Figure 6 It is a simplified circuit diagram of a shift register in a first gate driving circuit in an array substrate provided by an embodiment of the present application;

[0015] Figure 7 It is a simplified circuit diagram of a shift register in a fifth gate driving circuit in an array substrate provided in an embodiment of the present application;

[0016] Figure 8 It is a simplified schematic diagram of a circuit of an electrostatic shielding unit in an array substrate provided in an embodiment of the present application;

[0017] Fig. 9 is a structural schematic diagram of a local circuit in another array substrate provided in an embodiment of the present application;

[0018] Fig.10 is a structural schematic diagram of a local circuit in an array substrate provided in an embodiment of the present application;

[0019] Fig.11a and Fig.11b Schematic diagram of the partial cross-sectional structure of two array substrates provided in the embodiments of the present application

[0020] Fig.12 is a schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application;

[0021] Fig.13 It is a structural schematic diagram of a display device provided in an embodiment of the present application.

[0022] Marking Description:

[0023] 100, array substrate; 200, display panel; 300, display device;

[0024] 10. gate drive circuit; 11. shift register; 111. Nth stage shift register; 12. virtual register; 121. first virtual register; 122. second virtual register; 123. third virtual register; 13. first gate drive circuit; 10a. first type of gate drive circuit; 10b. second type of gate drive circuit; 10c. third type of gate drive circuit; S. shift register group;

[0025] 20. detection signal line; 21. first routing line; 211. first sub-section; 212. connection section; 22. second routing line;

[0026] 30. Electrode structure; 31. First connecting electrode; 32. Second connecting electrode; 33. First electrode group;

[0027] 40. Electrostatic shielding unit;

[0028] 50. substrate;

[0029] 60. pad structure; 61. first pad; 62. second pad;

[0030] 70. Circuit board structure;

[0031] P, pixel circuit; P1, pulse width modulation subcircuit; P2, amplitude modulation subcircuit; P3, circuit row; P4, circuit column; P5, Mth circuit row; F, light emitting element;

[0032] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0033] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0034] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0035] There are many types of display panels. Micro-luminescent display panels have received widespread attention due to their advantages such as higher brightness and wider color gamut. Micro-luminescent display panels use micro devices such as micro-light emitting diodes (Micro LED) or sub-millimeter light emitting diodes (Mini LED) as light-emitting elements to achieve light-emitting display functions. On this basis, how to improve the display reliability of micro-luminescent display panels has become one of the research directions of many manufacturers.

[0036] Regarding the above issues, please refer to Figure 1 As shown in Figure 3, an embodiment of the present application provides an array substrate 100, the array substrate 100 includes a gate drive circuit 10 and a detection signal line 20, the gate drive circuit 10 includes a shift register group S and a virtual register 12, the shift register group S includes N shift registers 11 arranged in cascade, the virtual register 12 is cascaded to the Nth stage shift register 111, and the detection signal line 20 is electrically connected to the output end of the virtual register 12.

[0037] The array substrate 100 is a key component for the subsequent formation of the display panel 200. The display panel 200 is a device for displaying images. In addition to the array substrate 100, the display panel 200 also includes a light-emitting element F. The light-emitting element F is a main component for realizing the light-emitting function. In the embodiment of the present application, the light-emitting element F may be a micro light-emitting element F such as a micron light-emitting diode (Micro Light Emitting Diode, Micro LED) or a sub-millimeter light-emitting diode (Mini Light Emitting Diode, MiniLED). Among them, the light-emitting element F can have a variety of structural forms. For example, the light-emitting element F can be a flip-chip, or a face-mounted chip, or a vertical chip. The embodiment of the present application does not limit this. Among them, in Figure 1 and Figure 2 The light emitting element F is not shown in FIG. 3 , but the light emitting element F and the circuit structure for driving and controlling the light emitting element F are shown in FIG. 3 .

[0038] The array substrate 100 includes a pixel circuit P, which is a circuit structure for driving and controlling the light-emitting element F to emit light. There are multiple pixel circuits P, and the multiple pixel circuits P respectively control different light-emitting elements F to realize the light-emitting function. The projections of the pixel circuits P and the corresponding light-emitting elements F in the thickness direction Z of the display panel 200 can be overlapped with each other, or can be relatively staggered, which is not limited in the embodiment of the present application.

[0039] The pixel circuit P includes a pulse width modulation subcircuit P1 and an amplitude modulation subcircuit P2, wherein the pulse width modulation subcircuit P1 is configured to control the pulse width of the driving current provided to the light emitting element F based on the pulse width modulation data voltage, and the amplitude modulation subcircuit P2 is configured to control the amplitude of the driving current provided to the light emitting element F based on the pulse amplitude modulation data voltage. The pulse width of the driving current can be understood as the duration of the driving current, and the amplitude of the driving current can be understood as the current value of the driving current.

[0040] Specifically, the light-emitting element F includes a first electrode, a second electrode and a light-emitting portion. Under the joint action of the first electrode and the second electrode, the light-emitting portion can realize the light-emitting display function. The pixel circuit P generates a driving current under the control of the amplitude modulation subcircuit P2 and the pulse width modulation subcircuit P1. The amplitude modulation subcircuit P2 can be used to control the amplitude of the driving current, and the pulse width modulation subcircuit P1 can be used to adjust the pulse width of the voltage applied to the second electrode of the light-emitting element F. The pulse width modulation subcircuit P1 adjusts the pulse width of the voltage applied to the second electrode of the light-emitting element F, that is, the pulse width modulation subcircuit P1 adjusts the actual emission period of the driving current applied to the light-emitting element F; at the same time, the driving current applied to the light-emitting element F can be maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting element F, rather than adjusting the grayscale or brightness displayed by the light-emitting element F by adjusting the magnitude of the driving current applied to the light-emitting element F. Therefore, the amplitude modulation subcircuit P2 can provide a driving current to the light emitting element F so that the light emitting element F is driven with the best luminous efficiency, and the light emission duty ratio (i.e., the emission period of the light emitting element F) of the light emitting element F is adjusted through the pulse width modulation subcircuit P1 to adjust the grayscale or brightness displayed by the light emitting element F. Among them, the output end of the pulse width modulation subcircuit P1 can be directly connected to the control end of a driving transistor in the amplitude modulation subcircuit P2 or indirectly controlled through a capacitor structure, that is, the electrical signal output by the output end of the pulse width modulation subcircuit P1 can be directly written to the control end of the driving transistor, or the control end of the driving transistor can be controlled by writing to the capacitor structure to achieve the adjustment of the driving current amplitude.

[0041] Furthermore, the specific circuit composition of the pulse width modulation subcircuit P1 and the amplitude modulation subcircuit P2 is not limited in the present embodiment. Figure 3a As shown, the pulse width modulation sub-circuit P1 includes a first driving transistor M3, a first gate reset transistor M5, a first data writing transistor M2, a first compensation transistor M4, a first control transistor M1, a second control transistor M6 and a storage capacitor Cst. The first control transistor M1 is connected between the first power supply voltage PWM-vdd and the first electrode of the first driving transistor M3, and the second control transistor M6 is connected between the second electrode of the first driving transistor M3 and the first node N1. The first data writing transistor M2 is connected to the first data signal PWM-data and the first electrode of the first driving transistor M3, the first compensation transistor M4 is connected to the second electrode and the control end of the first driving transistor M3, and the first gate reset transistor M5 is connected to the control end of the first driving transistor M3. The first plate of the storage capacitor Cst is connected to the control end of the first driving transistor M3, and the second plate of the storage capacitor Cst is connected to the sweep signal SWEEP. Among them, the control end of the first gate reset transistor M5 receives the first scan signal PWM-S1, and the control ends of the first data writing transistor M2 and the first compensation transistor M4 receive the second scan signal PWM-S2. The control terminals of the first control transistor M1 and the second control transistor M6 receive the first light emitting control signal PWM-EM.

[0042] The amplitude modulation subcircuit P2 includes a second driving transistor M9, a second gate reset transistor M11, a second data writing transistor M8, a second compensation transistor M10, a third control transistor M7, a fourth control transistor M12, and an electrode reset transistor M13. The third control transistor M7 is connected between the second power supply voltage PAM-vdd and the first electrode of the second driving transistor M9, and the fourth control transistor M12 is connected between the second electrode of the second driving transistor M9 and the light emitting element F. The second driving transistor M9 is configured to generate a driving current under the control of its control terminal voltage, that is, the voltage of the first node N1. The second data writing transistor M8 is connected to the second data signal PAM-data and the first electrode of the second driving transistor M9, the second compensation transistor M10 is connected to the second electrode and the control terminal of the second driving transistor M9, the second gate reset transistor M11 is connected to the control terminal of the second driving transistor M9, the electrode reset transistor M13 is connected to the second electrode of the light emitting element F, and the fourth control transistor M12 is also connected to the second electrode of the light emitting element F, and the first electrode of the light emitting element F is connected to the third power supply voltage PVEE. The control end of the second gate reset transistor M11 receives the third scan signal PAM-S1; the control ends of the second data write transistor M8, the second compensation transistor M10 and the electrode reset transistor M13 receive the fourth scan signal PAM-S2. The control ends of the third control transistor M7 and the fourth control transistor M12 receive the second light emission control signal PAM-EM.

[0043] Or Figure 3b As shown, the amplitude modulation subcircuit P2 and the pulse width modulation subcircuit P1 both include an initialization unit 111' / 121', a data writing unit 112 / 122', a threshold compensation unit 113 / 123', a light emitting control unit 114 / 124, storage capacitors C1, C2, C3, a compensation module 115, an electrode reset module 116, a voltage stabilization module 125, and a driving transistor PAM-DR / PWM-DR. The amplitude modulation subcircuit P2 includes an initialization unit 111', a data writing unit 112, a threshold compensation unit 113, a light emitting control unit 114, a storage capacitor C2, a voltage stabilization module 125, and a driving transistor PAM-DR; the pulse width modulation subcircuit P1 includes an initialization unit 121', a data writing unit 122', a threshold compensation unit 123', a light emitting control unit 124, storage capacitors C2 and C3, a compensation module 115, an electrode reset module 116, and a driving transistor PWM-DR. The storage capacitor C3 is located in the compensation module 115 , and the supplement module 115 also includes a plurality of transistor structures.

[0044] The initialization unit 111' / 121' is electrically connected between the initialization signal VREF and the first node N1 / N2. The initialization unit 111' / 121' is used to provide the initialization signal VREF to the first node N1 and the second node N2 during the initialization phase (the initialization signal provided by the initialization signal terminal of the amplitude modulation subcircuit P2 may be the same as or different from the initialization signal of the pulse width modulation subcircuit P1. Figure 3b The initialization signal VREF includes PAM-REF and PWM-REF respectively. The data writing unit 112 / 122' is electrically connected between the data signal PAM-DATA / PWM-DATA and the first electrode of the driving transistor PAM-DR / PWM-DR, and the control end of the driving transistor PAM-DR / PWM-DR and the first electrode plate of the storage capacitor C2 / C1 are electrically connected to the first node N1 and the second node N2; the data writing unit 112 / 122' is used to provide the data signal PAM-DATA / PWM-DATA to the first node N1 and the second node N2 through the driving transistor PAM-DR / PWM-DR during the data writing phase. The threshold compensation unit 113 / 123' is electrically connected to the second electrode of the driving transistor PAM-DR / PWM-DR, and the threshold compensation unit 113 / 123' is used to compensate the threshold voltage of the driving transistor PAM-DR / PWM-DR to the first node N1 and the second node N2. The electrode reset module 116 is electrically connected between the second reset signal PAM-INIT and the second electrode of the light emitting element F. The electrode reset module 116 is used to provide the second reset signal PAM-REF to the second electrode in the initialization stage to achieve the reset of the second electrode. The compensation module 115 is electrically connected to the second plate of the storage capacitor C2 to play a compensation role and reduce the problem of voltage drop in the pixel circuit P. The voltage stabilizing module 125 is electrically connected between the second plate of the storage capacitor C1 and the voltage stabilizing signal SWEEP-GND. The voltage stabilizing module 125 is used to stabilize the potential of the second node N2 when the sweep signal SWEEP is not working.

[0045] In addition to the pixel circuit P, the array substrate 100 also includes a gate drive circuit 10 and a detection signal line 20. The gate drive circuit 10 is a circuit structure for providing a corresponding gate control signal to the control end of the transistor in the pixel circuit P. According to different actual needs, the array substrate 100 may have multiple types of gate drive circuits 10. For example, multiple gate drive circuits 10 may be used to transmit multiple of the first scanning signal PWM-S1, the second scanning signal PWM-S2, the third scanning signal PAM-S1, the fourth scanning signal PAM-S2, the first light-emitting control signal PWM-EM, the second light-emitting control signal PAM-EM, and the sweep signal line SWEEP. According to different actual needs, at least one of the first light-emitting control signal PWM-EM, the second light-emitting control signal PAM-EM, and the sweep signal SWEEP may also be directly driven by directly connecting the driver chip to a specific signal routing. At this time, the multiple gate drive circuits 10 may not include a gate drive circuit 10 for transmitting at least one of the first light-emitting control signal PWM-EM, the second light-emitting control signal PAM-EM, and the sweep signal SWEEP.

[0046] The gate drive circuit 10 includes a shift register group S and a virtual register 12. The shift register group S is a circuit structure composed of N shift registers 11 cascaded. The shift register 11 is a sequential logic circuit, which is mainly used to store and transmit specific signals. The specific number of N is not limited in the embodiment of the present application, and N is a positive integer greater than 1. Among them, the first-stage shift register 11 is the first-row shift register 11, and the N-th-stage shift register 111 is the last-row shift register 11.

[0047] The output end of the shift register 11 is electrically connected to the control end of the transistor in the pixel circuit P through a specific signal line. A plurality of pixel circuits P arranged in a specific direction can together form a circuit row P3. Depending on actual needs, the output end of a single shift register 11 can be electrically connected only to the control ends of a plurality of transistors in a single circuit row P3, or the output end of a single shift register 11 can also be electrically connected to the control ends of a plurality of transistors in different circuit rows P3 at the same time. The embodiments of the present application do not impose any restrictions on this.

[0048] The specific positional relationship of the shift register 11 relative to the pixel circuit P is not limited in the embodiment of the present application. For example, the shift register 11 can be set at the position corresponding to the left and right borders of the display panel 200, or considering that the array substrate 100 provided in the embodiment of the present application is used to form a display panel 200 with micron light emitting diodes or sub-millimeter light emitting diodes as light-emitting elements, the shift register 11 can be set between adjacent pixel circuits P, so as to facilitate the realization of a nearly borderless display effect. On this basis, the shift register 11 can be set between adjacent circuit rows P3, or can also be set between adjacent circuit columns P4.

[0049] Similar to the shift register 11, the virtual register 12 is also a register structure and is used to store and transmit specific signals. The difference is that the output end of the shift register 11 is electrically connected to the control end of the transistor in the pixel circuit P through a specific signal line, while the output end of the virtual register 12 is not electrically connected to the control end of the transistor. In other words, the shift register 11 can provide a specific control signal to meet the operating needs of the pixel circuit P, while the virtual register 12 is not used to meet the operating needs of the pixel circuit P.

[0050] It should be noted that for a single gate drive circuit 10, there will be a shift register 11 and a virtual register 12 at the same time. On this basis, the shift register 11 and the virtual register 12 in the single gate drive circuit 10 can adopt the same circuit structure, or different circuit structures. For different gate drive circuits 10, the circuit structures corresponding to different shift registers 11 in different gate drive circuits 10 can remain the same, or they can be different. Similarly, the circuit structures corresponding to different virtual registers 12 in different gate drive circuits 10 can remain the same, or they can be different.

[0051] The detection signal line 20 is a signal routing line for realizing the detection function of the gate drive circuit 10. Specifically, during the preparation process of the array substrate 100, a motherboard structure is first formed. The motherboard structure includes a plurality of array areas arranged at intervals. Each array area includes a gate drive circuit 10 and a detection signal line 20. The detection signal line 20 is electrically connected to the gate drive circuit 10 located in the array area and the detection circuit located outside the array area, respectively. Then, the gate drive circuit 10 is detected by the detection circuit, and after the detection is completed, the plurality of array areas are removed to form a plurality of array substrates 100. In this way, in the array substrate 100 prepared, there will only be the gate drive circuit 10 and the detection signal line 20, and no detection circuit will be retained, thereby reducing the space occupied by the detection circuit and facilitating a lightweight design.

[0052] In the related art, the detection signal line 20 is connected to the output end of the last row shift register 11 of the gate drive circuit 10. Since the detection signal line 20 itself has a certain resistance, the existence of the detection signal line 20 will increase the load difference between the last row shift register 11 and other row shift registers 11, making the last row shift register 11, which easily leads to display differences between the last row or several rows of light-emitting elements corresponding to the last row shift register 11 and other rows of light-emitting elements, that is, it is easy to cause the problem of uneven display.

[0053] In view of this, the embodiment of the present application adds a virtual register 12, and cascades the virtual register 12 to the Nth shift register 11, that is, the virtual register 12 is cascaded to the last row shift register 11. On this basis, the detection signal line 20 is not electrically connected to the output end of the last row shift register 11, but is electrically connected to the output end of the virtual register 12. In this way, the last row shift register 11 can be isolated from the detection signal line 20 with the help of the virtual register 12, thereby reducing the load influence of the detection signal line 20 on the last row shift register 11 at the output end, reducing the load difference at the output end of the last row shift register 11 relative to other rows of shift registers 11, thereby reducing the display difference of the last row or rows of light-emitting elements relative to other rows of light-emitting elements, and improving the display uniformity of the display panel 200.

[0054] It should be noted that, according to different actual needs, the array substrate 100 may include a virtual pixel circuit, or may not include a virtual pixel circuit. The virtual pixel circuit has the same circuit structure as the pixel circuit P, but the difference is that the pixel circuit P can be electrically connected to the light-emitting element to meet the light-emitting display needs of the light-emitting element, while the virtual pixel circuit is not electrically connected to the light-emitting element, that is, the virtual pixel circuit is not used to meet the light-emitting display needs of the light-emitting element. Further, when the array substrate 100 includes a virtual pixel circuit, the output end of the virtual register 12 can be electrically connected to the virtual pixel circuit.

[0055] On this basis, considering that the array substrate 100 provided in the embodiment of the present application is used to form a display panel 200 using micrometer light emitting diodes or sub-millimeter light emitting diodes as light emitting elements, and this type of display panel 200 can be designed as a borderless display panel 200, that is, the display panel 200 does not include a border area for setting a virtual pixel circuit. In view of this, in some optional embodiments, only the virtual register 12 exists in the array substrate 100, and no virtual pixel circuit exists.

[0056] In addition, for multiple gate driving circuits 10, virtual registers 12 may be provided in all gate driving circuits 10, or virtual registers 12 may be provided in only some gate driving circuits 10, and the embodiments of the present application do not limit this.

[0057] In some embodiments, Figure 1 and Figure 2 As shown, the array substrate 100 further includes M circuit rows P3, the array substrate 100 includes a plurality of pixel circuits P, the circuit row P3 includes a plurality of pixel circuits P arranged along a first direction X, and the M circuit rows P3 are arranged in a second direction Y, the first direction X and the second direction Y are both parallel to the plane where the substrate 50 is located, and intersect each other. Among them, the Nth stage shift register 111 provides a gate control signal to the Mth circuit row P5. Among them, Figure 1 FIG. 4 shows a pixel circuit P in the Mth circuit row P5.

[0058] The first direction X is the row direction, and the second direction Y is the column direction. A plurality of pixel circuits P arranged in the first direction X can collectively form a circuit row P3, and similarly, a plurality of pixel circuits P arranged in the second direction Y can collectively form a circuit column P4. Taking the square structure of the array substrate 100 as an example, the row direction mentioned here is not limited to the width direction of the array substrate 100, and the column direction is not limited to the length direction of the array substrate 100. The first direction X and the second direction Y only represent two different arrangement directions corresponding to the plurality of pixel circuits P. The first direction X and the second direction Y are both parallel to the plane where the substrate 50 is located, that is, the first direction X and the second direction Y intersect the thickness direction Z of the array substrate 100. Optionally, the first direction X, the second direction Y, and the thickness direction Z of the array substrate 100 are arranged perpendicular to each other.

[0059] The array substrate 100 includes a total of M circuit rows P3, and the shift register group S includes a total of N shift registers 11 arranged in cascade. The embodiment of the present application does not limit the relationship between M and N. Exemplarily, M can be greater than N, that is, a row of shift registers 11 can drive multiple circuit rows P3 settings to achieve a one-drive-many driving mode. Or M can be equal to N, that is, a row of shift registers 11 only drives one circuit row P3 setting to achieve a one-drive-one driving mode.

[0060] In the embodiment of the present application, the N-th shift register 111 provides a gate control signal to the M-th circuit row P5, that is, the last shift register 11 transmits the corresponding gate control signal to the last circuit row P5. Further, each circuit row P3 can receive the gate control signal transmitted from the shift register 11, and does not need to receive the signal output from the virtual register 12, thereby reducing the impact of the output signal of the virtual register 12 on the display effect, which helps to improve the display uniformity.

[0061] In some embodiments, see Figure 2 and Figure 4, in the second direction Y, the shift register 11 is located between adjacent circuit rows P3; or, the array substrate 100 includes a plurality of circuit columns P4, the circuit column P4 includes a plurality of pixel circuits P arranged along the second direction Y, and in the first direction X, the shift register 11 is located between adjacent circuit columns P4.

[0062] Taking the shift register 11 located between adjacent circuit rows P3 as an example, depending on actual needs, only one shift register 11 may be provided between adjacent circuit rows P3, or multiple shift registers 11 may also be provided, wherein the "multiple shift registers 11" mentioned here may refer to the shift register 11 located in the same gate drive circuit 10, or may refer to the shift register 11 located in different gate drive circuits 10. Furthermore, for the shift register 11 in the same gate drive circuit 10 and located between different circuit rows P3, there may be only one circuit row P3 between adjacent shift registers 11, or there may be multiple circuit rows P3 at the same time, and the embodiment of the present application does not impose any restrictions on this, and the case where the shift register 11 is located in the adjacent circuit column P4 is the same. Among them, Figure 2 FIG. 4 shows a case where only one shift register 11 in a single gate drive circuit 10 is arranged between adjacent circuit rows P3. Figure 4 The case where each shift register in a single gate driving circuit 10 is arranged between adjacent circuit columns P4 is shown.

[0063] In the embodiment of the present application, the shift register 11 is not located on the same side of all pixel circuits P, but is located between some adjacent pixel circuits P. Among them, the area where the pixel circuit P is located usually corresponds to the light-emitting area of ​​the display panel 200. It can be seen that the shift register 11 in the embodiment of the present application is integrated in the light-emitting area of ​​the display panel 200. This design helps to achieve a borderless display effect and improve the viewing experience. On this basis, the shift register 11 can be selected to be set between adjacent circuit rows P3, or the shift register 11 can be set between adjacent circuit columns P4, so as to meet the actual layout requirements of different display panels 200, with strong practicality and flexibility.

[0064] The specific positional relationship of the virtual register 12 relative to the pixel circuit P is not limited in the embodiment of the present application. The virtual register 12 can be located on the same side of all the pixel circuits P, or can be located between some adjacent circuit rows P3, or can be located between adjacent circuit columns P4, as long as the virtual register 12 can be cascaded to the last row shift register 11, and the output end of the virtual register 12 does not transmit the gate control signal to any circuit row P3.

[0065] In some embodiments, Figure 1 and Figure 2As shown, in the second direction Y, the shift register 11 is located between adjacent circuit rows P3 , and the Mth circuit row P5 is located between the Nth stage shift register 111 and the dummy register 12 .

[0066] Combined with the above content, it can be known that the array substrate 100 has a total of M circuit rows P3, and the Mth circuit row P5 is the last circuit row P5; and the shift register group S includes N shift registers 11 arranged in cascade, and the Nth stage shift register 111 is the last row shift register 11.

[0067] On this basis, the Mth circuit row P5 is located between the Nth shift register 111 and the virtual register 12, which means that the last circuit row P5 is located between the last shift register 11 and the virtual register 12, the last shift register 11 is located between adjacent circuit rows P3, and the virtual register 12 is located on the same side of all circuit rows P3. Among them, the last shift register 11 can be located between the last circuit row P5 and the second to last circuit row P3, or can also be located between other two adjacent circuit rows P3 except the last circuit row P5. The embodiment of the present application does not limit this, as long as the last circuit row P5 is located between the last shift register 11 and the virtual register 12, and the last shift register 11 is located between adjacent circuit rows P3, Figure 1 FIG. 4 shows a case where the shift register 11 is located between the last circuit row P5 and the second to last circuit row P3.

[0068] In the embodiment of the present application, since the virtual register 12 is located on the same side of all the circuit rows P3, the detection signal line 20 electrically connected to the output end of the virtual register 12 is also located on the same side of all the circuit rows P3. In this case, the detection signal line 20 will not overlap with the pixel circuit P in the thickness direction Z of the array substrate 100, thereby helping to reduce the risk of parasitic capacitance generated between the detection signal line 20 and part of the conductor structure in the pixel circuit P, thereby improving the operating reliability of the pixel circuit P.

[0069] In some embodiments, see Figure 1 , Figure 2 as well as Figure 5 The array substrate 100 also includes a plurality of electrode structures 30, the electrode structure 30 includes a first connecting electrode 31 and a second connecting electrode 32 which are insulated, the second connecting electrode 32 is connected to the pixel circuit P, the plurality of electrode structures 30 include a first electrode group 33 connected to the Mth circuit row P5, and in the second direction Y, the virtual register 12 is located between the first electrode group 33 and the Mth circuit row P5.

[0070] The light-emitting element includes a first electrode, a second electrode and a light-emitting portion. Under the joint action of the first electrode and the second electrode, the light-emitting portion can realize the light-emitting display function. The electrode structure 30 is a structure in the array substrate 100 for connecting and fixing with two electrodes in the light-emitting element, wherein the first connection electrode 31 is a structure in the electrode structure 30 for bonding and connecting with the first electrode, and the second connection electrode 32 is a structure in the electrode structure 30 for bonding and connecting with the second electrode.

[0071] In order to meet the control requirements of the light-emitting element, the second connection electrode 32 needs to be connected to the pixel circuit P, and the first connection electrode 31 needs to transmit the second power signal PVEE, and the first connection electrode 31 and the second connection electrode 32 in the same electrode structure 30 are insulated from each other. Among them, for different electrode structures 30, each electrode structure 30 includes a first connection electrode 31 and a second connection electrode 32, and different electrode structures 30 are respectively arranged corresponding to different light-emitting elements, that is, in the thickness direction Z of the array substrate 100, the projection of the light-emitting element overlaps with the projection of the corresponding electrode structure 30.

[0072] It should be noted that, in order to meet the independent control requirements of different light-emitting elements, the second connection electrodes 32 in different electrode structures 30 need to be arranged in an insulated manner, and the first connection electrodes 31 in different electrode structures 30 can be connected as a whole, or can also be arranged in an insulated manner. Optionally, at least some of the first connection electrodes 31 in different electrode structures 30 are connected as a whole.

[0073] The first electrode group 33 is a single electrode row composed of a plurality of electrode structures 30 arranged along the first direction X, and the second connection electrodes 32 in the plurality of electrode structures 30 in the first electrode group 33 can be electrically connected to the plurality of pixel circuits P in the last circuit row P5, respectively, to achieve the control needs of the plurality of light-emitting elements corresponding to the last circuit row P5. Normally, the last circuit row P5 usually corresponds to the control of the last light-emitting elements. Therefore, the first electrode group 33 is the last electrode structure 30, and the plurality of light-emitting elements corresponding to the first electrode group 33 are the last light-emitting elements. Among them, Figure 1 , three electrode structures 30 are shown to be adjacent to each other in the first electrode group 33, but this does not mean that the first electrode group 33 only includes three electrode structures 30. Further, Figure 1 The light emitting elements corresponding to the three electrode structures 30 may together form a repeating unit, and a plurality of repeating units are repeatedly arranged along the first direction X and the second direction Y.

[0074] In the embodiment of the present application, the projections of the first electrode group 33 and the last circuit row P5 in the thickness direction Z of the array substrate 100 are not overlapped and arranged correspondingly, but the first electrode group 33 is located on the side of the last circuit row P5 away from other circuit rows P3 along the second direction Y. On this basis, considering that the projections of the first electrode group 33 and the corresponding last row of light-emitting elements on the array substrate 100 are usually overlapped, the projections of the last row of light-emitting elements and the last row of circuit row P5 in the thickness direction Z of the array substrate 100 are also not overlapped.

[0075] In view of this, the virtual register 12 is located between the first electrode group 33 and the Mth circuit row P5 along the second direction Y, which means that the virtual register 12 will be located between the last row of light-emitting elements and the last row of circuit row P5, and the last row of circuit row P5 is located on the side of the last row of light-emitting elements facing other light-emitting elements. Therefore, the virtual register 12 will be located between adjacent rows of light-emitting elements, rather than on the same side of all light-emitting elements. In other words, the virtual register 12 will be integrated in the light-emitting area of ​​the display panel 200, rather than in the border area, which helps to eliminate the border area of ​​the display panel 200 and achieve a borderless effect.

[0076] It should be noted that the embodiment of the present application does not limit the positional relationship between different rows of light-emitting elements relative to the virtual register 12. For example, the side of the virtual register 12 away from the last row of circuit row P5 may be provided with only the last row of light-emitting elements, or may be provided with the second-to-last row of light-emitting elements or even more rows of light-emitting elements. Similarly, the area between the virtual register 12 and the last row of circuit row P5 may be provided with light-emitting elements, or may not be provided with light-emitting elements. And the projection of the virtual register 12 in the thickness direction Z of the array substrate 100 may overlap with the projection of the electrode structure 30 and the corresponding light-emitting element, or may not overlap with the light-emitting element.

[0077] The embodiment of the present application also does not limit the positional relationship between the last row of light emitting elements and the detection signal line 20 . The orthographic projection of the last row of light emitting elements on the array substrate 100 may overlap with the detection signal line 20 , or may not overlap with the detection signal line 20 .

[0078] In addition, although the last row of circuit row P5 is not arranged corresponding to the position of the last row of light-emitting elements, for other rows of circuit row P3 and corresponding other rows of light-emitting elements, the positions between the two can be arranged correspondingly and overlapped, or of course, they can be arranged non-overlapped, and the embodiment of the present application does not limit this. Optionally, the distances between adjacent rows of light-emitting elements in the second direction Y remain the same or similar, the distances between adjacent circuit rows P3 in the second direction Y remain the same or similar, and the distances between adjacent rows of light-emitting elements are greater than the distances between adjacent circuit rows P3, thereby helping to improve the display uniformity of the display panel 200. At the same time, the light-emitting area of ​​the display panel 200 can cover and exceed the area where all pixel circuits P are located, so that outside the area where the pixel circuits P are located and at a part of the position within the light-emitting area, it can be used to arrange device structures or signal routings such as virtual registers 12, thereby canceling or reducing the border area of ​​the display panel 200 and achieving a borderless display effect.

[0079] In summary, the embodiment of the present application adjusts the position of the first electrode group 33 corresponding to the last circuit row P5, so that it is not arranged to overlap with the projection of the last circuit row P5, but is located on one side of the last circuit row P5 along the second direction Y, and the virtual register 12 is located between the first electrode group 33 and the last circuit row P5. Since the position of the first electrode group 33 usually corresponds to the position of the last row of light-emitting elements, under this design, the virtual register 12 can be located on the side of the last row of light-emitting elements facing the light-emitting elements of other rows, that is, the virtual register 12 can be located in the light-emitting area of ​​the display panel 200, thereby eliminating or reducing the border area of ​​the display panel 200, achieving a borderless display effect, and improving the viewing experience of the display panel 200.

[0080] In some embodiments, N=M, that is, the number of cascaded shift registers 11 in the shift register group S is equal to the number of circuit rows P3 in the array substrate 100. On this basis, each level of shift register 11 can transmit a gate control signal to the corresponding single circuit row P3 to achieve a one-drive-one driving mode.

[0081] In the embodiment of the present application, considering that the array substrate 100 can be used to form a borderless display panel 200, and the borderless setting means that the virtual circuit row P3 including the virtual pixel circuit P cannot be set, therefore, by setting the shift register 11 and the circuit row P3 in a one-to-one form, it is possible to keep the number of circuit rows P3 driven by the last row shift register 11 consistent with the number of circuit rows P3 driven by other row shift registers 11 without adding additional virtual circuit rows P3, which helps to reduce the display difference between the last row light-emitting elements and the other rows of light-emitting elements and improve display uniformity.

[0082] In some embodiments, N<M.

[0083] In an embodiment of the present application, the number of cascaded shift registers 11 in the shift register group S may also be smaller than the number of circuit rows P3 in the array substrate 100, thereby realizing a one-drive-many driving mode, which helps to reduce the overall number of shift registers 11 in the array substrate 100 and reduce the difficulty of layout between signal routing and device structures within the array substrate 100.

[0084] In some embodiments, the circuit structures of the virtual registers 12 in at least some of the different gate driving circuits 10 are different; and / or, the circuit structures of the virtual registers 12 in at least some of the gate driving circuits 10 remain consistent.

[0085] The “circuit structure remains consistent” mentioned here means that the number and type of device structures, such as transistors and capacitors, included in different virtual registers 12, and the connection method between the devices can remain the same, regardless of the size and shape corresponding to the different virtual registers 12. In other words, the sizes of different virtual registers 12 in the first direction X or the second direction Y can be the same, or they can be different. Similarly, the “circuit structure is different” mentioned here means that at least one of the number and type of device structures, such as transistors and capacitors, included in different virtual registers 12, and the connection method between the devices is different, regardless of the size and shape corresponding to the different virtual registers 12.

[0086] According to different actual needs, the circuit structures of the virtual registers 12 in different gate drive circuits 10 may be different, or they may all remain the same. Alternatively, the circuit structures of the virtual registers 12 in some different gate drive circuits 10 may remain the same, and the circuit structures of the virtual registers 12 in some different gate drive circuits 10 may be different.

[0087] In combination with the foregoing content, it can be seen that, unlike the shift register 11, the output end of the virtual register 12 will not be electrically connected to the control end of the transistor in the pixel circuit P, that is, the shift register 11 is used to drive the pixel circuit P, while the virtual register 12 is not used to drive the pixel circuit P, that is, the virtual register 12 does not play the same role of outputting the gate control signal as the shift register 11, so the circuit structure of the virtual register 12 can be flexibly adjusted or changed according to actual needs.

[0088] On this basis, in the embodiment of the present application, the circuit structure of the virtual register 12 in at least some of the different gate drive circuits 10 can be set differently, or the circuit structure of the virtual register 12 in at least some of the gate drive circuits 10 can be set to be consistent, so as to meet the layout requirements of different situations, with strong flexibility and practicality.

[0089] In some embodiments, in a single gate driving circuit 10 , the circuit structure in the virtual register 12 is consistent with the circuit structure in the shift register 11 .

[0090] In the embodiment of the present application, by setting the circuit structure of the virtual register 12 in a single gate drive circuit 10 to be consistent with that of the shift register 11, it is helpful to reduce the design difficulty of the virtual register 12, and at the same time, the structural load of the virtual register 12 in the single gate drive circuit 10 can be the same as the structural load of the shift register 11. The "structural load of the virtual register 12" mentioned here refers to: the load value corresponding to the structure of the virtual register 12 itself, rather than the load value corresponding to other structures connected to the output end of the virtual register 12, and the structural load of the shift register 11 is the same.

[0091] On this basis, since in a single gate drive circuit 10, the output end of the last row shift register 11 will be electrically connected to the virtual register 12, and the output ends of the other row shift registers 11 will be electrically connected to the shift register 11, this design helps to reduce the load difference at the output end of the last row shift register 11 relative to the other row shift registers 11, thereby reducing the display difference of the last row or several rows of light-emitting elements relative to the other rows of light-emitting elements, and improving the display uniformity of the display panel 200.

[0092] It should be noted that, for different gate drive circuits 10, the circuit structures of the shift registers 11 included therein may remain consistent, or there may be differences. On this basis, whether the circuit structures of the corresponding virtual registers 12 in different gate drive circuits 10 are the same or not depends on whether the circuit structures of the shift registers 11 in the different gate drive circuits 10 are the same, and the embodiments of the present application do not limit this.

[0093] In addition, in a single gate drive circuit 10, although the virtual register 12 has the same circuit structure as the shift register 11, the sizes of the corresponding occupied spaces of the two may be the same or different. For example, the size of the virtual register 12 in the first direction X may be greater than, less than, or equal to the size of the shift register 11 in the first direction X, and the size of the virtual register 12 in the second direction Y may also be greater than, less than, or equal to the size of the shift register 11 in the second direction Y.

[0094] In some embodiments, Figure 1 and Figure 2 As shown, in a single gate drive circuit 10, the virtual register 12 has the same size as the shift register 11 in the first direction X; and / or, in a single gate drive circuit 10, the virtual register 12 has the same size as the shift register 11 in the second direction Y.

[0095] In the embodiment of the present application, in addition to having the same circuit structure, the virtual register 12 and the shift register 11 in a single gate drive circuit 10 may also have the same size in at least one of the first direction X and the second direction Y. This helps to further improve the consistency of the virtual register 12 and the shift register 11 in the single gate drive circuit 10 and reduce the design difficulty of the virtual register 12.

[0096] Further optionally, in a single gate drive circuit 10, the positional relationship of the virtual register 12 relative to the last row of shift registers 11 is the same as the positional relationship of the last row of shift registers 11 relative to the second-to-last row of shift registers 11, so that the multiple shift registers 11 and the virtual registers 12 in a single gate drive circuit 10 can be arranged in a consistent and unified manner, thereby helping to reduce the difficulty of layout of device structures and signal routing inside the array substrate 100.

[0097] In some embodiments, the plurality of gate driving circuits 10 include a first type of gate driving circuit 10 a and a second type of gate driving circuit 10 b, wherein the first type of gate driving circuit 10 a is used to control the writing of data signals into the pixel circuit P, and the second type of gate driving circuit 10 b is used to control the writing of reset signals into the pixel circuit P. At least one of the first type of gate driving circuit 10 a and the second type of gate driving circuit 10 b includes a virtual register 12 .

[0098] The first type of gate driving circuit 10a is a circuit structure for controlling data signals to be written into the pixel circuit P, while the second type of gate driving circuit 10b is a circuit structure for controlling reset signals to be written into the pixel circuit P. The data signal includes a first data signal PWM-data and a second data signal PAM-data, and the reset signal includes a first reset signal PWM-REF and a second reset signal PAM-REF.

[0099] On this basis, combined with Figure 3a For example, the first type of gate driving circuit 10a may include two types of gate driving circuits 10, one of which is used to transmit the second scanning signal PWM-S2 to the control end of the first data writing transistor M2, and the other is used to output the fourth scanning signal PAM-S2 to the control end of the second data writing transistor M8. Similarly, the second type of gate driving circuit 10b may include two types of gate driving circuits 10, one of which is used to transmit the first scanning signal PWM-S1 to the control end of the first gate reset transistor M5, and the other is used to output the third scanning signal PAM-S3 to the control end of the second gate reset transistor M11.

[0100] In the embodiment of the present application, considering that the array substrate 100 includes multiple types of gate driving circuits 10, and the virtual register 12 can be set only in a specific type of gate driving circuit 10, or can also be set in all gate driving circuits 10, it can be flexibly adjusted according to the actual layout requirements, and has strong practicality and flexibility.

[0101] For example, the first type of gate driving circuit 10a is used to control the writing of data signals into the pixel circuit P. The first type of gate driving circuit 10a is the gate driving circuit 10 that has the greatest impact on brightness. Therefore, a virtual register 12 may be provided only in the first type of gate driving circuit 10a to improve the luminous brightness and luminous accuracy of the display panel 200. At the same time, the virtual register 12 may not be provided in the second type of gate driving circuit 10b. In this way, other signal routing lines or device structures may be provided in the area below the second type of gate driving circuit 10b to reduce the layout pressure of the array substrate 100.

[0102] Of course, in other embodiments, the virtual register 12 may be provided only in the second type of gate driving circuit 10b, while the virtual register 12 is not provided in the first type of gate driving circuit 10a, or the virtual register 12 may be provided in both the first type of gate driving circuit 10a and the second type of gate driving circuit 10b.

[0103] In some embodiments, the pixel circuit P includes an amplitude modulation subcircuit P2 and a pulse width modulation subcircuit P1, the first type of gate driving circuit 10a includes a first gate driving circuit and a second gate driving circuit, and the second type of gate driving circuit 10b includes a third gate driving circuit and a fourth gate driving circuit. The first gate driving circuit is used to control the first data signal PWM-data to be written into the pulse width modulation subcircuit P1, the second gate driving circuit is used to control the second data signal PAM-data to be written into the amplitude modulation subcircuit P2, the third gate driving circuit is used to control the first reset signal PWM-REF to be written into the pulse width modulation subcircuit P1, and the fourth gate driving circuit is used to control the second reset signal PAM-REF to be written into the amplitude modulation subcircuit P2.

[0104] Combination Figure 3a For example, the output end of the first gate driving circuit can transmit the second scanning signal PWM-S2 to the control end of the first data writing transistor M2 through the signal wiring, so that the first data writing transistor M2 is in an on state, thereby controlling the first data signal PWM-data to be written into the pulse width modulation sub-circuit P1. The output end of the second gate driving circuit can transmit the fourth scanning signal PAM-S2 to the control end of the second data writing transistor M8 through the signal wiring, so that the second data writing transistor M8 is in an on state, thereby controlling the second data signal PAM-data to be written into the amplitude modulation sub-circuit P2.

[0105] The output end of the third gate driving circuit can transmit the first scanning signal PWM-S1 to the control end of the first gate reset transistor M5 through the signal wiring, so that the first gate reset transistor M5 is in the on state, thereby controlling the first reset signal PWM-REF to be written into the pulse width modulation sub-circuit P1. The output end of the fourth gate driving circuit can transmit the third scanning signal PAM-S1 to the control end of the second gate reset transistor M11 through the signal wiring, so that the second gate reset transistor M11 is in the on state, thereby controlling the second reset signal PAM-REF to be written into the amplitude modulation sub-circuit P2.

[0106] Furthermore, in an embodiment of the present application, a virtual register 12 can be selectively provided in one or more of the first gate drive circuit, the second gate drive circuit, the third gate drive circuit, and the fourth gate drive circuit, so as to improve the reliability of the output signal of the last row shift register 11 in the corresponding gate drive circuit 10, which has strong practicality and flexibility.

[0107] In some embodiments, see Figure 5 and Figure 6 The first type of gate driving circuit 10a includes a first virtual register 121, and the second type of gate driving circuit 10b includes a second virtual register 122. The circuit structures of the first virtual register 121 and the second virtual register 122 are consistent.

[0108] The scanning signals in the pixel circuit P include a first scanning signal PWM-S1, a second scanning signal PWM-S2, a third scanning signal PAM-S1 and a fourth scanning signal PAM-S2. For these four types of scanning signals, the circuit structure of the shift register 11 in the corresponding gate driving circuit 10 can remain consistent. In other words, the first gate driving circuit, the second gate driving circuit, the third gate driving circuit and the fourth gate driving circuit all include a shift register 11 with the same circuit structure.

[0109] Next, the embodiment of the present application will introduce the structure of the shift register 11 in the first gate drive circuit in conjunction with the accompanying drawings, and the shift register 11 in the second gate drive circuit, the third gate drive circuit and the fourth gate drive circuit can adopt the same structure, which will not be repeated in the embodiment of the present application.

[0110] like Figure 6As shown, the shift register 11 includes a first output module K1, a second output module K2, a first control module K3 and a second control module K4. The first output module K1 is connected between the second clock terminal XCKS and the shift output terminal GOUT, and the control terminal of the first output module K1 is connected to the third node N3, and the potential of the third node N3 controls the on-off state of the first output module K1. Among them, the first output module K1 includes a transistor T8 and a capacitor C4, the control terminal of the transistor T8 is connected to the third node N3, the first electrode and the second electrode are respectively connected to the second clock terminal XCKS and the shift output terminal GOUT, and the two plates of the capacitor C4 are respectively connected to the second clock terminal XCKS and the shift output terminal GOUT.

[0111] The second output module K2 is connected between the first power supply terminal VGH and the shift output terminal GOUT, the control terminal of the second output module K2 is connected to the fourth node N4, and the potential of the fourth node N4 controls the on-off state of the second output module K2. The second output module K1 includes a transistor T7 and a capacitor C5, the control terminal of the transistor T7 is connected to the fourth node N4, the first electrode and the second electrode are respectively connected to the first power supply terminal VGH and the shift output terminal GOUT, and the two plates of the capacitor C5 are respectively connected to the first power supply terminal VGH and the shift output terminal GOUT.

[0112] The first control module K3 is connected to the third node N3, and is used to control the on-off state of the first output module K1. The first control module K3 includes a transistor T1, a transistor T4, a transistor T5, and a transistor T6. The control end of the transistor T1 is connected to the first clock end CKS, and the first pole and the second pole are respectively connected to the input end STVS and the fifth node N5. The control end of the transistor T4 is connected to the second clock end XCKS, and the first pole and the second pole are respectively connected to the fifth node N5 and the transistor T5. The control end of the transistor T5 is connected to the fourth node N4, and the first pole and the second pole are respectively connected to the transistor T4 and the first power supply end VGH. The control end of the transistor T6 is connected to the second power supply end VGL, and the first pole and the second pole are respectively connected to the fifth node N5 and the third node N3. The first power supply end VGH is a low voltage end, the second power supply end VGL is a high voltage end, and the input end STVS is connected to the output end GOUT of the previous shift register 11.

[0113] The second control module K4 is connected to the fourth node N4 and is used to control the on / off state of the second output module K2. The second control module K4 includes a transistor T2 and a transistor T3, the control end of the transistor T2 is connected to the fifth node N5, and the first electrode and the second electrode are respectively connected to the first clock end CKS and the fourth node N4. The control end of the transistor T3 is connected to the first clock end CKS, and the first electrode and the second electrode are respectively connected to the second power supply end VGL and the fourth node N4.

[0114] It should be noted that the above content is only a structural form of the shift register 11 in the first gate drive circuit, and it does not constitute a limitation on the circuit structure of the shift register 11. According to different actual needs, the shift register 11 can also adopt other circuit structures. For example, in other embodiments, the shift register 11 also includes a first output module K1, a second output module K2, a first control module K3 and a second control module K4, but the first output module K1 is no longer connected to the second clock terminal XCKS, but is connected to the second power supply terminal VGL. Of course, the corresponding circuit structures of the first control module K3 and the second control module K4 also need to be adjusted at this time, and the embodiments of the present application do not limit this.

[0115] On this basis, considering that in a single gate drive circuit 10, the circuit structures of the shift register 11 and the virtual register 12 can be set to be consistent, when the first type of gate drive circuit 10a includes a first virtual register 121, the first virtual register 121 can be consistent with the circuit structure of the shift register 11 in the first type of gate drive circuit 10a. When the second type of gate drive circuit 10b includes a second virtual register 122, the second virtual register 122 can be consistent with the circuit structure of the shift register 11 in the second type of gate drive circuit 10b.

[0116] Furthermore, since the circuit structure of the shift register 11 in the first type of gate drive circuit 10a can be consistent with that of the shift register 11 in the second type of gate drive circuit 10b, the circuit structure of the first virtual register 121 and the second virtual register 122 can also be set to be consistent, which helps to further reduce the design difficulty of the virtual register 12 and improve the layout reliability of the internal structure of the array substrate 100.

[0117] It should be noted that, for the first type of gate drive circuit 10a, the first virtual register 121 may be provided only in the first gate drive circuit, or the first virtual register 121 may be provided only in the second gate drive circuit, or the first virtual register 121 may be provided in both the first gate drive circuit and the second gate drive circuit. Similarly, for the second type of gate drive circuit 10b, the second virtual register 122 may be provided only in the third gate drive circuit, or the second virtual register 122 may be provided only in the fourth gate drive circuit, or the second virtual register 122 may be provided in both the third gate drive circuit and the fourth gate drive circuit.

[0118] In some embodiments, see Figures 5 to 7The plurality of gate drive circuits 10 further include a third type of gate drive circuit 10c, the third type of gate drive circuit 10c is used to output a light emitting control signal or a sweep signal SWEEP, the first type of gate drive circuit 10a includes a first virtual register 121, and the third type of gate drive circuit 10c includes a third virtual register 123. The circuit structures of the first virtual register 121 and the third virtual register 123 are different.

[0119] Combination Figure 3a For example, the light-emitting signal includes a first light-emitting control signal PWM-EM and a second light-emitting control signal PAM-EM, and the third type of gate driving circuit 10c may include at least one of a fifth gate driving circuit, a sixth gate driving circuit and a seventh gate driving circuit, wherein the fifth gate driving circuit is used to transmit the first light-emitting control signal PWM-EM to the control ends of the first control transistor M1 and the second control transistor M6, the sixth gate driving circuit is used to transmit the second light-emitting control signal PAM-EM to the control ends of the third control transistor M7 and the fourth control transistor M12, and the seventh gate driving circuit is used to transmit the sweep signal SWEEP to the second plate of the storage capacitor Cst.

[0120] It should be noted that, according to different actual needs, the third type of gate drive circuit 10c can include the fifth gate drive circuit, the sixth gate drive circuit and the seventh gate drive circuit at the same time, or one or two gate drive circuits 10 can be cancelled. Exemplarily, the third type of gate drive circuit 10c includes the fifth gate drive circuit and the sixth gate drive circuit, but does not include the seventh gate drive circuit. At this time, the sweep signal SWEEP can be directly connected to the driver chip through the signal routing to achieve direct drive transmission.

[0121] For the convenience of description, the present application embodiment will be described by taking the third type of gate driving circuit 10c including the fifth gate driving circuit as an example. Figure 7As shown, in the fifth gate driving circuit, the control end of transistor T1' is connected to the first clock end CKS, the first electrode of the transistor T1' is connected to the frame start signal line STV, and the second electrode of transistor T1' is connected to the node N1'. The control end of transistor T2' is connected to the node N1', the first electrode of transistor T2' is connected to the first clock end CKS, and the second electrode of transistor T2' is connected to the node N2'. The control end of transistor T3' is connected to the first clock end CKS, the first electrode of transistor T3' is connected to the second power supply end VGL, and the second electrode of transistor T3' is connected to the node N2'. The control end of transistor T4' is connected to the node N9', the first electrode of transistor T4' is connected to the second clock end XCKS, and the second electrode of transistor T4' is connected to the node N5'. The control end of transistor T5' is connected to the node N2', the first electrode of transistor T5' is connected to the first power supply end VGH, and the second electrode of transistor T5' is connected to the node N5'.

[0122] The control end of the sixth transistor T6' is connected to the node N6', the first electrode of the transistor T6' is connected to the second clock end XCKS, and the second electrode of the transistor T6' is connected to the node N3'. The control end of the transistor T7' is connected to the second clock end XCKS, the first electrode of the transistor T7' is connected to the node N3', and the second electrode of the transistor T7' is connected to the node N4'. The control end of the transistor T8' is connected to the node N1, the first electrode of the transistor T8' is connected to the first power supply end VGH, and the second electrode of the transistor T8' is connected to the node N4'. The control end of the transistor T9' is connected to the node N4', the first electrode of the transistor T9' is connected to the first power supply end VGH, and the second electrode of the transistor T9' is connected to the shift output end GOUT. The control end of the transistor T10' is connected to the node N7', the first electrode of the transistor T10' is connected to the second power supply end VGL, and the second electrode of the transistor T10' is connected to the shift output end GOUT.

[0123] The control end of the transistor T11' is connected to the second power supply end VGL, the first electrode of the transistor T11' is connected to the node N2', and the second electrode of the transistor T11' is connected to the node N6'. The control end of the transistor T12' is connected to the second power supply end VGL, the first electrode of the transistor T12' is connected to the node N1', and the second electrode of the transistor T12' is connected to the node N7. The control end of the transistor T13' is connected to the reset end RESET, the first electrode of the transistor T13' is connected to the first power supply end VGH, and the second electrode of the transistor T13' is connected to the node N1'. The control end of the transistor T14' is connected to the first clock end CKS, the first electrode of the transistor T14' is connected to the frame start signal line STV, and the second electrode of the transistor T14' is connected to the node N8'. The control end of the transistor T15' is connected to the second power supply end VGL, the first electrode of the transistor T15' is connected to the node N8', and the second electrode of the transistor T15' is connected to the node N9'. The control terminal of the transistor T16 ′ is connected to the node N9 ′, the first electrode of the transistor T16 ′ is connected to the node N7 ′, and the second electrode of the transistor T16 ′ is connected to the node N9 ′.

[0124] The first plate of capacitor C1' is connected to node N6', and the second plate is connected to node N3'. The first plate of capacitor C2' is connected to node N4', and the second plate is connected to the first power supply terminal VGH. The first plate of capacitor C3' is connected to node N5', and the second plate is connected to node N9'.

[0125] It should be noted that the above content is only a structural form of the shift register 11 in the fifth gate driving circuit, which does not constitute a limitation on the circuit structure of the shift register 11. According to different actual needs, the shift register 11 can also adopt other circuit structures. Figure 6 and Figure 7 It can be seen that in the array substrate 100 , the circuit structure of the shift register 11 in the first type of gate driving circuit 10 a is usually designed differently from the circuit structure of the shift register 11 in the third type of gate driving circuit 10 c .

[0126] On this basis, the embodiment of the present application sets the first virtual register 121 corresponding to the first type of gate drive circuit 10a to be different from the second virtual register 122 corresponding to the third type of gate drive circuit 10c, so that the circuit structure of the first virtual register 121 can be consistent with the cascaded shift register 11, and the circuit structure of the second virtual register 122 can be consistent with the cascaded shift register 11, thereby further improving the structural matching between the virtual register 12 and the shift register 11 in a single gate drive circuit 10, which helps to reduce the design and preparation difficulty of the array substrate 100.

[0127] In some embodiments, Figure 5 As shown, the array substrate 100 further includes an electrostatic shielding unit 40 , and the output end of the virtual register 12 is electrically connected to the detection signal line 20 through the electrostatic shielding unit 40 .

[0128] The electrostatic shielding unit 40 is a circuit structure used to reduce electrostatic damage to the gate drive circuit 10. During the use of the display panel 200, the electrostatic shielding unit 40 can detect the voltage peak received from the gate drive circuit 10 and start quickly when a high voltage is detected to limit the voltage to a safe range, thereby reducing the damage to the gate drive circuit 10 caused by electrostatic discharge. This protection mechanism improves the operating reliability of the display panel 200 when it is subjected to electrostatic shock.

[0129] Next, the specific structural composition of the electrostatic shielding unit 40 will be described in conjunction with the accompanying drawings in the present application embodiment. Figure 8 , the electrostatic shielding unit 40 includes a transistor T9 and a transistor T10, the first electrode of the transistor T9 is connected to the low voltage signal VGL1, and the control terminal and the second electrode of the transistor T9 are connected to the node N. The control terminal and the first electrode of the transistor T10 are connected to the high voltage signal VGH1, and the second electrode of the transistor T10 is connected to the node N. In addition, the input terminal IN and the output terminal OUT of the electrostatic shielding unit 40 are respectively connected to the node N. Further, in combination with the virtual register 12 and the detection signal line 20, the input terminal IN of the electrostatic shielding unit 40 is also connected to the output terminal of the virtual register 12 through the signal routing, and the output terminal OUT of the electrostatic shielding unit 40 is also connected to the detection signal line 20.

[0130] It should be noted that the number of transistors T9 and transistors T10 is not limited to two. Depending on actual needs, the number of transistors T9 and transistors T10 can be more. The above content is only a circuit form in the electrostatic shielding unit 40. Different electrostatic shielding units 40 required in practice may also adopt other circuit forms. And in the final display panel 200, there may only be an electrostatic shielding unit 40 corresponding to the gate drive circuit 10, or there may also be an electrostatic shielding structure corresponding to other circuits or conductor structures, for example, there may also be an electrostatic shielding structure corresponding to the touch lead setting, and the embodiment of the present application is not limited to this.

[0131] In the embodiment of the present application, the electrostatic shielding unit 40 is not directly electrically connected to the output end of the shift register 11, but is first electrically connected to the output end of the virtual register 12, so that the virtual register 12 can also play the role of separating the electrostatic shielding unit 40 from the shift register 11, thereby reducing the influence of the electrostatic shielding unit 40 on the load size at the output end of the last row shift register 11, reducing the load difference at the output end of the last row shift register 11 relative to other rows of shift registers 11, and improving the display uniformity of the display panel 200. At the same time, the output end of the virtual register 12 needs to be electrically connected to the detection signal line 20 through the electrostatic shielding unit 40 first, thereby reducing the adverse effects of external static electricity on the shift register 11 and improving the operating reliability of the gate drive circuit 10.

[0132] In some embodiments, Figure 5 As shown, the detection signal line 20 includes a first line 21, and the first line 21 includes a first sub-portion 211 extending along the first direction X and a connecting portion 212 connecting the first sub-portion 211 and the electrostatic shielding unit 40. In the second direction Y, the first sub-portion 211 is located between the electrostatic shielding unit 40 and the virtual register 12.

[0133] The detection signal line 20 includes at least a first routing line 21. The first sub-portion 211 is a routing structure in the first routing line 21 extending along the first direction X, i.e., along the row direction. In the motherboard structure, the first sub-portion 211 can be led out of the corresponding array area, i.e., extend to the outside of the array substrate 100 to meet the detection needs of related signals.

[0134] The connecting portion 212 is a connecting structure for connecting the first sub-portion 211 and the electrostatic shielding unit 40. The connecting portion 212 has a variety of film layer compositions and routing forms, as long as the connecting portion 212 can connect the first sub-portion 211 and the electrostatic shielding unit 40 and does not contact or interfere with other device structures and signal routings.

[0135] Optionally, the connecting portion 212 includes a first sub-portion extending along the second direction Y and a second sub-portion extending along the first direction X, the first sub-portion is connected to the first sub-portion 211 and the second sub-portion at two ends in the second direction Y, and the second sub-portion is connected to the first sub-portion and the electrostatic shielding unit 40 at two ends in the first direction X. Further, the first sub-portion and the second sub-portion are located in the same film layer and include the same conductive material.

[0136] As for the connecting portion 212 and the first sub-portion 211, the first sub-portion 211 and the connecting portion 212 can be located in different film layers. Optionally, the first sub-portion 211 can be located in the same film layer as the control terminal of the transistor in the pixel circuit P, and the connecting portion 212 can be located in the same film layer as the signal routing for transmitting data signals.

[0137] In addition, in the embodiment of the present application, in the second direction Y, the first sub-portion 211 is arranged between the electrostatic shielding unit 40 and the virtual register 12, that is, the first sub-portion 211 is located on the side of the virtual register 12 away from the shift register 11. In this way, the existence of the virtual register 12 can not only isolate the first sub-portion 211 from the last row of shift registers 11 at the electrical connection level, but also increase the distance between the first sub-portion 211 and the last row of shift registers 11 in the second direction Y from the physical level, thereby reducing the risk of parasitic capacitance generated between the two, which helps to further improve the operating reliability of the gate drive circuit 10.

[0138] It should be noted that since the first sub-section 211 and the electrostatic shielding unit 40 are both located on the side of the virtual register 12 away from the shift register 11, the connecting portion 212 used to connect the first sub-section 211 and the electrostatic shielding unit 40 is also located on the side of the virtual register 12 away from the shift register 11. Therefore, the embodiment of the present application can also further increase the distance between the connecting portion 212 and the last row shift register 11 in the second direction Y, thereby reducing the risk of parasitic capacitance generated between the two.

[0139] In some embodiments, Figure 5 As shown, the detection signal line 20 also includes a second line 22 , which connects the electrostatic shielding unit 40 and at least one of the first lines 21 , and at least a portion of the second line 22 extends along the second direction Y away from the gate driving circuit 10 .

[0140] The first wiring 21 and the second wiring 22 are both part of the structure of the detection signal line 20, and the difference is that the first wiring 21 includes a first sub-portion 211 extending along the first direction X, so that in the detection stage, the first wiring 21 can be led out of the array substrate 100 along the first direction X, and at least part of the structure of the second wiring 22 extends in the second direction Y away from the gate drive circuit 10, so that in the detection stage, the second wiring 22 can be led out of the array substrate 100 along the second direction Y. In other words, in the detection, the first wiring 21 and the second wiring 22 need to be led out from different edge positions of the array substrate 100 to meet the respective needs of different detections.

[0141] The second line 22 is connected to at least one of the electrostatic shielding unit 40 and the first line 21, that is, the second line 22 can be directly connected to the electrostatic shielding unit 40, or can also be connected to the first line 21, and optionally, the second line 22 is connected to the connecting portion 212. Further optionally, the second line 22 can be an integral structure with the connecting portion 212, that is, the two are located in the same film layer and include the same conductive material, and are prepared and formed in the same process.

[0142] According to different internal layouts of the array substrate 100, the second routing line 22 may completely extend along the second direction Y, or a portion of the second routing line 22 may extend along the first direction X, so as to meet the need of avoiding some device structures or signal routing lines. The embodiment of the present application does not impose any limitation on this, as long as the general extension trend of the second routing line 22 is to extend along the second direction Y.

[0143] In the embodiment of the present application, the detection signal line 20 includes a first routing line 21 that partially extends along the first direction X, and a second routing line 22 that at least partially extends along the second direction Y. The combination of the two makes the detection signal line 20 itself have a larger load. On this basis, by adding a virtual register 12, the virtual register 12 can be used to block the adverse effect of the load of the detection signal line 20 itself on the shift register 11, thereby reducing the load difference at the output end of the last row shift register 11 relative to the shift registers 11 of other rows, thereby improving the display uniformity of the display panel 200.

[0144] In some embodiments, Figure 1 and Figure 5 As shown, the array substrate 100 further includes a plurality of electrode structures 30, the electrode structures 30 include a first connection electrode 31 and a second connection electrode 32 which are insulated, and the second connection electrode 32 is connected to the pixel circuit P. The plurality of electrode structures 30 include a first electrode group 33 connected to the Mth circuit row P5, and in the second direction Y, the electrostatic shielding unit 40 is located between the first electrode group 33 and the virtual register 12.

[0145] In combination with the above content, it can be known that the Mth circuit row P5 is the last circuit row P5, and the last circuit row P5 usually corresponds to controlling the last light-emitting elements. Therefore, the first electrode group 33 is the last electrode structure 30, and the multiple light-emitting elements corresponding to the first electrode group 33 are the last light-emitting elements, and the projections of the first electrode group 33 and the corresponding last light-emitting elements on the array substrate 100 are usually overlapped.

[0146] In the embodiment of the present application, the electrostatic shielding unit 40 is located between the first electrode group 33 and the virtual register 12, which means that the electrostatic shielding unit 40 is located on the side of the last row of light-emitting elements facing the other rows of light-emitting elements, rather than on the same side of all rows of light-emitting elements. In other words, the electrostatic shielding unit 40 will be integrated into the light-emitting area of ​​the display panel 200, rather than in the border area, so as to help eliminate the border area of ​​the display panel 200 and achieve a borderless effect.

[0147] In some embodiments, in the second direction Y, the virtual register 12 is located between the Mth circuit row P5 and the electrostatic shielding unit 40 , and a distance L1 between the virtual register 12 and the electrostatic shielding unit 40 is greater than a distance L2 between the virtual register 12 and the Mth circuit row P5 .

[0148] The Mth circuit row P5 is the last circuit row P5, and its corresponding shift register 11 is the last shift register 11, and the last shift register 11 will be located on the side of the last circuit row P5 facing the other circuit rows P3. At the same time, since the virtual register 12 is located between the last circuit row P5 and the electrostatic shielding unit 40, the virtual register 12 and the last shift register 11 will be arranged on both sides of the last circuit row P5 in the second direction Y.

[0149] On this basis, the embodiment of the present application limits the distance L2 of the virtual register 12 relative to the last row of circuit row P5 in the second direction Y, so that it is smaller than the distance L1 between the virtual register 12 and the electrostatic shielding unit 40 in the second direction Y. In other words, compared with the electrostatic shielding unit 40, the virtual register 12 is arranged closer to the last row of circuit row P5 in the second direction Y, which helps to reduce the distance between the virtual register 12 and the last row of shift register 11 in the second direction Y, thereby reducing the length of the cascade routing used to connect the virtual register 12 and the last row of shift register 11, reducing the load problem caused by the excessive extension size of the cascade routing, reducing the load difference at the output end of the last row of shift register 11 relative to other rows of shift registers 11, and improving the display uniformity of the display panel 200.

[0150] In some embodiments, see Figure 9 to Figure 1 1, the array substrate 100 further includes a substrate 50, a plurality of electrode structures 30 and a plurality of pad structures 60, wherein the electrode structure 30 includes a first connecting electrode 31 and a second connecting electrode 32 which are insulated from each other, and the second connecting electrode 32 is connected to the pixel circuit P. The pad structure 60 includes a first pad 61, and the first pad 61 and the electrode structure 30 are located on the same side of the substrate 50.

[0151] Optionally, the pad structure 60 may further include a second pad 62 , and the second pad 62 is located on a side of the substrate 50 away from the first pad 61 .

[0152] The multiple electrode structures 30 include a first electrode group 33 connected to the Mth circuit row P5. In the second direction Y, the first electrode group 33 is located between the first solder pad 61 and the electrostatic shielding unit 40, and the distance between the first electrode group 33 and the electrostatic shielding unit 40 is greater than the distance between the first electrode group 33 and the first solder pad 61.

[0153] The substrate 50 is a film layer structure on the array substrate 100 that plays a supporting and bearing role. The thickness direction Z of the substrate 50 is usually parallel to the thickness direction Z of the array substrate 100 itself, and in the thickness direction Z of the substrate 50, the substrate 50 includes two opposite surfaces, the light-emitting element, the electrode structure 30 and the first pad 61 are all located on one side of the surfaces of the substrate 50, and the second pad 62 and the driving chip are both located on the other side of the surface of the substrate 50.

[0154] The pad structure 60 is a bridge for realizing the electrical connection between different device structures or signal lines located on both sides of the substrate 50. For example, the driving chip realizes the electrical connection with the data signal line through the pad structure 60.

[0155] According to different practical needs, the pad structure 60 can have different forms, specifically, Fig.11a As shown, the pad structure 60 includes a first pad 61 disposed on one side of the substrate 50, and the substrate 50 is provided with a side trace 63 and a package protection portion 64 on one side of the second direction Y. The side trace 63 is connected to the first pad 61 and bent to the side of the substrate away from the first pad 61, and the package protection portion 64 is attached to the surface of the side trace 63 to play a protective role. Among them, the part of the side trace 63 located on the side of the substrate away from the first pad 61 is arranged beyond the package protection portion 64 in the second direction Y, and is connected to the circuit board structure 70.

[0156] Or Fig.11b As shown, the pad structure 60 includes a first pad 61 and a second pad 62 respectively disposed on both sides of the substrate 50. The first pad 61 and the second pad 62 each include a plurality of pads and are arranged side by side along the first direction X. The plurality of first pads 61 and the plurality of second pads 62 can be arranged corresponding to each other, and the second pad 62 can be connected to the circuit board structure 70. The substrate 50 is provided with a side trace 63 and a package protection portion 64 on one side of the second direction Y. The side trace 63 is connected to the first pad 61 and the second pad 62 at the same time to meet the electrical connection requirements between the first pad 61 and the second pad 62, and the package protection portion 64 covers the side trace 63 to protect the side trace 63.

[0157] For the first pad 61, the first pad 61 is usually arranged close to the surface of the array substrate 100 in the second direction Y, and is located on the side of the last row of light emitting elements away from the other rows of light emitting elements. Combining the above contents, it can be known that the position of the last row of light emitting elements in the thickness direction Z of the array substrate 100 is usually arranged to overlap with the position of the first electrode group 33 in the thickness direction Z of the array substrate 100.

[0158] On this basis, the embodiment of the present application sets the distance between the first electrode group 33 and the first pad 61 in the second direction Y to be smaller than that between the first electrode group 33 and the electrostatic shielding unit 40, so that the last row of light-emitting elements is arranged closer to the first pad 61 relative to the electrostatic shielding unit 40. In this way, during the operation of the display panel 200, the light-emitting area corresponding to the last row of light-emitting elements can cover the area where the first pad 61 is located, and even cover the edge of the array substrate 100 in the second direction Y, thereby achieving a borderless display effect and improving the viewing experience.

[0159] In some embodiments, Figure 1 and Fig. 9 As shown, in the second direction Y, the virtual register 12 is overlapped with the pixel circuit P; and / or, in the second direction Y, the virtual register 12 is overlapped with the shift register 11; and / or, in the second direction Y, the virtual register 12 is overlapped with the electrostatic shielding unit 40.

[0160] The “overlapping arrangement in the second direction Y” mentioned here means that at least parts of the different structures are located at the same position in the first direction X, so that the projections of the different structures in the thickness direction Z of the array substrate 100 can be overlapped in the second direction Y accordingly.

[0161] In the embodiment of the present application, the virtual register 12 can be selectively overlapped with at least one of the pixel circuit P, the shift register 11 and the electrostatic shielding unit 40 in the second direction Y. This helps to reduce the risk of increasing the size of the array substrate 100 in the first direction X due to the presence of the virtual register 12. While satisfying the rationality of the internal structure layout of the array substrate 100, it is beneficial to reduce the size of the subsequently formed display panel 200 in the first direction X, thereby improving the feel of use.

[0162] In some optional embodiments, in the second direction Y, the dummy register 12 is arranged to overlap with the pixel circuit P, the shift register 11 and the electrostatic shielding unit 40 at the same time.

[0163] In some embodiments, the electrostatic shielding unit 40 includes a first signal terminal and a second signal terminal, wherein the first signal terminal is configured to receive a high voltage signal VGH1, and the second signal terminal is configured to receive a low voltage signal VGL1. The first signal terminals of at least some of the electrostatic shielding units 40 receive different low voltage signals VGL1; and / or the second signal terminals of at least some different electrostatic shielding units 40 receive different high voltage signals VGH1.

[0164] Combination Figure 8For example, the first signal end is the first electrode of the transistor T9, and the second signal end is the control end and the first electrode of the body tube T10. The array substrate 100 usually includes a plurality of electrostatic shielding units 40, and different electrostatic shielding units 40 are used to achieve electrostatic shielding effects on different device structures or signal routings. On this basis, the embodiment of the present application sets different first signal ends to receive different low-voltage signals VGL1, or sets different second signal ends to receive different high-voltage signals VGH1 for different electrostatic shielding units 40, so that different electrostatic shielding units 40 can be set independently of each other, thereby reducing the mutual influence between different electrostatic shielding units 40 and their corresponding device structures or signal routings, and improving the operational reliability of the internal structure of the array substrate 100.

[0165] In some embodiments, the pixel circuit P includes an amplitude modulation subcircuit P2 and a pulse width modulation subcircuit P1, and the plurality of gate drive circuits 10 include a fourth type of gate drive circuit for controlling the pulse width modulation subcircuit P1, and a fifth type of gate drive circuit for controlling the amplitude modulation subcircuit P2. The plurality of electrostatic shielding units 40 include a first type of electrostatic shielding unit and a second type of electrostatic shielding unit, the first type of electrostatic shielding unit is electrically connected to the output end of the virtual register 12 of the fourth type of gate drive circuit, and the second type of electrostatic shielding unit is electrically connected to the output end of the virtual register 12 of the fifth type of gate drive circuit; wherein the first signal end of the first type of electrostatic shielding unit and the first signal end of the second type of electrostatic shielding unit receive different high voltage signals VGH1; and / or the second signal end of the first type of electrostatic shielding unit and the second signal end of the second type of electrostatic shielding unit receive different low voltage signals VGL1.

[0166] The fourth type of gate driving circuit and the fifth type of gate driving circuit are gate driving circuits 10 that drive and control the pulse width modulation sub-circuit P1 and the amplitude modulation sub-circuit P2 respectively. Figure 3a For example, the fourth type of gate driving circuit includes at least a first gate driving circuit and a third gate driving circuit. The output end of the first gate driving circuit can transmit the second scanning signal PWM-S2 to the control end of the first data writing transistor M2 through a signal wiring, and the output end of the third gate driving circuit can transmit the first scanning signal PWM-S1 to the control end of the first gate reset transistor M5 through a signal wiring.

[0167] Further, according to different actual needs, the fourth type of gate drive circuit may also include at least one of the fifth gate drive circuit and the seventh gate drive circuit, the fifth gate drive circuit is used to transmit the first light control signal PWM-EM to the control end of the first control transistor M1 and the second control transistor M6, and the seventh gate drive circuit is used to transmit the sweep signal SWEEP to the second plate of the storage capacitor Cst. Of course, in other embodiments, the fourth type of gate drive circuit may not include the fifth gate drive circuit and the seventh gate drive circuit.

[0168] The fifth type of gate driving circuit includes at least a second gate driving circuit and a fourth gate driving circuit. The output end of the second gate driving circuit can transmit the fourth scanning signal PAM-S2 to the control end of the second data writing transistor M8 through the signal routing, and the output end of the fourth gate driving circuit can transmit the third scanning signal PAM-S1 to the control end of the second gate reset transistor M11 through the signal routing.

[0169] Further, according to different actual needs, the fifth type of gate driving circuit may also optionally include a sixth gate driving circuit, and the sixth gate driving circuit is used to transmit the second light-emitting control signal PAM-EM to the control terminals of the third control transistor M7 and the fourth control transistor M12. Of course, in other embodiments, the fifth type of gate driving circuit may also not include the sixth gate driving circuit.

[0170] In an embodiment of the present application, the fourth type of gate driving circuit and the fifth type of gate driving circuit are gate driving circuits 10 that respectively drive and control the pulse width modulation sub-circuit P1 and the amplitude modulation sub-circuit P2. On this basis, by setting the first signal end of the first type of electrostatic shielding unit corresponding to the fourth type of gate driving circuit to receive a different high-voltage signal VGH1, or setting the second signal end of the first type of electrostatic shielding unit and the second signal end of the second type of electrostatic shielding unit to receive different low-voltage signals VGL1, it helps to improve the signal independence of the fourth type of gate driving circuit and the first type of electrostatic shielding unit relative to the fifth type of gate driving circuit and the second type of electrostatic shielding unit, reduce the risk of mutual influence between the fourth type of gate driving circuit and the fifth type of gate driving circuit, and improve the operating reliability of the pixel circuit P.

[0171] Second, see Fig.12 An embodiment of the present application provides a display panel 200, and the display panel 200 includes the array substrate 100 and a light-emitting element in any of the aforementioned embodiments.

[0172] It should be noted that the display panel 200 provided in the embodiment of the present application has the beneficial effects of the array substrate 100 in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the array substrate 100 for details, and the embodiment of the present application will not be repeated.

[0173] In some embodiments, the light emitting element comprises a micro light emitting diode.

[0174] In the embodiment of the present application, the display panel 200 uses micro-light emitting diodes to realize the light-emitting display function. In this case, the display panel 200 can be designed as a borderless display panel 200, that is, the display panel 200 does not include a border area for setting the virtual pixel circuit P. In view of this, the array substrate 100 can only have a virtual register 12, but no virtual pixel circuit P, which can not only meet the borderless display needs, but also isolate the last row shift register 11 from the detection signal line 20 with the help of the virtual register 12, reduce the load influence of the detection signal line 20 on the last row shift register 11 at the output end, and reduce the load difference of the last row shift register 11 relative to other rows of shift registers 11 at the output end, thereby reducing the display difference of the last row or rows of light-emitting elements relative to other rows of light-emitting elements, and improving the display uniformity of the display panel 200.

[0175] Third, see Fig.13 An embodiment of the present application provides a display device 300, and the display device 300 includes the display panel 200 in any of the aforementioned embodiments.

[0176] It should be noted that the display device 300 provided in the embodiment of the present application has the beneficial effects of the display panel 200 in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the array substrate 100 and the display panel 200 for details, and the embodiment of the present application will not be repeated.

[0177] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0178] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: A gate driving circuit, comprising a shift register group and a virtual register, wherein the shift register group comprises N shift registers arranged in cascade connection, and the virtual register is cascaded to the Nth stage shift register; A detection signal line is electrically connected to an output end of the virtual register.

2. The array substrate according to claim 1, characterized in that: Also comprising M circuit rows, the array substrate comprising a plurality of pixel circuits, the circuit rows comprising a plurality of pixel circuits arranged along a first direction, the M circuit rows being arranged in a second direction, the first direction and the second direction being parallel to the plane where the array substrate is located and intersecting with each other; The Nth stage shift register provides a gate control signal to the Mth circuit row.

3. The array substrate according to claim 2, characterized in that: In the second direction, the shift register is located between adjacent circuit rows; or, The array substrate includes a plurality of circuit columns, each of which includes a plurality of pixel circuits arranged along the second direction. In the first direction, the shift register is located between adjacent circuit columns.

4. The array substrate according to claim 3, characterized in that: In the second direction, the shift register is located between adjacent circuit rows, and the Mth circuit row is located between the Nth stage shift register and the dummy register.

5. The array substrate according to claim 3, characterized in that: It also includes a plurality of electrode structures, wherein the electrode structure includes a first connecting electrode and a second connecting electrode that are insulated, and the second connecting electrode is connected to the pixel circuit; The plurality of electrode structures include a first electrode group connected to the Mth circuit row, and in the second direction, the virtual register is located between the first electrode group and the Mth circuit row.

6. The array substrate according to claim 2, characterized in that: N=M.

7. The array substrate according to claim 2, characterized in that: N<M.

8. The array substrate according to claim 2, characterized in that: The circuit structures of the virtual registers in at least some of the different gate drive circuits are different; and / or, The circuit structure of the virtual registers in at least some of the different gate drive circuits remains consistent.

9. The array substrate according to claim 8, characterized in that: In a single gate driving circuit, the circuit structure in the virtual register is consistent with the circuit structure in the shift register.

10. The array substrate according to claim 8, characterized in that: In a single gate driving circuit, the virtual register and the shift register have the same size in the first direction; and / or, In a single gate driving circuit, the dummy register and the shift register have the same size in the second direction.

11. The array substrate according to claim 2, characterized in that: The plurality of gate driving circuits include a first type of gate driving circuit and a second type of gate driving circuit, wherein the first type of gate driving circuit is used to control the data signal to be written into the pixel circuit, and the second type of gate driving circuit is used to write a reset signal into the pixel circuit; At least one of the first type of gate driving circuit and the second type of gate driving circuit includes the virtual register.

12. The array substrate according to claim 11, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, the first type of gate driving circuit includes a first gate driving circuit and a second gate driving circuit, and the second type of gate driving circuit includes a third gate driving circuit and a fourth gate driving circuit; The first gate drive circuit is used to control the first data signal to be written into the pulse width modulation sub-circuit, the second gate drive circuit is used to control the second data signal to be written into the amplitude modulation sub-circuit, the third gate drive circuit is used to control the first reset signal to be written into the pulse width modulation sub-circuit, and the fourth gate drive circuit is used to control the second reset signal to be written into the amplitude modulation sub-circuit.

13. The array substrate according to claim 11, characterized in that: The first type of gate driving circuit includes a first virtual register, and the second type of gate driving circuit includes a second virtual register. The circuit structure of the first virtual register is consistent with that of the second virtual register.

14. The array substrate according to claim 11, characterized in that: The plurality of gate drive circuits further include a third type of gate drive circuit, the third type of gate drive circuit is used to output a light emitting control signal or a frequency sweeping signal, the first type of gate drive circuit includes a first virtual register, and the third type of gate drive circuit includes a third virtual register; The circuit structures of the first virtual register and the third virtual register are different.

15. The array substrate according to claim 2, characterized in that: It also includes an electrostatic shielding unit, and the output end of the virtual register is electrically connected to the detection signal line through the electrostatic shielding unit.

16. The array substrate according to claim 15, characterized in that: The detection signal line includes a first routing line, wherein the first routing line includes a first sub-portion extending along the first direction and a connecting portion connecting the first sub-portion and the electrostatic shielding unit; Wherein, in the second direction, the first sub-portion is located between the electrostatic shielding unit and the virtual register.

17. The array substrate according to claim 16, characterized in that: The detection signal line also includes a second line connected to at least one of the electrostatic shielding unit and the first line, and at least a portion of the second line extends along the second direction and away from the gate driving circuit.

18. The array substrate according to claim 15, characterized in that: It also includes a plurality of electrode structures, wherein the electrode structure includes a first connecting electrode and a second connecting electrode that are insulated, and the second connecting electrode is connected to the pixel circuit; The plurality of electrode structures include a first electrode group connected to the Mth circuit row, and in the second direction, the electrostatic shielding unit is located between the first electrode group and the virtual register.

19. The array substrate according to claim 15, characterized in that: In the second direction, the virtual register is located between the Mth circuit row and the electrostatic shielding unit, and a distance between the virtual register and the electrostatic shielding unit is greater than a distance between the virtual register and the Mth circuit row.

20. The array substrate according to claim 15, characterized in that: It also includes a substrate, a plurality of electrode structures and a plurality of pad structures, wherein the electrode structure includes a first connecting electrode and a second connecting electrode that are insulated, and the second connecting electrode is connected to the pixel circuit; The pad structure includes a first pad, wherein the first pad and the electrode structure are located on the same side of the substrate; The multiple electrode structures include a first electrode group connected to the Mth circuit row. In the second direction, the first electrode group is located between the first pad and the electrostatic shielding unit, and the distance between the first electrode group and the electrostatic shielding unit is greater than the distance between the first electrode group and the first pad.

21. The array substrate according to claim 15, characterized in that: In the second direction, the virtual register and the pixel circuit are arranged to overlap; and / or, In the second direction, the virtual register and the shift register are arranged to overlap; and / or, In the second direction, the dummy register is arranged to overlap with the electrostatic shielding unit.

22. The array substrate according to claim 15, characterized in that: The electrostatic shielding unit comprises a first signal terminal and a second signal terminal, the first signal terminal is configured to receive a high voltage signal, and the second signal terminal is configured to receive a low voltage signal; Wherein, at least some of the first signal ends of different electrostatic shielding units receive different low-voltage signals; and / or, at least some of the second signal ends of different electrostatic shielding units receive different high-voltage signals.

23. The array substrate according to claim 22, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, and the plurality of gate drive circuits include a fourth type of gate drive circuit for controlling the pulse width modulation subcircuit, and a fifth type of gate drive circuit for controlling the amplitude modulation subcircuit; The plurality of electrostatic shielding units include a first type of electrostatic shielding unit and a second type of electrostatic shielding unit, the first type of electrostatic shielding unit is electrically connected to the output end of the virtual register of the fourth type of gate driving circuit, and the second type of electrostatic shielding unit is electrically connected to the output end of the virtual register of the fifth type of gate driving circuit; The first signal end of the first type of electrostatic shielding unit and the first signal end of the second type of electrostatic shielding unit receive different high voltage signals; and / or the second signal end of the first type of electrostatic shielding unit and the second signal end of the second type of electrostatic shielding unit receive different low voltage signals.

24. A display panel, characterized in that: It comprises the array substrate and the light emitting element as described in any one of claims 1 to 23.

25. The display panel according to claim 24, characterized in that: The light emitting element comprises a micro light emitting diode.

26. A display device, characterized in that: Comprising the display panel as claimed in claim 24 or 25.

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