Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display, and the display panel comprises a display area which comprises a plurality of rows of pixels; the non-display area comprises a gate drive circuit, the gate drive circuit comprises a plurality of cascaded shift registers, and the shift registers are electrically connected with the clock signal lines; the plurality of shifting registers comprise n first shifting registers and m second shifting registers, the trigger signal end of the first first shifting register is electrically connected with the driving chip, and the output end of the nth first shifting register is electrically connected with the trigger signal end of the first second shifting register; the output end of the first shift register is electrically connected with the pixel, and the output end of the second shift register is electrically connected with the load compensation structure; in one frame of time, the number of effective pulses output by the shift register is k, m is larger than k, and the brightness uniformity of the display panel can be improved by arranging the second shift register to be electrically connected with the load compensation structure.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a display panel and a display device. Background Art

[0002] Currently, dual data lines (DDL) and shift registers are often used in display products to generate scan signals. For example, a scan signal with 3 pulses is generated. Since the load at the same time in the n pixel rows at the bottom of the display panel tends to gradually decrease, the bottom display is darker, affecting the display effect. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display device, which can improve the brightness uniformity of the display panel and enhance the display effect.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including:

[0005] A display area, including a plurality of rows of pixels;

[0006] The non-display area includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, and the shift registers are electrically connected to the clock signal line;

[0007] The multiple shift registers include n first shift registers and m second shift registers, a trigger signal end of the first first shift register is electrically connected to the driving chip, and an output end of the nth first shift register is electrically connected to the trigger signal end of the first second shift register;

[0008] The output end of the first shift register is electrically connected to the pixel, and the output end of the second shift register is electrically connected to the load compensation structure;

[0009] In one frame time, the number of effective pulses output by the shift register is k, m>k.

[0010] In a second aspect, an embodiment of the present application provides a display device, including:

[0011] A display panel as provided in any one of the aforementioned first aspects.

[0012] The display panel and display device provided by the embodiments of the present application are configured such that n first shift registers and m second shift registers are arranged in a non-display area, and m second shift registers are arranged to be cascaded with n first shift registers. The first shift registers are electrically connected to pixels, and the second shift registers are electrically connected to a load compensation structure. In addition, within a frame time, the number m of the second shift registers is greater than the number k of valid pulses output by the shift registers. By arranging the second shift registers to be electrically connected to the load compensation structure, the load of the shift register at the bottom of the display panel can be compensated, thereby improving the brightness uniformity of the display panel and the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic structural diagram of an exemplary scan drive circuit provided for some embodiments of the present application.

[0015] Figure 2 A partial schematic diagram of an exemplary pixel circuit provided for some embodiments of the present application.

[0016] Figure 3 An exemplary pixel circuit timing diagram is provided for some embodiments of the present application.

[0017] Figure 4 A schematic structural diagram of an exemplary display panel provided for some embodiments of the present application.

[0018] Figure 5 A schematic diagram of an exemplary gate drive circuit provided for some embodiments of the present application.

[0019] Figure 6 A schematic diagram of another exemplary gate drive circuit provided for some embodiments of the present application.

[0020] Figure 7 A schematic diagram of another exemplary gate drive circuit provided for some embodiments of the present application.

[0021] Figure 8 A timing diagram of a gate driving circuit is provided for some embodiments of the present application.

[0022] Fig. 9 A schematic diagram of another exemplary gate drive circuit provided for some embodiments of the present application.

[0023] Fig.10A schematic diagram of an exemplary load compensation structure provided for some embodiments of the present application.

[0024] Fig.11 A schematic diagram of an exemplary display device provided for some embodiments of the present application. DETAILED DESCRIPTION

[0025] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0026] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0027] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0028] In display products, it is often connected to the pixel circuits in the pixel row through a shift register, such as Figure 1 As shown, Figure 1 FIG. 1 is a schematic diagram 100 of an exemplary scan driving circuit. Figure 1 The scan drive circuit may include multiple cascaded shift registers 10 and multiple rows of pixels 20, wherein the output end of each shift register 10 may be electrically connected to a row of pixels 20 through a first scan line S1, and electrically connected to another row of pixels 20 through a second scan line S2. Here, the shift register may be electrically connected to the pixel circuit in the pixel row, and the above-mentioned shift register 10 may transmit scan signals to pixels in different rows through the above-mentioned first scan line S1 and second scan line S2.

[0029] like Figure 2 As shown, Figure 2 A partial schematic diagram 200 of an exemplary pixel circuit is shown. Figure 2 The control end of the first reset module 201 can be electrically connected to the first end of the first scan line S1, the first end of the first reset module 201 can be electrically connected to the first reference voltage signal line Vref1, the second end of the first reset module 201 can be electrically connected to the first node N1, the above-mentioned first node N1 is the control end of the driving module 202, the control end of the data writing module 203 can be electrically connected to the second scan line S2, the first end of the data writing module 203 can be electrically connected to the data signal line Data, the second end of the data writing module 203 can be electrically connected to the first end of the driving module 202, and the second end of the driving module 202 can be electrically connected to the light-emitting device 204. The normal light emission of the light-emitting device can be achieved through the above-mentioned pixel circuit.

[0030] like Figure 3 As shown, Figure 3 For a Figure 2 A driving timing diagram corresponding to the pixel circuit shown in FIG. Figure 3 As shown, in the first node initialization phase t1, the control end of the first reset module 201 can be turned on in response to the first scan signal SCAN1 output by the first scan line S1, and other transistors are turned off, and the first reference voltage signal of the first reference voltage signal line Vref1 is transmitted to the first node N1 through the first reset module 201 to reset the first node N1. In the data writing phase t2, the control end of the data writing module 203 is turned on in response to the second scan signal SCAN2 output by the second scan line S2, and the data signal output by the data signal line Data is transmitted to the anode of the light-emitting device 204 through the data writing module 203.

[0031] Combination Figure 1-Figure 3 It can be known that the i-th shift register 10 can control the data writing module 203 of the pixel circuit in the i-th row of pixels 20 to be turned on through the second scanning signal SCAN2 output by the second scanning line S2, and the data signal transmitted by the data signal line Data can be written into the first node N1 of the pixel circuit in the i-th row of pixels 20. At the same time, the above-mentioned i-th shift register 10 can control the first reset module 201 in the pixel circuit in the i+1-th row of pixels 20 to be turned on through the first scanning signal SCAN1 output by the first scanning line S1, and the first reset module 201 in the pixel circuit in the i+1-th row of pixels 20 can transmit the first reference voltage signal to the first node N1 in the i+1-th row of pixels 20 to reset the first node N1.

[0032] Therefore, among the cascaded shift registers in the display panel, the bottom shift register can only be electrically connected to the pixel circuit of a row of pixels, resulting in inconsistent load (loading) of the shift register, causing the display brightness at the bottom of the display panel with smaller loading to be darker, and the display brightness of the display panel to be uneven, affecting the display effect.

[0033] Based on this, the embodiments of the present application provide a display panel and a display device, which can solve the above problems.

[0034] In some embodiments, Figure 4 As shown, Figure 4 A display panel 400 is provided for an embodiment of the present application. The display panel 400 may be AMOLED, OLED or other. The display panel may include:

[0035] The display area 401 may include a plurality of rows of pixels 40 ; and the non-display area 402 includes a gate driving circuit 41 .

[0036] Combine the following Figure 5 , Figure 5 is a schematic diagram of an exemplary gate drive circuit, such as Figure 5 As shown, the gate drive circuit 41 includes a plurality of cascaded shift registers, and the shift registers are electrically connected to the clock signal line, such as Figure 5 In the embodiment, the clock signal line may include a first clock signal line CK and a second clock signal line XCK, and the input end of each shift register is electrically connected to the above CK and XCK.

[0037] like Figure 5 As shown, the plurality of shift registers include n first shift registers 501 and m second shift registers 502, the trigger signal terminal STV1 of the first first shift register is electrically connected to the driver chip, the output terminal of the nth first shift register is electrically connected to the trigger signal terminal STV2 of the first second shift register. The output terminal of the i-th shift register can be electrically connected to the input terminal of the i+2-th shift register.

[0038] like Figure 5 , the output end of the first shift register 501 is electrically connected to the pixel 40, and the output end of the second shift register 502 is electrically connected to the load compensation structure 42; within one frame time, the number of effective pulses output by the shift register is k, m>k. The load structure can be a dummy pixel or a load capacitor formed by a signal line and a conductive block. Here, the number of effective pulses output by each shift register within one frame time can be k, and the k can be an integer greater than or equal to 3, and the number m of the second shift registers can be an integer greater than k.

[0039] The embodiment of the present application arranges a plurality of n first shift registers and m second shift registers in the non-display area of ​​the display panel, arranges the second shift register to be cascaded with the first shift register, and arranges the output end of the first shift register to be electrically connected to the pixel, and the output end of the second shift register to be electrically connected to the load compensation structure, so as to compensate the loads of the first shift register and the second shift register, thereby making the display of the display panel uniform and improving the display effect.

[0040] In some embodiments, Figure 6 As shown, Figure 6 is a schematic diagram of another exemplary gate drive circuit, such as Figure 6 As shown, the load compensation structure 42 may include a plurality of load compensation units 420 arranged along a first direction, the number of the load compensation units 420 may be the same as the number of the second shift register 502, and the first direction is the direction along the Y axis in the figure, such as Figure 6 As shown, the output end of each first shift register 501 is electrically connected to x rows of pixels, and the output end of each second shift register 502 is electrically connected to y load compensation units, where x is an integer greater than or equal to 2, y is an integer greater than or equal to 2, and x=y.

[0041] Here, if Figure 6 The output end of each first shift register 501 can be electrically connected to two rows of pixels through the first scan line S1 and the second scan line S2, and the output end of each second shift register 502 can be electrically connected to two load compensation units through the first scan line S1 and the second scan line S2.

[0042] In the embodiment of the present application, a load compensation structure is provided including a plurality of load compensation units arranged along a first direction. By providing the load compensation units, the size of the non-display area of ​​the display panel can be reduced, which is conducive to achieving a narrow frame. At the same time, the output end of each first shift register is electrically connected to more than or equal to 2 rows of pixels, and the output end of each second shift register is electrically connected to more than or equal to 2 load compensation units. This can relatively reduce the number of shift registers, thereby reducing the difficulty of layout of electrical components and wiring in the display panel.

[0043] In some embodiments, Figure 6, the output end of the i-th first shift register 501 can be electrically connected to the i+2-th row of pixels and the i-th row of pixels respectively through the first scan line S1 and the second scan line S2, and the output end of the j-th second shift register can be electrically connected to the j+2-th load compensation unit and the j-th load compensation unit respectively through the first scan line S1 and the second scan line S2, where i≤n, j≤m, here, the output end of the n-1-th first shift register 501 can be electrically connected to the n-1-th row of pixels and the 1st load compensation unit through the second scan line S2, and the output end of the n-th first shift register 501 can be electrically connected to the n-th row of pixels and the 2nd load compensation unit through the second scan line S2.

[0044] In some embodiments, Figure 7 As shown, Figure 7 A schematic diagram of another exemplary gate drive circuit provided in an embodiment of the present application is shown in FIG. Figure 7 In the gate driving circuit shown, the output end of the i-th first shift register 501 can be electrically connected to the i+1-th row of pixels and the i-th row of pixels through the first scan line S1 and the second scan line S2, respectively, and the output end of the j-th second shift register can be electrically connected to the j+1-th load compensation unit and the j-th load compensation unit through the first scan line S1 and the second scan line S2, respectively, where i≤n, j≤m. Figure 7 , the output end of the i-th shift register can be electrically connected to the input end of the i+1-th shift register.

[0045] In the embodiment of the present application, by setting the output end of the i-th first shift register to be electrically connected to the i-th row and the i+1-th row of pixels, and the output end of the j-th second shift register to be electrically connected to the j-th load compensation unit and the j+1-th load compensation unit; or setting the output end of the i-th first shift register to be electrically connected to the i-th row of pixels and the i+2-th row of pixels, and the output end of the j-th second shift register to be electrically connected to the j-th load compensation unit and the j+2-th load compensation unit, the scan signal SCAN output by the i-th first shift register can control the data writing in the data circuit of the i-th row of pixels and the resetting of the first node in the i+1-th or i+2-th row of pixel circuits, so that the pixel circuits in the display panel can achieve normal data writing and the resetting of the first node, and the display panel can emit light normally. At the same time, the loading of the second shift register is set to be consistent with that of the first shift register, so as to improve the brightness uniformity of the display panel.

[0046] In some embodiments, k≥3, each of the first shift registers 501 and each of the second shift registers 502 can output more than three valid pulses within one frame time, and each valid pulse can be used to write the data signal of the N1 node of the pixel circuit in a row of pixels, and reset the N1 node of the pixel circuit in another row of pixels.

[0047] like Figure 8 , Figure 8 is a timing diagram of an exemplary shift register, Figure 8 The timing diagram of the scanning signal at different times is shown, such as Figure 8 , within one frame time, the scan signal SCAN501 output by each first shift register 501 and the scan signal SCAN502 output by each second shift register may include more than three valid pulses.

[0048] In the embodiment of the present application, the first shift register and the second shift register are configured to output more than three valid pulses within one frame time, thereby achieving uniform brightness display of the display panel even in the case of multiple pulses.

[0049] In some embodiments, Fig. 9 As shown, Fig. 9 A schematic diagram of another gate drive circuit provided in an embodiment of the present application is shown as follows: Fig. 9 The first clock signal line CK may include a first sub-clock signal line CK1 and a second sub-clock signal line CK2, the second clock signal line XCK may include a third sub-clock signal line XCK1 and a fourth sub-clock signal line XCK2, and the number of the second shift registers may correspond to the number of the clock signal lines.

[0050] In some embodiments, the number of the second shift registers satisfies the following conditions:

[0051] m=z1×k-2 (1)

[0052] Wherein, z1 is the number of clock signal lines, z1=4; or,

[0053] m=z2×k-1 (2)

[0054] Wherein, z2 is the number of clock signal lines, z2=2.

[0055] In such Fig. 9 In the gate driving circuit shown, the number of clock signal lines is 4, and the number of second shift registers satisfies m=z1×k-2. For example, when the number of effective pulses k is 3, the number of the second shift registers 502 can be 10.

[0056] In such Figure 6 In the gate driving circuit shown, the number of clock signal lines is 2, and the number of second shift registers satisfies m=z2×k-1. For example, when the number of effective pulses k is 3, the number of the second shift registers 502 can be 5.

[0057] In such Figure 7 In the gate driving circuit shown, the number of the second shift registers may satisfy m=z2k-1. It is conceivable that the number of load compensation units equal to the number of the second shift registers may be set for the above different numbers of second shift registers.

[0058] It is conceivable that, when each second shift register and a corresponding load compensation unit electrically connected thereto are added, the width of the non-display area in the first direction may increase by about 5 μm.

[0059] The embodiment of the present application sets the number of second shift registers, and sets the number of second shift registers in relation to the number of clock signal lines and the number of valid pulses. It is thus possible to design different numbers of second shift registers for gate drive circuits in different situations, thereby improving the brightness uniformity of the display panel.

[0060] In some embodiments, Fig.10 As shown, Fig.10 is a schematic diagram of an exemplary load compensation structure, such as Fig.10 The load compensation structure includes a wiring 901 and a conductive block 902. The wiring 901 is electrically connected to the output end of the second shift register 502. The conductive block 902 can be electrically connected to a fixed voltage signal end. In some examples, the fixed voltage signal end can be a PVDD end electrically connected to a driving module in a pixel circuit. The fixed voltage signal end can also be other signal ends such as a signal end PVEE end connected to the cathode of a light-emitting device. Fig.10 , the routing lines and the conductive blocks at least partially overlap in the thickness direction of the display panel.

[0061] In some embodiments, the wiring 901 and the conductive block 902 can be arranged in any two different film layers. For example, the wiring 901 can be arranged in the same layer as the first plate of the storage capacitor in the pixel circuit, and the conductive block 902 can be arranged in the same layer as the second plate of the storage capacitor, and the second plate is far away from the substrate relative to the first plate.

[0062] In the embodiment of the present application, a load compensation structure is provided including a wiring and a conductive block. The wiring is electrically connected to the output end of the second shift register, and the conductive block is electrically connected to the voltage signal end. The wiring and the conductive block at least partially overlap in the thickness direction of the display panel. A load compensation structure can be formed by the wiring and the conductive block. The above-mentioned load compensation structure can reduce the width of the load compensation structure in the first direction and reduce the size of the non-display area.

[0063] In some embodiments, Fig.10 As shown, the routing includes m signal lines arranged along a first direction, and the signal lines may include a first scan line S1 and a second scan line S2. Fig.10 Each signal line can be electrically connected to the output end of at least one second shift register 502, and the conductive block 902 and the m signal lines at least partially overlap in the thickness direction of the display panel.

[0064] In the embodiment of the present application, m signal lines and conductive blocks are at least partially overlapped in the thickness direction of the display panel to form a load compensation structure, so that the loading of the first shift register is compensated by the load compensation structure, thereby improving the display brightness uniformity of the display panel.

[0065] In some embodiments, Fig.10 As shown, the conductive block 902 includes a plurality of conductive units 9021 arranged along the second direction. The plurality of conductive units 9021 can be electrically connected to the fixed voltage signal terminal. Each conductive unit at least partially overlaps with m signal lines in the thickness direction of the display panel.

[0066] In the embodiment of the present application, by configuring the conductive block to include a plurality of conductive units, the load size of the load compensation structure can be flexibly controlled by the number of conductive units, thereby improving the brightness uniformity of the display panel.

[0067] In some embodiments, the overlapping area of ​​a conductive unit 9021 and a signal line is smaller than the overlapping area of ​​two plates of the storage capacitor. By setting the overlapping area of ​​a conductive unit and a signal line smaller than the overlapping area of ​​two substrates of the storage capacitor, the loading of the shift register can be flexibly adjusted by adjusting the overlapping area of ​​the conductive unit and the signal line, so that the loading of the first shift register remains consistent, thereby improving the display uniformity of the display panel.

[0068] In some embodiments, Figure 5-Figure 9As shown, a plurality of shift registers may be arranged along the first direction, and the height of the second shift register 502 in the first direction is less than or equal to the height of the first shift register 501 in the first direction; the width of the second shift register 502 in the second direction is less than or equal to the width of the first shift register 501 in the second direction. In some examples, the second shift register 502 may be set to be a register of the same size as the first shift register 501, for example, the height of the second shift register 502 in the first direction may be equal to the height of the first shift register 501 in the first direction; the width of the second shift register 502 in the second direction may be equal to the width of the first shift register 501 in the second direction.

[0069] The embodiment of the present application can reduce the size of the second display area and realize a narrow frame of the display panel by setting the height of the second shift register in the first direction to be less than or equal to the height of the first shift register in the first direction, and setting the width of the second shift register in the second direction to be less than or equal to the width of the first shift register in the second direction.

[0070] Based on the display panel provided in the above embodiment, the present application also provides a display device, including the display panel provided in the present application. Fig.11 , Fig.11 A schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.11 The provided display device 1000 includes the display panel 400 provided by any of the above embodiments of the present application. Fig.11 In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 400 provided in the embodiment of the present application. For details, reference can be made to the specific description of the display panel 400 in the above embodiments, and this embodiment will not be repeated here.

[0071] It should be understood that the specific structure of the circuit and the cross-sectional structure of the display panel provided in the drawings of the embodiments of the present application are only some examples and are not used to limit the present application. In addition, the above embodiments provided by the present application can be combined with each other if there is no contradiction.

[0072] It should be clear that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in this application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that technicians in the relevant technical field can make good use of the application and the modified use based on the application. The application is only limited by the claims and their full scope and equivalents.

[0073] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0074] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0075] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or devices based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0076] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (device) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.

[0077] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described devices, modules and units can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: A display area, including a plurality of rows of pixels; The non-display area includes a gate driving circuit, wherein the gate driving circuit includes a plurality of cascaded shift registers, and the shift registers are electrically connected to a clock signal line; The multiple shift registers include n first shift registers and m second shift registers, a trigger signal end of the first first shift register is electrically connected to a driving chip, and an output end of the nth first shift register is electrically connected to a trigger signal end of the first second shift register; The output end of the first shift register is electrically connected to the pixel, and the output end of the second shift register is electrically connected to the load compensation structure; In one frame time, the number of effective pulses output by the shift register is k, where m>k.

2. The display panel according to claim 1, characterized in that: The load compensation structure includes a plurality of load compensation units arranged along a first direction, the output end of each of the first shift registers is electrically connected to x rows of pixels, and the output end of each of the second shift registers is electrically connected to y load compensation units, wherein x is an integer greater than or equal to 2, y is an integer greater than or equal to 2, and x=y.

3. The display panel according to claim 2, characterized in that: x=2, y=2, the output end of the i-th first shift register is electrically connected to the i-th row and the i+1-th row of pixels, and the output end of the j-th second shift register is electrically connected to the j-th load compensation unit and the j+1-th load compensation unit; or, x=2, y=2, the output end of the i-th first shift register is electrically connected to the i-th row of pixels and the i+2-th row of pixels, and the output end of the j-th second shift register is electrically connected to the j-th load compensation unit and the j+2-th load compensation unit.

4. The display panel according to claim 1, characterized in that: k≥3。 5. The display panel according to claim 3, characterized in that: The number of the second shift registers meets the following conditions: m = z1 × k-2; Wherein, z1 is the number of the clock signal lines, z1=4; or, m = z2 × k-1; Wherein, z2 is the number of the clock signal lines, z2=2.

6. The display panel according to claim 1, characterized in that: The load compensation structure includes a wiring and a conductive block, the wiring is electrically connected to the output end of the second shift register, the conductive block is electrically connected to the fixed voltage signal end, and the wiring and the conductive block at least partially overlap in the thickness direction of the display panel.

7. The display panel according to claim 6, characterized in that: The routing includes m signal lines arranged along a first direction, each of the signal lines is electrically connected to an output end of at least one second shift register, and the conductive blocks at least partially overlap with the m signal lines in a thickness direction of the display panel.

8. The display panel according to claim 7, characterized in that: The conductive block includes a plurality of conductive units arranged along the second direction, the plurality of conductive units are electrically connected to the fixed voltage signal end, and each of the conductive units at least partially overlaps with the m signal lines in the thickness direction of the display panel.

9. The display panel according to claim 8, characterized in that: The overlapping area of ​​one of the conductive units and one of the signal lines is smaller than the overlapping area of ​​two plates of the storage capacitor.

10. The display panel according to claim 1, characterized in that: The multiple shift registers are arranged along the first direction, the height of the second shift register in the first direction is less than or equal to the height of the first shift register in the first direction; the width of the second shift register in the second direction is less than or equal to the width of the first shift register in the second direction.

11. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 10.

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