Display panel and display device

Abstract

The application discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a display area and a non-display area. The display area comprises a plurality of rows of pixels. The non-display area comprises a gate drive circuit. The gate drive circuit comprises a plurality of cascaded shift registers. The shift registers are electrically connected with a clock signal line. The plurality of shift registers comprise n first shift registers and m second shift registers. The trigger signal end of the first first shift register is electrically connected with a driving chip. The output end of the n first shift register is electrically connected with the trigger signal end of the first second shift register. The output end of the first shift register is electrically connected with a pixel. The output end of the second shift register is electrically connected with a load compensation structure. In one frame time, the number of effective pulses output by the shift registers is k, and m > k. By electrically connecting the second shift register with the load compensation structure, the brightness uniformity of the display panel can be improved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Technology

[0002] Currently, dual data lines (DDL) and shift registers are often used in display products to generate scan signals, such as generating a scan signal with 3 pulses. Since the load in the n pixel rows at the bottom of the display panel gradually decreases at the same time, the bottom display is darker, affecting the display effect. Summary of the Invention

[0003] This application provides a display panel and a display device that can improve the brightness uniformity of the display panel and enhance the display effect.

[0004] In a first aspect, embodiments of this application provide a display panel, including:

[0005] The display area includes multiple rows of pixels;

[0006] The non-display area includes a gate drive circuit, which includes multiple cascaded shift registers, and the shift registers are electrically connected to the clock signal line.

[0007] The multiple shift registers include n first shift registers and m second shift registers. The trigger signal terminal of the first first shift register is electrically connected to the driver chip, and the output terminal of the nth first shift register is electrically connected to the trigger signal terminal of the first second shift register.

[0008] The output of the first shift register is electrically connected to the pixel, and the output of the second shift register is electrically connected to the load compensation structure.

[0009] Within one frame, the number of valid pulses output by the shift register is k, where m > k.

[0010] Secondly, embodiments of this application provide a display device, comprising:

[0011] The display panel provided in any of the first aspects mentioned above.

[0012] The display panel and display device provided in this application embodiment, by setting n first shift registers and m second shift registers in the non-display area, by setting m second shift registers and n first shift registers in cascade, by setting the first shift registers electrically connected to the pixels, by setting the second shift registers electrically connected to the load compensation structure, and by setting the number m of second shift registers to be greater than the number k of effective pulses output by the shift registers within one frame, and by setting the second shift registers to be electrically connected to the load compensation structure, can compensate the load of the shift registers at the bottom of the display panel, thereby improving the brightness uniformity of the display panel and improving the display effect. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of an exemplary scanning drive circuit provided for some embodiments of this application.

[0015] Figure 2 This is a partial schematic diagram of an exemplary pixel circuit provided for some embodiments of this application.

[0016] Figure 3 This is an exemplary pixel circuit timing diagram provided for some embodiments of this application.

[0017] Figure 4 This is a schematic diagram of the structure of an exemplary display panel provided for some embodiments of this application.

[0018] Figure 5 This is a schematic diagram of an exemplary gate drive circuit provided for some embodiments of this application.

[0019] Figure 6 This is a schematic diagram of another exemplary gate drive circuit provided for some embodiments of this application.

[0020] Figure 7 This is a schematic diagram of yet another exemplary gate drive circuit provided for some embodiments of this application.

[0021] Figure 8 This application provides a timing diagram of a gate driving circuit for some embodiments.

[0022] Figure 9 This is a schematic diagram of yet another exemplary gate drive circuit provided for some embodiments of this application.

[0023] Figure 10This is a schematic diagram of an exemplary load compensation structure provided for some embodiments of this application.

[0024] Figure 11 This is a schematic diagram of an exemplary display device provided for some embodiments of this application. Detailed Implementation

[0025] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0027] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0028] In display products, shift registers are often connected to the pixel circuits in pixel rows, such as... Figure 1 As shown, Figure 1 A schematic diagram 100 of an exemplary scanning drive circuit is shown below. Figure 1 The scanning drive circuit may include multiple cascaded shift registers 10 and multiple rows of pixels 20. The output of each shift register 10 can be electrically connected to one row of pixels 20 via a first scan line S1 and to another row of pixels 20 via a second scan line S2. Here, the shift register can be electrically connected to the pixel circuit in the pixel row. The shift register 10 can transmit scanning signals to pixels in different rows via the first scan line S1 and the second scan line S2.

[0029] like Figure 2 As shown, Figure 2 A partial schematic diagram 200 of an exemplary pixel circuit is shown below. Figure 2 The control terminal of the first reset module 201 can be electrically connected to the first end of the first scan line S1. The first end of the first reset module 201 can be electrically connected to the first reference voltage signal line Vref1. The second end of the first reset module 201 can be electrically connected to the first node N1. The first node N1 is the control terminal of the drive module 202. The control terminal of the data writing module 203 can be electrically connected to the second scan line S2. The first end of the data writing module 203 can be electrically connected to the data signal line Data. The second end of the data writing module 203 can be electrically connected to the first end of the drive module 202. The second end of the drive module 202 can be electrically connected to the light-emitting device 204. The normal light emission of the light-emitting device can be realized through the above pixel circuit.

[0030] like Figure 3 As shown, Figure 3 For a kind of Figure 2 The pixel circuit shown is a driving timing diagram, such as... Figure 3 As shown, during the first node initialization phase t1, the control terminal of the first reset module 201 can be turned on in response to the first scan signal SCAN1 output by the first scan line S1, while other transistors are turned off. The first reference voltage signal of the first reference voltage signal line Vref1 is transmitted to the first node N1 through the first reset module 201 to reset the first node N1. During the data writing phase t2, the control terminal of the data writing module 203 is turned on in response to the second scan signal SCAN2 output by the second scan line S2. The data signal output by the data signal line Data is transmitted to the anode of the light-emitting device 204 through the data writing module 203.

[0031] Combination Figures 1-3 It can be seen that the i-th shift register 10 can control the data writing module 203 of the pixel circuit in the i-th row of pixels 20 to be turned on by the second scan signal SCAN2 output by the second scan line S2. The data signal transmitted by the data signal line Data can be written to the first node N1 of the pixel circuit in the i-th row of pixels 20. At the same time, the i-th shift register 10 can control the first reset module 201 in the pixel circuit in the (i+1)-th row of pixels 20 to be turned on by the first scan signal SCAN1 output by the first scan line S1. The first reset module 201 in the pixel circuit in the (i+1)-th row of pixels 20 can transmit the first reference voltage signal to the first node N1 in the (i+1)-th row of pixels 20 to reset the first node N1.

[0032] Therefore, in the cascaded shift registers in the display panel, the bottom shift register can only be electrically connected to the pixel circuit of one row of pixels, which makes the load of the shift register inconsistent. This results in the bottom of the display panel with a smaller load being darker, and the display panel has uneven brightness, affecting the display effect.

[0033] Based on this, embodiments of this application provide a display panel and a display device that can solve the above-mentioned problems. The following is a detailed description of a display panel provided in an embodiment of this application.

[0034] In some embodiments, such as Figure 4 As shown, Figure 4 This application provides a display panel 400, which may be AMOLED, OLED, or other types. The display panel may include:

[0035] Display area 401, which may include multiple rows of pixels 40; non-display area 402, which includes gate driving circuit 41.

[0036] The following is combined Figure 5 , Figure 5 This is a schematic diagram of an exemplary gate drive circuit, such as... Figure 5 As shown, the gate drive circuit 41 includes multiple cascaded shift registers, which are electrically connected to the clock signal line, such as... Figure 5 In this, the clock signal lines may include a first clock signal line CK and a second clock signal line XCK, and the input of each shift register is electrically connected to both CK and XCK.

[0037] like Figure 5 As shown, the multiple shift registers include n first shift registers 501 and m second shift registers 502. The trigger signal terminal STV1 of the first first shift register is electrically connected to the driver chip, and the output terminal of the nth first shift register is electrically connected to the trigger signal terminal STV2 of the first second shift register. The output terminal of the ith shift register can be electrically connected to the input terminal of the (i+2)th shift register.

[0038] like Figure 5 The output of the first shift register 501 is electrically connected to pixel 40, and the output of the second shift register 502 is electrically connected to the load compensation structure 42. Within one frame, the number of effective pulses output by the shift registers is k, where m > k. The load structure can be a dummy pixel or a load capacitor formed by signal lines and conductive blocks. Here, the number of effective pulses output by each shift register within one frame can be k, where k can be an integer greater than or equal to 3, and the number m of the second shift registers can be an integer greater than k.

[0039] This application embodiment includes multiple n first shift registers and m second shift registers in the non-display area of ​​the display panel. By setting the second shift registers to be cascaded with the first shift registers, and setting the output terminal of the first shift register to be electrically connected to the pixel, and the output terminal of the second shift register to be electrically connected to the load compensation structure, the load of the first shift registers and the second shift registers can be compensated, so that the display of the display panel is uniform and the display effect is improved.

[0040] In some embodiments, such as Figure 6 As shown, Figure 6 A schematic diagram of another exemplary gate drive circuit, such as Figure 6 As shown, the load compensation structure 42 may include a plurality of load compensation units 420 arranged along a first direction. The number of load compensation units 420 may be the same as the number of second shift registers 502. The first direction is the direction along the Y-axis in the figure. Figure 6 As shown, the output of each first shift register 501 is electrically connected to the corresponding x rows of pixels, and the output of each second shift register 502 is electrically connected to y load compensation units, where x is an integer greater than or equal to 2, y is an integer greater than or equal to 2, and x = y.

[0041] Here, as Figure 6 Each first shift register 501 output terminal can be electrically connected to two rows of pixels respectively through the first scan line S1 and the second scan line S2, and each second shift register 502 output terminal can be electrically connected to two load compensation units respectively through the first scan line S1 and the second scan line S2.

[0042] This application embodiment sets a load compensation structure including multiple load compensation units arranged along a first direction. By setting load compensation units, the size of the non-display area of ​​the display panel can be reduced, which is beneficial to achieving a narrow bezel. At the same time, the output terminal of each first shift register is electrically connected to two or more rows of pixels, and the output terminal of each second shift register is electrically connected to two or more load compensation units, which can relatively reduce the number of shift registers, thereby reducing the layout difficulty of electrical components and wiring in the display panel.

[0043] In some embodiments, such as Figure 6The output of the i-th first shift register 501 can be electrically connected to the (i+2)-th row pixel and the i-th row pixel respectively through the first scan line S1 and the second scan line S2. The output of the j-th second shift register can be electrically connected to the (j+2)-th load compensation unit and the j-th load compensation unit respectively through the first scan line S1 and the second scan line S2, where i≤n and j≤m. Here, the output of the (n-1)-th first shift register 501 can be electrically connected to the (n-1)-th row pixel and the first load compensation unit through the second scan line S2. The output of the n-th first shift register 501 can be electrically connected to the n-th row pixel and the second load compensation unit through the second scan line S2.

[0044] In some embodiments, such as Figure 7 As shown, Figure 7 A schematic diagram of another exemplary gate driving circuit provided in the embodiments of this application, in which... Figure 7 In the gate driving circuit shown, the output terminal of the i-th first shift register 501 can be electrically connected to the (i+1)-th row pixel and the i-th row pixel respectively through the first scan line S1 and the second scan line S2, and the output terminal of the j-th second shift register can be electrically connected to the (j+1)-th load compensation unit and the j-th load compensation unit respectively through the first scan line S1 and the second scan line S2, where i≤n, j≤m. Figure 7 The output of the i-th shift register can be electrically connected to the input of the (i+1)-th shift register.

[0045] This application embodiment sets the output terminal of the i-th first shift register to electrically connect the pixels in the i-th row and the (i+1)-th row, and the output terminal of the j-th second shift register to electrically connect the j-th load compensation unit and the (j+1)-th load compensation unit; or sets the output terminal of the i-th first shift register to electrically connect the pixels in the i-th row and the (i+2)-th row, and the output terminal of the j-th second shift register to electrically connect the j-th load compensation unit and the (j+2)-th load compensation unit. This enables the scan signal SCAN output by the i-th first shift register to control the data writing in the data circuit of the i-th row pixel and the reset of the first node in the circuit of the (i+1)-th or (i+2)-th row pixel, allowing the pixel circuit in the display panel to achieve normal data writing and the reset of the first node, and enabling the display panel to emit light normally. At the same time, setting the loading of the second shift register to be consistent with that of the first shift register can improve the brightness uniformity of the display panel.

[0046] In some embodiments, k≥3, each of the first shift registers 501 and each of the second shift registers 502 can output more than 3 valid pulses within a frame time. Each valid pulse can be used to write the data signal of the N1 node of the pixel circuit in one row of pixels and to reset the N1 node of the pixel circuit in another row of pixels.

[0047] like Figure 8 , Figure 8 This is a timing diagram of an exemplary shift register. Figure 8 The timing diagrams of the scan signals at different times are shown, as follows: Figure 8 Within one frame, the scan signal SCAN501 output by each first shift register 501 and the scan signal SCAN502 output by each second shift register can include more than three valid pulses.

[0048] This application embodiment, by setting the first shift register and the second shift register to output more than 3 valid pulses within one frame, can still achieve uniform brightness display of the display panel even under multiple pulse counts.

[0049] In some embodiments, such as Figure 9 As shown, Figure 9 A schematic diagram of another gate driving circuit provided in an embodiment of this application is shown below. Figure 9 The first clock signal line CK may include a first sub-clock signal line CK1 and a second sub-clock signal line CK2, and the second clock signal line XCK may include a third sub-clock signal line XCK1 and a fourth sub-clock signal line XCK2. The number of the second shift registers may correspond to the number of clock signal lines.

[0050] In some embodiments, the number of second shift registers satisfies the following condition:

[0051] m=z1×k-2 (1)

[0052] Where z1 is the number of clock signal lines, z1 = 4; or,

[0053] m=z2×k-1 (2)

[0054] Where z2 is the number of clock signal lines, z2 = 2.

[0055] In such Figure 9 In the gate drive circuit shown, the number of clock signal lines is 4, and the number of second shift registers satisfies m = z1 × k - 2. For example, when the number of effective pulses k is 3, the number of the above-mentioned second shift registers 502 can be 10.

[0056] In such Figure 6 In the gate drive circuit shown, the number of clock signal lines is 2, and the number of second shift registers satisfies m = z2 × k - 1. For example, when the number of effective pulses k is 3, the number of the second shift registers 502 can be 5.

[0057] In such Figure 7 In the gate drive circuit shown, the number of second shift registers can satisfy m = z²k⁻¹. It is conceivable that, for the different numbers of second shift registers mentioned above, the number of load compensation units can be set to be the same as the number of second shift registers.

[0058] It is conceivable that with each additional second shift register and its corresponding electrically connected load compensation unit, the width of the non-display area in the first direction may increase by about 5μm.

[0059] This application embodiment improves the brightness uniformity of the display panel by setting the number of second shift registers, which is related to the number of clock signal lines and the number of effective pulses. This allows for the design of different numbers of second shift registers for gate drive circuits under different conditions.

[0060] In some embodiments, such as Figure 10 As shown, Figure 10 This is a schematic diagram of an exemplary load compensation structure, such as... Figure 10 The load compensation structure includes a trace 901 and a conductive block 902. The trace 901 is electrically connected to the output of the second shift register 502. The conductive block 902 can be electrically connected to a fixed voltage signal terminal. In some examples, the fixed voltage signal terminal can be a PVDD terminal electrically connected to the driving module in the pixel circuit. The fixed voltage signal terminal can also be other signal terminals, such as the PVEE terminal connected to the cathode of the light-emitting device. Figure 10 The traces and conductive blocks at least partially overlap in the thickness direction of the display panel.

[0061] In some embodiments, the above-mentioned trace 901 and conductive block 902 can be disposed on any two different film layers. For example, the above-mentioned trace 901 can be disposed on the same layer as the first electrode plate of the storage capacitor in the pixel circuit, and the above-mentioned conductive block 902 can be disposed on the same layer as the second electrode plate of the storage capacitor, wherein the second electrode plate is far away from the substrate relative to the first electrode plate.

[0062] This application embodiment sets up a load compensation structure including traces and conductive blocks. The traces are electrically connected to the output terminal of the second shift register, and the conductive blocks are electrically connected to the voltage signal terminal. The traces and conductive blocks overlap at least partially in the thickness direction of the display panel, thus forming a load compensation structure. The load compensation structure can reduce the width of the load compensation structure in the first direction and reduce the size of the non-display area.

[0063] In some embodiments, such as Figure 10 As shown, the traces include m signal lines arranged along a first direction. These signal lines may include a first scan line S1 and a second scan line S2, as shown below. Figure 10 Each signal line can be electrically connected to the output of at least one second shift register 502, and the conductive block 902 and the m signal lines at least partially overlap in the thickness direction of the display panel.

[0064] In this embodiment, a load compensation structure is formed by at least partial overlap of m signal lines and conductive blocks in the thickness direction of the display panel. This load compensation structure compensates for the loading of the first shift register, thereby improving the uniformity of the display brightness of the display panel.

[0065] In some embodiments, such as Figure 10 As shown, the conductive block 902 includes a plurality of conductive units 9021 arranged along the second direction. The plurality of conductive units 9021 can be electrically connected to a fixed voltage signal terminal. Each conductive unit overlaps at least partially with m signal lines in the thickness direction of the display panel.

[0066] This application embodiment, by setting the conductive block to include multiple conductive units, can flexibly control the load size of the load compensation structure by the number of conductive units, thereby improving the brightness uniformity of the display panel.

[0067] In some embodiments, the overlap area between a conductive unit 9021 and a signal line is smaller than the overlap area between the two plates of the storage capacitor. By setting the overlap area between a conductive unit and a signal line to be smaller than the overlap area between the two substrates of the storage capacitor, the loading of the shift register can be flexibly adjusted by adjusting the overlap area between the conductive unit and the signal line, so that the loading of the first shift register remains consistent, thereby improving the display uniformity of the display panel.

[0068] In some embodiments, such as Figures 5-9As shown, multiple shift registers can be arranged along a first direction. The height of the second shift register 502 in the first direction is less than or equal to the height of the first shift register 501 in the first direction; the width of the second shift register 502 in the second direction is less than or equal to the width of the first shift register 501 in the second direction. In some examples, the second shift register 502 can be set to the same size as the first shift register 501. For example, the height of the second shift register 502 in the first direction can be equal to the height of the first shift register 501 in the first direction; the width of the second shift register 502 in the second direction can be equal to the width of the first shift register 501 in the second direction.

[0069] This application embodiment reduces the size of the second display area and achieves a narrow bezel for the display panel by setting the height of the second shift register in the first direction to be less than or equal to the height of the first shift register in the first direction, and setting the width of the second shift register in the second direction to be less than or equal to the width of the first shift register in the second direction.

[0070] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 11 , Figure 11 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 11 The provided display device 1000 includes the display panel 400 provided in any of the above embodiments of this application. Figure 11 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 400 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 400 in the above embodiments. These descriptions will not be repeated here.

[0071] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0072] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0073] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0074] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0075] It should also be noted that the exemplary embodiments mentioned in this application describe methods or apparatuses based on a series of steps or devices. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0076] The aspects of this application have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this application. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0077] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: The display area includes multiple rows of pixels; The non-display area includes a gate driving circuit, which includes multiple cascaded shift registers, and the shift registers are electrically connected to the clock signal line. The plurality of shift registers includes n first shift registers and m second shift registers. The trigger signal terminal of the first first shift register is electrically connected to the driver chip, and the output terminal of the nth first shift register is electrically connected to the trigger signal terminal of the first second shift register. The output of the first shift register is electrically connected to the pixel, and the output of the second shift register is electrically connected to the load compensation structure. Within one frame, the number of valid pulses output by the shift register is k, where m > k; The load compensation structure includes a plurality of load compensation units arranged along a first direction. The output terminal of each first shift register is electrically connected to the corresponding x rows of pixels, and the output terminal of each second shift register is electrically connected to y load compensation units, where x is an integer greater than or equal to 2, y is an integer greater than or equal to 2, and x = y. The load compensation structure includes a trace and a conductive block. The trace is electrically connected to the output terminal of the second shift register, and the conductive block is electrically connected to a fixed voltage signal terminal. The trace and the conductive block at least partially overlap in the thickness direction of the display panel.

2. The display panel according to claim 1, characterized in that, x = 2, y = 2, the output terminal of the i-th first shift register is electrically connected to the pixels in the i-th row and the (i+1)-th row, and the output terminal of the j-th second shift register is electrically connected to the j-th load compensation unit and the (j+1)-th load compensation unit. or, x = 2, y = 2, the output of the i-th first shift register is electrically connected to the i-th row pixel and the (i+2)-th row pixel, and the output of the j-th second shift register is electrically connected to the j-th load compensation unit and the (j+2)-th load compensation unit.

3. The display panel according to claim 1, characterized in that, k≥3。 4. The display panel according to claim 2, characterized in that, The number of the second shift registers satisfies the following condition: m = z1 × k - 2; Where z1 is the number of clock signal lines, z1 = 4; or, m = z² × k⁻¹; Where z2 is the number of clock signal lines, z2 = 2.

5. The display panel according to claim 1, characterized in that, The traces include m signal lines arranged along a first direction, each of which is electrically connected to the output of at least one second shift register. The conductive block and the m signal lines at least partially overlap in the thickness direction of the display panel.

6. The display panel according to claim 5, characterized in that, The conductive block includes a plurality of conductive units arranged along the second direction. The plurality of conductive units are electrically connected to the fixed voltage signal terminal. Each conductive unit overlaps at least partially with m signal lines in the thickness direction of the display panel.

7. The display panel according to claim 6, characterized in that, The overlap area between one of the conductive units and one of the signal lines is smaller than the overlap area between the two plates of the storage capacitor.

8. The display panel according to claim 1, characterized in that, The plurality of shift registers are arranged along a first direction, wherein the height of the second shift register in the first direction is less than or equal to the height of the first shift register in the first direction; and the width of the second shift register in the second direction is less than or equal to the width of the first shift register in the second direction.

9. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 8.

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