Pixel circuit, display panel and display device

Abstract

The invention discloses a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving transistor and at least one switching transistor, the driving transistor comprises a first active layer, a first grid electrode arranged on the first side of the first active layer and a second grid electrode arranged on the first active layer and far away from the first side; the at least one switching transistor comprises a second active layer, a third grid electrode arranged on the first side of the second active layer and a fourth grid electrode arranged on the second active layer and far away from the first side; wherein the first active layer and the second active layer are arranged on the same layer; the first grid serves as a control end of the driving transistor; the fourth grid serves as a control end of the switching transistor; the second gate is used for receiving a first constant potential; the third gate is configured to receive a second constant potential. According to the technical scheme provided by the invention, the performance of the display panel is improved while the process of the display panel is simplified.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) refers to the phenomenon that luminescent materials emit light through carrier injection and recombination under the drive of electric field. Compared with liquid crystal display (LCD) devices, organic light-emitting display devices are lighter and thinner, have better viewing angle and contrast, etc., and therefore have attracted widespread attention.

[0003] Low Temperature Polycrystalline Oxide (LTPO) display panel is a combination of low temperature polycrystalline silicon (LTPS) technology and indium gallium zinc oxide (IGZO) technology in organic light emitting display (OLED) panel. However, the above combination makes the display panel process more complicated, and there are requirements for the compatibility of the display panel, which increases the production cost of the display panel. Summary of the invention

[0004] Embodiments of the present invention provide a pixel circuit, a display panel and a display device, so as to simplify the display panel process and improve the display panel performance.

[0005] In a first aspect, an embodiment of the present invention provides a pixel circuit, comprising: a driving transistor and at least one switching transistor;

[0006] The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side;

[0007] At least one of the switch transistors comprises a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side;

[0008] Among them, the first active layer and the second active layer are arranged in the same layer; the first gate serves as the control end of the driving transistor; the fourth gate serves as the control end of the switching transistor; the second gate is used to receive a first constant potential; and the third gate is used to receive a second constant potential.

[0009] In a second aspect, an embodiment of the present invention provides a pixel circuit, comprising: a driving transistor and at least one switching transistor;

[0010] The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side;

[0011] At least one of the switch transistors comprises a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side;

[0012] Among them, the first active layer and the second active layer are arranged in the same layer; the first gate serves as the control end of the driving transistor; the second gate is used to receive a third constant potential; the third gate and the fourth gate serve as the control ends of the switching transistor.

[0013] In a third aspect, an embodiment of the present invention provides a pixel circuit, comprising: a driving transistor and at least one switching transistor;

[0014] The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side;

[0015] At least one of the switch transistors comprises a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side;

[0016] Among them, the first active layer and the second active layer are arranged in the same layer; the first gate and the second gate serve as control terminals of the driving transistor; the fourth gate serves as the control terminal of the switching transistor; and the third gate is used to receive a fourth constant potential.

[0017] In a fourth aspect, an embodiment of the present invention further provides a display panel, comprising the pixel circuit provided by any embodiment of the present invention.

[0018] In a fifth aspect, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0019] In the present invention, the pixel circuit includes a driving transistor and at least one switching transistor, the driving transistor includes a first active layer, and a first gate and a second gate on opposite sides of the first active layer; the switching transistor includes a second active layer, and a third gate and a fourth gate on opposite sides of the second active layer. The first active layer and the second active layer are arranged in the same layer, the first gate and the third gate are arranged on the same side, and the second gate and the fourth gate are arranged on the same side. In this embodiment, at least one of the first gate and the second gate can be used as the control end of the driving transistor, and at least one of the third gate and the fourth gate can be used as the control end of the switching transistor. The control mode of the control end of the driving transistor is different from the control mode of the control end of the switching transistor to achieve different electrical properties, so that the switching transistor has a high mobility characteristic and the driving transistor has strong stability. In this embodiment, only one layer of full oxide active layer is set, which can take into account the stability of the driving transistor and the high mobility of the switching transistor. In this embodiment, there is no need to set multiple active layers to simultaneously integrate LTPS technology and IGZO technology to meet different electrical properties, simplify the process flow of the display panel, greatly reduce the process cost, and increase the circuit layout space. In addition, compared with the LTPO process, this embodiment itself is not easily affected by water vapor, etc., which reduces the difficulty of the process and facilitates the realization of mass production requirements of display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of an LTPO display panel provided in an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0024] Figure 5 A circuit diagram of a pixel circuit provided by an embodiment of the invention;

[0025] Figure 6 for Figure 5 Schematic diagram of the layout of the pixel circuit;

[0026] Figure 7 for Figure 5 A schematic diagram of the cross-sectional structure of the pixel circuit along line segment a-a';

[0027] Figure 8 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0028] Fig. 9 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0029] Fig.10 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0030] Fig.11 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0032] An embodiment of the present invention provides a pixel circuit, such as Figure 1 As shown, Figure 1 A schematic diagram of a pixel circuit provided by an embodiment of the present invention includes: a driving transistor T1 and at least one switching transistor T2;

[0033] The driving transistor T1 includes a first active layer 11, a first gate 12 disposed on a first side of the first active layer 11, and a second gate 13 disposed on the first active layer 11 away from the first side.

[0034] At least one switch transistor T2 includes a second active layer 14, a third gate 15 disposed on a first side of the second active layer 14, and a fourth gate 16 disposed on the second active layer 14 away from the first side;

[0035] Among them, the first active layer 11 and the second active layer 14 are arranged in the same layer; the first gate 12 serves as the control end of the driving transistor T1; the fourth gate 16 serves as the control end of the switching transistor T2; the second gate 13 is used to receive the first constant potential V1; the third gate 15 is used to receive the second constant potential V2.

[0036] In an embodiment of the present invention, a pixel circuit includes a driving transistor and at least one switching transistor, wherein the driving transistor includes a first active layer, and a first gate and a second gate on opposite sides of the first active layer; and the switching transistor includes a second active layer, and a third gate and a fourth gate on opposite sides of the second active layer. The first active layer and the second active layer are arranged in the same layer, the first gate and the third gate are arranged on the same side, and the second gate and the fourth gate are arranged on the same side. In this embodiment, at least one of the first gate and the second gate can be used as the control end of the driving transistor, and at least one of the third gate and the fourth gate can be used as the control end of the switching transistor. The control mode of the control end of the driving transistor is different from the control mode of the control end of the switching transistor to achieve different electrical properties, so that the switching transistor has the characteristics of high mobility and the driving transistor has strong stability. In this embodiment, only one layer of full oxide active layer is provided, which can take into account the stability of the driving transistor and the high mobility of the switching transistor. In this embodiment, there is no need to provide multiple active layers to simultaneously integrate LTPS technology and IGZO technology to meet different electrical properties, simplify the process flow of the display panel, greatly reduce the process cost, and increase the circuit layout space. In addition, compared with the LTPO process, this embodiment itself is not easily affected by water vapor, etc., which reduces the difficulty of the process and facilitates the realization of mass production requirements of display panels.

[0037] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The pixel circuit includes a driving transistor T1 and at least one switching transistor T2. The driving transistor T1 is used to generate a driving current for driving the corresponding light emitting element 111, and the switching transistor T2 is used to control the gate voltage and the source and drain voltage of the driving transistor T1 to control the magnitude of the driving current output by the driving transistor T1. Figure 1As shown, the display panel includes a substrate 31 and a pixel circuit and a light-emitting element 111 sequentially arranged on the substrate 31. The driving transistor T1 includes a first active layer 11, a first gate 12 on a first side of the first active layer 11, and a second gate 13 of the first active layer 11 away from the first side. That is, the driving transistor T1 includes two gates respectively arranged on opposite sides of the first active layer 11. Similarly, the switching transistor T2 includes a second active layer 14, a third gate 15 on a first side of the second active layer 14, and a third gate 15 on the second active layer 14 away from the first side. The switching transistor T2 includes two gates respectively arranged on opposite sides of the second active layer 14. In this embodiment, the first side of the first active layer 11 can be a side close to the substrate 31 or a side away from the substrate 31. This embodiment does not specifically limit this. For example, Figure 1 The first side is the side of the first active layer 11 and the second active layer 14 close to the substrate 31. Figure 1 As shown, the first active layer 11 and the second active layer 14 are arranged in the same active layer and are made by the same process, then the first gate 12 and the third gate 15 are arranged on the same side of the active layer, and the second gate 13 and the fourth gate 16 are arranged on the same side of the active layer. Optionally, in this embodiment, the active layer can be a full oxide layer, and the full oxide layer can realize electrical regulation or optimize the device during the adjustment process of the two gate potentials of the transistor, so as to realize the compatibility of transistors with different performances in the same display panel. Specifically, the potential control method of the two gates of the driving transistor T1 is different from the potential control method of the two gates of the switching transistor T2. In addition, the display panel may also include a source-drain layer 17, and the source-drain layer 17 can connect adjacent transistors to realize the transmission of current signals.

[0039] Optionally, the first gate 12 is used as the control terminal of the driving transistor T1, and the second gate 13 is connected to the first constant potential V1; the fourth gate 16 is used as the control terminal of the switch transistor T2, and the third gate 15 is connected to the second constant potential V2. For the driving transistor T1, with the first gate 12 as the control terminal, the first constant potential V1 of the second gate 13 affects the first active layer 11, and can significantly change the subthreshold swing of the first active layer 11. In this embodiment, the subthreshold swing of the first active layer 11 is increased by the first constant potential V1. The subthreshold swing represents the change in the voltage value of the control terminal required for the source-drain current (driving current) of the driving transistor T1 to change ten times. When the subthreshold swing is larger, if the voltage value of the control terminal fluctuates slightly, the driving current generated by the driving transistor T1 will not be greatly disturbed, and the stability is relatively strong. Especially in the low grayscale display screen, the driving force of the driving transistor T1 is strong, the screen is stable and the display effect is good. For the switching transistor T2, the second constant potential V2 of the third gate 15 can control the speed at which the carriers of the second active layer 14 form an inversion layer, and increase the speed at which the carriers move in the electric field, so that the switching transistor T2 has high mobility, improves conductivity, and achieves a smaller subthreshold swing.

[0040] This embodiment only has one active layer, and by providing a dual gate for each transistor, the gates of the driving transistor T1 and the switching transistor T2 are controlled in different ways, thereby adjusting the electrical performance of the devices of different transistors. This embodiment uses fewer film layers and a simple film layer process, which can simultaneously ensure the different device performances of the driving transistor T1 and the switching transistor T2. Figure 2 A schematic diagram of the structure of the LTPO display panel provided by an embodiment of the present invention. In the prior art, in order to simultaneously accommodate the different device performances of the driving transistor and the switching transistor, the LTPO manufacturing process is adopted, such as Figure 2As shown, a transistor T1' made by LTPO process, a transistor T2' made by IGZO process and a light-emitting element 111' are arranged on the substrate 11'. The active layer 12' of the transistor T1' is low-temperature polysilicon. In order to increase the subthreshold swing, a larger width-to-length ratio needs to be set. The active layer 13' of the transistor T2' is indium gallium zinc oxide, which has a higher carrier mobility. The LTPO display panel needs to be provided with two active layers of different materials, which is difficult to process and has high compatibility requirements for hybrid devices, resulting in increased costs. Each pixel circuit will occupy a large layout space, thereby increasing the difficulty of further development of the display panel. In addition, because LTPO needs to take into account the performance of IGZO and LTPS devices at the same time, the electrical properties of the IGZO device itself are easily affected by water vapor, and the performance requirements for the process edge are high. In order to ensure low grayscale visual effects and uniformity of the picture, LTPS needs to increase the width-to-length ratio of the driving transistor, further increase the layout space of the pixel circuit, and affect the PPI of the display panel. This embodiment adopts a film structure with a simple structure and little structural change, and is compatible with the different device performances of the driving transistor T1 and the switching transistor T2. Compared with the LTPO process, the process flow of this embodiment is simplified, and the driving transistor T1 does not need to be set with a large width-to-length ratio, which reduces the layout space and simplifies the difficulty of device development. In addition, the sensitivity of the switching transistor T2 is not high and the stability is strong. This embodiment can also autonomously adjust the electrical properties of the device through the first constant potential V1 and the second constant potential V2 to achieve different display requirements.

[0041] Optionally, the materials of the first active layer 11 and the second active layer 14 can both be oxides of a set metal; the set metal includes at least one of the following: gallium, hafnium, tin, lanthanum, indium, praseodymium and zinc. With the gradual maturity of LTPO technology, this embodiment uses a full oxide process to reduce costs. The full oxide is an oxide of a set metal. The set metal may include rare metals such as tin and hafnium, or rare earth metals such as lanthanum and praseodymium, or may include scattered metals such as gallium and indium, or may also include more widely used metal elements such as zinc, to form the first active layer 11 and the second active layer 14 of full oxide, without the need to set an active layer of low-temperature polysilicon material, effectively simplifying the process flow of the pixel circuit.

[0042] Figure 3A schematic diagram of another pixel circuit structure provided by an embodiment of the present invention. Optionally, the first active layer 11 and the second active layer 14 may include a first oxide layer 21 and a second oxide layer 22; the first oxide is disposed on the side of the second oxide layer 22 close to the first gate 12 or the third gate 15; the mobility of the carriers of the first oxide layer 21 is less than the mobility of the carriers of the second oxide layer 22. In this embodiment, the first active layer 11 and the second active layer 14 may include a double-layer oxide: a first oxide layer 21 and a second oxide layer 22, and the first oxide layer 21 and the second oxide layer 22 may be provided with different electrical properties. Exemplarily, because the first oxide layer 21 is disposed on the first side of the active layer, close to the control terminal of the driving transistor T1, the first oxide layer 21 may be provided as a semiconductor layer with low mobility and strong stability to meet the device performance of the driving transistor T1; because the second oxide layer 22 is disposed on the side of the active layer away from the first side, close to the control terminal of the switching transistor T2, the second oxide layer 22 may be provided as a semiconductor layer with high mobility and weak stability to meet the device performance of the switching transistor T2. Optionally, in the second oxide layer 22, the content of metal elements such as gallium, tin, lanthanum and hafnium is relatively high to achieve a lower carrier mobility. In addition, the double-layer full oxide layer can further amplify the advantages brought by the structural change. For example, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be adjusted to further adjust the performance of each device.

[0043] Optionally, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 may be in the range of 3:1 to 1:1. The mobility and stability of the entire active layer may be adjusted by adjusting the thickness ratio of the first oxide layer 21 and the second oxide layer 22. In this embodiment, it is necessary to reduce the width-to-length ratio of the driving transistor T1 while ensuring the stability of the driving transistor T1. In this embodiment, the first oxide layer 21 closer to the driving transistor T1 may be provided with a thicker film layer. Because in the LTPS process, it is necessary to increase the subthreshold swing by increasing the width-to-length ratio, which will increase the layout space of the pixel circuit and affect the PPI of the display panel. In this embodiment, it is only necessary to increase the thickness of the first oxide layer 21 to increase the subthreshold swing of the entire active layer, and the first oxide layer 21 is located on one side close to the control end of the driving transistor T1. The first oxide layer 21 serves as the main driving layer of the driving transistor T1, further increasing the stability of the driving transistor T1. The second oxide layer 22 is provided close to the control end of the switching transistor T2. The second oxide layer 22 serves as the main driving layer of the switching transistor T2, which increases the stability of the driving transistor T1 while maintaining the high mobility characteristics of the switching transistor T2.

[0044] Optionally, the first oxide layer 21 may include indium oxide, gallium oxide and zinc oxide; the second oxide layer 22 may include indium oxide, gallium oxide, zinc oxide and tin oxide. In this embodiment, the first oxide layer 21 includes indium oxide, gallium oxide and zinc oxide, and the target material is formed by sintering three oxide powders, which can be called IGZO; the second oxide layer 22 includes indium oxide, gallium oxide, zinc oxide and tin oxide, and the target material is formed by sintering four oxide powders, which can be called IGZTO. Compared with the first oxide layer 21, the second oxide layer 22 has an additional tin oxide, thereby improving the carrier mobility of the second oxide layer 22. When the first oxide layer 21 is made of IGZO material and the second oxide layer 22 is made of IGZTO material, optionally, the thickness ratio of the first oxide layer 21 to the second oxide layer 22 can be 2:1, so that the first oxide layer 21 meets the performance requirement of the high subthreshold swing of the driving transistor T1, and the second oxide layer 22 meets the performance requirement of the high mobility of the switching transistor T2. Only one active layer is provided to be compatible with the electrical performance of different transistor devices. In addition, both the driving transistor T1 and the switching transistor T2 can maintain a small width-to-length ratio, thereby reducing the occupied area of ​​the pixel circuit and improving the PPI of the display panel.

[0045] Of course, the first oxide layer 21 and the second oxide layer 22 can also be other materials. Exemplarily, the first oxide layer 21 can be a praseodymium (Pr)-doped oxide (ITZO) system containing indium, tin and zinc, that is, ITZO:Pr. The above materials have excellent light stability, but low mobility. The second active layer 14 can also be ITZO with a higher indium content (In-rich ITZO). The mobility of the In-rich ITZO material is high, but the light stability is poor. Therefore, the above two materials form a coupling relationship between mobility and stability. ITZO:Pr forms an auxiliary photoelectron relaxation (Carrier Relaxation Layer, CRL), and In-rich ITZO forms a carrier transport layer (Carrier Transport Layer, CTL). When the active layer includes the first oxide layer 21 and the second oxide layer 22, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be adjusted, as shown in Table 1. Table 1 is a parameter table of the thickness ratio of the first oxide layer and the second oxide layer. The total thickness of the first oxide layer 21 and the second oxide layer 22 can be set to 30 nm. The thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be respectively defined, and the mobility μ FE and the threshold voltage offset △Vth under negative bias light stress NBIS. Specifically, as shown in Table 1, when the 30nm active layer structure is all ITZO:Pr, the mobility μ FEis 16.2, the threshold voltage offset △Vth is -0.71, the carrier mobility is low, the threshold voltage offset is small, and the stability is excellent; when the CTL thickness is 5nm and the CRL thickness is 25nm in the 30nm active layer structure, the mobility μ FE is 27.2, the threshold voltage offset △Vth is -1.56, the carrier mobility gradually increases, the threshold voltage offset gradually increases, and the stability decreases; similarly, when the CTL thickness is 10nm and the CRL thickness is 20nm in the 30nm active layer structure, the mobility μ FE is 36.4, and the threshold voltage offset △Vth is -1.12; when the CTL thickness is 15nm and the CRL thickness is 15nm in the 30nm active layer structure, the mobility μ FE is 43.3, and the threshold voltage offset △Vth is -1.70; when the CTL thickness is 20nm and the CRL thickness is 10nm in the 30nm active layer structure, the mobility μ FE is 50.1, and the threshold voltage offset △Vth is -9.13; when the 30nm active layer structure is all In-rich ITZO (CRL), its mobility μ FE The value is 51.6, and the threshold voltage offset △Vth is greater than -15. It can be seen that when the CTL thickness increases, the mobility is high. When the thickness ratio of CTL and CRL reaches 20 / 10, it is close to the level of all In-rich ITZO, but at this time the proportion of CRL is small and cannot meet the stability requirements of NBIS.

[0046] Table 1: Thickness ratio parameter table of the first oxide layer and the second oxide layer

[0047]

[0048]

[0049] Based on the above Table 1, this embodiment continues to increase the thickness of CRL to form Table 2, which is a parameter table of the thickness ratio of the first oxide layer and the second oxide layer after adjustment. Since the CTL achieves a higher mobility at a thickness of 20nm, the thickness of the CTL can be kept at 20nm and the thickness of the CRL can be further increased. As can be seen from Table 1, when the thickness of the CTL is 20nm and the thickness of the CRL is 10nm, the mobility μ FE is 50.1, and the threshold voltage offset △Vth is -9.13. Referring to Table 2, the CTL thickness is 20nm, and the CRL thickness is 20nm, then its mobility μ FE is 47.1, the threshold voltage offset △Vth is -4.66; the CTL thickness is 20nm, the CRL thickness is 30nm, then its mobility μFE is 46.8, and the threshold voltage offset ΔVth is -1.56. As can be seen from Table 2, keeping the CTL thickness unchanged and increasing the CRL thickness ratio, the mobility does not change much, but the stability of NBIS becomes better. In this embodiment, if the first oxide layer 21 is CRL and the second oxide layer 22 is CTL, the thickness of the first oxide layer 21 can be set to 30nm and the thickness of the second oxide layer 22 can be set to 20nm, which can meet the high subthreshold swing requirements of the driving transistor T1 and the high mobility requirements of the switching transistor T2.

[0050] Table 2: Parameter table of the thickness ratio of the first oxide layer and the second oxide layer after adjustment

[0051] CTL / CRL <![CDATA[μ FE (cm 2 / Vs)]]> NBIS△Vth(V) 20 / 10 50.1 -9.13 20 / 20 47.1 -4.66 20 / 30 46.8 -1.56

[0052] Continue to refer Figure 1 Optionally, the display panel where the pixel circuit is located may include at least a stacked substrate 31, a first metal layer 32, an active layer 33, and a second metal layer 34; the first active layer 11 and the second active layer 14 are both arranged in the active layer 33; the first gate 12 and the third gate 15 are arranged in the first metal layer 32; the fourth gate 16 and the second gate 13 are arranged in the second metal layer 34. In this embodiment, the pixel circuit includes a first metal layer 32, an active layer 33, and a second metal layer 34 arranged away from the substrate 31 in sequence, the active layer 33 is provided with the first active layer 11 and the second active layer 14, the first metal layer 32 is provided with the first gate 12 and the third gate 15, and the second metal layer 34 is provided with the fourth gate 16 and the second gate 13. Of course, in other embodiments of the present invention, such as Figure 4 As shown, Figure 4A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present invention, wherein the first gate 12 and the third gate 15 can also be arranged on the second metal layer 34, and the fourth gate 16 and the second gate 13 can be arranged on the first metal layer 32. In this embodiment, only the three-layer structure of the first metal layer 32, the active layer 33 and the second metal layer 34 can achieve compatibility with transistors with different electrical characteristics, and the process flow is more simplified than the LTPO process, thereby improving the mass production efficiency of the display panel. In addition, the active layer 33 can be a double-layer structure, further amplifying the advantages brought by the structural change and achieving performance adjustment. In addition, the thickness ratio of the double-layer structure can further adjust the device performance to meet the performance requirements of different types of transistors. For example, when the double-layer structure is a first oxide layer 21 with low mobility and a second oxide layer 22 with high mobility, the first gate 12 close to the first oxide layer 21 is used as the control end of the driving transistor, and the fourth gate 16 close to the second oxide layer 22 is used as the control end of the switching transistor. For the driving transistor, it is bottom-gate driven, and the top gate inputs a constant potential, which can greatly increase the subthreshold swing, improve stability, and ensure low grayscale display performance. On this basis, by setting the first oxide layer 21 to have a low mobility, the stability is further increased. For the switching transistor, it is top-gate driven, and the bottom gate inputs a constant potential, ensuring a smaller aspect ratio, achieving a smaller subthreshold swing, and achieving high mobility. By adjusting the bottom gate constant potential, the electrical properties can be adjusted autonomously and the device stability can be optimized.

[0053] Optionally, the value range of the first constant potential V1 can be 0V to 1.5V; the value range of the second constant potential V2 can be -3V to 0V. In the dual-gate structure, if one of the gates is used as the control terminal, the other gate can be used as the auxiliary control terminal. The constant potential connected to the auxiliary control terminal can be set according to the needs. Different constant potentials have different auxiliary effects. The first gate 12 of the driving transistor T1 is the control terminal, and the second gate 13 is connected to a constant voltage of 0V to 1.5V as an auxiliary control terminal. The fourth gate 16 of the switching transistor T2 is the control terminal, and the third gate 15 is connected to a constant voltage of -3V to 0V as an auxiliary control terminal. And because the second gate 13 is a top gate structure, the first constant potential V1 connected to the second gate 13 can achieve fine control of the control terminal of the driving transistor T1. The third gate 15 is a bottom gate structure, and the second constant potential V2 connected to the third gate 15 is used to control the switching speed and stability of the switching transistor T2.

[0054] Optionally, the first constant potential V1 and the second constant potential V2 may be the same, so that the second gate 13 of the driving transistor T1 and the third gate 15 of the switch transistor T2 may share a signal line to obtain a constant potential, thereby reducing the wiring density of the display panel and further increasing the layout space of the display panel.

[0055] Optionally, the second constant potential V2 can be reused as a reference voltage signal Vref in the pixel circuit. Because the value range of the second constant potential V2 can preferably be -3V to 0V, the second constant potential V2 in this embodiment can be reused as a reference voltage signal Vref in the pixel circuit to further reduce panel wiring and reduce panel power consumption. However, the thickness of the gate insulating layer between the top gate and the active layer is relatively thin. If the first constant potential V1 is connected to a negative value, it will have a greater impact on the threshold voltage of the driving transistor T1, which will reduce the stability of the driving transistor T1. Therefore, the driving transistor T1 of the driving transistor T1 is preferably a positive value to increase the subthreshold swing of the driving transistor T1, and the second constant potential V2 is preferably a negative value to increase the switching speed of the switching transistor T2. Optionally, both the driving transistor T1 and the switching transistor T2 can be N-type transistors. Because the active layer in this embodiment is a full oxide material, each transistor in the pixel circuit can be set as an N-type transistor.

[0056] Taking N-type transistor as an example, Figure 5 A circuit diagram of a pixel circuit provided by an embodiment of the invention, Figure 6 for Figure 5 Schematic diagram of the pixel circuit layout. Figure 7 for Figure 5 Schematic diagram of the cross-sectional structure of the pixel circuit along the line segment a-a'. Figures 5 to 7, optionally, the pixel circuit may further include: a storage capacitor Cst and a light emitting element 111; the switch transistor T2 includes: a first light emitting control transistor M1, a second light emitting control transistor M6, a first reset transistor M5, a second reset transistor M7, a threshold compensation transistor M4 and a data writing transistor M2; the control end of the first light emitting control transistor M1 is connected to the light emitting control signal EMIT; the first end of the first light emitting control transistor M1 is connected to the first power supply signal PVDD; the second end of the first light emitting control transistor M1 is electrically connected to the first end of the driving transistor T1; the control end of the driving transistor T1 is connected to the first power supply signal PVDD through the storage capacitor Cst; the second end of the driving transistor T1 is electrically connected to the first end of the second light emitting control transistor M6; the control end of the second light emitting control transistor M6 is used to connect to the light emitting control signal EMIT; the second end of the second light emitting control transistor M6 is electrically connected to the first electrode of the light emitting element 111, and the second electrode of the light emitting element 111 is connected to the second power supply signal signal PVEE; the control end of the first reset transistor M5 is connected to the first scanning signal SCAN1; the first end of the first reset transistor M5 is connected to the reference voltage signal Vref; the second end of the first reset transistor M5 is electrically connected to the control end of the driving transistor T1; the control end of the second reset transistor M7 is connected to the second scanning signal SCAN2; the first end of the second reset transistor M7 is connected to the reference voltage signal Vref; the second end of the second reset transistor M7 is electrically connected to the second end of the driving transistor T1; the control end of the threshold compensation transistor M4 is connected to the third scanning signal SCAN3; the first end of the threshold compensation transistor M4 is electrically connected to the control end of the driving transistor T1; the second end of the threshold compensation transistor M4 is electrically connected to the second end of the driving transistor T1; the control end of the data writing transistor M2 is connected to the fourth scanning signal SCAN4; the first end of the data writing transistor M2 is connected to the data signal Vdata; the second end of the data writing transistor M2 is electrically connected to the first end of the driving transistor T1.

[0057] This embodiment provides a schematic diagram of a 7T1C pixel circuit, which includes a driving transistor T1 and six switch transistors T2 (a first light-emitting control transistor M1, a second light-emitting control transistor M6, a first reset transistor M5, a second reset transistor M7, a threshold compensation transistor M4 and a data writing transistor M2). Figure 5 As shown, each transistor has a dual-gate structure. It should be noted that Figure 5In the dual-gate structure shown for each transistor, the gate with a darker grayscale is the top gate, and the gate with a lighter grayscale is the bottom gate. It can be seen that the bottom gate of the driving transistor T1 is the control terminal, and the top gate is connected to the first constant potential V1; the bottom gates of other switching transistors T2 are connected to the second constant potential V2, and the top gates serve as control terminals. The first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4 and the light-emitting control signal EMIT are used to control the light emission of the pixel circuit. Optionally, the third scan signal SCAN3 is multiplexed as the fourth scan signal SCAN4. And, as Figure 6 As shown, in order to further simplify the film layer arrangement of the display panel in this embodiment, the first constant potential V1 and the second constant potential V2 are set to be the same, and thus, only one constant potential transmission line 18 is required in this embodiment.

[0058] refer to Figure 6 and Figure 7 , which only shows the film layers of the substrate 31, the first metal layer 32, the active layer 33, the second metal layer 34 and the source and drain layer 17. In addition, Figure 6 The third metal layer 35 is also shown. The third metal layer 35 can be arranged on the side of the first metal layer 32 close to the substrate 31, or can be arranged between the source-drain layer 17 and the substrate 31, so that the first metal layer 32 can be electrically connected to the constant potential transmission line 18 of the third metal layer 35 through the jumper 19 on the source-drain layer 17. The first metal layer 32 can be provided with a first gate 12 and a third gate 15; the active layer 33 is provided with a first active layer 11 and a second active layer 14; the second metal layer 34 is provided with a second gate 13 and a fourth gate 16; the source-drain layer 17 can be provided with a data line 20 and a jumper 19 for outputting a data signal Vdata.

[0059] Figure 7 The driving transistor T1 and the switching transistor M5 are shown. The top gate (fourth gate 16) of the switching transistor M5 serves as the control terminal of the switching transistor M5, and the bottom gate (third gate 15) is used to access a constant voltage. The top gate (second gate 13) of the driving transistor T1 is connected to a constant voltage through a connecting line 171, and the bottom gate (first gate 12) serves as a control terminal and is electrically connected to the switching transistor M5. Figure 6 and Figure 7As shown, compared with the LTPO display panel, this embodiment changes the existing LTPO complex process flow through structural design, making the idea of ​​the full oxide active layer 33 possible. The top gate of the switch transistor is the control terminal, and the bottom gate is connected to a constant voltage. The advantage of this structure is that it can adjust the electrical properties and optimize the stability of the device independently; the bottom gate of the driving transistor T1 is the control terminal, and the top gate is connected to a constant voltage, which can greatly increase the subthreshold swing SS and ensure low grayscale performance. At the same time, the width-to-length ratio W / L of the driving transistor T1 is low, and a small-sized device can meet the performance requirements of the driving transistor T1. On this basis, the active layer 33 adopts a double-layer design (a high-mobility film layer combined with a low-mobility film layer), which can further amplify the advantages brought by the structural change, meet the requirements of the switch transistor for small W / L, small SS, and high mobility, and the requirements of the driving transistor for small W / L, large SS, and low mobility, and ensure high PPI. The film layer structure is simple, which greatly improves the layout space and simplifies the difficulty of device development. It is not easily affected by water vapor, etc., which reduces the process difficulty and facilitates the mass production requirements of the display panel.

[0060] Figure 8 A schematic diagram of another pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 8 As shown, in another embodiment of the present invention, the embodiment of the present invention further provides a pixel circuit, including:

[0061] A driving transistor T3 and at least one switching transistor T4; the driving transistor T1 includes a first active layer 112, a first gate 121 arranged on a first side of the first active layer 112, and a second gate 131 arranged on the first active layer 112 away from the first side; at least one switching transistor T4 includes a second active layer 141, a third gate 151 arranged on a first side of the second active layer 141, and a fourth gate 161 arranged on the second active layer 141 away from the first side; wherein the first active layer 112 and the second active layer 141 are arranged in the same layer; the first gate 121 serves as a control terminal of the driving transistor T3; the second gate 131 is used to receive a third constant potential V3; the third gate 151 and the fourth gate 161 serve as control terminals of the switching transistor T4.

[0062] In an embodiment of the present invention, a pixel circuit includes a driving transistor and at least one switching transistor, wherein the driving transistor includes a first active layer, and a first gate and a second gate on opposite sides of the first active layer; and the switching transistor includes a second active layer, and a third gate and a fourth gate on opposite sides of the second active layer. The first active layer and the second active layer are arranged in the same layer, the first gate and the third gate are arranged on the same side, and the second gate and the fourth gate are arranged on the same side. In this embodiment, the first gate can be used as the control end of the driving transistor, the second gate receives the fineness of the control end of the third constant potential control, and the third gate and the fourth gate are used as the control end of the switching transistor. The control mode of the control end of the driving transistor is different from the control mode of the control end of the switching transistor to achieve different electrical properties, so that the switching transistor has the characteristics of high mobility and the driving transistor has strong stability. In this embodiment, only one layer of full oxide active layer is set, which can take into account the stability of the driving transistor and the high mobility of the switching transistor. In this embodiment, there is no need to set multiple active layers to simultaneously integrate LTPS technology and IGZO technology to meet different electrical properties, simplify the process flow of the display panel, greatly reduce the process cost, and increase the circuit layout space. In addition, compared with the LTPO process, this embodiment itself is not easily affected by water vapor, etc., which reduces the difficulty of the process and facilitates the realization of mass production requirements of display panels.

[0063] Fig. 9 A schematic diagram of another pixel circuit provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, in another embodiment of the present invention, the embodiment of the present invention further provides a pixel circuit, including:

[0064] A driving transistor T5 and at least one switching transistor T6; the driving transistor T5 includes a first active layer 113, a first gate 122 arranged on a first side of the first active layer 113, and a second gate 132 arranged on the first active layer 113 away from the first side; at least one switching transistor T6 includes a second active layer 142, a third gate 152 arranged on a first side of the second active layer 142, and a fourth gate 162 arranged on the second active layer 142 away from the first side; wherein the first active layer 113 and the second active layer 142 are arranged in the same layer; the first gate 122 and the second gate 132 serve as control terminals of the driving transistor T5; the fourth gate 165 serves as a control terminal of the switching transistor T6; the third gate 152 is used to receive a fourth constant potential V4.

[0065] In an embodiment of the present invention, a pixel circuit includes a driving transistor and at least one switching transistor, wherein the driving transistor includes a first active layer, and a first gate and a second gate on opposite sides of the first active layer; and the switching transistor includes a second active layer, and a third gate and a fourth gate on opposite sides of the second active layer. The first active layer and the second active layer are arranged in the same layer, the first gate and the third gate are arranged on the same side, and the second gate and the fourth gate are arranged on the same side. In this embodiment, the first gate and the second gate can be used as the control end of the driving transistor, and the fourth gate can be used as the control end of the switching transistor. The third gate is connected to the fourth constant potential to control the switching speed and stability of the switching transistor. The control mode of the control end of the driving transistor is different from the control mode of the control end of the switching transistor to achieve different electrical properties, so that the switching transistor has the characteristics of high mobility and the driving transistor has strong stability. In this embodiment, only one layer of full oxide active layer is set, which can take into account the stability of the driving transistor and the high mobility of the switching transistor. In this embodiment, there is no need to set multiple active layers to simultaneously integrate LTPS technology and IGZO technology to meet different electrical properties, simplify the process flow of the display panel, greatly reduce the process cost, and increase the circuit layout space. In addition, compared with the LTPO process, this embodiment itself is not easily affected by water vapor, etc., which reduces the difficulty of the process and facilitates the realization of mass production requirements of display panels.

[0066] Based on the same idea, an embodiment of the present invention further provides a display panel, such as Fig.10 As shown, Fig.10 A schematic structural diagram of a display panel provided in an embodiment of the present invention includes a pixel circuit 100 provided in any embodiment of the present invention.

[0067] The display panel provided by the embodiment of the present invention includes the technical features of the pixel circuit provided by any embodiment of the present invention, and has the beneficial effects of the corresponding technical features.

[0068] An embodiment of the present invention further provides a display device. Fig.11 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.11 As shown, the display device provided by the embodiment of the present invention includes the display panel 200 described in any embodiment of the present invention. The display device can be as follows Fig.11 The mobile phone shown in the figure may also be a computer, a television, a smart wearable device, etc., and this embodiment does not specifically limit this.

[0069] In this embodiment, the display device includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features, which will not be described in detail here.

[0070] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that: include: a driving transistor and at least one switching transistor; The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side; At least one of the switch transistors comprises a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side; Among them, the first active layer and the second active layer are arranged in the same layer; the first gate serves as the control end of the driving transistor; the fourth gate serves as the control end of the switching transistor; the second gate is used to receive a first constant potential; and the third gate is used to receive a second constant potential.

2. The pixel circuit according to claim 1, characterized in that: The materials of the first active layer and the second active layer are both oxides of a given metal; The predetermined metal includes at least one of the following: gallium, hafnium, tin, lanthanum, indium and zinc.

3. The pixel circuit according to claim 1, characterized in that: The first active layer and the second active layer both include a first oxide layer and a second oxide layer; The first oxide is disposed on a side of the second oxide layer close to the first gate or the third gate; The mobility of carriers in the first oxide layer is smaller than the mobility of carriers in the second oxide layer.

4. The pixel circuit according to claim 3, characterized in that: The thickness ratio of the first oxide layer to the second oxide layer is in a range of 3:1 to 1:

1.

5. The pixel circuit according to claim 3, characterized in that: The first oxide layer includes indium oxide, gallium oxide and zinc oxide; The second oxide layer includes indium oxide, gallium oxide, zinc oxide and tin oxide.

6. The pixel circuit according to claim 5, characterized in that: The thickness ratio of the first oxide layer to the second oxide layer is 2:

1.

7. The pixel circuit according to claim 1, characterized in that: The display panel where the pixel circuit is located includes at least a substrate, a first metal layer, an active layer and a second metal layer which are stacked; The first active layer and the second active layer are both arranged on the active layer; the first gate and the third gate are arranged on the first metal layer; The fourth gate and the second gate are disposed on the second metal layer.

8. The pixel circuit according to claim 7, characterized in that: The value range of the first constant potential is 0V to 1.5V; The second constant potential has a value range of -3V to 0V.

9. The pixel circuit according to claim 8, characterized in that: The second constant potential is multiplexed as a reference voltage signal in the pixel circuit.

10. The pixel circuit according to claim 7, characterized in that: The first constant potential is the same as the second constant potential.

11. The pixel circuit according to claim 2, characterized in that: The driving transistor and the switching transistor are both N-type transistors.

12. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: a storage capacitor and a light-emitting element; the switch transistor includes: a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, a threshold compensation transistor and a data writing transistor; The control end of the first light-emitting control transistor is connected to the light-emitting control signal; the first end of the first light-emitting control transistor is connected to the first power supply signal; the second end of the first light-emitting control transistor is electrically connected to the first end of the driving transistor; the control end of the driving transistor is connected to the first power supply signal through the storage capacitor; the second end of the driving transistor is electrically connected to the first end of the second light-emitting control transistor; the control end of the second light-emitting control transistor is used to connect to the light-emitting control signal; the second end of the second light-emitting control transistor is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is connected to the second power supply signal; The control end of the first reset transistor is connected to the first scanning signal; the first end of the first reset transistor is connected to the reference voltage signal; the second end of the first reset transistor is electrically connected to the control end of the driving transistor; the control end of the second reset transistor is connected to the second scanning signal; the first end of the second reset transistor is connected to the reference voltage signal; the second end of the second reset transistor is electrically connected to the second end of the driving transistor; The control end of the threshold compensation transistor is connected to the third scanning signal; the first end of the threshold compensation transistor is electrically connected to the control end of the driving transistor; the second end of the threshold compensation transistor is electrically connected to the second end of the driving transistor; the control end of the data writing transistor is connected to the fourth scanning signal; the first end of the data writing transistor is connected to the data signal; the second end of the data writing transistor is electrically connected to the first end of the driving transistor.

13. A pixel circuit, characterized in that: include: a driving transistor and at least one switching transistor; The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side; At least one of the switch transistors comprises a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side; Among them, the first active layer and the second active layer are arranged in the same layer; the first gate serves as the control end of the driving transistor; the second gate is used to receive a third constant potential; the third gate and the fourth gate serve as the control ends of the switching transistor.

14. A pixel circuit, characterized in that: include: a driving transistor and at least one switching transistor; The driving transistor includes a first active layer, a first gate disposed on a first side of the first active layer, and a second gate disposed on the first active layer away from the first side; At least one of the switch transistors comprises a second active layer, a third gate disposed on a first side of the second active layer, and a fourth gate disposed on the second active layer away from the first side; The first active layer and the second active layer are arranged in the same layer; the first gate and the second gate serve as control terminals of the driving transistor; and the fourth gate serves as a control terminal of the switching transistor; The third gate is used for receiving a fourth constant potential.

15. A display panel, characterized in that: The pixel circuit comprises any one of claims 1 to 14.

16. A display device, characterized in that: The display panel comprises the display panel as claimed in claim 15.

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