Ferroelectric memory and method for reading memory unit of ferroelectric memory

Abstract

The invention discloses a ferroelectric memory and a method for reading a memory cell thereof. The ferroelectric memory includes: a ferroelectric memory cell which can be set to a first state corresponding to first data or a second state corresponding to second data and has a first port, a second port, and a first control port; plate lines; a bit line; a word line; the first port of the reading circuit is connected with the plate line, the second port of the reading circuit is connected with the bit line, and the first control port of the reading circuit is connected with the word line; the conduction of the second port is controlled through the first control port; wherein the reading circuit applies a reading current to the bit line to obtain the first data or the second data.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of memory, and more specifically, to a ferroelectric memory and a method for reading a memory cell thereof. Background Art

[0002] FeRAM (Ferroelectric RAM) is a random access memory. It has the advantages of high speed, high density, low power consumption, non-volatility, high temperature resistance, radiation resistance, and strong process compatibility. Therefore, ferroelectric memory has attracted much attention in the fields of IC cards, mobile phones, embedded microprocessors, aerospace, and military applications. Ferroelectric memory stores data based on the high dielectric constant and ferroelectric polarization characteristics of its ferroelectric materials. Depending on the polarization, the ferroelectric capacitor in the ferroelectric memory can be set to have different capacitances. The two stable states of the ferroelectric polarization characteristics are used to represent the state "0" and state "1" in digital logic.

[0003] Generally, the storage unit of a ferroelectric memory may include a ferroelectric capacitor and a switch device for controlling the connection state of the ferroelectric capacitor, such as a MOS tube. One end of the storage unit is connected to BL (Bit Line) and the other end is connected to PL (Plate Line). At present, the ferroelectric memory charges PL so that the voltage at BL is raised due to capacitive coupling. Since the equivalent capacitance value of the ferroelectric capacitor is different in different states, the voltage raised by BL is also different, so the state stored in the ferroelectric capacitor can be read out by the difference in the raised voltage. Summary of the invention

[0004] The disclosed embodiments provide a new ferroelectric memory and a reading method thereof.

[0005] In a first aspect, a ferroelectric memory is provided, comprising: a ferroelectric memory cell, which can be set to a first state corresponding to first data or a second state corresponding to second data and has a first port, a second port and a first control port; a plate line; a bit line; a word line and a read circuit, wherein the first port is connected to the plate line, the second port is connected to the bit line, and the first control port is connected to the word line; wherein the conduction of the second port is controlled by the first control port; wherein the read circuit obtains the first data or the second data by applying a read current to the bit line.

[0006] In a second aspect, a method for reading a ferroelectric memory cell in a ferroelectric memory according to the first aspect is provided, comprising: obtaining first data or second data by applying a read current to a bit line based on at least one of a charging speed and a discharging speed of a ferroelectric capacitor.

[0007] In various embodiments of the present disclosure, a ferroelectric memory having a new structure and a corresponding reading method thereof are proposed.

[0008] Other features and advantages of the embodiments of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0010] Figure 1 A schematic structural diagram of a ferroelectric memory according to an embodiment is shown.

[0011] Figure 2 A schematic structural diagram of a ferroelectric memory cell of a ferroelectric memory according to another embodiment is shown.

[0012] Figure 3 A schematic diagram of a ferroelectric memory including a plurality of ferroelectric memory cells according to another embodiment is shown.

[0013] Figure 4 FIG. 4 is a schematic structural diagram of a reading circuit of a ferroelectric memory according to another embodiment.

[0014] Figure 5 A schematic circuit diagram of a comparison circuit according to another embodiment is shown.

[0015] Figure 6 A schematic circuit diagram of a ferroelectric memory including a reference signal generating circuit according to another embodiment is shown.

[0016] Figure 7 FIG. 4 is a schematic structural diagram of a reading circuit of a ferroelectric memory according to another embodiment.

[0017] Figure 8 A schematic circuit diagram of a latch unit according to another embodiment is shown.

[0018] Fig. 9 A schematic circuit diagram of a reference output generating circuit for generating a reference output DLR of a ferroelectric memory according to another embodiment is shown.

[0019] Fig.10 A schematic circuit diagram of a current source in a ferroelectric memory according to another embodiment is shown.

[0020] Fig.11 A schematic circuit diagram of a current source in a ferroelectric memory according to another embodiment is shown.

[0021] Fig.12 A schematic circuit diagram of a read circuit according to another embodiment is shown.

[0022] Fig.13 A schematic diagram of a method for reading a ferroelectric memory cell in a ferroelectric memory according to another embodiment is shown. DETAILED DESCRIPTION

[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0024] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0025] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0026] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0027] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0028] Figure 1 A schematic structural diagram of a ferroelectric memory according to an embodiment is shown.

[0029] Figure 1 The ferroelectric memory shown includes: a ferroelectric memory cell 1 , a plate line PL, a bit line BL, a word line WL and a read circuit 3 .

[0030] The ferroelectric memory cell 1 can be set to a first state corresponding to first data or a second state corresponding to second data. Figure 1 As shown, the ferroelectric memory cell 1 has a first port a1, a second port a2 and a first control port c1. The first port a1 is connected to the plate line PL, the second port a2 is connected to the bit line BL, and the first control port c1 is connected to the word line WL. The conduction of the second port a2 is controlled by the first control port c1. The read circuit 3 obtains the first data or the second data by applying a read current to the bit line BL.

[0031] In some embodiments, the first data may be a signal corresponding to a logic "1", and the second data may be a signal corresponding to a logic "0". The first state corresponding to the first data may be the first capacitor of the ferroelectric memory cell 1, and the second state corresponding to the second data may be the second capacitor of the ferroelectric memory cell 1. As described above, the ferroelectric properties of the ferroelectric memory cell 1 may be utilized to set the ferroelectric memory cell to have the first capacitor or the second capacitor, thereby realizing data storage.

[0032] In some embodiments, a current source may be connected through the bit line BL to apply a current to the bit line BL. In this case, the read circuit 3 may include a current source.

[0033] In some embodiments, during the reading process, in the initial state, the initial state of the ferroelectric memory is set to BL=PL=0, WL=0. Then, by setting the word line WL to 1, the second port a2 of the ferroelectric memory cell 1 is turned on. A read current is applied to the bit line BL. Next, the reading circuit 3 reads the first data or the second data stored in the ferroelectric memory 1.

[0034] In the embodiment here, the storage data is obtained by directly applying a read current to the bit line BL. Therefore, the influence of the parasitic capacitance on the transmission line when a voltage is applied to the plate line PL can be at least partially alleviated. The parasitic capacitance is usually uncertain. In this way, the requirements for the parasitic capacitance can be reduced during the design, thereby reducing the difficulty of circuit design.

[0035] The reading principle here is different from the principle of the ferroelectric memory in the prior art. Here, the capacitance characteristics of the ferroelectric memory are used to read data. Therefore, the embodiments here can improve the reading performance of the ferroelectric memory.

[0036] Optionally, this may improve the stability of the memory circuit.

[0037] Optionally, in some embodiments, this may provide a balance between power consumption and speed.

[0038] In some embodiments, a write voltage is applied to the bit line BL and the plate line PL to set the state of the ferroelectric memory cell 1, thereby storing the first data or the second data in the ferroelectric memory cell 1. Since the connection state between the bit line BL and the ferroelectric memory cell 1 can be controlled by the word line WL, the effectiveness and / or efficiency of writing to the ferroelectric memory cell 1 can be achieved in this way.

[0039] In some embodiments, a write voltage may be applied to the bit line BL and the plate line PL through a current source connected to the bit line BL.

[0040] For example, when a forward voltage is applied to the bit line BL, the state of the ferroelectric memory cell storing data is the first capacitor corresponding to logic "1". Accordingly, when a reverse voltage is applied to the bit line BL, the state of the ferroelectric memory cell storing data is the second capacitor corresponding to logic "0".

[0041] As an example, Figure 1 The ferroelectric memory 1 shown may further include a reference signal generating circuit 5. For example, the reference signal generating circuit 5 may include a reference capacitor.

[0042] In some embodiments, Figure 2 As shown, the ferroelectric memory cell 1 includes a ferroelectric capacitor 20 and a switch unit 22. The ferroelectric capacitor 20 includes a third port a3 and a fourth port a4. The switch unit 22 includes a fifth port a5, a sixth port a6 and a second control port c2. The third port a3 is connected to the first port a1, the fourth port a4 is connected to the fifth port a5, the sixth port a6 is connected to the second port a2, and the second control port c2 is connected to the first control port c1. Those skilled in the art should understand that the "connection" here may include a direct connection, an indirect connection, or some coupling such as inductive or capacitive.

[0043] Those skilled in the art will appreciate that the ferroelectric capacitor 20 may be a capacitor made of any material exhibiting ferroelectric properties, such as conventional lead zirconate titanate material, novel hafnium oxide material, or other materials discovered later.

[0044] The switch unit 22 may be a transistor, such as a field effect transistor, etc. For example, the fifth port a5 may be a drain of the field effect transistor, the sixth port a6 may be a source of the field effect transistor, and the second control port c2 may be a gate of the field effect transistor.

[0045] Figure 3 FIG. 4 shows a schematic diagram of a ferroelectric memory including a plurality of ferroelectric memory cells 1 according to another embodiment. Figure 3 As shown, each ferroelectric memory cell 1 includes a ferroelectric capacitor 20 and a switch unit 22 such as a MOS transistor. The first port of each ferroelectric memory cell 1 is connected to the plate line PL m-1 , PL m , PL m+1 The second port of each ferroelectric memory cell 1 is connected to the bit line BL n-1 BL n BL n+1 The control ports of each ferroelectric memory cell 1 are connected to the word lines WL m-1 , WL m , WL m+1 connect.

[0046] The first state may correspond to the first capacitance of the ferroelectric capacitor 20, and the second state may correspond to the second capacitance of the ferroelectric capacitor 20. In some embodiments, by applying a read current to the bit line BL, the first data or the second data may be acquired based on at least one of the charging speed and the discharging speed of the ferroelectric capacitor 20.

[0047] The read current may include at least one of a source current and a sink current.

[0048] In some embodiments, during the reading process, in the initial state, the initial state of the ferroelectric memory is set to BL=PL=0, WL=0. Then, by setting the word line WL to 1, the second port a2 of the ferroelectric memory cell 1 is turned on. A read current is applied to the ferroelectric memory cell 1 through the bit line BL. Since the ferroelectric memory cell 1 is in different data storage states (i.e., the capacitance of the ferroelectric memory is different), the time required to charge or discharge the ferroelectric capacitor 20 through the bit line BL is different. Using the time for charging or discharging the ferroelectric capacitor 20 in different states, the reading circuit 3 reads out the first data or the second data stored in the ferroelectric memory cell 1.

[0049] As an example, when the ferroelectric memory cell 1 stores the first data, the capacitance value of the ferroelectric capacitor 20 is the first capacitance, and the time for charging or discharging the ferroelectric capacitor 20 is the first time T1. When the ferroelectric memory cell 1 stores the second data, the capacitance value of the ferroelectric capacitor 20 is the second capacitance, and the time for charging or discharging the ferroelectric capacitor 20 is the second time T2. When reading, based on the difference between T1 and T2, it can be determined whether the ferroelectric memory cell 1 stores the first data or the second data.

[0050] In this case, the influence of parasitic capacitance on the reading process can be reduced, thereby reducing uncertain factors in the circuit and reducing the difficulty of circuit design.

[0051] In one example, the voltage of the bit line BL within a predetermined time from the start of charging or discharging can be detected to determine whether the first data or the second data is stored. The predetermined time is less than the larger value of T1 and T2.

[0052] Figure 4 FIG. 2 shows a schematic diagram of a read circuit of a ferroelectric memory according to another embodiment. Figure 4 As shown, the read circuit 3 includes a current source 310 and a comparison circuit 320. The current source 310 can apply a read current to the bit line BL. The comparison circuit 320 can compare a signal of the bit line BL with a reference signal to obtain the first data or the second data.

[0053] Figure 4Also shown is a ferroelectric memory cell 1. The signal on the bit line BL may be a voltage at which a ferroelectric capacitor 20 in the ferroelectric memory cell 1 is charged or discharged.

[0054] The reference signal can be a reference voltage Vref directly provided by a voltage source, or a voltage provided by a signal generating circuit, for example, a voltage generated by charging or discharging a reference capacitor. By adjusting the magnitude of the reference voltage, the timing of determining data can be controlled. In some embodiments, the reference voltage can be multiplexed for multiple bit lines BL at the same time. In this way, maximum resource utilization can be achieved.

[0055] The comparison circuit 320 may be a voltage amplifier, a current amplifier, or a differential amplifier circuit. As an example, the comparison circuit 320 compares the voltage of the bit line BL with a reference voltage to obtain the first data or the second data.

[0056] In some embodiments, the comparison circuit 320 compares the signal of the bit line with the reference signal at a first predetermined time to obtain the first data or the second data. The first predetermined time is less than the larger time between the first time and the second time.

[0057] As an example, during the reading process, in the initial state, the initial state of the ferroelectric memory is set to BL=PL=0, WL=0. Then, by setting the word line WL to 1, the second port a2 of the ferroelectric memory cell 1 is turned on. A read current is applied to the bit line BL, thereby charging the ferroelectric capacitor 20 in the ferroelectric memory cell 1. At this time, the voltage Vbl output by the bit line BL to the reading circuit 3 is raised. At the first predetermined time T, Vbl is compared with Vref, and the output OUT of the first data or the second data can be obtained, where Vbl is the voltage on the bit line and Vref is the reference voltage. For example, if Vbl is greater than Vref, the stored data is judged to be logic "1", and if Vbl is less than Vref, the stored data is judged to be logic "0".

[0058] As an example, Figure 5 FIG. 4 shows a schematic circuit diagram of a comparison circuit according to another embodiment. Figure 5As shown, one input terminal of the comparison circuit is connected to the bit line BL to receive the voltage output by the ferroelectric memory cell via the bit line BL, and the other input terminal of the comparison circuit receives the reference voltage Vref. For example, when the ferroelectric memory cell 1 stores a logic "0", the capacitance of the corresponding ferroelectric memory cell 1 is smaller, and the voltage Vbl on the bit line rises faster. Within the first predetermined time T, Vbl > Vref. At this time, the output of the output line DL is logic "1". When the ferroelectric memory stores a logic "1", the capacitance of the corresponding ferroelectric memory cell 1 is larger, and Vbl rises slowly. At the first predetermined time T, Vbl < Vref. At this time, the output of the output line DL is logic "0".

[0059] As Figure 6 shown, in some embodiments, the reference signal generation circuit 5 of the ferroelectric memory may include a reference capacitor 51. The reference signal such as Vref is provided through the reference capacitor 51. In addition, the reference signal generation circuit 5 may further include a switching element 52 such as a switching transistor for controlling the connection of the reference capacitor 51.

[0060] The reference signal generation circuit 5 may be symmetrically arranged with respect to the comparison circuit 320 relative to the ferroelectric memory cell 1. The second port of the ferroelectric memory cell 1 may be connected to the input terminal of the comparison circuit 320 through the bit line BL, and the output terminal of the reference capacitor 5 is connected to the reference terminal of the comparison circuit 320. The comparison circuit 320 compares the signal on the bit line BL with the reference signal within the second predetermined time to obtain the first data or the second data.

[0061] The reference capacitor 51 may include a ferroelectric capacitor or an ordinary capacitor.

[0062] As an example, as Figure 6 shown, the structure of the reference signal generation circuit 5 may be the same as that of the ferroelectric memory cell 1, that is, it may include a ferroelectric capacitor 51 and a switching unit 52. Relative to the comparison circuit 320, the reference signal generation circuit 5 may be symmetrically arranged with the ferroelectric memory cell 1. One end of the comparison circuit 320 is connected to the bit line BL, and the other end is connected to the reference bit line BLR.

[0063] The reference bit line BLR is connected to the reference signal generation circuit 5. The ferroelectric capacitor 51 may be a capacitor corresponding to the first data (i.e., having a first capacitance), or a capacitor corresponding to the second data (i.e., having a second capacitance), or a capacitor having a state between the first state and the second state (i.e., its capacitance is between the first capacitance and the second capacitance).

[0064] The second predetermined time is less than the larger of the first time and the second time.

[0065] As an example, during the reading process, in the initial state, the initial state of the ferroelectric memory is set to BL=PL=0, WL=0. The initial state of the reference capacitor 51 is set to BLR=PL=0, WL=0. Then, by setting the word line WL to 1, the ferroelectric memory cell 1 and the reference capacitor 51 are respectively connected to the bit line BL and the reference bit line BLR. A read current is applied to the bit line BL and the reference bit line BLR. At this time, the voltage Vbl output by the bit line BL to the reading circuit 3 is raised. The voltage Vref output by the reference bit line BLR is also raised. At the second predetermined time T, Vbl is compared with Vref, and the first data or the second data can be obtained. For example, if Vbl is greater than Vref, OUT outputs logic "1", and if Vbl is less than Vref, OUT outputs logic "0".

[0066] In some embodiments, the reference signal generating circuit 5 may use a linear combination of the outputs of the ferroelectric memory cell in the first state and the outputs of the ferroelectric memory cell in the second state as the reference signal.

[0067] The linear combination of the output of the ferroelectric memory cell in the first state and the output of the ferroelectric memory cell in the second state can be a combination of the output value of the ferroelectric memory cell in the first state multiplied by the coefficient A and the output value of the ferroelectric memory cell in the second state multiplied by the coefficient (1-A). Where A is any number between 0 and 1. For example, A can be 0.5.

[0068] For example, the reference signal may be a combination of half the output value of the ferroelectric memory cell in the first state and half the output value of the ferroelectric memory cell in the second state (i.e., the average of the output value of the ferroelectric memory cell in the first state and the output value of the ferroelectric memory cell in the second state), or may be a combination of the output value of the ferroelectric memory cell in the first state multiplied by 0.3 and the output value of the ferroelectric memory cell in the second state multiplied by 0.7. For another example, the reference signal may be the output value of the ferroelectric memory cell in the first state, or may be the output value of the ferroelectric memory cell in the second state. The specific value of coefficient A is not limited here.

[0069] Alternatively, if Figure 7 As shown, the read circuit 3 of the ferroelectric memory may further include a latch unit 330. The latch unit 330 may receive the output DL of the comparison circuit 320 and compare the output DL with the reference output DLR to latch the output signal as the first data or the second data.

[0070] The reference output DLR may be an output corresponding to the first state in terms of time change, or an output corresponding to the second state, or an output corresponding to a third state between the first state and the second state. For example, in the case of corresponding to the first state, the time point of the amplitude transition of the reference output DLR corresponds to the first time point, which is the time point at which the amplitude of the output signal changes when the first capacitor is charged; in the case of corresponding to the second state, the time point of the amplitude transition of the reference output DLR corresponds to the second time point, which is the time point at which the amplitude of the output signal changes when the second capacitor is charged; or, in the case of corresponding to the third state, the time point of the amplitude transition of the reference output DLR corresponds to the third time point, which is between the first time point and the second time point.

[0071] The current source 310 may be connected to the ferroelectric memory cell 1 through the bit line BL, and may be connected to the comparison circuit 320 , and the comparison circuit 320 is connected to the latch unit 330 .

[0072] In some embodiments, Figure 8 As shown, the latch unit 330 may include a NAND latch.

[0073] As an example, in Figure 8 In the embodiment, when the output DL changes to "1" earlier (when the data stored in the ferroelectric memory cell 1 is "0"), the output OUT is maintained at "0" and the output OUTB is maintained at "1". When the output DLR changes to "1" earlier (when the data stored in the ferroelectric memory cell 1 is "1"), the output OUTB is maintained at "0" and the output OUT is maintained at "1".

[0074] The output DL can be Figure 5 The output of the circuit shown.

[0075] As an example, Fig. 9 FIG. 2 schematically shows a reference output generating circuit for generating a reference output DLR according to another embodiment. Fig. 9 As shown, the reference output generating circuit uses the linear combination (average value) of the output BLR0 of the ferroelectric memory cell in the first state and the output BLR1 of the ferroelectric memory cell in the second state as the first input signal, and uses the reference voltage Vref as the second input signal. By comparing the first input signal and the second input signal, the reference output DLR is obtained.

[0076] In this embodiment, the margin of the latch unit 330 latching the output result can be adjusted by changing the reference voltage Vref.

[0077] As an example, Fig.10 and Fig.11Examples of two current source settings are shown.

[0078] like Fig.10 As shown, a separate current source may be provided for the bit line BL to apply the current I1 , and a separate current source may be provided for the reference bit line BLR to apply the current I2 .

[0079] like Fig.11 As shown, the same current source is provided for the bit line BL and the reference bit line BLR to apply the same current I.

[0080] Alternatively, if Fig.12 As shown, the ferroelectric memory may further include: a discharge circuit 9. The discharge circuit 9 can be used to initialize the state of the ferroelectric memory.

[0081] In some embodiments, the bit line BL and the reference bit line BLR share a discharge circuit 9. When the switch unit SENB is disconnected and the switch unit sel_r is disconnected, the voltage outputted via the bit line BL and the reference bit line BLR is pulled down to 0 by the discharge circuit 9, and OUT and OUTB also become 0. As an example, when the bit line BL is connected to a ferroelectric memory cell storing logic "0", the capacitance of the corresponding ferroelectric memory cell 1 is small, and Vbl rises quickly. When the bit line BL is connected to a ferroelectric memory cell 1 storing logic "1", the capacitance of the corresponding ferroelectric memory cell 1 is large, and Vbl rises slowly. When the reference bit line BLR is connected to a linear combination of a ferroelectric memory cell 1 storing logic "0" and a ferroelectric memory cell 1 storing logic "1", at this time, the voltage Vref outputted via BLR rises slower than the Vbl of the ferroelectric memory cell 1 storing logic "0" alone, and rises faster than the Vbl of the ferroelectric memory cell 1 storing logic "1" alone. At a predetermined time point, SENB=0 is set, and OUT is output through positive feedback of the amplifier.

[0082] Optionally, Fig.13 A schematic diagram of a method for reading a ferroelectric memory cell 1 in the ferroelectric memory according to another embodiment is shown. The method comprises: step S100, obtaining first data or second data by applying a read current to a bit line based on at least one of a charging speed and a discharging speed of a ferroelectric capacitor.

[0083] Each embodiment in the present disclosure is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the device and equipment embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the device and equipment embodiment.

[0084] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A ferroelectric memory, comprising: A ferroelectric memory cell capable of being set to a first state corresponding to first data or a second state corresponding to second data and having a first port, a second port and a first control port; Plate line; bit line; word line; and Reading circuit, wherein the first port is connected to the plate line, the second port is connected to the bit line, and the first control port is connected to the word line; Wherein, the conduction of the second port is controlled by the first control port; The reading circuit obtains the first data or the second data by applying a reading current to the bit line.

2. The ferroelectric memory according to claim 1, wherein: By applying a write voltage to the bit line and the plate line, the state of the ferroelectric memory cell is set, thereby storing the first data or the second data in the ferroelectric memory cell.

3. The ferroelectric memory according to claim 1, wherein: The ferroelectric storage unit includes a ferroelectric capacitor and a switching unit, the ferroelectric capacitor includes a third port and a fourth port, the switching unit includes a fifth port, a sixth port and a second control port, the third port is connected to the first port, the fourth port is connected to the fifth port, the sixth port is connected to the second port, and the second control port is connected to the first control port.

4. The ferroelectric memory according to claim 3, wherein: The first state corresponds to a first capacitance of the ferroelectric capacitor, the second state corresponds to a second capacitance of the ferroelectric capacitor, and Wherein, the first data or the second data is obtained by applying a read current to the bit line based on at least one of a charging speed and a discharging speed of the ferroelectric capacitor.

5. The ferroelectric memory according to claim 4, wherein: The read current includes at least one of a source current and a sink current.

6. The ferroelectric memory according to claim 5, wherein: The reading circuit includes a current source and a comparison circuit. wherein the current source provides a read current for the bit line; The comparison circuit compares the signal of the bit line with the reference signal to obtain the first data or the second data.

7. The ferroelectric memory according to claim 6, wherein: The comparison circuit compares a signal of the bit line with a reference signal within a first predetermined time to obtain first data or second data.

8. The ferroelectric memory according to claim 7, further comprising: Reference capacitor, The reference capacitor and the ferroelectric memory cell are symmetrically arranged relative to the comparison circuit, the second port of the ferroelectric memory cell is connected to the input terminal of the comparison circuit through the bit line, and the output terminal of the reference capacitor is connected to the reference terminal of the comparison circuit; The comparison circuit compares the signal of the bit line with the reference signal within a second predetermined time to obtain the first data or the second data.

9. The ferroelectric memory according to claim 7, further comprising: Reference signal generating circuit, The reference signal generating circuit uses a linear combination of the outputs of the ferroelectric memory cell in the first state and the outputs of the ferroelectric memory cell in the second state as a reference signal.

10. The ferroelectric memory according to claim 6, wherein: The reading circuit further includes a latch unit, The latch unit receives the output of the comparison circuit and latches the output as the first data or the second data.

11. A method for reading a ferroelectric memory cell in the ferroelectric memory according to claim 1, comprising: The first data or the second data is acquired by applying a read current to the bit line based on at least one of a charging speed and a discharging speed of the ferroelectric capacitor.

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