A control method and device of a multi-level converter, an electronic device and a medium

Abstract

This invention discloses a control method, device, electronic device, and medium for a multilevel converter, relating to the field of control. In this solution, when the flying capacitor voltage of the multilevel converter is in an uneven voltage state, a set of mutually paired upper arm switch control sequences and a set of lower arm switch control sequences are determined based on the number of switches in the multilevel converter. Corresponding upper arm PWM waves and lower arm PWM waves are generated to control the on / off states of the upper and lower arm switches. Since sequentially sending a pair of mutually paired upper arm PWM waves and a pair of lower arm PWM waves in adjacent cycles can balance the flying capacitor voltage, this solution periodically sends the first upper arm PWM wave, the second upper arm PWM wave, the first lower arm PWM wave, and the second lower arm PWM wave to balance the flying capacitor voltage as much as possible, thereby eliminating the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is uneven.

Description

Technical Field

[0001] This invention relates to the field of control, and in particular to a control method, apparatus, electronic device, and medium for a multilevel converter. Background Technology

[0002] Flying capacitor multilevel converters are gaining increasing attention due to their high power density and high efficiency. The circuit structure of an N-level flying capacitor multilevel converter is as follows: Figure 1 As shown, it uses multiple switches connected in series to form the upper and lower bridge arms, and flying capacitors are placed between the nodes of the switches to limit the stress on the switches. However, since the voltage of the flying capacitor must be 1 / (N-1), 2 / (N-1), ... (N-2) / (N-1) times the Vbus voltage (bus voltage), that is, to achieve steady-state natural voltage equalization of the flying capacitor, in order to ensure the average distribution of stress among the switches, the voltage of the flying capacitor must be controlled.

[0003] Generally, the control of multilevel converters typically employs phase-shift PWM (Pulse Width Modulation) with a common duty cycle. For example... Figure 1 The N-level flying capacitor multilevel converter shown has its upper arm switches numbered S1a, S2a…S(N-1)a sequentially from the midpoint upwards, and S1b, S2b, …, S(N-1)b sequentially downwards. Existing multilevel converters control the switches in the same order and with the same on / off time within each switching cycle. Furthermore, the control methods for S1b, S2b…S(N-1)b are complementary to those for S1a, S2a…S(N-1)a, meaning the switching order of the upper arm switches is the reverse of the lower arm switches. For example, in each switching cycle, the upper arm switches S1a, S2a…S(N-1)a close sequentially, and each switch has the same on / off time. This modulation method, in principle, can achieve steady-state natural voltage equalization of the flying capacitor. However, when the voltage of the flying capacitor does not meet the requirement of 1 / (N-1), 2 / (N-1)...(N-2) / (N-1) times the Vbus voltage (bus voltage), the flying capacitor voltage will oscillate under this control method, which will lead to a serious overvoltage problem on the switching transistor. Therefore, there is an urgent need for a control method to eliminate the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is in an uneven voltage state. Summary of the Invention

[0004] The purpose of this invention is to provide a control method, device, electronic device, and medium for a multilevel converter. In this solution, when the flying capacitor voltage of the multilevel converter is in an uneven voltage state, the flying capacitor voltage of the multilevel converter is balanced as much as possible by periodically sending mutually paired first upper bridge arm PWM waves, second upper bridge arm PWM waves, and mutually paired first lower bridge arm PWM waves, second lower bridge arm PWM waves, to eliminate the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is in an uneven voltage state.

[0005] To solve the above-mentioned technical problems, the present invention provides a control method for a multilevel converter, comprising:

[0006] Determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state;

[0007] If the flying capacitor of the multilevel converter is in an uneven voltage state, then determine the number of first switches in the upper arm and the number of second switches in the lower arm of the multilevel converter.

[0008] The control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm are determined according to the number of the first switch transistors and the number of the second switch transistors. The control sequence of the first switch of the upper bridge arm and the control sequence of the second switch of the upper bridge arm are mutually paired, the control sequence of the first switch of the lower bridge arm and the control sequence of the second switch of the lower bridge arm are mutually paired, the control sequence of the first switch of the upper bridge arm and the control sequence of the first switch of the lower bridge arm are opposite to the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the upper bridge arm and the control sequence of the second switch of the lower bridge arm are opposite to the control sequence of the second switch of the lower bridge arm.

[0009] Based on the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, the control sequence of the second switch of the lower bridge arm, and the preset duty cycle, corresponding first upper bridge arm PWM wave, second upper bridge arm PWM wave, first lower bridge arm PWM wave, and second lower bridge arm PWM wave are generated. Within a preset period range, the first upper bridge arm PWM wave and the second upper bridge arm PWM wave are periodically sent to the upper bridge arm switch of the multilevel converter, and the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are periodically sent to the lower bridge arm switch of the multilevel converter.

[0010] Optionally, determining whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state includes:

[0011] Determine the bus voltage of the bus capacitor of the multilevel converter;

[0012] Determine whether the bus voltage is within the preset voltage range;

[0013] If the bus voltage is within the preset voltage range, it is determined that the flying capacitor voltage of the multilevel converter is not in the uneven voltage state.

[0014] If the bus voltage is not within the preset voltage range, then the flying capacitor voltage of the multilevel converter is determined to be in the uneven voltage state.

[0015] Optionally, determining the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors includes:

[0016] A set of dual phase sequence disks is determined based on the number of the first switch transistors and the number of the second switch transistors;

[0017] The control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm are determined based on the dual phase sequence wheel.

[0018] Optionally, determining the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the dual phase sequence wheel includes:

[0019] The dual phase sequence wheel determines N upper bridge arm switch control sequence combinations and N lower bridge arm switch control sequence combinations with dual phase sequence relationships.

[0020] Select any target upper arm switch sequence control combination from the various upper arm switch sequence control combinations, and use the upper arm switch sequence corresponding to the target upper arm switch sequence control combination as the first upper arm switch control sequence and the second upper arm switch control sequence.

[0021] Select a target lower arm switch sequence control combination that is opposite to the target upper arm switch sequence control combination from each of the lower arm switch sequence control combinations, and use the lower arm switch sequence corresponding to the target lower arm switch sequence control combination as the first switch control sequence and the second switch control sequence of the lower arm.

[0022] Optionally, if the flying capacitor of the multilevel converter is in an uneven voltage state, the following further steps are included:

[0023] Based on the time of occurrence of the uneven pressure state and the uneven pressure state, a corresponding fault report is generated, and the alarm device is controlled to issue a corresponding alarm.

[0024] Optionally, the step of periodically sending the first upper-arm PWM wave and the second upper-arm PWM wave to the upper-arm switch of the multilevel converter and periodically sending the first lower-arm PWM wave and the second lower-arm PWM wave to the lower-arm switch of the multilevel converter within a preset period range includes:

[0025] Determine the preset upper bridge arm PWM wave transmission sequence and the preset lower bridge arm PWM wave transmission sequence;

[0026] Within the preset period, the first upper arm PWM wave and the second upper arm PWM wave are sent to the upper arm switching transistor in the preset upper arm PWM wave transmission order.

[0027] Within the preset period, the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are sent to the lower bridge arm switch in the preset lower bridge arm PWM wave sending order, and the number of the first upper bridge arm PWM wave, the second upper bridge arm PWM wave, the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are equal.

[0028] Optionally, after periodically sending the first upper-arm PWM wave and the second upper-arm PWM wave to the upper-arm switch of the multilevel converter and periodically sending the first lower-arm PWM wave and the second lower-arm PWM wave to the lower-arm switch of the multilevel converter within a preset period range, the method further includes:

[0029] Determine whether the upper bridge arm switch and the lower bridge arm switch perform corresponding switching actions within a preset time.

[0030] If the upper arm switch or the lower arm switch performs the corresponding switching action within a preset time, it is determined that the upper arm switch and the lower arm switch are not faulty.

[0031] If the upper arm switch or the lower arm switch fails to perform the corresponding switching action within a preset time, it is determined that the upper arm switch or the lower arm switch has malfunctioned, and the alarm device is controlled to issue a corresponding alarm.

[0032] To address the aforementioned technical problems, the present invention also provides a control device for a multilevel converter, comprising:

[0033] The judgment unit is used to determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state.

[0034] The first determining unit is used to determine the number of first switching transistors in the upper arm and the number of second switching transistors in the lower arm of the multilevel converter when the flying capacitor of the multilevel converter is in an uneven voltage state.

[0035] The second determining unit is used to determine the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors. The control sequence of the first switch of the upper bridge arm and the control sequence of the second switch of the upper bridge arm are paired, the control sequence of the first switch of the lower bridge arm and the control sequence of the second switch of the lower bridge arm are paired, the control sequence of the first switch of the upper bridge arm and the control sequence of the first switch of the lower bridge arm are opposite, and the control sequence of the second switch of the upper bridge arm and the control sequence of the second switch of the lower bridge arm are opposite.

[0036] The transmitting unit is configured to generate corresponding first upper arm PWM waves, second upper arm PWM waves, first lower arm PWM waves, and second lower arm PWM waves based on the control sequence of the first upper arm switch, the control sequence of the second upper arm switch, the control sequence of the first lower arm switch, the control sequence of the second lower arm switch, and a preset duty cycle, and periodically transmit the first upper arm PWM waves and the second upper arm PWM waves to the upper arm switch of the multilevel converter and periodically transmit the first lower arm PWM waves and the second lower arm PWM waves to the lower arm switch of the multilevel converter within a preset period range.

[0037] To address the aforementioned technical problems, the present invention also provides an electronic device, comprising:

[0038] Memory, used to store computer programs;

[0039] A processor is configured to implement the steps of the control method for the multilevel converter as described above when executing the computer program.

[0040] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the control method for the multilevel converter described above.

[0041] The purpose of this invention is to provide a control method, device, electronic device, and medium for a multilevel converter. In this solution, when the flying capacitor voltage of the multilevel converter is in an uneven voltage state, a set of mutually paired upper arm switch control sequences and a set of lower arm switch control sequences are determined based on the number of switches in the multilevel converter. Corresponding upper arm PWM waves and lower arm PWM waves are generated to control the opening and closing of the upper and lower arm switches. Because sequentially sending a pair of mutually paired upper arm PWM waves and a pair of lower arm PWM waves in adjacent cycles can balance the flying capacitor voltage, this solution periodically sends the first upper arm PWM wave, the second upper arm PWM wave, the first lower arm PWM wave, and the second lower arm PWM wave to balance the flying capacitor voltage as much as possible, thereby eliminating the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is uneven. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] Figure 1 This invention provides a schematic diagram of the structure of an N-level converter;

[0044] Figure 2 A process flowchart of a control method for a multilevel converter provided by the present invention;

[0045] Figure 3 A modulation principle diagram of a phase-shift PWM with a common duty cycle provided for this invention;

[0046] Figure 4 A schematic diagram of a five-level converter with a flying capacitor provided by the present invention;

[0047] Figure 5 The present invention provides a phenomenon of voltage oscillation of the flying capacitor when a five-level converter with a flying capacitor starts from an uneven initial state in a 1234 phase sequence.

[0048] Figure 6 This invention provides a key mode diagram of a flying capacitor five-level converter under Seq.1234 control;

[0049] Figure 7 The present invention provides a mode diagram of a five-level converter with a flying capacitor in Seq.1234.

[0050] Figure 8This invention provides a key mode diagram of a flying capacitor five-level converter under Seq.4321 control;

[0051] Figure 9 The present invention provides a mode diagram of a five-level converter with a flying capacitor in Seq.4321.

[0052] Figure 10 A schematic diagram of a phase sequence wheel with a 1234 phase sequence is provided for this invention;

[0053] Figure 11 A schematic diagram of a phase sequence wheel with a 4321 phase sequence is provided for this invention;

[0054] Figure 12 A schematic diagram of an interleaved phase sequence (1234-1432) modulation provided by the present invention;

[0055] Figure 13 A schematic diagram illustrating the dynamic voltage experiment effect of a non-interleaved phase sequence provided by the present invention;

[0056] Figure 14 A schematic diagram illustrating the voltage dynamics experiment effect of another non-interleaved phase sequence provided by the present invention;

[0057] Figure 15 This invention provides a schematic diagram of three pairs of dual phase sequences for a five-level converter.

[0058] Figure 16 A schematic diagram of the dual phase sequence wheel of a four-level converter provided by the present invention;

[0059] Figure 17 This invention provides a schematic diagram of switching the phase sequence in one switching cycle or two switching cycles.

[0060] Figure 18 A schematic diagram of a triangular wave dual phase sequence modulation provided by the present invention;

[0061] Figure 19 This is a schematic diagram of the structure of a control device for a multilevel converter provided by the present invention;

[0062] Figure 20 This is a schematic diagram of the structure of an electronic device provided by the present invention. Detailed Implementation

[0063] The core of this invention is to provide a control method, device, electronic device, and medium for a multilevel converter. When the flying capacitor voltage of the multilevel converter is in an uneven voltage state, this solution periodically sends mutually paired first upper bridge arm PWM waves, second upper bridge arm PWM waves, and mutually paired first lower bridge arm PWM waves, second lower bridge arm PWM waves to balance the flying capacitor voltage of the multilevel converter as much as possible, thereby eliminating the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is in an uneven voltage state.

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0065] Please refer to Figure 2 , Figure 2 A flowchart illustrating a control method for a multilevel converter provided by the present invention. The control method for the multilevel converter includes:

[0066] S11: Determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state;

[0067] S12: If the flying capacitor of the multilevel converter is in an uneven voltage state, then determine the number of first switching transistors in the upper arm and the number of second switching transistors in the lower arm of the multilevel converter.

[0068] S13: Determine the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors. The control sequence of the first switch of the upper bridge arm and the control sequence of the second switch of the upper bridge arm are paired, the control sequence of the first switch of the lower bridge arm and the control sequence of the second switch of the lower bridge arm are paired, the control sequence of the first switch of the upper bridge arm and the control sequence of the first switch of the lower bridge arm are opposite, and the control sequence of the second switch of the upper bridge arm and the control sequence of the second switch of the lower bridge arm are opposite.

[0069] S14: Based on the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, the control sequence of the second switch of the lower bridge arm, and the preset duty cycle, generate corresponding first upper bridge arm PWM wave, second upper bridge arm PWM wave, first lower bridge arm PWM wave, and second lower bridge arm PWM wave, and periodically send the first upper bridge arm PWM wave and the second upper bridge arm PWM wave to the upper bridge arm switch of the multilevel converter within a preset period range, and periodically send the first lower bridge arm PWM wave and the second lower bridge arm PWM wave to the lower bridge arm switch of the multilevel converter.

[0070] In this invention, considering that when the flying capacitor voltage of the multilevel converter is in an uneven voltage state, if the upper and lower bridge arm switches of the multilevel converter are controlled in the same switching sequence in each switching cycle, voltage oscillation will occur in the multilevel converter. Therefore, this solution first addresses the situation where the flying capacitor voltage of the multilevel converter is in an uneven voltage state. Secondly, it changes the switching sequence of the upper and lower bridge arm switches in this situation to eliminate voltage oscillation as much as possible. Therefore, this solution first needs to determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state. If so, it needs to determine the number of first switches in the upper bridge arm and the number of second switches in the lower bridge arm of the multilevel converter, because the number of switches determines the determination of the actual paired switches. Then, based on the number of first switches and the number of second switches, the mutually paired upper bridge arm first switch control sequence and upper bridge arm second switch control sequence are determined. The sequence, and the control sequence of the first and second switches of the mutually paired lower bridge arms, are determined because sending a pair of mutually paired upper bridge arm PWM waves and a pair of mutually paired lower bridge arm PWM waves in adjacent cycles can balance the voltage of the flying capacitor. Therefore, after determining the control sequence of the mutually paired upper bridge arm switches and the control sequence of the mutually paired lower bridge arms, the corresponding first upper bridge arm PWM wave, second upper bridge arm PWM wave, first lower bridge arm PWM wave, and second lower bridge arm PWM wave can be generated according to the corresponding switch sequence and preset duty cycle. Finally, the first upper bridge arm PWM wave and the second upper bridge arm PWM wave can be periodically sent to the upper bridge arm switches of the multilevel converter and the first lower bridge arm PWM wave and the second lower bridge arm PWM wave can be periodically sent to the lower bridge arm switches of the multilevel converter within a preset period range to balance the voltage of the flying capacitor as much as possible, so as to eliminate the voltage oscillation effect of the multilevel converter when the voltage of the flying capacitor is uneven.

[0071] It should be noted that, as Figure 3As shown, PWM modulation requires a carrier wave and a modulating wave. The carrier waves are named Carrier1 to Carrier4, and they are compared with the modulating wave CMP. If the carrier wave's magnitude is less than CMP, the corresponding PWM signal is set high; otherwise, it is set low. This modulation generates a PWM signal whose driving carrier signal is sequentially phase-shifted by 180° / (N-1). Figure 1 The control methods of the switches S1b, S2b…S(N-1)b in the lower arm of the multilevel converter are complementary to those of the switches S1a, S2a…S(N-1)a in the upper arm of the multilevel converter. In principle, this modulation method can achieve steady-state natural voltage equalization of the flying capacitor. However, under dynamic conditions of uneven voltage distribution, the voltage across the flying capacitor will oscillate under this control method, thus causing severe overvoltage problems on the switches.

[0072] It should also be noted that when the common duty cycle is controlled under uneven voltage dynamics, the voltage across the flying capacitor will oscillate under this control method, thus causing a serious overvoltage problem on the switching transistor. Currently, no particularly good control scheme for this situation has been found. To aid understanding, this application provides further details... Figure 4 The five-level flying capacitor boost circuit shown employs, as follows: Figure 5 The control phase sequence shown in Seq.1234 is used for control. Seq.1234 refers to... Figure 3 In this context, the control phase sequence is as follows: S1a, S2a, S3a, S4a are activated sequentially. For example... Figure 4 An experiment was conducted using a five-level circuit as shown, and the bus voltage was started from a low voltage uneven initial state. We can see that the voltage across the flying capacitor oscillates in the experiment, and the oscillation will cause overvoltage to be applied to the switching transistor.

[0073] It should also be noted that, taking a five-level circuit as an example, the technical solution of this application will be explained. The so-called dual phase sequence is as follows: Figure 6 Seq.1234 and Figure 8 The key mode diagrams of the multilevel circuits corresponding to the two driving sequences of Seq.4321 are shown below. The characteristic of these two driving sequences is that the dynamic behavior of the flying capacitor derived from them is completely opposite. The derivation process is as follows:

[0074] Assuming that the flying capacitor voltage ripple and input / output voltage ripple are ignored within a switching cycle, and parasitic parameters such as resistance and inductance in the circuit are also ignored. If it is Seq.1234, its corresponding modal diagram is as follows: Figure 7 As shown, S1a-S4a are the first to fourth switching transistors respectively, S1b-S4b are the fifth to eighth switching transistors respectively, Cf1 is the first flying capacitor, Cf2 is the second flying capacitor, Cf3 is the third flying capacitor, and Cbus is the bus capacitor.

[0075] In M1 mode, the flying capacitor Cf1 is charged, the inductor current decreases, so the charge Q of the first flying capacitor is... C1 And the change in inductor current is equal to:

[0076] Where D is the duty cycle, Ts is the switching period of the switching transistor, and V... in V is the input voltage of the five-level converter. Cf1 The voltage value of the first flying capacitor, V Cf2 The voltage value of the second flying capacitor, V Cf3 I0-I8 are the voltage values ​​of the third flying capacitor, I0-I8 are the current values ​​of the inductor at the input of the five-level converter at different times, L is the inductance value of the inductor at the input of the five-level converter, and Q is the voltage value of the third flying capacitor. C1 The charge on the first flying capacitor, Q C2 The charge on the second flying capacitor, Q C3 The charge on the third flying capacitor, Q D1 The discharge quantity of the first flying capacitor, Q D2 The discharge quantity of the second flying capacitor, Q D3 This is the discharge amount of the third flying capacitor;

[0077] In M2 mode, no flying capacitor is charged or discharged, and the inductor current rises. The current change during this period is as follows:

[0078] ;

[0079] In M3 mode, Cf1 is discharged while Cf2 is charged, and current flows through both connected in series. Therefore, the discharge quantity Q of Cf1 is... D1 The charge equal to Cf2, the changing current equals:

[0080] ;

[0081] In M4 mode, no flying capacitor is charged or discharged, and the inductor current rises. The current change during this period is as follows:

[0082] ;

[0083] In M5 mode, Cf2 is discharged while Cf3 is charged, and current flows through both connected in series. Therefore, the amount of discharge of Cf2 equals the amount of charge of Cf3, and the changing current is equal to:

[0084] ;

[0085] In M6 mode, no flying capacitor is charged or discharged, and the inductor current rises. The current change during this period is as follows:

[0086] ;

[0087] In M7 mode, Cf3 is discharged while Cbus is charged, but the bus voltage is generally constant. Therefore, the discharge amount of Cf3 and the changing current are equal to:

[0088] V bus This is the voltage across the bus capacitor.

[0089] In M8 mode, no flying capacitor is charged or discharged, and the inductor current rises. The current change during this period is as follows:

[0090] ;

[0091] Based on this modal analysis using the volt-second and ampere-second relationship, the charge change of each flying capacitor can be calculated. , , :

[0092] ;

[0093] For simplicity of calculation, it is assumed that the capacitance values ​​of all three flying capacitors are equal and equal to the capacitance value Cf of the bus capacitor.

[0094] Therefore, we can deduce that:

[0095] ;

[0096] in, , , These are the voltage values ​​of the first flying capacitor to the third flying capacitor, respectively.

[0097] However, if the same derivation process is used to calculate Seq.4321, the final derived voltage change is exactly the opposite of Seq.1234, and the mode diagram corresponding to Seq.4321 is as follows: Figure 9 As shown:

[0098] ;

[0099] It should also be noted that this application defines two control phase sequences with completely opposite dynamics as dual phase sequences. For dual phase sequences, there are also equivalent phase sequences. For example, for Seq.1234, Seq.2341, Seq.3412, and Seq.4123 also have completely identical control dynamics. Therefore, we use the following... Figure 10 The diagram shows a wheel representing phase sequence 1, 2, 3, and 4. All four phase sequences mentioned above are represented on this wheel, only their starting points differ. Therefore... Figure 11 This describes the phase sequence wheel for the corresponding dual phase sequence 4321. It can be observed that the rotation directions of the dual phase sequences on the phase sequence wheel are opposite. Since the control dynamics of the dual phase sequences are completely opposite, these dynamics can be completely canceled out by alternating the two phase sequences. This is the so-called method of achieving dynamic cancellation through phase sequence interleaving.

[0100] It should also be noted that, such as Figure 12 As shown, this scheme achieves interleaved phase sequences of 1234 and 1432 by changing the phase shift of the carrier wave once per switching cycle. Since 1432 is the equivalent phase sequence of 4321, this phase sequence interleaving can also achieve dynamic cancellation. Figure 13 and Figure 14 As shown, the dynamic effects of interleaved and non-interleaved phase sequences were compared in the experiment. It can be seen that the interleaved dual phase sequence completely eliminates the voltage oscillation of the flying capacitor, which confirms the feasibility of this application.

[0101] It should also be noted that there are three pairs of dual phase sequences in a five-level multilevel converter circuit, such as... Figure 15 As shown, besides the five-level multilevel converter, other levels also have the concept of dual phase sequence, such as the four-level phase sequence wheel. Figure 16 As shown.

[0102] It should also be noted that the phase sequence alternation can occur once per switching cycle or once per multiple switching cycles, such as... Figure 17 As shown, for example, the phase sequence is switched once every 1 switching cycle, or once every 2 switching cycles.

[0103] It should also be noted that in practical applications, interleaved phase sequence modulation can be implemented using sawtooth waves, or other wave types such as triangular waves. Figure 18 As shown, if the PWM wave corresponding to the triangular wave carrier is transmitted to each switch of the multilevel converter, the adjacent switches corresponding to adjacent PWM waves will be in the same state for a period of time. As for the actual effect of other waveforms, this application does not make any special limitations here, as long as the voltage of the flying capacitor is balanced.

[0104] This embodiment provides a control method for a multilevel converter. When the flying capacitor voltage of the multilevel converter is in an uneven voltage state, this scheme determines a set of dual upper arm switch control sequences and a set of lower arm switch control sequences based on the number of switches in the multilevel converter, and generates corresponding upper arm PWM waves and lower arm PWM waves to control the opening and closing of the upper arm and lower arm switches. Because sending a pair of dual upper arm PWM waves and a pair of lower arm PWM waves in adjacent cycles can balance the voltage of the flying capacitor, this scheme periodically sends the first upper arm PWM wave, the second upper arm PWM wave, the first lower arm PWM wave, and the second lower arm PWM wave to balance the flying capacitor voltage as much as possible, thereby eliminating the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is in an uneven voltage state.

[0105] Based on the above embodiments:

[0106] As an optional embodiment, determining whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state includes:

[0107] Determine the bus voltage of the bus capacitor of the multilevel converter;

[0108] Determine whether the bus voltage is within the preset voltage range;

[0109] If the bus voltage is within the preset voltage range, it is determined that the flying capacitor voltage of the multilevel converter is not in the uneven voltage state.

[0110] If the bus voltage is not within the preset voltage range, then the flying capacitor voltage of the multilevel converter is determined to be in the uneven voltage state.

[0111] In this invention, considering that whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state is related to the magnitude of the bus voltage of the bus capacitor, this solution first determines the bus voltage of the bus capacitor of the multilevel converter, and then determines whether the bus voltage is within a preset voltage range. If the bus voltage is within the preset voltage range, it proves that the flying capacitor voltage of the multilevel converter is not in the uneven voltage state; conversely, if the bus voltage is not within the preset voltage range, it proves that the flying capacitor voltage of the multilevel converter is not in the uneven voltage state, thus ensuring the completeness and accuracy of the uneven voltage state judgment process.

[0112] As an optional embodiment, determining the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors includes:

[0113] A set of dual phase sequence disks is determined based on the number of the first switch transistors and the number of the second switch transistors;

[0114] The control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm are determined based on the dual phase sequence wheel.

[0115] In this invention, considering that the control sequences of the first and second switches of the upper bridge arm are mutually dual, and the control sequences of the first and second switches of the lower bridge arm are mutually dual, and that the dual phase sequence can be determined by the corresponding phase sequence wheel based on the number of switches, thereby determining the mutually dual switch control sequence, this scheme first determines a set of dual phase sequence wheels based on the number of the first and second switches, and then determines the control sequences of the first, second, and third switches of the upper bridge arm, the first, and second switches of the lower bridge arm based on the dual phase sequence wheels, thus ensuring the completeness and accuracy of the process for determining the mutually dual switch control sequence.

[0116] As an optional embodiment, determining the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the dual phase sequence wheel includes:

[0117] The dual phase sequence wheel determines N upper bridge arm switch control sequence combinations and N lower bridge arm switch control sequence combinations with dual phase sequence relationships.

[0118] Select any target upper arm switch sequence control combination from the various upper arm switch sequence control combinations, and use the upper arm switch sequence corresponding to the target upper arm switch sequence control combination as the first upper arm switch control sequence and the second upper arm switch control sequence.

[0119] Select a target lower arm switch sequence control combination that is opposite to the target upper arm switch sequence control combination from each of the lower arm switch sequence control combinations, and use the lower arm switch sequence corresponding to the target lower arm switch sequence control combination as the first switch control sequence and the second switch control sequence of the lower arm.

[0120] In this invention, considering that the number of switches on the upper and lower arms of the multilevel converter determines the number of dual phase sequence switching control sequences, and that in actual control, only one set of mutually dual switching control sequences needs to be selected to balance the voltage of the flying capacitor, this scheme first determines N combinations of upper arm switching control sequences and N combinations of lower arm switching control sequences with dual phase sequence relationships based on the dual phase sequence wheel. Then, a target upper arm switching sequence control sequence is selected from each of the upper arm switching sequence control sequences, and the upper arm switching sequence corresponding to the target upper arm switching sequence control sequence is taken as the first and second upper arm switching control sequences. Similarly, a target lower arm switching sequence control sequence that is opposite to the target upper arm switching sequence control sequence is selected from each of the lower arm switching sequence control sequences, and the lower arm switching sequence corresponding to the target lower arm switching sequence control sequence is taken as the first and second lower arm switching control sequences. The selection of a set of mutually paired upper arm switch control sequences and a set of mutually paired lower arm switch control sequences was accurately completed, improving the reliability of the scheme.

[0121] As an optional embodiment, after the flying capacitor of the multilevel converter is in an uneven voltage state, the following further step is included:

[0122] Based on the time of occurrence of the uneven pressure state and the uneven pressure state, a corresponding fault report is generated, and the alarm device is controlled to issue a corresponding alarm.

[0123] In this invention, considering that when the flying capacitor of the multilevel converter is in an uneven voltage state, on the one hand, it is necessary to automatically switch the switching sequence, and on the other hand, for the safety of the multilevel converter, it is also necessary for users or maintenance personnel to observe the voltage oscillation of the multilevel converter in real time, this solution will generate a corresponding fault report based on the time of the uneven voltage state after determining that the flying capacitor of the multilevel converter is in an uneven voltage state, so that users or maintenance personnel can check it later. In addition, in order to enable users or maintenance personnel to observe the uneven voltage state of the flying capacitor of the multilevel converter in a timely manner, this solution will also control the issuance of corresponding alarms during the alarm period to improve the safety and reliability of the solution.

[0124] As an optional embodiment, the step of periodically sending the first upper-arm PWM wave and the second upper-arm PWM wave to the upper-arm switch of the multilevel converter and periodically sending the first lower-arm PWM wave and the second lower-arm PWM wave to the lower-arm switch of the multilevel converter within a preset period range includes:

[0125] Determine the preset upper bridge arm PWM wave transmission sequence and the preset lower bridge arm PWM wave transmission sequence;

[0126] Within the preset period, the first upper arm PWM wave and the second upper arm PWM wave are sent to the upper arm switching transistor in the preset upper arm PWM wave transmission order.

[0127] Within the preset period, the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are sent to the lower bridge arm switch in the preset lower bridge arm PWM wave sending order, and the number of the first upper bridge arm PWM wave, the second upper bridge arm PWM wave, the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are equal.

[0128] In this invention, considering that sequentially sending a pair of mutually paired upper bridge arm PWM waves and a pair of mutually paired lower bridge arm PWM waves within adjacent cycles can completely balance the voltage of the flying capacitor, it is undoubtedly known that whether the voltage of the flying capacitor can be completely balanced within a preset cycle range depends on the number of mutually paired upper bridge arm PWM waves and mutually paired lower bridge arm PWM waves. Therefore, this scheme first determines the preset upper bridge arm PWM wave sending order and the preset lower bridge arm PWM wave sending order, and then sequentially sends the first upper bridge arm PWM wave and the second upper bridge arm PWM wave to the upper bridge arm switch in the preset cycle range according to the preset upper bridge arm PWM wave sending order. At the same time, within the preset cycle range, sequentially sends the first lower bridge arm PWM wave and the second lower bridge arm PWM wave to the lower bridge arm switch in the preset lower bridge arm PWM wave sending order. However, in order to completely balance the voltage of the flying capacitor, the number of the first upper bridge arm PWM wave, the second upper bridge arm PWM wave, the first lower bridge arm PWM wave, and the second lower bridge arm PWM wave are equal. Therefore, this scheme can completely eliminate the voltage oscillation effect of the multilevel converter when the voltage of the flying capacitor is uneven.

[0129] It should be noted that in practical applications, for example, within a preset cycle range, there are four switching cycles. In the first and second switching cycles, the phase sequence can be selected as 1234, and in the third and fourth switching cycles, the phase sequence can be selected as 4321. As long as the number of the first upper bridge arm PWM waves and the second upper bridge arm PWM waves that are mutually dual within the preset cycle range are the same, the voltage of the flying capacitor can be completely balanced, thereby completely eliminating the voltage oscillation effect of the multilevel converter when the flying capacitor voltage is in an uneven voltage state.

[0130] As an optional embodiment, after periodically sending the first upper-arm PWM wave and the second upper-arm PWM wave to the upper-arm switch of the multilevel converter and periodically sending the first lower-arm PWM wave and the second lower-arm PWM wave to the lower-arm switch of the multilevel converter within a preset period range, the method further includes:

[0131] Determine whether the upper bridge arm switch and the lower bridge arm switch perform corresponding switching actions within a preset time.

[0132] If the upper arm switch or the lower arm switch performs the corresponding switching action within a preset time, it is determined that the upper arm switch and the lower arm switch are not faulty.

[0133] If the upper arm switch or the lower arm switch fails to perform the corresponding switching action within a preset time, it is determined that the upper arm switch or the lower arm switch has malfunctioned, and the alarm device is controlled to issue a corresponding alarm.

[0134] Please refer to Figure 19 , Figure 19 A schematic diagram of a control device for a multilevel converter provided by the present invention. The control device for the multilevel converter includes:

[0135] Judgment unit 11 is used to determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state;

[0136] The first determining unit 12 is used to determine the number of first switching transistors in the upper arm and the number of second switching transistors in the lower arm of the multilevel converter when the flying capacitor of the multilevel converter is in an uneven voltage state.

[0137] The second determining unit 13 is used to determine the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors. The control sequence of the first switch of the upper bridge arm and the control sequence of the second switch of the upper bridge arm are paired with each other, the control sequence of the first switch of the lower bridge arm and the control sequence of the second switch of the lower bridge arm are paired with each other, the control sequence of the first switch of the upper bridge arm and the control sequence of the first switch of the lower bridge arm are opposite to the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the upper bridge arm and the control sequence of the second switch of the lower bridge arm are opposite to the control sequence of the second switch of the lower bridge arm.

[0138] The transmitting unit 14 is configured to generate corresponding first upper arm PWM wave, second upper arm PWM wave, first lower arm PWM wave and second lower arm PWM wave based on the control sequence of the first upper arm switch, the control sequence of the second upper arm switch, the control sequence of the first lower arm switch, the control sequence of the second lower arm switch and a preset duty cycle, and periodically transmit the first upper arm PWM wave and the second upper arm PWM wave to the upper arm switch of the multilevel converter and periodically transmit the first lower arm PWM wave and the second lower arm PWM wave to the lower arm switch of the multilevel converter within a preset period range.

[0139] The control device for the multilevel converter provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above. Therefore, for the embodiment of the control device of the multilevel converter, please refer to the description of the embodiment in the method section, which will not be repeated here.

[0140] Please refer to Figure 20 , Figure 20 A schematic diagram of the structure of an electronic device provided by the present invention. The electronic device includes:

[0141] Memory 20 is used to store computer programs;

[0142] The processor 21 is configured to implement the steps of the control method for the multilevel converter as described above when executing the computer program.

[0143] The electronic devices provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.

[0144] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0145] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the control method for the multilevel converter disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the control method for the multilevel converter.

[0146] In some embodiments, the electronic device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0147] Those skilled in the art will understand that Figure 20 The structures shown do not constitute a limitation on electronic devices and may include more or fewer components than those shown.

[0148] The purpose of this embodiment is to provide an electronic device in which the memory 20 is used to store computer programs and the processor 21 is used to execute the computer programs to implement the steps of the control method of the multilevel converter described above, so that the control process is more efficient and accurate.

[0149] The present invention also provides an embodiment corresponding to a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps of the control method for the multilevel converter as described above.

[0150] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0151] The computer-readable storage medium provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above. Therefore, for the embodiments of the computer-readable storage medium, please refer to the description of the embodiments in the method section, which will not be repeated here.

[0152] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0153] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method for a multilevel converter, characterized in that, include: Determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state; If the flying capacitor of the multilevel converter is in an uneven voltage state, then determine the number of first switches in the upper arm and the number of second switches in the lower arm of the multilevel converter. The control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm are determined according to the number of the first switch transistors and the number of the second switch transistors. The control sequence of the first switch of the upper bridge arm and the control sequence of the second switch of the upper bridge arm are mutually paired, the control sequence of the first switch of the lower bridge arm and the control sequence of the second switch of the lower bridge arm are mutually paired, the control sequence of the first switch of the upper bridge arm and the control sequence of the first switch of the lower bridge arm are opposite to the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the upper bridge arm and the control sequence of the second switch of the lower bridge arm are opposite to the control sequence of the second switch of the lower bridge arm. Based on the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, the control sequence of the second switch of the lower bridge arm, and the preset duty cycle, corresponding first upper bridge arm PWM wave, second upper bridge arm PWM wave, first lower bridge arm PWM wave, and second lower bridge arm PWM wave are generated. Within a preset period range, the first upper bridge arm PWM wave and the second upper bridge arm PWM wave are periodically sent to the upper bridge arm switch of the multilevel converter, and the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are periodically sent to the lower bridge arm switch of the multilevel converter. The step of determining the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors includes: A set of dual phase sequence wheel is determined based on the number of the first switch tube and the number of the second switch tube. Two control phase sequences with completely opposite dynamics are dual phase sequences, and the rotation directions of the dual phase sequences on the phase sequence wheel are opposite. The control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, and the control sequence of the first switch of the lower bridge arm are determined based on the dual phase sequence wheel. The determination of the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the dual phase sequence wheel includes: Based on the dual phase sequence wheel, determine N upper bridge arm switch control sequence combinations and N lower bridge arm switch control sequence combinations with dual phase sequence relationship, where N≥1; Select any target upper arm switch sequence control combination from the various upper arm switch sequence control combinations, and use the upper arm switch sequence corresponding to the target upper arm switch sequence control combination as the first upper arm switch control sequence and the second upper arm switch control sequence. Select a target lower arm switch sequence control combination that is opposite to the target upper arm switch sequence control combination from each of the lower arm switch sequence control combinations, and use the lower arm switch sequence corresponding to the target lower arm switch sequence control combination as the first switch control sequence and the second switch control sequence of the lower arm.

2. The control method for the multilevel converter as described in claim 1, characterized in that, The determination of whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state includes: Determine the bus voltage of the bus capacitor of the multilevel converter; Determine whether the bus voltage is within the preset voltage range; If the bus voltage is within the preset voltage range, it is determined that the flying capacitor voltage of the multilevel converter is not in the uneven voltage state; If the bus voltage is not within the preset voltage range, then the flying capacitor voltage of the multilevel converter is determined to be in the uneven voltage state.

3. The control method for a multilevel converter as described in claim 1, characterized in that, If the flying capacitor of the multilevel converter is in an uneven voltage state, the following steps are also included: Based on the time of occurrence of the uneven pressure state and the uneven pressure state, a corresponding fault report is generated, and the alarm device is controlled to issue a corresponding alarm.

4. The control method for the multilevel converter as described in claim 1, characterized in that, The step of periodically sending the first upper-arm PWM wave and the second upper-arm PWM wave to the upper-arm switch of the multilevel converter and periodically sending the first lower-arm PWM wave and the second lower-arm PWM wave to the lower-arm switch of the multilevel converter within a preset period range includes: Determine the preset upper bridge arm PWM wave transmission sequence and the preset lower bridge arm PWM wave transmission sequence; Within the preset period, the first upper arm PWM wave and the second upper arm PWM wave are sent to the upper arm switching transistor in the preset upper arm PWM wave transmission order. Within the preset period, the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are sent to the lower bridge arm switch in the preset lower bridge arm PWM wave sending order, and the number of the first upper bridge arm PWM wave, the second upper bridge arm PWM wave, the first lower bridge arm PWM wave and the second lower bridge arm PWM wave are equal.

5. The control method for a multilevel converter as described in any one of claims 1 to 4, characterized in that, After periodically sending the first upper-arm PWM wave and the second upper-arm PWM wave to the upper-arm switch of the multilevel converter within a preset period range, and periodically sending the first lower-arm PWM wave and the second lower-arm PWM wave to the lower-arm switch of the multilevel converter, the process further includes: Determine whether the upper bridge arm switch and the lower bridge arm switch perform corresponding switching actions within a preset time. If the upper arm switch or the lower arm switch performs the corresponding switching action within a preset time, it is determined that the upper arm switch and the lower arm switch are not faulty. If the upper arm switch or the lower arm switch fails to perform the corresponding switching action within a preset time, it is determined that the upper arm switch or the lower arm switch has malfunctioned, and the alarm device is controlled to issue a corresponding alarm.

6. A control device for a multilevel converter, characterized in that, The control method applied to the multilevel converter according to any one of claims 1-5 includes: The judgment unit is used to determine whether the flying capacitor voltage of the multilevel converter is in an uneven voltage state. The first determining unit is used to determine the number of first switching transistors in the upper arm and the number of second switching transistors in the lower arm of the multilevel converter when the flying capacitor of the multilevel converter is in an uneven voltage state. The second determining unit is used to determine the control sequence of the first switch of the upper bridge arm, the control sequence of the second switch of the upper bridge arm, the control sequence of the first switch of the lower bridge arm, and the control sequence of the second switch of the lower bridge arm based on the number of the first switch transistors and the number of the second switch transistors. The control sequence of the first switch of the upper bridge arm and the control sequence of the second switch of the upper bridge arm are paired, the control sequence of the first switch of the lower bridge arm and the control sequence of the second switch of the lower bridge arm are paired, the control sequence of the first switch of the upper bridge arm and the control sequence of the first switch of the lower bridge arm are opposite, and the control sequence of the second switch of the upper bridge arm and the control sequence of the second switch of the lower bridge arm are opposite. The transmitting unit is configured to generate corresponding first upper arm PWM waves, second upper arm PWM waves, first lower arm PWM waves, and second lower arm PWM waves based on the control sequence of the first upper arm switch, the control sequence of the second upper arm switch, the control sequence of the first lower arm switch, the control sequence of the second lower arm switch, and a preset duty cycle, and periodically transmit the first upper arm PWM waves and the second upper arm PWM waves to the upper arm switch of the multilevel converter and periodically transmit the first lower arm PWM waves and the second lower arm PWM waves to the lower arm switch of the multilevel converter within a preset period range.

7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the control method for the multilevel converter as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the control method for the multilevel converter as described in any one of claims 1 to 5.

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