Ultra-wideband passive delay

Abstract

The present application relates to a kind of ultra-wideband passive delay, comprising: a plurality of delay units with different delay time, and a control unit;First delay unit receives the signal of full-band range;Each delay unit includes: two single-pole double-throw switches, and passive delay and transmission unit between the two single-pole double-throw switches;In a delay unit, the control end of the two single-pole double-throw switches is connected with the control unit, and in response to different control signals sent by the control unit, passive delay or transmission unit is synchronously turned on, so that passive delay carries out delay processing to the signal input into passive delay, and the signal after delay processing is transmitted to the next delay unit;Or, so that transmission unit transmits the signal input into transmission unit to the next delay unit.The device can not be limited by bandwidth, process high-quality ultra-wide range radar signal, meet design requirements.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog integrated circuits, and particularly relates to an ultra-wideband passive delay. BACKGROUND

[0002] Ultra Wide Band (UWB) technology is a wireless carrier communication technology, which does not use a sine carrier, but transmits data by using a nanosecond-level non-sine wave narrow pulse, so that the frequency spectrum range occupied thereby is very wide. The UWB technology solves the major problem of propagation that has plagued traditional wireless communication technologies for many years, and has the advantages of being not sensitive to channel fading, having low transmit signal power spectrum density, low interception rate, low system complexity, and being able to provide a positioning accuracy of several centimeters. With the development of the ultra-wideband radar, the traditional delay cannot process the ultra-wide range of radar signals due to the bandwidth limitation, and cannot meet the design requirements. SUMMARY

[0003] In order to solve the above problems existing in the prior art, the application provides an ultra-wideband passive delay. The technical problem to be solved by the application is solved by the following technical scheme:

[0004] The application provides an ultra-wideband passive delay, comprising: a plurality of delay units with different delay time lengths, and a control unit; control ends of the plurality of delay units are connected with the control unit; a first delay unit in the plurality of delay units receives a signal in a full frequency band range; wherein each delay unit comprises: two single-pole double-throw switches, and a passive delay and a transmission unit arranged between the two single-pole double-throw switches; in a delay unit, control ends of the two single-pole double-throw switches are connected with the control unit, for synchronously turning on the passive delay or the transmission unit in response to different control signals sent by the control unit, so as to make the passive delay perform delay processing on a signal input into the passive delay, and transmit the signal after delay processing to a next delay unit; or, so as to make the transmission unit transmit a signal input into the transmission unit to the next delay unit.

[0005] Compared with the prior art, the application has the beneficial effects:

[0006] In view of the problem that the traditional time delay device cannot process radar signals in a super wide range due to bandwidth limitation and cannot meet design requirements, the application provides an ultra-wideband passive time delay device, which comprises a plurality of time delay units with different time delay lengths, and each time delay unit is provided with two passing paths, one path can delay the input signal in the full frequency band range, and the other path can pass the input signal to the next unit, wherein the specific communication path of the signal is determined by synchronously turning on or turning off the two single-pole double-throw switches in response to the control signal, which can effectively improve the control accuracy of the time delay device; based on the different conduction states of the plurality of units, the time delay device for different frequency band ranges is simulated to flexibly process the input signal in the full frequency band range, which can greatly expand the bandwidth, and by setting different time delay lengths for each time delay unit, the small time delay unit and the large time delay unit can be covered, which helps to improve the time delay flatness of the device, reduce the insertion loss, well retain the characteristics and power of the input signal, and ensure the signal transmission quality. The ultra-wideband passive time delay device provided by the application can process radar signals in a super wide range without bandwidth limitation and high quality, which meets the design requirements. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a structural block diagram of the ultra-wideband passive time delay device provided by the embodiment of the application;

[0008] Figure 2 is an example block diagram of the ultra-wideband passive time delay device provided by the embodiment of the application;

[0009] Figure 3 is a circuit connection schematic diagram of the first passive time delay device provided by the embodiment of the application;

[0010] Figure 4 is a circuit connection schematic diagram of the second passive time delay device provided by the embodiment of the application;

[0011] Figure 5 is a circuit connection schematic diagram of the fourth passive time delay device provided by the embodiment of the application;

[0012] Figure 6 is a circuit connection block diagram of the fifth passive time delay device provided by the embodiment of the application;

[0013] Figure 7 is a circuit connection block diagram of the sixth passive time delay device provided by the embodiment of the application;

[0014] Figure 8 is a circuit connection block diagram of the sixth passive time delay device provided by the embodiment of the application; Figure 2 is an example diagram of the normalized time delay signal output by the ultra-wideband passive time delay device when 12 single-pole double-throw switches are turned on in the passive time delay device and / or the transmission unit;

[0015] Figure 9is an embodiment of the present application Figure 2 is an example graph of the maximum delay error and the root mean square error corresponding to the ultra-wideband passive delay device in the present application

[0016] Figure 10 is an embodiment of the present application Figure 2 is an example graph of the insertion loss variation corresponding to the ultra-wideband passive delay device in the present application when processing signals in the full frequency band range in different delay states. DETAILED DESCRIPTION

[0017] The present application will be further described below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0018] In the description of the present application, the terms "first", "second", are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0019] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the drawings, the disclosure, and the appended claims in the process of implementing the claimed present application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Some measures are recorded in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0020] The ultra-wideband passive delay device proposed by the present application will be described in detail in conjunction with the drawings. Figure 1 is a structural block diagram of the ultra-wideband passive delay device provided by an embodiment of the present application. As shown in Figure 1As shown, the ultra-wideband passive delay device includes a plurality of delay units with different delay time lengths and a control unit; control ends of the plurality of delay units are connected with the control unit; a first delay unit of the plurality of delay units receives a signal in a full-band range; wherein each delay unit includes two single-pole double-throw switches and a passive delay device and a transmission unit arranged between the two single-pole double-throw switches; in a delay unit, control ends of the two single-pole double-throw switches are connected with the control unit, for synchronously turning on the passive delay device or the transmission unit in response to different control signals sent by the control unit, so as to make the passive delay device delay the signal input into the passive delay device and transmit the delayed signal to the next delay unit; or make the transmission unit transmit the signal input into the transmission unit to the next delay unit.

[0021] Here, the preset bandwidth range is 2GHz-18GHz. The control unit is a digital control unit, which determines the route of the signal by sending a digital control signal to the single-pole double-throw switch. The digital control signal includes a high-level signal and a low-level signal. When the digital control signal is a high-level signal, the passive delay device is turned on. When the digital control signal is a low-level signal, the transmission unit is turned on. Exemplarily, the voltage of the high-level signal is 2.5V, and the voltage of the low-level signal is 0V.

[0022] Here, the use of single-pole double-throw switches can achieve good matching with the overall circuit, has high isolation and low insertion loss, thereby effectively reducing the insertion loss of the overall circuit. It should be noted that the types of single-pole double-throw switches in each delay unit are the same.

[0023] Figure 2 is an example block diagram of the ultra-wideband passive delay device provided by the embodiment of the present application. As shown in the figure, Figure 2 In a possible implementation, the plurality of delay units includes a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit and a sixth delay unit; wherein the transmission units in the first delay unit to the fourth delay unit are all transmission lines, and the transmission units in the fifth delay unit and the sixth delay unit are both all-pass networks; and the delay time length of the first delay unit is the shortest, and the delay time length of the sixth delay unit is the longest.

[0024] It should be noted that the structure, material and type of the transmission line in different passive delay devices are the same. The all-pass network is an APN model, which includes a first inductor, a second inductor, a first capacitor and a second capacitor; two ends of the first capacitor are respectively a signal input end and a signal output end, one end of the first inductor and one end of the second inductor are connected with the signal input end and the signal output end, the other end of the first inductor and the other end of the second inductor are both connected with one end of the second capacitor, and the second capacitor is grounded.

[0025] It should be noted that the delay time length corresponding to each delay unit is a relative delay time length. Since the signal will produce a delay time length after passing through the transmission unit, the difference between the delay time length produced by the signal passing through the transmission unit and the delay time length produced by the signal passing through the passive delay device is the delay time length corresponding to each delay unit. Taking the fourth delay unit as an example, the delay time length of the fourth passive delay device inside it is 54ps, and the delay time length of the transmission unit connected in parallel with the fourth passive delay device is 6ps, and the difference between the two is the relative delay time length (48ps) of the fourth delay unit.

[0026] Exemplarily, the (relative) delay time length of the first delay unit is 6ps, the (relative) delay time length of the second delay unit is 12ps, the (relative) delay time length of the third delay unit is 24ps, the (relative) delay time length of the fourth delay unit is 48ps, the (relative) delay time length of the fifth delay unit is 96ps, and the (relative) delay time length of the sixth delay unit is 192ps. When the six delay units are all turned on, the input signal will be relatively delayed (6+12+24+48+96+192)ps. When the six delay units are partially turned on, the delay time length corresponding to the turned-on delay unit is the delay time length of the input signal.

[0027] It should be understood that the delay time length corresponding to each delay unit here can be adjusted according to the actual design requirements, such as adjusting the inductance or capacitance inside the delay unit to change the delay time length corresponding to the delay unit. For example, in order to improve the delay precision, the delay time length of the first delay unit is reduced to 3ps, and in order to provide a longer delay time length, the delay time length of the sixth delay unit is increased to 220ps.

[0028] It should be understood that this is only an example, and in actual operation, the number of delay units can be increased or decreased according to requirements.

[0029] In one possible implementation, in the first delay unit, the first passive delay device is connected in parallel between the single-pole double-throw switch S1 and the single-pole double-throw switch S2. Figure 3 is a circuit connection schematic diagram of the first passive delay device provided by the embodiment of the application. As shown in Figure 3 The first passive delay device includes a capacitor C1, a capacitor C2 and an inductor L1; wherein the inductor L1 is arranged between the single-pole double-throw switch S1 and the single-pole double-throw switch S2, the capacitor C1 is arranged between the inductor L1 and the single-pole double-throw switch S1, and one end of the capacitor C1 is grounded; the capacitor C2 is arranged between the inductor L1 and the single-pole double-throw switch S2, and one end of the capacitor C2 is grounded.

[0030] Here, the first passive delay device adopts an ATL model of a pi-type CLC structure, has a small model layout area and a simple structure, only has an inductor L1 and two same capacitors C1 and C2, has high delay flatness in a full frequency band of 2-18 GHz, and has small insertion loss.

[0031] In a possible implementation, in the second delay unit, the second passive delay device is connected in parallel with the transmission line line2 between the single-pole double-throw switch S3 and the single-pole double-throw switch S4; in the third delay unit, the third passive delay device is connected in parallel with the transmission line line3 between the single-pole double-throw switch S5 and the single-pole double-throw switch S6; and the second passive delay device and the third passive delay device have the same structure. Specifically, the second passive delay device and the third passive delay device both adopt an APN structure, and compared with an ATL structure, the APN structure has a smaller layout area, high delay flatness in a full frequency band of 2-18 GHz, and small insertion loss.

[0032] Figure 4 is a circuit connection schematic diagram of the second passive delay device provided by the embodiment of the present application. As shown in Figure 4 , the second passive delay device includes a capacitor C3, a capacitor C4, an inductor L3, and an inductor L4; the capacitor C3 is arranged between the single-pole double-throw switch S3 and the single-pole double-throw switch S4, one end of the inductor L3 is arranged between the capacitor C3 and the single-pole double-throw switch S3, the other end is connected with one end of the capacitor C4, one end of the inductor L4 is arranged between the capacitor C3 and the single-pole double-throw switch S4, and the other end is also connected with one end of the capacitor C4; and the other end of the capacitor C4 is grounded.

[0033] Similarly, the third passive delay device includes a capacitor C5, a capacitor C6, an inductor L5, and an inductor L6; the capacitor C5 is arranged between the single-pole double-throw switch S3 and the single-pole double-throw switch S4, one end of the inductor L5 is arranged between the capacitor C5 and the single-pole double-throw switch S3, the other end is connected with one end of the capacitor C6, one end of the inductor L6 is arranged between the capacitor C5 and the single-pole double-throw switch S4, and the other end is also connected with one end of the capacitor C6; and the other end of the capacitor C6 is grounded.

[0034] In a possible implementation, in the fourth delay unit, the fourth passive delay device is connected in parallel with the transmission line line4 between the single-pole double-throw switch S7 and the single-pole double-throw switch S8; Figure 5 is a circuit connection schematic diagram of the fourth passive delay device provided by the embodiment of the present application. As shown in Figure 5 , the fourth passive delay device includes a first delay module and a second delay module connected in sequence; and the delay time of the first delay module is less than the delay time of the second delay module. Exemplarily, the delay time corresponding to the first delay module is 20 ps, the delay time of the second delay module is 32 ps, and the delay time of the transmission line line4 is 6 ps.

[0035] Here, the first delay module includes two ATL models of π-type CLC structures connected in sequence. Specifically, the first delay module includes: inductor L7, inductor L8, inductor L9, inductor L10, inductor L11, inductor L12, capacitor C7, capacitor C8, capacitor C9 and capacitor C10; inductor L7 and inductor L8 are connected in sequence between single-pole double-throw switch S7 and the second delay module, capacitor C7 and inductor L9 are connected in series between inductor L7 and single-pole double-throw switch S7, and one end of inductor L9 is grounded; capacitor C8 and inductor L10 are connected in series between inductor L7 and inductor L8, and one end of inductor L10 is grounded; capacitor C9 and inductor L11 are connected in parallel with capacitor C8 and inductor L10, and one end of inductor L11 is grounded; capacitor C10 and inductor L12 are connected in series between inductor L8 and the second delay module, and one end of inductor L12 is grounded.

[0036] Here, capacitors C7, C8, C9, and C10 have the same structure, and inductors L9, L10, L11, and L12 have the same value. This setting can ensure that the signal delay has good flatness.

[0037] Here, the second delay module includes an APN model. Specifically, the second delay module includes: capacitor C11, capacitor C12, inductor L13, and inductor L14; capacitor C11 is arranged between inductor L8 and single-pole double-throw switch S8, one end of inductor L13 is connected to one end of capacitor C11, the other end of inductor L13 is connected to one end of capacitor C12, one end of inductor L14 is connected to the other end of capacitor C11, the other end of inductor L14 is connected to one end of capacitor C12, and the other end of capacitor C12 is grounded.

[0038] In one possible implementation, Figure 6 : is a circuit connection block diagram of a fifth passive delay device provided by an embodiment of the present invention, such as Figure 6 As shown, in the fifth delay unit, the fifth passive delay element and the all-pass network Ref-APN1 are connected in parallel between single-pole double-throw switch S9 and single-pole double-throw switch S10. The third, fourth, fifth, and sixth delay modules are connected in sequence. The structures of the third and fourth delay modules are identical to those of the second delay module, while the structures of the fifth and sixth delay modules are identical to those of the first delay module. Here, the delay length of the all-pass network Ref-APN1 is set to 12 ps.

[0039] In one possible implementation, Figure 7 : is a circuit connection block diagram of a sixth passive delay device provided by an embodiment of the present invention, such as Figure 7As shown, in the sixth delay unit, the sixth passive delay device and the all-pass network Ref-APN2 are connected in parallel between the single-pole double-throw switch S11 and the single-pole double-throw switch S12. The sixth passive delay device includes a seventh delay module, an eighth delay module, a ninth delay module, a tenth delay module, an eleventh delay module, a twelfth delay module, a thirteenth delay module, and a fourteenth delay module. The structures of the seventh, eighth, ninth, and tenth delay modules are the same as those of the first delay module, and the structures of the eleventh, twelfth, thirteenth, and fourteenth delay modules are the same as those of the second delay module. Here, the delay length of the all-pass network Ref-APN2 is set to 24 ps.

[0040] In order to verify the output effect of the ultra-wideband passive delay device provided by the present invention, a Figure 2 The circuit chip of the ultra-wideband passive delay device is soldered on the test fixture PCB to test it. Figure 8 The embodiment of the present invention provides Figure 2 An example diagram of the normalized delay signal output by the ultra-wideband passive delay device when 12 single-pole double-throw switches turn on the passive delay device and / or the transmission unit is shown in FIG. Figure 8 As shown, the vertical axis is the normalized group delay signal output by the ultra-wideband passive delay device, and the horizontal axis is the signal frequency range. The six delay units can produce 64 different delay states. Under different delay states, the adjustable effect of the normalized group delay changes approximately linearly with the signal frequency value, is less affected by the signal frequency, and has excellent flatness.

[0041] Figure 9 The embodiment of the present invention provides Figure 2 The maximum delay error and root mean square error of the ultra-wideband passive delay device in the figure are tested when processing signals in the full frequency band. Figure 9 As shown, the root mean square error (i.e. Figure 9 The average value of RMS ERROR in the delay time is 4.1ps, and the maximum delay error (i.e. Figure 9 The average value of MAX ERROR in is 8ps, which shows that the ultra-wideband passive delay device provided by the embodiment of the present invention has extremely high control accuracy.

[0042] Figure 10 The embodiment of the present invention provides Figure 2 When the ultra-wideband passive delay device in the figure processes the full-band signal under different delay conditions, the corresponding insertion loss changes are shown in the figure. Figure 10 As shown, under 64 different delay states, the insertion loss (S21) is in the range of 5dB to 18dB, and the root mean square error of the delay is less than 6ps of the minimum delay unit, which can well preserve the characteristics and power of the input signal and ensure the quality of signal transmission.

[0043] In order to solve the problem that the traditional delay device cannot process radar signals in a super wide range due to bandwidth limitation and cannot meet design requirements, the application provides a super wideband passive delay device, which comprises a plurality of delay units with different delay time lengths, and each delay unit is provided with two passing paths, one path can delay the input signal in a full frequency band range, and the other path can pass the input signal to the next unit, wherein two single-pole double-throw switches are used to determine the specific communication path of the signal by synchronously turning on or off in response to a control signal, so as to effectively improve the control accuracy of the delay device; based on the different conduction states of the plurality of units, the delay device for different frequency band ranges is simulated to flexibly process the input signal in the full frequency band range, which can greatly expand the bandwidth, and by setting different delay time lengths for each delay unit, the small delay unit and the large delay unit can be covered, which helps to improve the delay flatness of the device, reduce the insertion loss, well reserve the characteristics and power of the input signal, and ensure the signal transmission quality. The super wideband passive delay device provided by the application can process radar signals in a super wide range without bandwidth limitation and with high quality, and can meet the design requirements.

[0044] The above is a further detailed description of the application in combination with specific preferred embodiments, and the specific implementation of the application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the application belongs, some simple deductions or substitutions can be made without departing from the concept of the application, and all of them should be regarded as falling within the protection scope of the application.

Claims

1. An ultra-wideband passive delay, characterized by, The application relates to a delay unit and a delay device. The delay unit comprises a plurality of delay units with different delay time lengths and a control unit; the control ends of the plurality of delay units are connected with the control unit; the first delay unit of the plurality of delay units receives signals in a full-band range; wherein each delay unit comprises two single-pole double-throw switches, a passive delay device and a transmission unit arranged between the two single-pole double-throw switches; In one delay unit, the control ends of the two single-pole double-throw switches are connected with the control unit, and the passive delay device or the transmission unit is synchronously turned on in response to different control signals sent by the control unit, so that the passive delay device performs delay processing on the signals input into the passive delay device and transmits the delay-processed signals to the next delay unit, or the transmission unit transmits the signals input into the transmission unit to the next delay unit; The plurality of delay units comprise a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit and a sixth delay unit; wherein the transmission units in the first delay unit to the fourth delay unit are transmission lines, the transmission units in the fifth delay unit and the sixth delay unit are all-pass networks; and the delay time length of the first delay unit is the shortest, and the delay time length of the sixth delay unit is the longest; In the fourth delay unit, a fourth passive delay device is connected in parallel with the transmission line line4 between the single-pole double-throw switch S7 and the single-pole double-throw switch S8; wherein the fourth passive delay device comprises a first delay module and a second delay module connected in sequence; the delay time length of the first delay module is shorter than that of the second delay module; The first delay module comprises an inductor L7, an inductor L8, an inductor L9, an inductor L10, an inductor L11, an inductor L12, a capacitor C7, a capacitor C8, a capacitor C9 and a capacitor C10; The inductor L7 and the inductor L8 are connected in sequence between the single-pole double-throw switch S7 and the second delay module, the capacitor C7 and the inductor L9 are connected in series between the inductor L7 and the single-pole double-throw switch S7, one end of the inductor L9 is grounded; the capacitor C8 and the inductor L10 are connected in series between the inductor L7 and the inductor L8, one end of the inductor L10 is grounded; the capacitor C9, the inductor L11 and the capacitor C8, the inductor L10 are connected in parallel, one end of the inductor L11 is grounded; the capacitor C10 and the inductor L12 are connected in series between the inductor L8 and the second delay module, one end of the inductor L12 is grounded.

2. The ultra-wideband passive delay of claim 1, wherein, In the first delay unit, a first passive delay device is connected in parallel with the transmission line line1 between the single-pole double-throw switch S1 and the single-pole double-throw switch S2; the first passive delay device comprises a capacitor C1, a capacitor C2 and an inductor L1; The inductor L1 is arranged between the single-pole double-throw switch S1 and the single-pole double-throw switch S2, the capacitor C1 is arranged between the inductor L1 and the single-pole double-throw switch S1, and one end of the capacitor C1 is grounded; the capacitor C2 is arranged between the inductor L1 and the single-pole double-throw switch S2, and one end of the capacitor C2 is grounded.

3. The ultra-wideband passive delay of claim 1, wherein, In the second delay unit, a second passive delay device is connected in parallel with the transmission line line2 between the single-pole double-throw switch S3 and the single-pole double-throw switch S4; in the third delay unit, a third passive delay device is connected in parallel with the transmission line line3 between the single-pole double-throw switch S5 and the single-pole double-throw switch S6; wherein the second passive delay device and the third passive delay device have the same structure.

4. The ultra-wideband passive delay of claim 3, wherein, The second passive delay device comprises a capacitor C3, a capacitor C4, an inductor L3 and an inductor L4. The capacitor C3 is arranged between the single-pole double-throw switch S3 and the single-pole double-throw switch S4, one end of the inductor L3 is arranged between the capacitor C3 and the single-pole double-throw switch S3, the other end is connected with one end of the capacitor C4, one end of the inductor L4 is arranged between the capacitor C3 and the single-pole double-throw switch S4, and the other end is also connected with one end of the capacitor C4; the other end of the capacitor C4 is grounded.

5. The ultra-wideband passive delay of claim 1, wherein, The second delay module comprises a capacitor C11, a capacitor C12, an inductor L13 and an inductor L14. The capacitor C11 is arranged between the inductor L8 and the single-pole double-throw switch S8, one end of the inductor L13 is connected with one end of the capacitor C11, the other end of the inductor L13 and one end of the capacitor C12 are connected, one end of the inductor L14 is connected with the other end of the capacitor C11, the other end of the inductor L14 and one end of the capacitor C12 are connected, and the other end of the capacitor C12 is grounded.

6. The ultra-wideband passive delay of claim 1, wherein, In the fifth delay unit, a fifth passive delay device and an all-pass network Ref-APN1 are connected in parallel between the single-pole double-throw switch S9 and the single-pole double-throw switch S10. The fifth passive delay device comprises a third delay module, a fourth delay module, a fifth delay module and a sixth delay module connected in sequence; the third delay module and the fourth delay module have the same structure as the second delay module, and the fifth delay module and the sixth delay module have the same structure as the first delay module.

7. The ultra-wideband passive delay of claim 1, wherein, In the sixth delay unit, a sixth passive delay device and an all-pass network Ref-APN2 are connected in parallel between the single-pole double-throw switch S11 and the single-pole double-throw switch S12. The sixth passive delay device comprises a seventh delay module, an eighth delay module, a ninth delay module, a tenth delay module, an eleventh delay module, a twelfth delay module, a thirteenth delay module and a fourteenth delay module connected in sequence; wherein the structures of the seventh delay module, the eighth delay module, the ninth delay module and the tenth delay module are the same as those of the first delay module, and the structures of the eleventh delay module, the twelfth delay module, the thirteenth delay module and the fourteenth delay module are the same as those of the second delay module.

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