Improved FIR filter structure based on distributed algorithm (DA)

Abstract

The invention relates to the technical field of digital filters, and provides an improved FIR filter structure based on a distributed algorithm (DA). The structure comprises a DA table, a partial product selection module and a shift accumulator. Wherein the DA table generates all possible partial products according to input; the partial product selection module selects an actual partial product according to the address sequence; the shift accumulator realizes accumulation and summation of partial products. Compared with the traditional DA-FIR filter, the method disclosed by the invention has the advantage that the consumed lookup table (LUT) and register (FF) resources are obviously reduced.

Description

Technical Field

[0001] The invention relates to the technical field of digital filters, and in particular to an improved FIR filter structure based on a distributed algorithm (DA). Background Art

[0002] In today's digital age, digital signal processing technology plays a key role in fields such as communication, audio processing and image processing.

[0003] A digital filter is a filtering device based on digital signal processing technology, which is used to extract useful information or remove noise from the input signal. Compared with traditional analog filters, digital filters have higher flexibility, programmability and stability. They can achieve complex filtering characteristics, such as low-pass, high-pass, band-pass and band-stop filtering, and can adjust parameters according to specific application requirements. The core of digital filters lies in their algorithm design. Common filter types include FIR filters and IIR (Infinite Impulse Response) filters.

[0004] The basic principle of FIR filter is to filter by weighted summing the input signal. Compared with IIR filter, FIR filter not only has better linear phase characteristics, but also has the advantages of stability, strong flexibility and easy hardware implementation.

[0005] Distributed Algorithm (DA) is often used in the optimization design of FIR filters. This algorithm splits the input digital signal bit by bit and converts the multiplication and addition operation with fixed coefficients into a simple lookup table operation and shift accumulation operation. The specific algorithm is as follows:

[0006] Figure 1 A schematic diagram of a fourth-order traditional DA-FIR filter is given.

[0007] For an FIR filter consisting of N product terms, its output y is the product of the input x. k and coefficient w k The sum of the products of :

[0008] Among them, w k and x k (0≤k≤N-1) represent the kth coefficient and the corresponding input respectively; for a coefficient w with a bit width of L k , which can be expressed as:

[0009] w kl Yes k The value of the lth bit of . Therefore, the output y can be expanded as:

[0010] The partial product y in the above formula l There are N inputs x k And the corresponding coefficient w k The kth bit w kl The sum of the products of (k=0, 1...N-1), for the partial product y l Perform shift accumulation to obtain the output y.

[0011] The generalized parallel counter (GPC) mentioned in "Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs" published by TB Preuβer at the FPL conference is a computing unit in the adder, which is usually used for multi-operand addition. GPC makes full use of the structural characteristics of the lookup table LUT and carry chain in the FPGA chip to combine and arrange the digital signals to be summed in a certain way, thereby achieving compression of the adder. Summary of the invention

[0012] The present invention proposes an improved FIR filter structure based on a DA algorithm, which reduces the number of lookup tables (LUTs) and registers (FFs) consumed by a traditional DA-FIR filter.

[0013] Figure 2 The structure diagram of the improved DA_FIR filter of the present invention is given;

[0014] like Figure 2 As shown, the filter structure of the present invention is composed of three parts: a DA table, a partial product selection module and a shift accumulator;

[0015] The DA table generates all possible partial products based on the input;

[0016] The partial product selection module selects the address sequence {w kl}Select the actual partial product;

[0017] The shift accumulator shifts the accumulated result of the previous clock cycle and accumulates the partial product generated by the current clock cycle to finally obtain the filter output. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the schematic diagram of a 4th-order traditional DA-FIR filter;

[0019] Figure 2It is a structural diagram of the improved DA-FIR filter of the present invention;

[0020] Figure 3 It is the internal structure diagram of the improved DA table of the present invention;

[0021] Figure 4 is an internal structure diagram of a partial product selection module of the present invention;

[0022] Figure 5 It is a structural diagram of the shift accumulator of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0024] The present invention converts the address sequence {w kl} are grouped, and the following takes the 4th-order FIR filter as an example:

[0025] In the above formula, the partial product Partial Product

[0026] Figure 3 The internal structure diagram of the improved DA table of the present invention is given;

[0027] like Figure 3 As shown, the improved DA table consists of six registers and two adders. The serially input data x_i is shifted and summed to generate six possible partial products (x1, x0, x1+x0, x3, x2, x3+x2).

[0028] Figure 4 The internal structure diagram of the partial product selection module of the present invention is given;

[0029] like Figure 4 As shown, the partial product selection module is composed of two 4-to-1 multiplexers (MUX), and each MUX outputs a partial product;

[0030] The data generated by the DA table (including two 0s) is based on the address sequence {w 1l ,w 0l}、{w 3l ,w 2l}Select to get the actual two partial products sum1 and sum2;

[0031] Figure 5 The structural diagram of the shift accumulator of the present invention is given;

[0032] like Figure 5 As shown, the shift accumulator in the present invention uses a GPC (3, 3) addition structure constructed by LUT6-2 (a six-input and two-output lookup table in Xilinx FPGA) and CARRY (a carry chain structure in Xilinx FPGA) to sum the two partial products sum1 and sum2 generated by the partial product selection module with the data in the shifted register; the above process is repeated L times to obtain the filter output (L is the coefficient w k of digits).

[0033] Table 1 respectively lists the hardware resources obtained after logic synthesis of the traditional DA-FIR filter (the structure in "Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic" published by SYPark et al. in IEEE) and the improved DA-FIR filter proposed in the present invention. Table 1 Hardware resource comparison table

[0034] The comparison of the results in Table 1 shows that the improved DA-FIR filter of the present invention has obvious advantages over the traditional structure in terms of hardware resource consumption.

[0035] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. An improved FIR filter structure based on a distributed algorithm (DA), characterized in that: It includes three parts: DA table, partial product selection module and shift accumulator; compared with traditional DR-FIR filter, this structure has obvious advantages in hardware resource consumption.

2. The DA meter according to claim 1, characterized in that: It consists of multiple registers and adders, which are used to shift and sum the serially input data to generate multiple possible partial products.

3. The partial product selection module according to claim 1, characterized in that: It consists of a multiplexer that is used to select the actual partial product based on the address sequence.

4. The shift accumulator according to claim 1, characterized in that: The generalized parallel counter (GPC) addition structure built using LUT6-2 and CARRY is used to accumulate the accumulated result of the previous clock cycle after shifting it with the partial product obtained by the partial product selection module of the current clock cycle.

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