A high-speed clock and data recovery circuit supporting dual-mode input

Abstract

The application provides a high-speed clock and data recovery circuit supporting dual-mode input, comprising a linear phase discriminator, a voltage / current converter, a loop filter, an LC voltage-controlled oscillator, an injection-locked multiphase clock generation circuit, a data recovery circuit and a logic decision circuit; the linear phase discriminator can directly discriminate NRZ and PAM4 data, and high gain and linearity are realized by matching the logic decision circuit, and loop bandwidth is increased; the injection-locked multiphase clock generation circuit realizes good locking stability and low noise performance of the LC voltage-controlled oscillator, and eliminates the mutual deterioration of jitter tolerance and recovery clock phase noise caused by the traditional architecture. The application can realize high jitter tolerance and good recovery clock phase noise performance at the same time, has low bit energy consumption, and supports dual-mode input.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically discloses a high-speed clock and data recovery circuit that supports dual-mode input. Background Technology

[0002] While the continuous evolution of CMOS technology has significantly reduced feature size, Rent's Law states that as transistor integration density surges, the demand for I / O pins must increase accordingly to meet the growing needs of communication bandwidth and multimedia content. In particular, the expansion of global internet users has led to a doubling of total I / O bandwidth every two years, while chips operating at high frequencies require more power / ground pins to suppress switching noise. Limited by packaging costs and pin counts, I / O growth lags far behind transistor integration speed, forcing individual I / O interfaces to handle higher bandwidths, posing challenges to chip, board, and system interconnects. Therefore, parallel interfaces, due to their high cost, significant interference, and substantial power consumption, have gradually been replaced by serial interface technology based on SerDes. SerDes, with its advantages of low pin count, small area, and high speed, has become an indispensable standard interface for high-performance CPUs, DSPs, and communication chips.

[0003] Due to channel loss and power consumption limitations, transmitters in SerDes circuits mostly only transmit data and not the clock. High-speed clock and data recovery (CDR) circuits are therefore indispensable parts of SerDes, and the performance of the CDR directly affects the overall performance of the SerDes system. Current designs use Bang-Bang phase detectors to achieve high gain, but this leads to significant jitter in the oscillator control voltage, causing substantial spurious noise in the recovered clock and degrading noise performance. Furthermore, the poor phase noise of the loop oscillator itself may further worsen the loop bandwidth. Therefore, current CDR circuits used in high-speed SerDes are limited by trade-offs between input data type and rate, jitter tolerance, RMS jitter of the recovered clock, and power efficiency, making it difficult to achieve a high-performance high-speed CDR circuit. Designing a high-speed CDR circuit and method that balances these key performance indicators is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed clock and data recovery circuit that supports dual-mode input, so as to solve the defects of existing clock and data recovery circuits applied in high-speed SerDes that are limited by the input data type and rate, jitter tolerance, root mean square jitter of the recovery clock, and trade-offs in power efficiency.

[0005] This invention is achieved through the following technical solution:

[0006] This invention provides a high-speed clock and data recovery circuit that supports dual-mode input, comprising: a linear phase detector, a voltage / current converter, a loop filter, an LC voltage-controlled oscillator, an injection-locked multiphase clock generation circuit, a data recovery circuit, and a logic decision circuit;

[0007] The first input terminal of the linear phase detector is connected to the high-speed input data. The second input terminal of the linear phase detector is connected to the output terminal of the injection-locked multiphase clock generation circuit. The output terminal of the linear phase detector is connected to the first input terminal of the voltage / current converter. The second input terminal of the voltage / current converter is connected to the output terminal of the logic decision circuit. The output terminal of the voltage / current converter is connected to the input terminal of the loop filter. The output terminal of the loop filter is connected to the input terminal of the LC voltage-controlled oscillator. The output terminal of the LC voltage-controlled oscillator is connected to the input terminal of the injection-locked multiphase clock generation circuit. The output terminal of the injection-locked multiphase clock generation circuit is connected to the second input terminal of the data recovery circuit and the first input terminal of the logic decision circuit. The first input terminal of the data recovery circuit is connected to the high-speed input data. The output terminal of the data recovery circuit is connected to the second input terminal of the logic decision circuit.

[0008] Preferably, the loop filter includes: resistor R L Capacitor C L1 and capacitor C L2 Resistance R L The input terminal is connected to the output terminal of the voltage / current converter and the capacitor C. L2 Connect to the input terminal; capacitor C L1 The input terminal and resistor R L Connect to the output terminal; capacitor C L1 The output terminal is connected to ground; capacitor C L2 The output terminal is connected to ground; capacitor C L2 The input terminal is connected to the input terminal of the LC voltage-controlled oscillator.

[0009] Preferably, the injection-locked multiphase clock generation circuit includes: a voltage-controlled delay line, a voltage-controlled ring oscillator, first to sixteenth injection buffers, a frequency and phase detector, a resistor R, a capacitor C1, a charge pump, and a capacitor C2; the voltage-controlled delay line includes first to eighth delay units, and the voltage-controlled ring oscillator includes first to eighth delay units.

[0010] The differential input terminal of the first delay unit of the voltage-controlled delay line is connected to the output terminal of the LC voltage-controlled oscillator; the first to eighth delay units of the voltage-controlled delay line are arranged sequentially, with the positive output terminal of the previous delay unit connected to the inverting input terminal of the next delay unit, and vice versa; the first to eighth delay units of the voltage-controlled ring oscillator are arranged sequentially, with the positive output terminal of the previous delay unit connected to the inverting input terminal of the next delay unit, and vice versa; the first to eighth delay units of the voltage-controlled delay line correspond one-to-one with the first to eighth delay units of the voltage-controlled ring oscillator; the positive output terminal of each delay unit of the voltage-controlled delay line is connected to the positive output terminal of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer, and the inverting output terminal of each delay unit of the voltage-controlled delay line is connected to the inverting output terminal of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer; the positive output terminal CK of the fourth delay unit of the voltage-controlled delay line... r3 Connected to the first input terminal of the frequency and phase detector, the inverting output terminal CK r11 Connected to the second input terminal of the frequency and phase detector; the positive output terminal CK of the eighth delay unit of the voltage-controlled delay line. r15 Connect to the third input terminal of the frequency and phase detector, and the inverting output terminal CK r7 Connect to the fourth input terminal of the frequency and phase detector; connect the output terminal of the frequency and phase detector to the input terminal of resistor R; connect the output terminal of resistor R to the input terminal of capacitor C1 and the input terminal of the charge pump; connect the output terminal of capacitor C1 to ground; connect the output terminal of the charge pump to V. COSC It is connected to the input terminal of capacitor C2, the voltage control input terminal of the voltage-controlled delay line, and the voltage control input terminal of the voltage-controlled ring oscillator; the output terminal of capacitor C2 is connected to ground.

[0011] Preferably, the data recovery circuit includes: a sample-and-hold circuit, resistors R1, R2, R3, R4, R5, and R6, a first comparator, a second comparator, a third comparator, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, an XOR gate, and an AND gate.

[0012] The first input terminal of the sample-and-hold circuit is connected to the high-speed input data; the second input terminal of the sample-and-hold circuit is connected to the output terminal CK of the injection-locked multiphase clock generation circuit. 2n The sample-and-hold circuit is connected to the first input of the first comparator, the first input of the second comparator, and the first input of the third comparator; the input of resistor R1 is connected to ground; the output of resistor R1 is V. RefLThe input terminal of resistor R2 is connected to the second input terminal of the third comparator; the output terminal of resistor R2 is connected to the input terminal of resistor R3; the output terminal of resistor R3 is V. RefM The input terminal of resistor R4 is connected to the input terminal of the second comparator; the output terminal of resistor R4 is connected to the input terminal of resistor R5; the output terminal of resistor R5 is V. RefH The resistor R6 is connected to the input terminal of the first comparator and the second input terminal of the first comparator; the output terminal of the resistor R6 is connected to the input reference voltage V. Ref Connected to each other; the third input terminals of the first comparator, the second comparator, and the third comparator are all connected to the output terminal CK of the injection-locked multiphase clock generation circuit. 2n+1 The first comparator is connected to the first input of the first D flip-flop DFF1; the second comparator is connected to the first input of the second D flip-flop DFF2; the third comparator is connected to the first input of the third D flip-flop DFF3; the output of the first D flip-flop DFF1 is connected to the first input of the second D flip-flop DFF2. H Connected to the first input of the XOR gate; the output T of the second D flip-flop DFF2 M The second input of the XNOR gate is connected to the first input of the fourth D flip-flop DFF4; the output of the XNOR gate is connected to the first input of the AND gate; the output of the third D flip-flop DFF3 is T. L The second input of the AND gate is connected to the second input of the AND gate; the output of the AND gate is connected to the input of the fifth D flip-flop DFF5; the second inputs of the first D flip-flop DFF1, the second D flip-flop DFF2, and the third D flip-flop DFF3 are all connected to the output CK of the injection-locked multiphase clock generation circuit. 2n+4 The second input terminals of the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 are connected to the output terminal CK3 of the injection-locked multiphase clock generation circuit.

[0013] Furthermore, the logic decision circuit includes: a fourth comparator, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a second NOR gate NOR2;

[0014] The input of the fourth comparator is connected to the output of the sample-and-hold circuit in the data recovery circuit; the output of the fourth comparator is connected to the first input of the sixth D flip-flop DFF6; the inputs of the first XOR gate XOR1, the second XOR gate XOR2, and the third XOR gate XOR3 are respectively connected to the output T of the data recovery circuit. H T M T L The following connections are made: the output of the first XOR gate XOR1 is connected to the first input of the first NAND gate NAND1, the first input of the first NOR gate NOR1, and the first input of the second NAND gate NAND2; the output of the second XOR gate XOR2 is connected to the second input of the first NAND gate NAND1, the second input of the first NOR gate NOR1, and the second input of the second NAND gate NAND2; the output of the third XOR gate XOR3 is connected to the input of the NOT gate; the output of the NOT gate is connected to the third input of the first NAND gate NAND1 and the second input of the second NOR gate NOR2; the output of the first NAND gate NAND1 is connected to the first input of the seventh D flip-flop DFF7; the output of the second NOR gate NOR2 is connected to the first input of the eighth D flip-flop DFF8; the output of the second NAND gate NAND2 is connected to the first input of the ninth D flip-flop DFF9; the second inputs of the seventh D flip-flop DFF7, the eighth D flip-flop DFF8, and the ninth D flip-flop DFF9 are all connected to the output of the injection-locked multiphase clock generation circuit.

[0015] The first and second outputs of the sixth D flip-flop DFF6 serve as the outputs of the logic decision circuit, respectively. CP and output terminal V CN The first and second outputs of the seventh D flip-flop (DFF7) serve as the outputs of the logic decision circuit, respectively. CP1P V CP1N The first and second outputs of the eighth D flip-flop (DFF8) serve as the outputs of the logic decision circuit, respectively. CP2P and V CP2N The first and second output terminals of the ninth D flip-flop (DFF9) serve as the output terminals V of the logic decision circuit, respectively. CP3P and V CP3N .

[0016] Furthermore, the voltage / current converter includes a polarity switching switch, a voltage / current conversion unit, and an output control circuit. The output terminal of the polarity switching switch is connected to the input terminal of the voltage / current conversion unit, and the output terminal of the voltage / current conversion unit is connected to the input terminal of the output control circuit. The input terminal of the polarity switching switch is connected to the output terminal V of the logic decision circuit. CP V CNConnected; the input terminal of the output control circuit is connected to the output terminal V of the logic decision circuit. CP1P V CP2P V CP3P V CP1N V CP2N V CP3N Connected.

[0017] Furthermore, the polarity switching switch includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the voltage / current conversion unit includes a first voltage / current conversion unit, a second voltage / current conversion unit, and a third voltage / current conversion unit; the output control circuit includes a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3.

[0018] The first input terminal V of the first switch S1 P The positive output terminal of the linear phase detector and the first input terminal of the second switch S2 are connected; the first input terminal V of the third switch S3 is connected. N The inverting output of the linear phase detector and the first input of the fourth switch S4 are connected; the second inputs of the first switch S1 and the third switch S3 are connected to the output V of the logic decision circuit. CP Connected; the second input terminal of the second switch S2 and the second input terminal of the fourth switch S4 are both connected to the output terminal V of the logic decision circuit. CN The following connections are made: the output terminal of the first switch S1 is connected to the output terminal of the fourth switch S4, the inverting input terminal of the first voltage / current conversion unit, the inverting input terminal of the second voltage / current conversion unit, and the inverting input terminal of the third voltage / current conversion unit; the output terminal of the second switch S2 is connected to the output terminal of the third switch S3, the non-inverting input terminal of the first voltage / current conversion unit, the non-inverting input terminal of the second voltage / current conversion unit, and the non-inverting input terminal of the third voltage / current conversion unit; the output terminal of the first voltage / current conversion unit is connected to the first input terminal of the first transmission gate TG1; the output terminal of the second voltage / current conversion unit is connected to the first input terminal of the second transmission gate TG2; the output terminal of the third voltage / current conversion unit is connected to the first input terminal of the third transmission gate TG3; the positive control input terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are respectively connected to the output terminal V of the logic decision circuit. CP1P V CP2P and V CP3P Connected to each other; the inverting control input terminals of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are respectively connected to the output terminal V of the logic decision circuit. CP1N V CP2N and V CP3NThe output terminals of the first transmission gate TG1 are connected to the output terminals of the second transmission gate TG2 and the third transmission gate TG3.

[0019] Preferably, the high-speed input data is NRZ data or PAM4 data.

[0020] Preferably, the linear phase detector is composed of eight identical linear phase detector slice units connected in parallel. The input terminals of the eight linear phase detector slice units are connected in series to receive the same high-speed input data, and the outputs of the eight linear phase detector slice units are used to control the voltage / current converter in parallel.

[0021] Preferably, the voltage / current converter is composed of eight identical voltage / current converter slice units connected in parallel, and the outputs of the eight voltage / current converter slice units are connected in series to control the loop filter and the LC voltage-controlled oscillator; the data recovery circuit is composed of eight identical data recovery circuit slice units connected in parallel, and the parallel outputs of the eight data recovery circuit slice units are used to control the logic decision circuit; the logic decision circuit is composed of eight identical logic decision circuit slice units connected in parallel, and the outputs of the eight logic decision circuit slice units control the voltage / current converter.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] This invention supports a high-speed clock and data recovery circuit with dual-mode input, employing a linear phase detector. This linear phase detector can directly detect the phase of NRZ and PAM4 data, and, combined with a logic decision circuit, achieves high gain and linearity, increasing loop bandwidth. The invention utilizes the aforementioned injection-locked multiphase clock generation circuit, achieving good locking stability and the low-noise performance of an LC voltage-controlled oscillator, eliminating the mutual degradation of jitter tolerance and recovery clock jitter phase noise caused by traditional architectures. This invention can simultaneously achieve high jitter tolerance and good recovery clock phase noise performance, with low bit power consumption, and supports dual-mode input.

[0024] Furthermore, this invention employs a multi-phase clock sampling slicing method, enabling the entire circuit to operate at a frequency of 1 / 16 baud rate, reducing the delay requirements for manufacturing process devices and the complexity of circuit design, while also reducing power consumption. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the high-speed clock and data recovery circuit supporting dual-mode input according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the injection-locked multiphase clock generation circuit according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the data recovery circuit according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the logic decision circuit according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the circuit structure of a voltage / current converter according to an embodiment of the present invention. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] It should be noted that the process equipment or apparatus not specifically mentioned in the following embodiments are all conventional equipment or apparatus in the art.

[0033] It should be noted that the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Furthermore, unless otherwise stated, the numbering of each method step is merely a convenient tool for identifying each method step, and not intended to limit the order of the method steps or define the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0034] Furthermore, it should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In addition, unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection or a detachable connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements.

[0035] refer to Figure 1 The high-speed clock and data recovery circuit supporting dual-mode input described in this invention includes: a linear phase detector, a voltage / current converter, a loop filter, an LC voltage-controlled oscillator (VOC), an injection-locked multiphase clock generation circuit, a data recovery circuit, and a logic decision circuit.

[0036] The linear phase detector has the following configuration: its first input terminal is connected to high-speed input data; its second input terminal is connected to the output terminal of the injection-locked multiphase clock generation circuit; its output terminal is connected to the first input terminal of the voltage / current converter; its second input terminal is connected to the output terminal of the logic decision circuit; its output terminal is connected to the input terminal of the loop filter; its output terminal is connected to the input terminal of the LC voltage-controlled oscillator; its output terminal is connected to the input terminal of the injection-locked multiphase clock generation circuit; its output terminal is connected to the second input terminal of the data recovery circuit and the first input terminal of the logic decision circuit; its first input terminal is connected to high-speed input data; and its output terminal is connected to the second input terminal of the logic decision circuit.

[0037] In one embodiment of the present invention, the loop filter includes: a resistor R L Capacitor C L1 Capacitor C L2 ; wherein, the resistor R LThe input terminal is connected to the output terminal of the voltage / current converter and the capacitor C. L2 The input terminal is connected; the capacitor C L1 The input terminal is connected to the resistor R. L The output terminal of the capacitor C is connected to the capacitor C. L1 The output terminal of the capacitor C is connected to ground level; L2 The output terminal of the capacitor C is connected to ground level; L2 The input terminal is connected to the input terminal of the LC voltage-controlled oscillator.

[0038] The linear phase detector of this invention can directly perform linear phase detection on input high-speed NRZ (non-return-to-zero code) and PAM4 (four-level pulse amplitude modulation signal), and has a large phase detection gain. The closed-loop transfer function of the Type-II loop structure used in this invention is calculated by the following formula:

[0039]

[0040] in, K PD It is the gain of the linear phase detector. I CP It is the current of the charge pump. K VCO It is the gain of the LC voltage-controlled oscillator. R L It is the resistor in the loop filter. C L1 It is the first-order filter capacitor in the loop filter. C L2 It is a second-order filter capacitor in a loop filter.

[0041] Furthermore, the loop bandwidth is calculated using the following formula:

[0042]

[0043] It should be noted that increasing the gain of the linear phase detector can not only increase the closed-loop bandwidth, but also reduce the in-band noise of the charge pump and the LC voltage-controlled oscillator.

[0044] refer to Figure 2In one embodiment of the present invention, the injection-locked multiphase clock generation circuit includes: a voltage-controlled delay line, a voltage-controlled ring oscillator, a phase-frequency detector (PFD), a resistor R, a capacitor C1, a charge pump CP, and a capacitor C2. The input to the voltage-controlled delay line is a complementary clock generated by a low-frequency LC voltage-controlled oscillator in the loop, and the output is a clock with 16 identical frequencies. Because the injection intensity generated by the multiphase clock injection technology is very high, the requirement for phase accuracy is relatively low. The multiphase injection technology can simultaneously generate high-precision and low-noise multiphase clocks. The phase-frequency detector (PFD) performs phase detection on the quadrature injected clocks, and the output high-frequency phase detection result is filtered to a low frequency before being fed into the charge pump to achieve phase-frequency alignment.

[0045] It should be noted that the bandwidth of the injection-locked multiphase clock generation circuit is very large, and the noise of the generated multiphase clock is mainly the noise of the input reference clock. It is very easy to realize a low-noise low-frequency LC voltage-controlled oscillator. At the same time, since a linear phase detector is used, the output clock has low spurious emissions and can generate strong injection-lock strength, thus realizing a high-precision, low-noise multiphase clock.

[0046] Specifically, the injection-locked multiphase clock generation circuit includes: a first delay unit of a voltage-controlled delay line, a second delay unit of a voltage-controlled delay line, a third delay unit of a voltage-controlled delay line, a fourth delay unit of a voltage-controlled delay line, a fifth delay unit of a voltage-controlled delay line, a sixth delay unit of a voltage-controlled delay line, a seventh delay unit of a voltage-controlled delay line, an eighth delay unit of a voltage-controlled delay line, a first injection buffer, a second injection buffer, a third injection buffer, a fourth injection buffer, a fifth injection buffer, a sixth injection buffer, a seventh injection buffer, an eighth injection buffer, a ninth injection buffer, a tenth injection buffer, an eleventh injection buffer, a twelfth injection buffer, a thirteenth injection buffer, a fourteenth injection buffer, a fifteenth injection buffer, a sixteenth injection buffer, a first delay unit of a voltage-controlled ring oscillator, a second delay unit of a voltage-controlled ring oscillator, a third delay unit of a voltage-controlled ring oscillator, a fourth delay unit of a voltage-controlled ring oscillator, a fifth delay unit of a voltage-controlled ring oscillator, a sixth delay unit of a voltage-controlled ring oscillator, a seventh delay unit of a voltage-controlled ring oscillator, an eighth delay unit of a voltage-controlled ring oscillator, a frequency and phase detector PFD, a resistor R, a capacitor C1, a charge pump CP, and a capacitor C2.

[0047] The differential input terminal of the first delay unit of the voltage-controlled delay line is connected to the output terminal of the LC voltage-controlled oscillator; the positive output terminal CK of the first delay unit of the voltage-controlled delay line is connected to the output terminal of the LC voltage-controlled oscillator. r8 The voltage-controlled delay line is connected to the inverting input of the second delay unit and the input of the first injection buffer; the voltage-controlled delay line's first delay unit's inverting output CK is connected to... r0The positive input terminal of the second delay unit of the voltage-controlled delay line and the input terminal of the second injection buffer are connected; the positive output terminal CK of the second delay unit of the voltage-controlled delay line is connected. r1 The inverting input terminal of the third delay unit of the voltage-controlled delay line and the input terminal of the third injection buffer are connected; the inverting output terminal CK of the second delay unit of the voltage-controlled delay line is connected. r9 The positive input terminal of the third delay unit of the voltage-controlled delay line and the input terminal of the fourth injection buffer are connected; the positive output terminal CK of the third delay unit of the voltage-controlled delay line is connected. r10 The voltage-controlled delay line is connected to the inverting input of the fourth delay unit and the input of the fifth injection buffer; the voltage-controlled delay line is connected to the inverting output CK of the third delay unit. r2 The positive input terminal of the fourth delay unit of the voltage-controlled delay line and the input terminal of the sixth injection buffer are connected; the positive output terminal CK of the fourth delay unit of the voltage-controlled delay line is connected. r3 The voltage-controlled delay line is connected to the inverting input of the fifth delay unit and the input of the seventh injection buffer; the voltage-controlled delay line is connected to the inverting output CK of the fourth delay unit. r11 The positive input terminal of the fifth delay unit of the voltage-controlled delay line and the input terminal of the eighth injection buffer are connected; the positive output terminal CK of the fourth delay unit of the voltage-controlled delay line is connected. r3 The voltage-controlled delay line is connected to the inverting input of the fifth delay unit, the input of the seventh injection buffer, and the first input of the frequency and phase detector; the inverting output CK of the fourth delay unit of the voltage-controlled delay line is connected to the inverting input of the fifth delay unit, the input of the seventh injection buffer, and the first input of the frequency and phase detector. r11 It is connected to the positive input terminal of the fifth delay unit of the voltage-controlled delay line, the input terminal of the eighth injection buffer, and the second input terminal of the frequency and phase detector; the positive output terminal CK of the fifth delay unit of the voltage-controlled delay line is connected to... r12 The voltage-controlled delay line is connected to the inverting input of the sixth delay unit and the input of the ninth injection buffer; the voltage-controlled delay line's fifth delay unit's inverting output CK is connected to... r4 The positive input terminal of the sixth delay unit of the voltage-controlled delay line and the input terminal of the tenth injection buffer are connected; the positive output terminal CK of the sixth delay unit of the voltage-controlled delay line is connected. r5 The voltage-controlled delay line is connected to the inverting input of the seventh delay unit and the input of the eleventh injection buffer; the voltage-controlled delay line's sixth delay unit's inverting output CK is connected to... r13The positive input terminal of the seventh delay unit of the voltage-controlled delay line and the input terminal of the twelfth injection buffer are connected; the positive output terminal CK of the seventh delay unit of the voltage-controlled delay line is connected. r14 The voltage-controlled delay line is connected to the inverting input of the eighth delay unit and the input of the thirteenth injection buffer; the voltage-controlled delay line's seventh delay unit's inverting output CK is connected to... r6 The positive input terminal of the eighth delay unit of the voltage-controlled delay line and the input terminal of the fourteenth injection buffer are connected; the positive output terminal CK of the eighth delay unit of the voltage-controlled delay line is connected. r15 The input terminal of the fifteenth injection buffer and the third input terminal of the frequency and phase detector are connected; the inverting output terminal CK of the eighth delay unit of the voltage-controlled delay line is connected. r7 The first injection buffer is connected to the input terminal of the sixteenth injection buffer and the fourth input terminal of the frequency and phase detector. The output terminal of the first injection buffer is connected to the positive output terminal CK8 of the first delay unit of the voltage-controlled ring oscillator and the inverting input terminal of the second delay unit of the voltage-controlled ring oscillator; the output terminal of the second injection buffer is connected to the inverting output terminal CK0 of the first delay unit of the voltage-controlled ring oscillator and the positive input terminal of the second delay unit of the voltage-controlled ring oscillator; the output terminal of the third injection buffer is connected to the positive output terminal CK1 of the second delay unit of the voltage-controlled ring oscillator and the inverting input terminal of the third delay unit of the voltage-controlled ring oscillator; the output terminal of the fourth injection buffer is connected to the inverting output terminal CK9 of the second delay unit of the voltage-controlled ring oscillator and the positive input terminal of the third delay unit of the voltage-controlled ring oscillator; the output terminal of the fifth injection buffer is connected to the positive output terminal CK8 of the third delay unit of the voltage-controlled ring oscillator. 10 The output of the sixth injection buffer is connected to the inverting input of the fourth delay unit of the voltage-controlled ring oscillator; the output of the seventh injection buffer is connected to the inverting output CK2 of the third delay unit of the voltage-controlled ring oscillator and the positive input of the fourth delay unit of the voltage-controlled ring oscillator; the output of the eighth injection buffer is connected to the inverting output CK3 of the fourth delay unit of the voltage-controlled ring oscillator and the inverting input of the fifth delay unit of the voltage-controlled ring oscillator; the output of the eighth injection buffer is connected to the inverting output CK2 of the fourth delay unit of the voltage-controlled ring oscillator. 11 The output of the ninth injection buffer is connected to the positive input terminal of the fifth delay unit of the voltage-controlled ring oscillator; the output terminal of the ninth injection buffer is connected to the positive output terminal CK of the fifth delay unit of the voltage-controlled ring oscillator. 12The output of the tenth injection buffer is connected to the inverting input of the sixth delay unit of the voltage-controlled ring oscillator (VCO); the output of the eleventh injection buffer is connected to the inverting output CK4 of the fifth delay unit of the VCO and the positive input of the sixth delay unit of the VCO; the output of the eleventh injection buffer is connected to the positive output CK5 of the sixth delay unit of the VCO and the inverting input of the seventh delay unit of the VCO; the output of the twelfth injection buffer is connected to the inverting output CK5 of the sixth delay unit of the VCO. 13 The output of the thirteenth injection buffer is connected to the positive input terminal of the seventh delay unit of the voltage-controlled ring oscillator; the output terminal of the thirteenth injection buffer is connected to the positive output terminal CK of the seventh delay unit of the voltage-controlled ring oscillator. 14 The output of the fourteenth injection buffer is connected to the inverting input of the eighth delay unit of the voltage-controlled ring oscillator (VCO); the output of the fifteenth injection buffer is connected to the inverting output of the eighth delay unit of the VCO and the inverting input of the first delay unit of the VCO; the output of the sixteenth injection buffer is connected to the inverting output of the eighth delay unit of the VCO. 15 The voltage-controlled ring oscillator is connected to the positive input terminal of the first delay unit; the output terminal of the frequency and phase detector is connected to the input terminal of the resistor R; the output terminal of the resistor R is connected to the input terminal of the capacitor C1 and the input terminal of the charge pump; the output terminal of the capacitor C1 is connected to ground; the output terminal of the charge pump is V. COSC The capacitor C2 is connected to the input terminal of the capacitor C2, the voltage control input terminal of the voltage-controlled delay line, and the voltage control input terminal of the voltage-controlled ring oscillator; the output terminal of the capacitor C2 is connected to ground.

[0048] refer to Figure 3 In one embodiment of the present invention, the data recovery circuit includes a comparator, a D flip-flop, and logic circuitry. For NRZ data, the intermediate reference voltage V is directly used as the reference voltage. RefM The comparator, after passing through a D flip-flop, yields the recovered low-frequency data. For PAM4 data, it requires three reference voltages, with the high reference voltage V... RefH Intermediate reference voltage V RefM Low reference voltage V RefL The comparator, after passing through three D flip-flops, generates a three-bit thermometer code T. H T M TL Specifically, for the four level signals -3, -1, +1, and +3 of the input PAM4 data, a three-digit thermometer code T is generated. H T M T L They are 000, 001, 011, and 111 respectively.

[0049] The logic circuit implements the following logical operation:

[0050]

[0051] When the three-dimensional thermometer code T H T M T L When the values ​​are 000, 001, 011, and 111 respectively, the two-bit binary codes generated by the logic circuit are 00, 01, 10, and 11 respectively. The two-bit binary codes are then retimed to generate recovered low-frequency parallel data.

[0052] Specifically, the data recovery circuit includes: a sample-and-hold circuit, resistors R1, R2, R3, R4, R5, and R6, a first comparator, a second comparator, a third comparator, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, an XOR gate, and an AND gate.

[0053] The first input terminal of the sample-and-hold circuit is connected to the high-speed input data; the second input terminal of the sample-and-hold circuit is connected to the output terminal CK of the injection-locked multiphase clock generation circuit. 2n The sample-and-hold circuit is connected to the first input of the first comparator, the first input of the second comparator, and the first input of the third comparator; the input of resistor R1 is connected to ground; the output of resistor R1 is V. RefL The resistor R2 is connected to the input terminal of the resistor R2 and the second input terminal of the third comparator; the output terminal of the resistor R2 is connected to the input terminal of the resistor R3; the output terminal of the resistor R3 is V. RefM The resistor R4 is connected to the input terminal of the resistor R4 and the second input terminal of the second comparator; the output terminal of the resistor R4 is connected to the input terminal of the resistor R5; the output terminal of the resistor R5 is V. RefH The resistor R6 is connected to its input terminal and the second input terminal of the first comparator; the output terminal of the resistor R6 is connected to the input reference voltage V. RefThe three input terminals of the first comparator, the second comparator, and the third comparator are all connected to the output terminal CK of the injection-locked multiphase clock generation circuit. 2n+1 The first comparator is connected to the first input of the first D flip-flop DFF1; the second comparator is connected to the first input of the second D flip-flop DFF2; and the third comparator is connected to the first input of the third D flip-flop DFF3. The output of the first D flip-flop DFF1 is T... H Connected to the first input terminal of the XOR gate; the output terminal T of the second D flip-flop DFF2 M The XNOR gate is connected to the second input terminal of the XNOR gate and the first input terminal of the fourth D flip-flop DFF4; the output terminal of the XNOR gate is connected to the first input terminal of the AND gate; the output terminal T of the third D flip-flop DFF3 is connected to the first input terminal of the AND gate. L The AND gate is connected to the second input terminal; the AND gate's output terminal is connected to the input terminal of the fifth D flip-flop DFF5; the second input terminals of the first D flip-flop DFF1, the second D flip-flop DFF2, and the third D flip-flop DFF3 are all connected to the output terminal CK of the injection-locked multiphase clock generation circuit. 2n+4 The second input terminals of the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 are connected to the output terminal CK3 of the injection-locked multiphase clock generation circuit.

[0054] refer to Figure 4 In one embodiment of the present invention, the logic decision circuit includes a comparator, a D flip-flop, and a logic circuit.

[0055] It should be noted that the logic decision circuit performs the following two functions: determining the direction of the transition edge of the input data and determining the transition type.

[0056] Specifically, the comparator input is the data sampling voltage V before the data transition edge. n and the data sampling voltage V after the data transition edge n+1 The output is the result of the judgment, V. CP V CN The decision result controls the input polarity of the voltage / current converter through logic control. The decision transition type is implemented through logic circuitry, firstly by determining the three-digit thermometer code T corresponding to the data before and after the data transition edge. H[n] T M[n] T L[n] and T H[n+1] T M[n+1] T L[n+1]The XOR operation is performed sequentially, and the output of the XOR gate is fed to the logic circuit. The logic circuit then performs the following logical operation:

[0057]

[0058] Furthermore, for edges of the minimum transition type, i.e. 000→001, 001→000, 001→011, 011→001, 011→111, 111→011, the decision is to obtain V. CP1P V CP2P V CP3P The value is 111; for edges that occur in the intermediate transition type, i.e., 000→011, 011→000, 001→111, 111→001, the decision is V. CP1P V CP2P V CP3P It is 110 or 001; for the edge that occurs with the largest jump type, i.e. 000→111, 111→000, the decision is to obtain V. CP1P V CP2P V CP3P It is 010. Minimum delay logic control is achieved using only three levels of logic circuitry.

[0059] Specifically, the logic decision circuit includes: a fourth comparator, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a second NOR gate NOR2.

[0060] The input terminal of the fourth comparator is connected to the output terminal of the sample-and-hold circuit in the data recovery circuit; the output terminal of the fourth comparator is connected to the first input terminal of the sixth D flip-flop DFF6; the input terminals of the first XOR gate XOR1, the second XOR gate XOR2, and the third XOR gate XOR3 are respectively connected to the output terminal T of the data recovery circuit. H T M T LThe first XOR gate (XOR1) is connected to the first input of the first NAND gate (NAND1), the first input of the first NOR gate (NOR1), and the first input of the second NAND gate (NAND2); the output of the second XOR gate (XOR2) is connected to the second input of the first NAND gate (NAND1), the second input of the first NOR gate (NOR1), and the second input of the second NAND gate (NAND2); the output of the third XOR gate (XOR3) is connected to the input of the NOT gate; and the output of the NOT gate is connected to the third input of the first NAND gate (NAND1). The output of the first NAND gate NAND1 is connected to the first input of the seventh D flip-flop DFF7; the output of the second NOR gate NOR2 is connected to the first input of the eighth D flip-flop DFF8; the output of the second NAND gate NAND2 is connected to the first input of the ninth D flip-flop DFF9; the second inputs of the seventh D flip-flop DFF7, the eighth D flip-flop DFF8, and the ninth D flip-flop DFF9 are all connected to the output of the injection-locked multiphase clock generation circuit.

[0061] The first and second output terminals of the sixth D flip-flop DFF6 are respectively used as the output terminals V of the logic decision circuit. CP and output terminal V CN The first and second output terminals of the seventh D flip-flop DFF7 are respectively used as the output terminals V of the logic decision circuit. CP1P V CP1N The first and second output terminals of the eighth D flip-flop DFF8 are respectively used as the output terminals V of the logic decision circuit. CP2P and V CP2N The first and second output terminals of the ninth D flip-flop DFF9 are respectively used as the output terminals V of the logic decision circuit. CP3P and V CP3N .

[0062] join Figure 5 In one embodiment of the present invention, the voltage / current converter includes a polarity switching switch, a voltage / current conversion unit, and an output control circuit. The polarity switching switch is determined by a decision result V generated by a logic decision circuit. CP V CN The control is such that when the decision result for the transition direction is reversed, the input polarity of the voltage / current conversion unit is also reversed.

[0063] The output control circuit consists of the V of the logic decision circuit. CP1P V CP2P VCP3P and V CP1N V CP2N V CP3N The control system achieves an output current ratio of 1:1:1 when the input voltage difference is 1:2:3, improving the phase detection linearity of the circuit and further enhancing the gain and stability.

[0064] Specifically, the polarity switching switch includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the voltage / current conversion unit includes a first voltage / current conversion unit, a second voltage / current conversion unit, and a third voltage / current conversion unit; and the output control circuit includes a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3.

[0065] Wherein, the first input terminal V of the first switch S1 P The positive output terminal of the linear phase detector and the first input terminal of the second switch S2 are connected; the first input terminal V of the third switch S3 is connected. N The inverting output terminal of the linear phase detector and the first input terminal of the fourth switch S4 are connected; the second input terminals of the first switch S1 and the second input terminal of the third switch S3 are connected to the output terminal V of the logic decision circuit. CP Connected; the second input terminal of the second switch S2 and the second input terminal of the fourth switch S4 are both connected to the output terminal V of the logic decision circuit. CN The first switch S1 is connected to the output of the fourth switch S4, the inverting input of the first voltage / current conversion unit, the inverting input of the second voltage / current conversion unit, and the inverting input of the third voltage / current conversion unit; the second switch S2 is connected to the output of the third switch S3, the non-inverting input of the first voltage / current conversion unit, the non-inverting input of the second voltage / current conversion unit, and the non-inverting input of the third voltage / current conversion unit; the output of the first voltage / current conversion unit is connected to the first input of the first transmission gate TG1; the output of the second voltage / current conversion unit is connected to the first input of the second transmission gate TG2; the output of the third voltage / current conversion unit is connected to the first input of the third transmission gate TG3; the positive control inputs of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are respectively connected to the output of the logic decision circuit V. CP1P V CP2P and V CP3PThe inverting control inputs of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are connected to the output V of the logic decision circuit, respectively. CP1N V CP2N and V CP3N The first transmission gate TG1 is connected to the output of the second transmission gate TG2 and the third transmission gate TG3.

[0066] In one embodiment of the present invention, the linear phase detector can support high-speed input data of both NRZ and PAM4 data types, realizing dual-mode data input function.

[0067] In one embodiment of the present invention, the linear phase detector is composed of eight identical linear phase detector slice units connected in parallel. In this structure, the eight input terminals are connected in series to receive the same high-speed input data, while the eight parallel circuit outputs of the linear phase detector are used to control the voltage / current converter in parallel.

[0068] The voltage / current converter is composed of eight identical voltage / current converter slice units connected in parallel. In this structure, the eight parallel outputs are connected in series to control the loop filter and the LC voltage-controlled oscillator.

[0069] In one embodiment of the present invention, the data recovery circuit is composed of eight identical data recovery circuit slice units connected in parallel. In this structure, the eight parallel outputs control the logic decision circuit.

[0070] In one embodiment of the present invention, the logic decision circuit is composed of eight identical logic decision circuit slice units connected in parallel. The eight parallel outputs control the voltage / current converter.

[0071] This invention achieves high jitter tolerance through a high-gain linear phase detector. At the same time, the high linearity reduces the control voltage ripple of the LC voltage-controlled oscillator in the steady loop, further reducing the clock peak jitter of the LC voltage-controlled oscillator when steady. It can effectively perform multi-phase latch-up to generate low-noise multi-phase clocks, achieving a simultaneous improvement in jitter tolerance and phase noise. Meanwhile, it achieves low bit power consumption while supporting dual-mode input.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high speed clock and data recovery circuit supporting dual mode input, characterized by, The application relates to a high-speed data recovery circuit. The first input end of the linear phase discriminator is connected with high-speed input data, the second input end of the linear phase discriminator is connected with the output end of the injection-locked multiphase clock generation circuit, the output end of the linear phase discriminator is connected with the first input end of the voltage / current converter, the second input end of the voltage / current converter is connected with the output end of the logic decision circuit, the output end of the voltage / current converter is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the LC voltage-controlled oscillator, the output end of the LC voltage-controlled oscillator is connected with the input end of the injection-locked multiphase clock generation circuit, the output end of the injection-locked multiphase clock generation circuit is connected with the second input end of the data recovery circuit and the first input end of the logic decision circuit, the first input end of the data recovery circuit is connected with high-speed input data, and the output end of the data recovery circuit is connected with the second input end of the logic decision circuit. The logic decision circuit comprises a fourth comparator, a first exclusive OR gate XOR1, a second exclusive OR gate XOR2, a third exclusive OR gate XOR3, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1 and a second NOR gate NOR2. The injection-locked multiphase clock generation circuit comprises a voltage-controlled delay line, a voltage-controlled ring oscillator, first to sixteenth injection buffers, a frequency discriminator, a resistor R, a capacitor C1, a charge pump and a capacitor C2; the voltage-controlled delay line comprises first to eighth delay units, and the voltage-controlled ring oscillator comprises first to eighth delay units. The input end of the fourth comparator is connected with the output end of the sample and hold circuit in the data recovery circuit, and the input of the fourth comparator is the data sample voltage V n before the data jump edge and the data sample voltage V n+1 after the data jump edge; the output end of the fourth comparator is connected with the first input end of the sixth D flip-flop DFF6; one input end of the first exclusive OR gate XOR1 is connected with the thermometer code T H[n] corresponding to the data before the data jump edge in the data recovery circuit, and the other input end is connected with the thermometer code T H[n+1] corresponding to the data after the data jump edge in the data recovery circuit; one input end of the second exclusive OR gate XOR2 is connected with the thermometer code T M[n] corresponding to the data before the data jump edge in the data recovery circuit, and the other input end is connected with the thermometer code T M[n+1] corresponding to the data after the data jump edge in the data recovery circuit; one input end of the third exclusive OR gate XOR3 is connected with the thermometer code T L[n] corresponding to the data before the data jump edge in the data recovery circuit, and the other input end is connected with the thermometer code T L[n+1] corresponding to the data after the data jump edge in the data recovery circuit; the output end of the first exclusive OR gate XOR1 is connected with the first input end of the first NAND gate NAND1, the first input end of the first NOR gate NOR1 and the first input end of the second NAND gate NAND2; the output of the second exclusive OR gate XOR2 is connected with the second input end of the first NAND gate NAND1, the second input end of the first NOR gate NOR1 and the second input end of the second NAND gate NAND2; the output end of the third exclusive OR gate XOR3 is connected with the input end of the NOT gate; the output end of the NOT gate is connected with the third input end of the first NAND gate NAND1 and the second input end of the second NOR gate NOR2; the output end of the first NAND gate NAND1 is connected with the first input end of the seventh D flip-flop DFF7; the output end of the second NOR gate NOR2 is connected with the first input end of the eighth D flip-flop DFF8; the output end of the second NAND gate NAND2 is connected with the first input end of the ninth D flip-flop DFF9; the second input end of the seventh D flip-flop DFF7, the second input end of the eighth D flip-flop DFF8 and the second input end of the ninth D flip-flop DFF9 are all connected with the output end of the injection-locked multiphase clock generating circuit; The first output end and the second output end of the sixth D flip-flop DFF6 are respectively as the output ends V CP and V CN of the logic decision circuit; the first output end and the second output end of the seventh D flip-flop DFF7 are respectively as the output ends V CP1P and V CP1N of the logic decision circuit; the first output end and the second output end of the eighth D flip-flop DFF8 are respectively as the output ends V CP2P and V CP2N of the logic decision circuit; the first output end and the second output end of the ninth D flip-flop DFF9 are respectively as the output ends V CP3P and V CP3N of the logic decision circuit; The voltage / current converter comprises a polarity conversion switch, a voltage / current conversion unit and an output control circuit, an output end of the polarity conversion switch is connected with an input end of the voltage / current conversion unit, an output end of the voltage / current conversion unit is connected with an input end of the output control circuit; an input end of the polarity conversion switch is connected with an output end V CP 、 CN of the logic decision circuit; an input end of the output control circuit is connected with an output end V CP1P 、 CP2P 、 CP3P 、 CP1N 、 CP2N 、 CP3N of the logic decision circuit.

2. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that, The loop filter comprises a resistor R L , a capacitor C L1 and a capacitor C L2 ; the input end of the resistor R L is connected with the output end of the voltage / current converter and the input end of the capacitor C L2 ; the input end of the capacitor C L1 is connected with the output end of the resistor R L ; the output end of the capacitor C L1 is connected with the ground level; the output end of the capacitor C L2 is connected with the ground level; and the input end of the capacitor C L2 is connected with the input end of the LC voltage-controlled oscillator.

3. The high speed clock and data recovery circuit supporting dual mode input of claim 1, wherein, The data recovery circuit comprises a sample-and-hold circuit, resistors R1, R2, R3, R4, R5, R6, first to fifth comparators, first to fifth D flip-flops, an exclusive NOR gate and an AND gate. The differential input terminal of the first delay unit of the voltage-controlled delay line is connected to the output terminal of the LC voltage-controlled oscillator; the first to eighth delay units of the voltage-controlled delay line are arranged sequentially, with the positive output terminal of the previous delay unit connected to the inverting input terminal of the next delay unit, and vice versa; the first to eighth delay units of the voltage-controlled ring oscillator are arranged sequentially, with the positive output terminal of the previous delay unit connected to the inverting input terminal of the next delay unit, and vice versa; the first to eighth delay units of the voltage-controlled delay line correspond one-to-one with the first to eighth delay units of the voltage-controlled ring oscillator; the positive output terminal of each delay unit of the voltage-controlled delay line is connected to the positive output terminal of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer, and the inverting output terminal of each delay unit of the voltage-controlled delay line is connected to the inverting output terminal of the corresponding delay unit in the voltage-controlled ring oscillator through another injection buffer; the positive output terminal CK of the fourth delay unit of the voltage-controlled delay line... r3 Connected to the first input terminal of the frequency and phase detector, the inverting output terminal CK r11 Connected to the second input terminal of the frequency and phase detector; the positive output terminal CK of the eighth delay unit of the voltage-controlled delay line. r15 Connect to the third input terminal of the frequency and phase detector, and the inverting output terminal CK r7 Connect to the fourth input terminal of the frequency and phase detector; connect the output terminal of the frequency and phase detector to the input terminal of resistor R; connect the output terminal of resistor R to the input terminal of capacitor C1 and the input terminal of the charge pump; connect the output terminal of capacitor C1 to ground; connect the output terminal of the charge pump to V. COSC It is connected to the input terminal of capacitor C2, the voltage control input terminal of the voltage-controlled delay line, and the voltage control input terminal of the voltage-controlled ring oscillator; the output terminal of capacitor C2 is connected to ground.

4. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that, The polarity conversion switch comprises first to fourth switches S1, S2, S3 and S4; the voltage / current conversion unit comprises first to third voltage / current conversion units; and the output control circuit comprises first to third transmission gates TG1, TG2 and TG3. The first input end of the sample-and-hold circuit is connected with high-speed input data; the second input end of the sample-and-hold circuit is connected with the output end CK of the injection-locked multiphase clock generating circuit 2n The output end of the sample-and-hold circuit is connected with the first input end of the first comparator, the first input end of the second comparator and the first input end of the third comparator; the input end of the resistor R1 is connected with the ground level; the output end V RefL of the resistor R1 is connected with the input end of the resistor R2 and the second input end of the third comparator; the output end of the resistor R2 is connected with the input end of the resistor R3; the output end V RefM of the resistor R3 is connected with the input end of the resistor R4 and the second input end of the second comparator; the output end of the resistor R4 is connected with the input end of the resistor R5; the output end V RefH of the resistor R5 is connected with the input end of the resistor R6 and the second input end of the first comparator; the output end of the resistor R6 is connected with the input reference voltage V Ref ; the third input end of the first comparator, the third input end of the second comparator and the third input end of the third comparator are all connected with the output end CK of the injection-locked multiphase clock generating circuit 2n+1 ; the output end of the first comparator is connected with the first input end of the first D flip-flop DFF1; the output end of the second comparator is connected with the first input end of the second D flip-flop DFF2; the output end of the third comparator is connected with the first input end of the third D flip-flop DFF3; the output end T H of the first D flip-flop DFF1 is connected with the first input end of the XNOR gate; the output end T M of the second D flip-flop DFF2 is connected with the second input end of the XNOR gate and the first input end of the fourth D flip-flop DFF4; the output end of the XNOR gate is connected with the first input end of the AND gate; the output end T L of the third D flip-flop DFF3 is connected with the second input end of the AND gate; the output end of the AND gate is connected with the input end of the fifth D flip-flop DFF5; the second input end of the first D flip-flop DFF1, the second input end of the second D flip-flop DFF2 and the second input end of the third D flip-flop DFF3 are all connected with the output end CK of the injection-locked multiphase clock generating circuit 2n+4 ; the second input end of the fourth D flip-flop DFF4 and the second input end of the fifth D flip-flop DFF5 are both connected with the output end CK3 of the injection-locked multiphase clock generating circuit.

5. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, wherein, The high-speed input data is NRZ data or PAM4 data. the first input terminal V of the first switch S1 P the positive output terminal of the linear phase discriminator and the first input terminal of the second switch S2; the first input terminal V of the third switch S3 N the negative output terminal of the linear phase discriminator and the first input terminal of the fourth switch S4; the second input terminal of the first switch S1 and the second input terminal of the third switch S3 are connected to the output terminal V of the logic decision circuit CP the second input terminal of the second switch S2 and the second input terminal of the fourth switch S4 are connected to the output terminal V of the logic decision circuit CN the output terminal of the first switch S1 is connected to the output terminal of the fourth switch S4, the inverting input terminal of the first voltage / current conversion unit, the inverting input terminal of the second voltage / current conversion unit and the inverting input terminal of the third voltage / current conversion unit; the output terminal of the second switch S2 is connected to the output terminal of the third switch S3, the non-inverting input terminal of the first voltage / current conversion unit, the non-inverting input terminal of the second voltage / current conversion unit and the non-inverting input terminal of the third voltage / current conversion unit; the output terminal of the first voltage / current conversion unit is connected to the first input terminal of the first transmission gate TG1; the output terminal of the second voltage / current conversion unit is connected to the first input terminal of the second transmission gate TG2; the output terminal of the third voltage / current conversion unit is connected to the first input terminal of the third transmission gate TG3; the positive control input terminal of the first transmission gate TG1 is connected to the output terminal V of the logic decision circuit CP1P the positive control input terminal of the second transmission gate TG2 is connected to the output terminal V of the logic decision circuit CP2P the positive control input terminal of the third transmission gate TG3 is connected to the output terminal V of the logic decision circuit CP3P the negative control input terminal of the first transmission gate TG1 is connected to the output terminal V of the logic decision circuit CP1N the negative control input terminal of the second transmission gate TG2 is connected to the output terminal V of the logic decision circuit CP2N the negative control input terminal of the third transmission gate TG3 is connected to the output terminal V of the logic decision circuit CP3N the output terminal of the first transmission gate TG1 is connected to the output terminal of the second transmission gate TG2 and the output terminal of the third transmission gate TG3.

6. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, wherein, The linear phase discriminator is composed of eight identical linear phase discriminator slice units connected in parallel, the input ends of the eight linear phase discriminator slice units are connected in series to receive the same high-speed input data, and the output ends of the eight linear phase discriminator slice units are used for parallel control of the voltage / current converter.

7. The double-mode input supported high-speed clock and data recovery circuit of claim 1, wherein, ​ 8. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, wherein, The voltage / current converter is connected in parallel by 8 same voltage / current converter slice units, the outputs of the 8 voltage / current converter slice units control the loop filter and the LC voltage-controlled oscillator in series; the data recovery circuit is connected in parallel by 8 same data recovery circuit slice units, the parallel outputs of the 8 data recovery circuit slice units are used for controlling the logic decision circuit; the logic decision circuit is connected in parallel by 8 same logic decision circuit slice units, the outputs of the 8 logic decision circuit slice units control the voltage / current converter.

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