Shift driving system of phased-array antenna

Abstract

The invention discloses a shift driving system of a phased-array antenna, which relates to the field of phased-array antennas and comprises an upper computer, a shift register driving board and the phased-array antenna. The upper computer sends phased-array antenna control data, a clock signal and a synchronous trigger signal to the shift register driving board; the shift register drive board converts the serial control data of the phased-array antenna into parallel control data of each unit of the phased-array antenna through the shift register serial array; and according to the synchronous trigger signal, each path of parallel control data is synchronously sent to the corresponding unit, and each unit controls the radio frequency diode to work according to the parallel control data. According to the invention, the complexity of the RIS phased-array antenna driving control system can be effectively reduced, the hardware resource consumption is reduced, the cost of the driving system is reduced, and large-scale application of the RIS phased-array antenna in a mobile communication network is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array antennas, and more particularly to a displacement driving system of a phased array antenna. Background Art

[0002] RIS phased array technology is an emerging antenna technology. In order to save equipment, energy consumption and deployment costs of communication base stations, the global communications industry has begun to study RIS technology. RIS is usually an array surface composed of large-scale, reconfigurable units, which can intelligently reconfigure the wireless transmission environment and significantly improve the performance of mobile communication networks.

[0003] However, due to the large number of array units, each antenna has hundreds of unit modules, and sometimes even thousands of modules, which is undoubtedly a huge pressure on the control chip. According to the traditional control chip, one IO corresponds to one control, which obviously cannot meet the driving requirements; and the use of traditional FPGA for control will consume a lot of hardware resources, and the cost cannot be effectively controlled.

[0004] Therefore, how to reduce the complexity of the RIS phased array antenna drive control system, reduce hardware resource consumption, and reduce the cost of the drive system is an urgent problem that technical personnel in this field need to solve. Summary of the invention

[0005] In view of this, the present invention provides a shift drive system for a phased array antenna, which controls the beam of the phased array antenna through an LVDS serial port to reduce hardware resource consumption, uses a shift register to control the antenna RF diode, and adopts a serial-to-parallel conversion method to drive the antenna, thereby reducing the complexity of the phased array antenna drive control system.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] The invention discloses a shift drive system for a phased array antenna, comprising: a host computer, a shift register drive board, and a phased array antenna;

[0008] The host computer sends phased array antenna control data, clock signal and synchronization trigger signal to the shift register driver board;

[0009] The shift register driving board converts the serial control data of the phased array antenna into parallel control data of each unit of the phased array antenna through a shift register serial array; and according to the synchronization trigger signal, each channel of the parallel control data is synchronously sent to the corresponding unit, and each unit controls the operation of the RF diode according to the parallel control data.

[0010] Furthermore, the shift register driver board includes an input data buffer, a shift register serial array, a first output buffer, a second output buffer, an output interface, and a power supply module;

[0011] The input data buffer is used to receive and buffer the phased array antenna control data, and input the data into the data input end of the shift register serial array bit by bit;

[0012] The shift register serial array receives the clock signal, and shifts the input phased array antenna control data once in each clock cycle, and caches the data in the corresponding first output cache; until all the phased array antenna control data cached in the input data cache is shifted;

[0013] The shift register serial array receives the synchronous trigger signal, and caches the data in each of the first output buffers into the corresponding second output buffer each time a transition trigger is received;

[0014] When each of the second output buffers is full, the corresponding output interface sends the data to the corresponding unit of the phased array antenna, and then clears the second output buffer;

[0015] The power supply module supplies power to the input data buffer, the control shift register, the first output buffer, the second output buffer and the output interface.

[0016] Furthermore, the first output buffer, the second output buffer and the output interface all correspond one-to-one to the output ends of the shift register serial array.

[0017] Furthermore, the cache size of the first output cache is 1 bit, and the cache size of the second output cache is 14 bits, including 8 bits of phase control data and 6 bits of phase amplitude data.

[0018] Furthermore, the shift register serial array is composed of one shift register or multiple shift registers cascaded; the shift register includes a serial data input terminal, a clock signal input terminal, a trigger signal input terminal, a power supply input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, a sixth output terminal, a seventh output terminal, an eighth output terminal, and a cascade output terminal.

[0019] Further, when the shift register serial array is composed of one shift register, the data input terminal of the shift register serial array is the serial data input terminal;

[0020] When the shift register serial array is composed of multiple cascaded shift registers, the data input end of the shift register serial array is the serial data input end of the first cascaded shift register; when cascading, the cascade output end of the previous stage shift register is connected to the serial data input end signal of the next stage; the output ends of the cascaded shift registers are arranged in sequence as the output ends of the shift register serial array.

[0021] Furthermore, the clock signal input terminal and the trigger signal input terminal of the shift register are both connected to the host computer signal to receive the clock signal and the synchronous trigger signal.

[0022] Furthermore, the host computer outputs the phased array antenna control data via an LVDS serial port, and the number of the LVDS serial ports is consistent with and corresponds one to one with the number of the shift register driver boards, which is one or more.

[0023] Furthermore, when there are multiple LVDS serial ports, all units of the phased array antenna are first divided into multiple groups, and then the phased array antenna control data of each group is sent to the corresponding shift register driver board.

[0024] It can be known from the above technical scheme that compared with the prior art, the present invention discloses a shift drive system for a phased array antenna, which adopts a shift register serial array structure, can convert the serial data sent by the host computer into parallel data, and can synchronously send the parallel control data to the corresponding antenna unit through a synchronous trigger signal, so as to ensure the accurate synchronization of the phase and amplitude data of each unit, and improve the beamforming performance of the phased array antenna. And it supports single or multiple LVDS serial ports to output antenna control data, and can flexibly configure the number of drive boards according to the number of antenna array elements to meet the driving requirements of phased array antennas of different sizes; the shift register drive board includes input buffer, shift register array, output buffer and other modules, and has a clear structure, which is conducive to the maintenance and upgrading of the system; the interface between the shift register drive board and the host computer and the antenna is standardized, which is convenient for integration and expansion with other systems. The present invention can effectively reduce the complexity of the RIS phased array antenna drive control system, reduce the consumption of hardware resources, reduce the cost of the drive system, and facilitate the large-scale application of RIS phased array antennas in mobile communication networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0026] Figure 1 It is a schematic diagram of the overall structure of an embodiment of the present invention.

[0027] Figure 2 FIG. 4 is a schematic diagram of a shift register according to an embodiment of the present invention.

[0028] Figure 3 Schematic diagram of the shift register cascade structure according to an embodiment of the present invention.

[0029] Figure 4 Schematic diagram of the timing relationship of the shift register according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The embodiment of the present invention discloses a displacement driving system of a phased array antenna, such as Figure 1 As shown, it includes: a host computer, a shift register driver board, and a phased array antenna;

[0032] The host computer sends the phased array antenna control data, clock signal and synchronization trigger signal to the shift register driver board;

[0033] The shift register driver board converts the serial phased array antenna control data into parallel control data of each unit of the phased array antenna through the shift register serial array; and according to the synchronous trigger signal, each parallel control data is synchronously sent to the corresponding unit, and each unit controls the operation of the RF diode according to the parallel control data.

[0034] In a specific embodiment, the shift register driver board includes an input data buffer, a shift register serial array, a first output buffer, a second output buffer, an output interface, and a power supply module;

[0035] The input data buffer is used to receive and buffer the phased array antenna control data, and input the data into the data input end of the shift register serial array bit by bit;

[0036] The shift register serial array receives the clock signal, and shifts the input phased array antenna control data once in each clock cycle, and caches it in the corresponding first output cache; until the shift of all the phased array antenna control data cached in the input data cache is completed;

[0037] The shift register serial array receives a synchronous trigger signal, and caches the data in each first output buffer into the corresponding second output buffer every time a jump trigger is received;

[0038] When each second output buffer is full, it is sent to the corresponding unit of the phased array antenna by the corresponding output interface, and then the second output buffer is cleared;

[0039] The power supply module supplies power to the input data buffer, the control shift register, the first output buffer, the second output buffer and the output interface.

[0040] In a specific embodiment, the first output buffer, the second output buffer and the output interface all correspond one-to-one to the output ends of the shift register serial array.

[0041] In a specific embodiment, the cache size of the first output cache is 1 bit, and the cache size of the second output cache is 14 bits, including 8 bits of phase control data and 6 bits of phase amplitude data.

[0042] In a specific embodiment, the shift register serial array is composed of one shift register or multiple shift registers cascaded; the shift register includes a serial data input terminal, a clock signal input terminal, a trigger signal input terminal, a power supply input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, a sixth output terminal, a seventh output terminal, an eighth output terminal, and a cascade output terminal.

[0043] In a specific embodiment, when the shift register serial array is composed of one shift register, the data input terminal of the shift register serial array is a serial data input terminal;

[0044] When the shift register serial array is composed of multiple cascaded shift registers, the data input end of the shift register serial array is the serial data input end of the first shift register in the cascade; when cascading, the cascade output end of the previous stage shift register is connected to the serial data input end signal of the next stage; the output ends of the cascaded shift registers are arranged in sequence as the output ends of the shift register serial array.

[0045] Specifically, the shift register is as follows Figure 2 As shown in the figure, SER represents the serial data input terminal, SCK represents the clock signal input terminal, RCK represents the trigger signal input terminal; VCC represents the power supply input terminal, and the power supply voltage is 3.3V; Q0 to Q7 represent the first output terminal to the eighth output terminal respectively, and SDO represents the cascade output terminal; CON1 to CON8 represent the 1st to 8th parallel control data output by the shift register serial array respectively.

[0046] The main functions of the shift register are: the SER end receives the serial control data stream provided by the host computer. In order to maintain the stability of data reception, the shift register driver board is provided with an input data cache. The size of the cache capacity is set to correspond to the number of phased array antenna units. For example, if the number of phased array antenna units is 8, then the input data cache capacity is 8 binary bits. SCK0 is the synchronous clock signal that accompanies the data. After each clock cycle, the data is shifted once, and in accordance with the time sequence of the clock, it shifts from Q0 to Q7, and finally shifts to SDO to the next chip. When the data is shifted, the host computer sends a synchronous trigger signal RCK0, and the first output cache corresponding to each output end transfers one bit of cached data to the second output cache. The timing relationship of a bit register is as follows: Figure 4 The cache size of the second output cache is 14 bits. When the cache is full, the complete 8-bit phase control data and 6-bit phase amplitude data for controlling the phased array antenna unit are obtained, which are directly and synchronously sent to the corresponding antenna units through the output interface and signal line. Each unit adjusts the excitation phase and amplitude of the array element according to the phase data and amplitude data. The excitation phase is controlled by adjusting the working time of the RF diode, and the excitation amplitude is adjusted by controlling the power of the RF diode. The power of the RF diode is the square of the excitation amplitude.

[0047] like Figure 3 As shown, two shift registers are cascaded, where U1 represents shift register No. 1, and U2 represents shift register No. 2. The eight outputs of shift register No. 2 correspond to the 9th to 16th parallel control data of the shift register serial array. The number of cascaded shift registers is adapted to the unit direction of the phased array antenna. Taking the control of 256 units as an example, each shift register chip has 8 outputs, and 256 outputs require 32 shift register chips. Figure 1 As shown, a shift register requires three-way control, data-clock-synchronization. The clock signals of the 32 shift registers and the input ends of the synchronization trigger signal are connected together respectively, and only two control signals are still needed. The data of shift register No. 1 is input by SER, and finally connected to the SER input of shift register No. 2 through SDO output; and so on, through SER and SDO, the data chains of the last 32 shift registers are cascaded together, and the data is transmitted from Q0 to Q8, from Q8 to Q16, and finally to Q256, and finally a SER data input is realized, which is converted into parallel data output of Q1~Q256, which is equivalent to 256 SCK clocks. If necessary, Q1~Q512 can be cascaded, or even more, but the control IO of the control chip has always used only three, and more driving paths are obtained by serial-to-parallel conversion. When the phased array units reach tens of thousands, the driving method of this shift register has more obvious advantages.

[0048] In a specific embodiment, the clock signal input terminal and the trigger signal input terminal of the shift register are both connected to the host computer signal to receive the clock signal and the synchronous trigger signal.

[0049] In a specific embodiment, the host computer outputs the phased array antenna control data through the LVDS serial port, and the number of the LVDS serial port and the shift register driver board is consistent and one-to-one corresponding, and the number is one or more.

[0050] In a specific embodiment, when there are multiple LVDS serial ports, all units of the phased array antenna are first divided into multiple groups, and then the phased array antenna control data of each group is sent to the corresponding shift register driver board.

[0051] Specifically, when there are a large number of shift registers and multiple units are controlled in parallel through a single LVDS serial port, the control data of the phased array antenna is long. Due to the frequency limitation of the synchronous clock signal, the delay between each control signal will increase. By grouping and controlling multiple LVDS serial port signals, the control signal delay can be effectively reduced without significantly increasing the number of IO interfaces of the host computer control chip.

[0052] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0053] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A displacement drive system for a phased array antenna, characterized in that: include: Host computer, shift register driver board, phased array antenna; The host computer sends phased array antenna control data, clock signal and synchronization trigger signal to the shift register driver board; The shift register driving board converts the serial control data of the phased array antenna into parallel control data of each unit of the phased array antenna through a shift register serial array; and according to the synchronization trigger signal, each channel of the parallel control data is synchronously sent to the corresponding unit, and each unit controls the operation of the RF diode according to the parallel control data.

2. The phased array antenna displacement drive system according to claim 1, characterized in that: The shift register driving board includes an input data buffer, a shift register serial array, a first output buffer, a second output buffer, an output interface, and a power supply module; The input data buffer is used to receive and buffer the phased array antenna control data, and input the data into the data input end of the shift register serial array bit by bit; The shift register serial array receives the clock signal, and shifts the input phased array antenna control data once in each clock cycle, and caches the data in the corresponding first output cache; until all the phased array antenna control data cached in the input data cache is shifted; The shift register serial array receives the synchronous trigger signal, and caches the data in each of the first output buffers into the corresponding second output buffer each time a transition trigger is received; When each of the second output buffers is full, the corresponding output interface sends the data to the corresponding unit of the phased array antenna, and then clears the second output buffer; The power supply module supplies power to the input data buffer, the control shift register, the first output buffer, the second output buffer and the output interface.

3. The displacement drive system of a phased array antenna according to claim 2, characterized in that: The first output buffer, the second output buffer and the output interface all correspond one-to-one to the output ends of the shift register serial array.

4. The displacement drive system of a phased array antenna according to claim 2, characterized in that: The cache size of the first output cache is 1 bit, and the cache size of the second output cache is 14 bits, including 8 bits of phase control data and 6 bits of phase amplitude data.

5. The displacement driving system of a phased array antenna according to claim 1, characterized in that: The shift register serial array is composed of one shift register or multiple shift registers cascaded; the shift register includes a serial data input terminal, a clock signal input terminal, a trigger signal input terminal, a power supply input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, a sixth output terminal, a seventh output terminal, an eighth output terminal, and a cascade output terminal.

6. The phased array antenna displacement drive system according to claim 5, characterized in that: When the shift register serial array is composed of one shift register, the data input terminal of the shift register serial array is the serial data input terminal; When the shift register serial array is composed of multiple cascaded shift registers, the data input end of the shift register serial array is the serial data input end of the first cascaded shift register; when cascading, the cascade output end of the previous stage shift register is connected to the serial data input end signal of the next stage; the output ends of the cascaded shift registers are arranged in sequence as the output ends of the shift register serial array.

7. The phased array antenna displacement drive system according to claim 6, characterized in that: The clock signal input terminal and the trigger signal input terminal of the shift register are both connected to the host computer signal to receive the clock signal and the synchronous trigger signal.

8. The phased array antenna displacement drive system according to claim 1, characterized in that: The host computer outputs the phased array antenna control data via an LVDS serial port, and the number of the LVDS serial ports is consistent with and corresponds one to one with the number of the shift register driver boards, and the number is one or more.

9. The phased array antenna displacement drive system according to claim 8, characterized in that: When the number of the LVDS serial ports is multiple, firstly, all the units of the phased array antenna are divided into multiple groups, and then the phased array antenna control data of each group is sent to the corresponding shift register driving board respectively.

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