Autonomous controllable time service method and time service system thereof
By using domestic independent and controllable processors and programmable logic array devices to build a timing system in the Ethernet routing switching solution, the existing solutions have high energy consumption and are unable to effectively solve the internal delay of the equipment, and the high-precision and low-power multi-channel timing function is realized.
Patent Information
- Application Number
- CN202510037005.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-04-11
AI Technical Summary
While supporting the IEEE 1588V2 protocol, the existing Ethernet routing switching solution also has high overall energy consumption and is not suitable for application scenarios with few timing channels, low power consumption requirements, and small device size. It cannot effectively solve the delay problems caused by internal circuits and software resolution protocols of the equipment.
The time delivery system is built using domestic independent and controllable processors and programmable logic array devices. The time delay is calculated through the reference line between the time system unit and the time processing unit, and compensated to the reference clock to achieve accurate time delivery between units.
It realizes a method of completing multiple precise timing while supporting routing. It has the characteristics of autonomous controllability, routing, high timing accuracy and low power consumption. It is suitable for scenarios with low bandwidth, low power consumption and small size.
Smart Images
Figure CN119814217A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of Ethernet communication, and more specifically, to an autonomous and controllable timing method and a timing system thereof. Background Art
[0002] At present, the industry usually uses a central processor plus a three-layer switching chip to provide solutions that can provide Ethernet routing switching and accurate timing. The current mainstream is the solution of international communication giants such as Qualcomm and Broadcom. Under the increasingly stringent requirements of the country for independent control, solutions such as Qualcomm and Broadcom can no longer be used directly under the current situation. The products of domestic Ethernet switching chip manufacturers, while supporting the IEEE 1588V2 protocol, also support a large switching capacity. At the same time, the overall solution has high energy consumption and is not suitable for application scenarios with few timing channels, low power consumption requirements, and small equipment size. At the same time, the IEEE 1588V2 protocol is mainly based on solving the delay between devices during network transmission, but it is not suitable for delays caused by internal circuits of the device and software parsing protocols.
[0003] Based on the above situation, it is urgent to propose an autonomous and controllable timing method and its timing system in a timely manner. Summary of the invention
[0004] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.
[0005] In order to achieve these purposes and other advantages of the present invention, an autonomous and controllable timing method is provided, comprising:
[0006] S1. Use domestically controlled processors and programmable logic array devices to build a timing system including a time unit and a time processing unit;
[0007] S2, using the on-time edge and time-coded TOD reference information output by the time system unit as the reference clock of the time processing unit;
[0008] A reference line is added between the time control unit and the time processing unit to calculate the time delay on the circuit lines of the two units, and the above time delay is compensated to the time value of the reference clock to complete the precise timing between the units;
[0009] S3. After the routing unit calculates the path through the routing algorithm, the Ethernet data packet is stamped with the compensated reference clock by the time processing unit to complete the synchronous timing operation for the external target network terminal.
[0010] Preferably, in S2, the time delay is calculated as follows:
[0011] S20, at time T1, the P0 interface and the P1 interface of the time system unit output the time coding TOD reference information and the punctual edge 1PPS0 to the D0 interface and the D1 interface of the time processing unit respectively, and the P2 interface of the time system unit sends the punctual edge 1PPS1 to the D2 interface of the time processing unit;
[0012] S21, after the time processing unit analyzes the TOD signal, it records the time value T1;
[0013] The time processing unit multiplies the 10MHZ clock given by the constant temperature crystal oscillator and counts the clock cycle from 0;
[0014] S22, after receiving the punctual edge 1PPS1, the D2 interface of the time processing unit records the current clock cycle number n1, so as to obtain the time value It1 caused by the length difference between the reference line and the 1PPS0 signal line by conversion,
[0015] After detecting 1PPS1, the D2 interface of the time processing unit returns a pulse signal FB1 to the P2 interface at the same time;
[0016] S23, after receiving FB1, the P2 interface of the timing unit sends a punctual edge 1PPS2 signal to the D2 interface again;
[0017] S24, after detecting the punctual edge 1PPS2 signal, the D2 interface of the time processing unit records the clock cycle number n2 at this time, obtains a time value IIt2 by conversion, and calculates the line delay ΔT1 from the P1 interface to the D1 interface by the following formula:
[0018] ΔT1=(Δt1 / 2)-t1
[0019] In the above formula, Δt1 is the difference between time value I and time value II;
[0020] S24. The time processing unit compensates ΔT1 to the time value of the reference clock to obtain the accurate current actual time T2.
[0021] Preferably, the time processing unit makes the line delay ΔT1 into an external interface for external manual correction of the value.
[0022] Preferably, in S3, it further includes: after receiving the Ethernet data packet from outside the unit, the time processing unit obtains the current time and re-time stamps the unpacked data according to the IEEE 1588V2 protocol, and then packages and sends it to the outside;
[0023] Among them, when re-time-stamping, the current time needs to be compensated through a feedback comparison mechanism to achieve accurate timing forwarded on the time local unit.
[0024] Preferably, the process of using the feedback comparison mechanism to compensate the real-time local time includes:
[0025] S30, when obtaining the current time T2, the time stamp module of the time processing unit feeds back a pulse signal FB2;
[0026] S31, compare FB2 with the PPS on-time delay 1PPS0 within this second, record the corresponding clock cycle n3, and obtain the clock cycle difference Δt2 consumed by the internal protocol processing of the time processing unit through conversion;
[0027] S32, compensating Δt2 to the time value T2 to obtain the accurate current time T3.
[0028] An autonomous and controllable timing system is applied to an autonomous and controllable timing method, comprising:
[0029] A timing unit providing external timing input;
[0030] A time processing unit that updates the local time based on the reference clock provided by the time system unit;
[0031] A routing unit that gives a path to external Ethernet data through a routing algorithm and timestamps it through a time processing unit;
[0032] Wherein, the time processing unit adopts a field programmable gate array device, the field programmable gate array device is connected with an external RTC real-time clock and a battery through a processor, and the routing unit works on the processor;
[0033] The field programmable gate array device is also connected to a constant temperature crystal oscillator, an Ethernet physical layer transceiver, and a serial port transceiver.
[0034] The present invention at least includes the following beneficial effects: the present invention proposes a simple method that supports routing and can also complete multi-channel precise timing, and has the characteristics of autonomous controllability, routableness, high timing accuracy and low power consumption.
[0035] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 An autonomous and controllable timing system in one embodiment of the present invention;
[0037] Figure 2 It is a principle block diagram of the autonomous and controllable timing method of the present invention;
[0038] Figure 3 The time system unit and the time processing unit of the present invention are
[0039] Figure 4 It is a schematic diagram of the layout of the autonomous and controllable timing system of the present invention;
[0040] Figure 5 The figure is a block diagram of the timing working principle of the timing system unit of the present invention. DETAILED DESCRIPTION
[0041] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.
[0042] Example 1
[0043] The present invention proposes a simple method that can support routing and complete multi-channel precise timing, and has the characteristics of autonomous controllability, routing, high timing accuracy and low power consumption.
[0044] like Figure 1 As shown, the present invention proposes an autonomous and controllable timing method, comprising:
[0045] S1. Select domestically controlled processors and programmable logic array devices to build the timing system; as shown in the attached Figure 1 It can be seen that the constructed circuit is a universal architecture, and no dedicated chips are used. Processors from domestic manufacturers with independent and controllable qualifications such as Loongson Zhongke, Feiteng and other manufacturers, as well as programmable logic array devices with high-speed data interfaces from Fudan Micro, Guowei and other manufacturers can be independently selected.
[0046] S2, the PPS and TOD reference information output by the time synchronization unit are used as reference clocks and transmitted to the time processing unit, and a reference line is set up at the same time. Figure 2-Figure 4As shown, at time T1, the time system unit outputs the time-coded TOD reference information and the punctual edge 1PPS0 at P0 and P1 to the D0 and D1 of the high-precision time processing unit respectively, and at the same time, P2 also sends 1PPS1 to D2 of the high-precision time processing unit. After the high-precision time processing unit analyzes the TOD signal, it records the time value T1. The unit multiplies the frequency of the 10MHZ clock given by the constant temperature crystal oscillator and counts the clock cycle from 0. At the same time, after receiving 1PPS1, the high-precision time processing unit D2 records the current clock cycle number n1, and obtains a time t1 by conversion. This time is the time difference caused by the length difference between the reference line and the 1PPS0 signal line. After D2 detects 1PPS1, it immediately sends a pulse signal FB1 back to P2. After receiving FB1, P2 immediately sends a punctual 1PPS2 signal to D2 again. When D2 detects the signal, it records the number of clock cycles n2 at this time, and obtains a time t2 through conversion, and obtains a time difference Δt1 (i.e., t2-t1). This time difference is twice the line delay of the reference line, so as to calculate the line delay ΔT1 from P1 to D1 (i.e., (Δt1 / 2)-t1), and compensate ΔT1 to the moment value to obtain the accurate current actual time T2. The line delay ΔT1 has an interface for manual modification of the value by the outside;
[0047] The necessary prerequisite for high-precision time processing is to select a highly stable constant temperature crystal oscillator. The 10MHZ clock provided by the crystal oscillator is connected to the time system unit and the high-precision time processing unit at the same time to ensure that the clocks of the two units are low-jitter and highly stable, and the frequency and waveform are consistent, which provides the necessary premise for measuring and calculating various time differences. After entering the high-precision time processing unit, the 10MHZ clock will be multiplied to a 250MHZ clock, so the clock can achieve an accuracy of 4ns. The unit counts clock cycles based on this stable clock source. The accuracy of time processing depends on the frequency stability of the high-stable constant temperature crystal oscillator. Within the operating temperature range, the frequency stability should be required to be no greater than ±5x10 -9 , short-term frequency stability should not be greater than ±5x10 -12 .
[0048] This step realizes the precise timing operation between units.
[0049] S3, such as Figure 1-Figure 2As shown, since the high-precision time processing unit has a certain protocol processing time when timestamping Ethernet data, in this step, by adding a feedback comparison mechanism, a pulse signal FB2 is fed back when the current time is to be obtained, and compared with the PPS punctual delay within this second, the corresponding clock cycle n3 is recorded, and the clock cycle difference is obtained. After conversion, the time Δt2 consumed by the protocol processing is obtained, and it is compensated to the moment value T2 to obtain the accurate current time T3 (i.e., T2+Δt2), and then stamped on the Ethernet data for external transmission.
[0050] This step achieves accurate timing operation during the unit's internal protocol processing.
[0051] Example 2
[0052] The following will be combined with the attached Figure 1-Figure 5 To illustrate in detail, the present invention proposes an autonomous and controllable timing system, which is constructed by using a domestic autonomous and controllable processor and a programmable logic array device, and mainly includes a routing unit 1, a timing unit 2, a high-precision time processing unit 3, an Ethernet physical layer transceiver 4, and a serial port transceiver 5. In practical applications, the routing unit works on a processor 10, and the high-precision time processing unit 3 is implemented by a field programmable gate array device FPGAⅠ. The timing unit mainly includes: a timing module 20 composed of a field programmable gate array device FPGAⅡ+ARM processor, a high-stable constant temperature crystal oscillator 21, and a battery / RIC real-time clock Ⅱ 22:
[0053] 1. Processor
[0054] The routing unit mainly uses the routing algorithm to give a path to the Ethernet data entering the unit, and then sends it to the high-precision time processing unit for time stamping;
[0055] The routing unit works on the processor, mainly completing functions such as data exchange control, routing protocol processing, network situation awareness, dynamic flow control, and time-frequency processing, so as to realize the networking between multiple lower-level terminal devices and ensure the smooth routing and exchange of data from each terminal device. The processor uses self-controlled components, and manufacturers such as Loongson and Feiteng can be selected.
[0056] 2. Field Programmable Gate Array Devices
[0057] The functions of the high-precision time processing unit are mainly completed by field programmable gate array devices. It mainly completes three functions: first, the high-precision time processing unit parses the year, month, day, hour, minute, and second information according to the TOD and 1PPS signals given by the time system unit, updates the local time of the high-precision time processing unit in real time, and uses the reference clock given by the high-stable constant temperature crystal oscillator of the time system unit for internal timing; second, it receives Ethernet data packets from outside the unit, unpacks them, re-time-stamps the real-time local time according to the IEEE 1588V2 protocol, and then encapsulates them and sends them out; third, it directly copies multiple copies of the TOD and 1PPS signals given by the time system unit and distributes them to external terminals.
[0058] The high-precision time processing unit can provide a reliable synchronous time source of 1-50 nanoseconds due to the high-precision and low-latency characteristics of the field programmable gate array device itself, and the low-jitter characteristics of the reference clock provided by the high-stable constant temperature crystal oscillator.
[0059] In actual applications, high-precision time processing units need to use devices with integrated high-speed transceivers, such as Guowei, Fudan Micro and other manufacturers. The power consumption of field programmable gate array devices is generally low, generally not exceeding 3W. Together with the processor, the overall solution generally does not exceed 10W. The high-speed transceiver mainly completes the transmission and reception of Ethernet SGMII format data and PCIE bus data. The Ethernet data is converted into SGMII format by the Ethernet physical layer transceiver and enters the high-speed transceiver of the field programmable gate array device. After real-time timestamping according to the IEEE 1588V2 protocol inside the field programmable gate array device, it is converted into PCIE bus data and enters the processor. The reverse is the same. For autonomous and controllable devices, devices with high-speed transceivers from Guowei and Fudan Microstrip can be selected.
[0060] 3. The timing unit is made into a module with independent functions to improve the maintainability of the system. The timing working principle block diagram of the timing unit is as follows: Figure 5 The time synchronization module receives the external input pps and time code tod reference information, parses the year, month, day, hour, minute, second information and the punctual time of the pps rising edge, synchronizes and updates the local time of the real-time operating system and the external RTC real-time clock through the module ARM processor and logic unit, filters and smoothes the input punctual edge pps information, tames and locks the local high-stability constant temperature crystal oscillator, and combines high-precision time code information processing technology to achieve 1pps, tod, NTP and other timing functions synchronized with the external reference source.
[0061] When the external source is disconnected or invalid, the timekeeping function can be achieved by relying on its own frequency source. In the event of a power outage, the power-off timekeeping function can be achieved through the external RTC real-time clock.
[0062] The ARM processor can choose the 32 series of single-chip microcomputers, and there are many domestic independent controllable manufacturers, such as Zhongtian Xingkong. The logic unit is a field programmable logic array device, and ordinary devices from Fudan Micro and Guowei can be selected. Or, in order to reduce costs, the processor of the routing unit and the logic device of the high-precision time unit can be directly reused.
[0063] 4. Ethernet physical layer transceiver
[0064] The Ethernet physical layer transceiver mainly converts the digital signal in SGMII format into an analog signal so as to transmit data through the network medium (such as twisted pair or optical cable). For independent and controllable devices, devices from manufacturers such as Shengke Networks and Chengdu Ruiyuan can be selected.
[0065] 5. Serial transceiver
[0066] The serial port transceiver mainly converts the TOD and 1PPS signals of TTL level into RS232 and RS422 level signals. Self-controlled devices can be selected from manufacturers such as Wuxi Tianhe and Chengdu Ruiyuan.
[0067] 6. High stability constant temperature crystal oscillator
[0068] High-stability constant temperature crystal oscillator minimizes the change in oscillator output frequency caused by ambient temperature changes, so the clock stability provided is very high. For self-controlled devices, Chengdu Hengjing's devices can be selected. The main technical parameters of the crystal oscillator selected in the example are shown in Table 1 below:
[0069] Table 1
[0070]
[0071]
[0072] 7. RTC real-time clock, battery and other components.
[0073] In case of power failure, the external RTC real-time clock is used to realize the power failure timing function.
[0074] In actual applications, field programmable gate array devices are selected according to the number of routes required for routing switching. For example, if only 4 Ethernet data channels are required, a field programmable gate array device that supports more than and close to 5 high-speed data interfaces (4 SGMII channels and 1 PCIE channel) should be selected, so as not to cause excessive redundancy in switching capacity. The power consumption of field programmable gate array devices themselves is much lower than that of finished three-layer switching chips, so the heat generation is lower. Figure 2The implementation method shown in the figure shows that the overall solution requires fewer devices, has a high degree of integration, and a small circuit area. The system is well suited for low-bandwidth, low-power, and small-volume scenarios, while also supporting Ethernet routing and high-precision timing functions.
[0075] The circuits involved in building the system of the present invention do not use dedicated chips. Instead, the device integration is made autonomous and controllable by independently selecting processors from domestic manufacturers with independent and controllable qualifications, such as Loongson Zhongke, Feiteng, etc., and programmable logic array devices with high-speed data interfaces from manufacturers such as Fudan Micro and Guowei.
[0076] The above solution is only an illustration of a preferred embodiment, but is not limited thereto. When implementing the present invention, appropriate replacement and / or modification can be performed according to user needs.
[0077] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and the embodiments. It can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily realized. Therefore, without departing from the general concept defined by the claims and equivalent scope, the present invention is not limited to the specific details and the illustrations shown and described here.
Claims
1. An autonomous and controllable timing method, characterized in that: include: S1. Use domestically controlled processors and programmable logic array devices to build a timing system including a time unit and a time processing unit; S2, using the on-time edge and time-coded TOD reference information output by the time system unit as the reference clock of the time processing unit; A reference line is added between the time system unit and the time processing unit to calculate the time delay on the circuit lines of the two, and the above time delay is compensated to the time value of the reference clock to complete the precise timing between the units; S3. After the routing unit calculates the path through the routing algorithm, the Ethernet data packet is stamped with the compensated reference clock by the time processing unit to complete the synchronous timing operation for the external target network terminal.
2. The autonomous and controllable timing method according to claim 1, characterized in that: In S2, the time delay is calculated as follows: S20, at time T1, the P0 interface and the P1 interface of the time system unit output the time coding TOD reference information and the punctual edge 1PPS0 to the D0 interface and the D1 interface of the time processing unit respectively, and the P2 interface of the time system unit sends the punctual edge 1PPS1 to the D2 interface of the time processing unit; S21, after the time processing unit analyzes the TOD signal, it records the time value T1; The time processing unit multiplies the 10MHZ clock given by the constant temperature crystal oscillator and counts the clock cycle from 0; S22, after receiving the punctual edge 1PPS1, the D2 interface of the time processing unit records the current clock cycle number n1, so as to obtain the time value It1 caused by the length difference between the reference line and the 1PPS0 signal line by conversion, After detecting 1PPS1, the D2 interface of the time processing unit returns a pulse signal FB1 to the P2 interface at the same time; S23, after receiving FB1, the P2 interface of the timing unit sends a punctual edge 1PPS2 signal to the D2 interface again; S24, after detecting the punctual edge 1PPS2 signal, the D2 interface of the time processing unit records the clock cycle number n2 at this time, obtains a time value IIt2 by conversion, and calculates the line delay ΔT1 from the P1 interface to the D1 interface by the following formula: ΔT1=(Δt1 / 2)-t1 In the above formula, Δt1 is the difference between time value I and time value II; S24. The time processing unit compensates ΔT1 to the time value of the reference clock to obtain the accurate current actual time T2.
3. The autonomous and controllable timing method according to claim 2, characterized in that: The time processing unit makes the line delay ΔT1 into an external interface for external manual correction of the value.
4. The autonomous and controllable timing method according to claim 1, characterized in that: In S3, it also includes: after receiving the Ethernet data packet from outside the unit, the time processing unit obtains the current time and re-time stamps the unpacked data according to the IEEE 1588V2 protocol, and then packages it for external transmission; Among them, when re-time-stamping, the current time needs to be compensated through a feedback comparison mechanism to achieve accurate timing forwarded on the time local unit.
5. The autonomous and controllable timing method according to claim 1, characterized in that: The process of compensating the real-time local time using the feedback comparison mechanism includes: S30, when obtaining the current time T2, the time stamp module of the time processing unit feeds back a pulse signal FB2; S31, compare FB2 with the PPS on-time delay 1PPS0 in this second, record the corresponding clock cycle n3, and obtain the clock cycle difference Δt2 consumed by the internal protocol processing of the time processing unit through conversion; S32, compensating Δt2 to the time value T2 to obtain the accurate current time T3.
6. An autonomous and controllable timing system, applied to the autonomous and controllable timing method according to any one of claims 1 to 4, characterized in that: include: A timing unit providing external timing input; A time processing unit that updates the local time based on the reference clock provided by the time system unit; A routing unit that gives a path to external Ethernet data through a routing algorithm and timestamps it through a time processing unit; Wherein, the time processing unit adopts a field programmable gate array device, the field programmable gate array device is connected with an external RTC real-time clock and a battery through a processor, and the routing unit works on the processor; The field programmable gate array device is also connected to a constant temperature crystal oscillator, an Ethernet physical layer transceiver, and a serial port transceiver.