Method, device and electronic device for optimizing adaptive cache queue based on 104 protocol data

Abstract

The present invention provides a method, device, and electronic device for optimizing data adaptive cache queues based on the 104 protocol. The implementation scheme is as follows: determining the comprehensive priority of the first data based on attributes such as the data type, time sensitivity, and data priority of the first data; merging the first cache queues based on the data transmission frequency of each of the multiple first cache queues to obtain a merged queue; determining the insertion order of the first data based on the total number of arranged data in the merged queue and the comprehensive priority of the first data, so as to insert the first data into the merged queue; splitting the merged queue after the data is inserted based on the starting bit data and the last bit data of each first cache queue, so as to determine each updated first cache queue based on each split queue; and sending the data in each updated first cache queue separately based on the 104 protocol. The present invention can optimize data transmission performance.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a method, device and electronic device for optimizing a cache queue based on 104 protocol data self-adaptation. Background Art

[0002] Protocol 104 is a widely used communication protocol in power systems, enabling data transmission and control between power devices. In distribution network automation, the reliable transmission of Protocol 104 data is crucial for the safe and stable operation of the power grid. As a TCP / IP-based protocol, Protocol 104 plays a vital role in power systems.

[0003] In practical applications, especially under weak network conditions, the 104 protocol faces numerous challenges. Due to high network latency, high packet loss rates, unstable bandwidth, and the large number of devices (tens of thousands of devices in a single prefecture-level city), the traditional TCP / IP-based 104 protocol performs poorly in terms of data transmission reliability and success rate under weak network conditions. This has a serious impact on key areas such as distribution network automation, potentially leading to inaccurate equipment status monitoring and control command transmission failures, which in turn affects the safe and stable operation of the power grid.

[0004] Furthermore, since the 104 protocol is the current standard for power systems, it cannot be replaced in the short term due to the complexity and stability requirements of power systems. This necessitates finding an effective solution to optimize data transmission performance under weak network conditions without changing the 104 protocol itself or its application interfaces. Summary of the Invention

[0005] The present invention provides a method, device and electronic device for optimizing a cache queue based on 104 protocol data self-adaptation, which can solve at least one of the above technical problems.

[0006] According to one aspect of the present invention, a method for adaptively optimizing a cache queue based on 104 protocol data is provided, comprising:

[0007] Determine, based on the 104 protocol, a data type, time sensitivity, data priority, data structure, and data production method of the first data;

[0008] determining a comprehensive priority of the first data based on a data type, time sensitivity, data priority, data structure, and data production method of the first data;

[0009] Merging the multiple first cache queues based on the data sending frequency of each of the first cache queues to obtain a merged queue;

[0010] determining an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data;

[0011] Inserting the first data into the merge queue based on the insertion order of the first data to obtain the merge queue after the data is inserted;

[0012] Splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues;

[0013] Based on each of the split queues, updating each of the first cache queues to obtain each updated first cache queue;

[0014] Based on the 104 protocol and the updated data sending frequency of each of the first cache queues, the data in each of the updated first cache queues are sent respectively.

[0015] According to another aspect of the present invention, there is provided a device for adaptively optimizing a cache queue based on protocol data 104, comprising:

[0016] a data attribute determination module, configured to determine the data type, time sensitivity, data priority, data structure, and data production method of the first data based on the 104 protocol;

[0017] a comprehensive priority determination module, configured to determine the comprehensive priority of the first data based on the data type, time sensitivity, data priority, data structure, and data production method of the first data;

[0018] a queue merging module, configured to merge the plurality of first cache queues based on a data sending frequency of each of the plurality of first cache queues to obtain a merged queue;

[0019] an insertion order determination module, configured to determine an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data;

[0020] a data insertion module, configured to insert the first data into the merge queue based on an insertion order of the first data, to obtain the merge queue after the data is inserted;

[0021] a queue splitting module, configured to split the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues;

[0022] a queue updating module, configured to update each of the first cache queues based on each of the split queues to obtain each updated first cache queue;

[0023] The data sending module is configured to send the data in each updated first cache queue based on the 104 protocol and the data sending frequency of each updated first cache queue.

[0024] The technical solution of the present invention sets up multiple first cache queues with different data transmission frequencies. When parsing and obtaining first data, the first data's comprehensive priority is determined based on its data type, time sensitivity, data priority, data structure, and data production method under the 104 protocol. The multiple first cache queues are then arranged and merged into a merged queue. The first data's insertion order in the merged queue is determined using the first data's comprehensive priority and the total amount of data in the merged queue. The first data is then inserted into the merged queue according to this insertion order. The merged queue is then split according to the starting and ending data bits of each of the original, unmerged first cache queues, resulting in multiple split queues. Finally, the corresponding, unmerged first cache queues are updated based on each split queue to obtain updated first cache queues. Thus, the first data to be transmitted is not simply arranged in the cache queues according to its comprehensive priority. Instead, data is inserted into the queues by merging, inserting, and splitting the cache queues. Thus, even if the first data to be transmitted has a low comprehensive priority, it may be inserted into a cache queue at a higher position due to other factors, thereby optimizing data transmission performance.

[0025] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are provided for a better understanding of the present invention and do not constitute a limitation of the present invention.

[0027] Figure 1 This is a flow chart of a method for adaptively optimizing cache queues based on protocol data 104 according to an embodiment of the present invention;

[0028] Figure 2 is a schematic diagram of a first sequential queue according to an embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of a distribution network automation terminal according to an embodiment of the present invention;

[0030] Figure 4This is a structural block diagram of a device for adaptively optimizing cache queues based on 104 protocol data according to an embodiment of the present invention;

[0031] Figure 5 is a block diagram of an electronic device for implementing the method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following description of exemplary embodiments of the present invention is made in conjunction with the accompanying drawings, and various details of the embodiments of the present invention are included to facilitate understanding. These details should be considered as merely exemplary. Therefore, it should be appreciated by those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present invention. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0033] Figure 1 This is a flowchart of a method for adaptively optimizing a cache queue based on 104 protocol data according to an embodiment of the present invention.

[0034] like Figure 1 As shown, the adaptive cache queue optimization method based on protocol data 104 may include:

[0035] S110, based on the 104 protocol, determining the data type, time sensitivity, data priority, data structure, and data production method of the first data;

[0036] S120, determining a comprehensive priority of the first data based on a data type, time sensitivity, data priority, data structure, and data production method of the first data;

[0037] S130, merging the multiple first cache queues based on the data sending frequency of each of the multiple first cache queues to obtain a merged queue;

[0038] S140, determining an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data;

[0039] S150, inserting the first data into the merge queue based on the insertion order of the first data, to obtain a merge queue after the data is inserted;

[0040] S160, splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each first cache queue to obtain multiple split queues;

[0041] S170, updating each first cache queue based on each split queue to obtain each updated first cache queue;

[0042] S180 , based on the 104 protocol and the data sending frequency of each updated first cache queue, respectively send the data in each updated first cache queue.

[0043] It can be understood that the first data can be any data in the distribution network, and the data is 104 protocol data.

[0044] For example, the data types under the 104 protocol may include telemetry data, remote control data, remote adjustment data, etc.

[0045] For example, the time sensitivity under the 104 protocol refers to the validity period of the data, for example, valid within one minute, valid within two minutes, etc.

[0046] For example, the data priority level under the 104 protocol may include high, medium, and low, or a numerical level.

[0047] For example, the type of the data structure under the 104 specification may include binary, decimal or structured data.

[0048] For example, the data production methods under the 104 protocol may include frequency-based production and demand-based production.

[0049] Exemplarily, based on the data type, time sensitivity, data priority, data structure, and data production method of the first data, a data type score, a time sensitivity score, a data priority score, a data structure score, and a data production method score are determined, respectively. Based on the data type weight, the time sensitivity weight, the data priority weight, the data structure weight, and the data production method weight, a weighted sum of the data type score, the time sensitivity score, the data priority score, the data structure score, and the data production method score is performed to determine the comprehensive priority of the first data.

[0050] Exemplarily, the comprehensive priority of the first data may be a scoring value.

[0051] For example, the first cache queue can be any cache queue in a buffer zone waiting to transmit data. The data transmission frequencies of each of the multiple first cache queues are different. For example, cache queue Q1 transmits data every two seconds, cache queue Q2 transmits data every minute, and cache queue Q3 transmits data every hour.

[0052] For example, in step S130, all first cache queues can be directly merged. Alternatively, based on the relationship between the first data's overall priority or time sensitivity and each first cache queue, some cache queues can be selected from the multiple first cache queues for merging. After merging the queues, the aforementioned insertion and splitting steps can be performed. Data is then sent based on the splitting steps and the remaining cache queues not participating in the queue.

[0053] For example, in the merged queue, the higher the data sending frequency of the cache queue is, the closer the cache queues are in the merged queue.

[0054] like Figure 2 As shown, cache queue Q1 is sorted before cache queue Q2, and cache queue Q2 is sorted before cache queue Q3, thus forming a merged queue.

[0055] For any data P1, P2, or P3, its insertion position in the merge queue can be determined based on the comprehensive priority of the data P1, P2, or P3, and the data can be inserted into the merge queue according to the insertion position. For example, data P1, P2, or P3 is inserted into the merge queue to form a merge queue after the data is inserted.

[0056] It is understandable that the starting bit data of the first cache queue before the update is the same as the starting bit data of the first cache queue after the update, and the last bit data of the first cache queue before the update is the same as the last bit data of the first cache queue after the update. In this way, according to this requirement, each cache queue in the second sequential queue can be split to obtain an updated first cache queue. Each updated first cache queue is a split queue.

[0057] Of course, in actual operation, the identification information of the above data can be queued, the identification can be inserted, and the queue can be split, so as to improve the data processing efficiency.

[0058] Exemplarily, according to the 104 protocol, the data in the updated first cache queue are sent respectively based on the data sending frequency of the updated first cache queue.

[0059] According to the above embodiment, multiple first cache queues with different data sending frequencies are set. When the first data is parsed and obtained, the comprehensive priority of the first data is determined based on the data type, time sensitivity, data priority, data structure and data production method of the first data under the 104 protocol, and the multiple first cache queues are arranged and merged into a merged queue. The insertion order of the first data in the merged queue is determined using the comprehensive priority of the first data and the total amount of data in the merged queue. The first data is inserted into the merged queue according to the insertion order. Then, the merged queue is split according to the starting bit data and the last bit data of each original first cache queue before the merger. Multiple split queues can be used. Finally, the corresponding first cache queues before the merger are updated according to each split queue to obtain each updated first cache queue. In this way, the first data to be sent is not simply arranged in the cache queue according to its comprehensive priority. Instead, the data is inserted into the queue by merging, inserting, and splitting the cache queue. In this way, even if the comprehensive priority of the first data to be sent is low, it may be inserted into a cache queue at an early position due to other factors. Or even if the comprehensive priority is high, it may be inserted into a cache queue at a late position due to other factors. Thus, data transmission performance can be optimized.

[0060] In one embodiment, the above-mentioned merging of multiple first cache queues based on the data sending frequency of each first cache queue in the multiple first cache queues to obtain a merged queue includes: based on the data sending frequency of each first cache queue in the multiple first cache queues, determining at least one second cache queue in the multiple first cache queues that has a mapping relationship between the data sending frequency and the comprehensive priority of the first data; based on the data sending frequency of each second cache queue, determining the merging order of each second cache queue; based on the merging order of each second cache queue, merging the second cache queues to obtain a merged queue.

[0061] For example, a comprehensive priority level can correspond to multiple data transmission frequencies. For example, if the priority level falls between 80 and 90, it corresponds to multiple data transmission frequencies: data transmission every 10 minutes, data transmission every 15 minutes, and data transmission every 30 minutes. The cache queues corresponding to each of these multiple data transmission frequencies are then used as the second cache queue.

[0062] It can be understood that the second cache queue is one of the multiple first cache queues. The second cache queue is a queue to be merged.

[0063] Exemplarily, the higher the data sending frequency of the second cache queue is, the higher the merging order of the second cache queue is.

[0064] According to the above embodiment, based on the mapping relationship between data transmission frequency and the comprehensive priority of the first data, queues to be merged are screened from multiple first cache queues, and each queue to be merged is merged according to the queue's data transmission frequency to form a merged queue. This reduces the number of queues to be merged and the number of post-splitting operations, while ensuring the insertion efficiency of the queues, thereby improving the efficiency of queue optimization.

[0065] In one embodiment, the above-mentioned merging of multiple first cache queues based on the data sending frequency of each first cache queue in the multiple first cache queues to obtain a merged queue includes: determining the degree of matching between each first cache queue and the first data based on the data sending frequency of each first cache queue in the multiple first cache queues and the time sensitivity of the first data; determining at least one third cache queue in the multiple first cache queues based on the degree of matching between each first cache queue and the first data; determining a merging order of each third cache queue based on the data sending frequency of each third cache queue; and merging each third cache queue based on the merging order of each third cache queue to obtain a merged queue.

[0066] For example, the higher the time sensitivity of the first data, the higher the data transmission frequency of the first cache queue, and the higher the matching degree between the two. The lower the time sensitivity of the first data, the lower the data transmission frequency of the first cache queue, and the higher the matching degree between the two. The higher the time sensitivity of the first data, the lower the data transmission frequency of the first cache queue, and the lower the matching degree between the two. The lower the time sensitivity of the first data, the higher the data transmission frequency of the first cache queue, and the lower the matching degree between the two.

[0067] Illustratively, a distance formula may be used to calculate the distance between the data sending frequency of the first cache queue and the time sensitivity of the first time, and based on the distance between the two, the matching degree between the first cache queue and the first data is determined.

[0068] Exemplarily, based on the matching degree between each first cache queue and the first data, a cache queue with a matching degree greater than a preset matching degree threshold among the multiple first cache queues is used as the third cache queue.

[0069] It is understandable that the third cache queue is one of the multiple first cache queues. The third cache queue is a queue to be merged. The second cache queue in the aforementioned embodiment and the third cache queue in this example are both queues to be merged, and there may be overlapping queues between the two.

[0070] Exemplarily, the higher the data sending frequency of the third cache queue is, the higher the merging order of the third cache queue is.

[0071] According to the above embodiment, the data transmission frequency of each first cache queue and the time sensitivity of the first data are used to determine the degree of match between each first cache queue and the first data. Then, based on the degree of match, queues to be merged are selected from each first cache queue. The order in which the queues to be merged are determined based on the data transmission frequency of each queue to be merged, thereby merging the queues.

[0072] Based on the data transmission frequency of each first cache queue in multiple first cache queues and the time sensitivity of the first data, the degree of matching between each first cache queue and the first data is determined; based on the degree of matching between each first cache queue and the first data, at least one third cache queue is determined in the multiple first cache queues; based on the data transmission frequency of each third cache queue, the merging order of each third cache queue is determined; based on the merging order of each third cache queue, each third cache queue is merged to obtain a merged queue. In this way, it can be ensured that the first data can be inserted into the queue whose data transmission frequency matches its time sensitivity, and the number of queues that need to be merged can be reduced, as well as the number of post-splitting actions, thereby improving the efficiency of queue optimization.

[0073] In one embodiment, the above-mentioned determination of the insertion order of the first data based on the total number of arranged data in the merged queue and the comprehensive priority of the first data may include: determining the sorting percentage of the first data based on the ratio between the comprehensive priority of the first data and a preset comprehensive priority upper limit; determining the sorting order of the first data based on the product of the total number of arranged data in the first sequence queue and the sorting percentage of the first data.

[0074] Exemplarily, the comprehensive priority of the first data may be a score between 0 and 100, and the upper limit of the comprehensive priority is 100.

[0075] Exemplarily, the comprehensive priority of the first data may be an integer level between 1 and 10, and the upper limit of the combined priority is 10.

[0076] For example, if the product of the total number of arranged data in the merged queue and the ranking percentage of the first data is not an integer, it can be rounded to obtain a corresponding integer ranking order.

[0077] According to the above embodiment, the first data can be inserted once to determine its cache queue and position in the cache queue according to its priority, that is, the data sending frequency of the first data and its position in the cache queue corresponding to the data sending frequency are determined.

[0078] In one embodiment, the method further includes: determining a target queue length of each first cache queue based on a data insertion frequency of each first cache queue; and when a queue length of a fourth cache queue among the multiple first cache queues is greater than the target queue length of the fourth cache queue, clearing data on the fourth cache queue so that the queue length of the fourth cache queue after data clearing matches its target queue length.

[0079] It is understood that the fourth cache queue is one of the multiple first cache queues. The fourth cache queue is a queue whose queue length is greater than its corresponding target queue length, that is, a queue whose queue length exceeds its predicted storage space length. The fourth cache queue contains redundant data that needs to be cleared to avoid congestion in the data transmission channel, thereby improving data transmission efficiency.

[0080] Illustratively, at regular intervals, the target queue length of each first cache queue may be determined based on the data insertion frequency of each first cache queue.

[0081] For example, Figure 2 As shown, the target queue lengths of the cache queues Q1, Q2 and Q3 can be adjusted. If the actual queue length of the cache queue exceeds the target queue length, data can be cleared from the cache queue.

[0082] Exemplarily, the faster the data insertion frequency of the first cache queue is, the longer the target queue length of the first cache queue is.

[0083] It can be understood that the queue length is the total amount of data in the queue, and the target queue length is the upper limit of the total amount of data in the queue.

[0084] It can be understood that the second cache queue is any queue in the plurality of first cache queues whose queue length is greater than its corresponding target queue length.

[0085] It can be understood that when the queue length of the second cache queue is greater than its corresponding target queue length, the cache space of the second cache queue is insufficient.

[0086] Exemplarily, the cache space capacity of each first cache queue is set based on the target queue length of the first cache queue.

[0087] According to the above embodiment, the upper limit of the total amount of data allowed to be queued in the cache queue is adjusted in real time based on the frequency of data insertion into the cache queue, ensuring that the queue size can adapt to changes in the data generation rate. Furthermore, if the queue's cache space is insufficient, data can be cleared from the queue to avoid data congestion in the cache queue.

[0088] In one embodiment, the target queue length of each first cache queue is determined based on the data insertion frequency of each first cache queue, including: determining an adjustment coefficient based on the data insertion frequency of the first cache queue; and determining the target queue length of the first cache queue based on the product of the data insertion frequency of the first cache queue and the adjustment coefficient, and the basic queue length corresponding to the first cache queue.

[0089] Exemplarily, different cache queues have corresponding basic queue lengths that are different.

[0090] For example, different data insertion frequencies correspond to different adjustment coefficients, and the faster the frequency, the larger the adjustment coefficient.

[0091] For example, the data insertion frequency can be the frequency of data insertion into the cache queue. Alternatively, it can be considered the update frequency of the cache queue. If each time data is inserted into the cache queue, the queue is updated once. If no new data is inserted into the queue after participating in the aforementioned merging, insertion, and splitting steps, although the queue is nominally an updated queue, it can actually be considered an unupdated queue. Alternatively, the data insertion frequency can be considered the frequency of data generation. For example, the amount of data generated per second.

[0092] Exemplarily, the product of the data insertion frequency of the first cache queue and the adjustment coefficient is summed with 1, and the sum is multiplied by the basic queue length corresponding to the first cache queue to obtain the target queue length of the first cache queue.

[0093] According to the above embodiment, the target queue length of the first cache queue can be accurately adjusted.

[0094] In one embodiment, data cleaning is performed on the fourth cache queue, including: determining historical feedback data of the corresponding historical data based on the attribute information of each second data in each fourth cache queue; determining a comprehensive score of each second data based on the load score of the operating system, the feedback score of the historical feedback data corresponding to each second data, and the dimension score of each information in the attribute information of each second data; and based on the comprehensive score of each second data, cleaning the second data in the fourth cache queue whose comprehensive score does not meet the preset comprehensive score conditions.

[0095] Exemplarily, the attribute information of the second data is the same as the attribute information of the historical data corresponding to the second data. For example, the data type, time sensitivity, data priority, data structure, data generation frequency, and data usage of the second data are the same as the data type, time sensitivity, data priority, data structure, data generation frequency, and data usage of the corresponding historical data.

[0096] Exemplarily, the historical feedback data of the historical data is data that a sending end sends historical data to a receiving end and is fed back by the receiving end.

[0097] For example, embodiments of the present invention can be applied to a distribution network automation terminal serving as a transmitter. The operating system is the transmitter's operating system. The operating system's load score can be determined based on the ratio between the operating system's current load and a preset load limit. For example, the higher the operating system load, the lower the score. When the operating system load is high, the cache size corresponding to the queue needs to be reduced to reduce the load.

[0098] For example, the corresponding score is calculated based on the return time of the feedback data of each type of transmission protocol. For example, the slower the feedback, the lower the score.

[0099] Exemplarily, the attribute information of data includes data type, time sensitivity, data priority, data structure, data generation frequency and data usage method.

[0100] For example, different data types may have different scores: remote control data may have a higher score because it is usually more critical.

[0101] For example, the time sensitivity of data is the validity period of the data. The shorter the validity period of the data, the higher the corresponding dimension score.

[0102] Illustratively, the higher the priority, the higher the score.

[0103] For example, the data structure may be structured data or binary data. For example, structured data may be easier to process, so the score may be slightly lower; while binary data may require more storage space and processing time, so the score may be slightly higher.

[0104] For example, data generated frequently may have a lower score because the space it occupies in the cache will be quickly replaced by new data.

[0105] For example, the score is calculated based on how the data is used. For example, a scenario using the latest data may give the most recently generated data a higher score, while a scenario using the oldest data may give the oldest data a higher score.

[0106] Exemplarily, a weighted sum is performed on the load score of the operating system, the feedback score of the historical feedback data corresponding to the second data, and the dimension score of each information in the attribute information of the second data to obtain a comprehensive score of the second data.

[0107] For example, when the cache space is insufficient, the data items with the lowest comprehensive scores are deleted first. For example, a threshold can be set, and when the comprehensive score of a data item is lower than the threshold, it is regarded as low-priority data that can be deleted.

[0108] According to the above embodiment, the importance of data, i.e., the above-mentioned comprehensive score, can be dynamically determined based on the system load, the speed of feedback data, and the attribute information of the data itself. When the queue cache space is insufficient, the data with low comprehensive scores can be deleted first based on the comprehensive scores.

[0109] In one embodiment, the above-mentioned merged queue after the data is inserted is split based on the starting bit data and the last bit data of each first cache queue to obtain multiple split queues, including: based on the starting bit data and the last bit data of the first cache queue, the corresponding target starting bit data and the target last bit data are determined in the merged queue after the data is inserted; in the merged queue after the data is inserted, the queue from the target starting bit data to the target last bit data is intercepted to obtain a split queue.

[0110] For example, the identifier of the start bit data can be used to determine the target start bit data with the same identifier in the merged queue, and the identifier of the end bit data can be used to determine the target end bit data with the same identifier in the merged queue.

[0111] It is understandable that for each first cache queue, data search and queue interception can be performed according to the steps of this example, so as to obtain multiple split queues. Subsequently, based on the multiple split queues and the remaining first cache queues that did not participate in the merger, the final updated first cache queues are determined.

[0112] According to the above embodiment, queues corresponding to the original queues before merging can be split. Subsequently, the final updated first cache queues can be determined based on the split queues and the remaining first cache queues that did not participate in the merge. Thus, the data in each queue can be sent in combination with the sending frequency of the updated first cache queue.

[0113] Figure 3 It is a structural diagram of a distribution network automation terminal according to an embodiment of the present invention.

[0114] like Figure 3 As shown, any method of the embodiment of the present invention can be applied to Figure 2 In the distribution network automation terminal in the system, the cache optimization and data transmission of the distribution network data are realized. The distribution network automation terminal can be a sending end or a receiving end, and the above method is applied to the sending end.

[0115] When the distribution network automation terminal generates 104 protocol data, the data parsing / processing module parses the data according to the business needs. Based on the parsed information and the cache queue allocation policy, the policy executor writes the 104 protocol data to the corresponding hierarchical priority queue for transmission. Simultaneously, the data acquisition module collects feedback on the current system load and data transmission and submits it to the policy executor. The executor cleans and streamlines the data in the queue based on the current cache size of the hierarchical priority queue, message type, and collected feedback information, optimizing cache space and adjusting the data (message) position in the cache.

[0116] According to the above implementation method, by comprehensively considering multiple factors such as data type (telemetry, remote control, remote adjustment, etc.), data time sensitivity requirements (such as valid within 1 minute), data priority, data content type (such as structured data, binary data, etc.), data generation method (production by frequency, production on demand, etc.), operating system load, data transmission feedback, etc., the sending end cache queue is dynamically configured and adjusted in real time to ensure that important data is stored in the cache queue and sent first, and ultimately achieves the optimization of 104 protocol data transmission efficiency based on the characteristics of high network latency, large packet loss rate, unstable bandwidth and a large number of devices in a weak network environment (such as tens of thousands of devices in a city), and supports reliable data transmission under large-scale device access and weak network conditions.

[0117] Figure 4 It is a structural block diagram of a 104 protocol data-adaptive cache queue optimization device according to an embodiment of the present invention.

[0118] like Figure 4 As shown, the adaptive cache queue optimization device based on 104 protocol data includes:

[0119] a data attribute determination module 410 for determining the data type, time sensitivity, data priority, data structure, data production method, and data usage method of the first data based on the specification 104;

[0120] a comprehensive priority determination module 420 for determining the comprehensive priority of the first data based on the data type, time sensitivity, data priority, data structure, data production method, and data usage method of the first data;

[0121] a queue merging module 430 configured to merge the plurality of first cache queues based on a data sending frequency of each of the plurality of first cache queues to obtain a merged queue;

[0122] an insertion order determination module 440, configured to determine an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data;

[0123] A data inserting module 450 is configured to insert the first data into the merge queue based on the insertion order of the first data, thereby obtaining the merge queue after the data is inserted;

[0124] a queue splitting module 460 for splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues;

[0125] A queue updating module 470 is configured to update each of the first cache queues based on each of the split queues to obtain each updated first cache queue;

[0126] The data sending module 480 is configured to send the data in each updated first cache queue based on the protocol 104 and the data sending frequency of each updated first cache queue.

[0127] In one embodiment, the queue merging module 430 includes:

[0128] a first queue-to-be-merged determining unit configured to determine, based on the data sending frequencies of each of the first cache queues in the plurality of first cache queues, at least one second cache queue in the plurality of first cache queues having a mapping relationship between the data sending frequency and the comprehensive priority of the first data;

[0129] a first merging order determining unit, configured to determine a merging order of each of the second cache queues based on a data sending frequency of each of the second cache queues;

[0130] The first merging unit is configured to merge the second cache queues based on a merging order of the second cache queues to obtain a merged queue.

[0131] In one embodiment, the queue merging module 430 includes:

[0132] a matching degree determining unit, configured to determine a matching degree between each of the plurality of first cache queues and the first data based on a data sending frequency of each of the first cache queues and a time sensitivity of the first data;

[0133] a second to-be-merged queue determining unit, configured to determine at least one third cache queue from the plurality of first cache queues based on a degree of matching between each of the first cache queues and the first data;

[0134] a second merging order determining unit, configured to determine a merging order of each of the third cache queues based on a data sending frequency of each of the third cache queues;

[0135] The first merging unit is configured to merge the third cache queues based on a merging order of the third cache queues to obtain a merged queue.

[0136] In one embodiment, the arrangement order determination module includes:

[0137] a percentage determining unit, configured to determine a ranking percentage of the first data based on a ratio between the comprehensive priority of the first data and a preset comprehensive priority upper limit;

[0138] The sequence determining unit is configured to determine an insertion sequence of the first data based on a product of a total amount of arranged data in the merge queue and a sorting percentage of the first data.

[0139] In one embodiment, it further includes:

[0140] a target queue length determining module, configured to determine a target queue length of each of the first cache queues based on a data insertion frequency of each of the first cache queues;

[0141] and a data cleaning module configured to clean up data in a fourth cache queue among the plurality of first cache queues when the queue length of the fourth cache queue is greater than the target queue length of the fourth cache queue, so that the queue length of the fourth cache queue after data cleaning matches the target queue length.

[0142] In one embodiment, the target queue length determination module includes:

[0143] an adjustment coefficient determining unit, configured to determine an adjustment coefficient based on a data insertion frequency of the first cache queue;

[0144] The length determining unit is configured to determine a target queue length of the first cache queue based on a product of a data insertion frequency of the first cache queue and the adjustment coefficient, and a basic queue length corresponding to the first cache queue.

[0145] In one embodiment, the data cleaning module includes:

[0146] a historical feedback data determining unit, configured to determine historical feedback data of the corresponding historical data based on the attribute information of each second data in each of the fourth cache queues;

[0147] a comprehensive scoring unit, configured to determine a comprehensive score for each second data item based on a load score of the operating system, a feedback score of the historical feedback data corresponding to each second data item, and a dimension score of each information item in the attribute information of each second data item;

[0148] A data cleaning unit is configured to clean up the second data in the fourth cache queue whose comprehensive scores do not meet a preset comprehensive scoring condition based on the comprehensive scores of the respective second data.

[0149] In one embodiment, the queue splitting module 460 includes:

[0150] a start and end data determining unit, configured to determine corresponding target start and end data in the merge queue after data insertion based on the start and end data of the first cache queue;

[0151] The queue screenshot unit is used to intercept the queue from the target starting position data to the target last position data in the merged queue after the data is inserted, so as to obtain the split queue.

[0152] For the description of specific functions and examples of each module and submodule of the system in the embodiment of the present invention, please refer to the relevant description of the corresponding steps in the above method embodiment, which will not be repeated here.

[0153] In the technical solution of the present invention, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0154] According to an embodiment of the present invention, the present invention further provides a system and a readable storage medium.

[0155] Figure 5 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0156] like Figure 5As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. Computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to bus 804.

[0157] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0158] The computing unit 801 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the method for adaptive cache queue optimization based on the 104 protocol data. For example, in some embodiments, the method for adaptive cache queue optimization based on the 104 protocol data can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the method for adaptive cache queue optimization based on the 104 protocol data described above can be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the adaptive cache queue optimization method based on the protocol data 104 in any other appropriate manner (eg, by means of firmware).

[0159] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system comprising at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0160] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0161] In the context of the present invention, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0162] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0163] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0164] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0165] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present invention can be achieved. This is not limited herein.

[0166] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for optimizing cache queues based on 104 protocol data self-adaptation, characterized in that: include: Determine, based on the 104 protocol, a data type, time sensitivity, data priority, data structure, and data production method of the first data; determining a comprehensive priority of the first data based on a data type, time sensitivity, data priority, data structure, and data production method of the first data; Merging the multiple first cache queues based on the data sending frequency of each of the first cache queues to obtain a merged queue; determining an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; Inserting the first data into the merge queue based on the insertion order of the first data to obtain the merge queue after the data is inserted; Splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues; Based on each of the split queues, updating each of the first cache queues to obtain each updated first cache queue; Based on the 104 protocol and the updated data sending frequency of each of the first cache queues, respectively sending the data in each of the updated first cache queues; determining a target queue length of each of the first cache queues based on a data insertion frequency of each of the first cache queues; When a queue length of a fourth cache queue among the plurality of first cache queues is greater than a target queue length of the fourth cache queue, data is cleaned up in the fourth cache queue so that the queue length of the fourth cache queue after data cleansing matches the target queue length. The step of clearing data from the fourth cache queue includes: Determining historical feedback data of the respective corresponding historical data based on the attribute information of each second data in each of the fourth cache queues; Determine a comprehensive score for each second data item based on the load score of the operating system, the feedback score of the historical feedback data corresponding to each second data item, and the dimension score of each information item in the attribute information of each second data item; Based on the comprehensive scores of the respective second data, data clearing is performed on the second data in the fourth cache queue whose comprehensive scores do not meet the preset comprehensive scoring conditions.

2. The method according to claim 1, characterized in that The step of merging the plurality of first cache queues based on the data sending frequency of each of the plurality of first cache queues to obtain a merged queue includes: Based on the data sending frequency of each of the first cache queues in the plurality of first cache queues, determining at least one second cache queue in the plurality of first cache queues having a mapping relationship between the data sending frequency and the comprehensive priority of the first data; determining a merging order of the second cache queues based on data sending frequencies of the second cache queues; Based on the merging order of each second cache queue, each second cache queue is queue-merged to obtain a merged queue.

3. The method according to claim 1, characterized in that The step of merging the plurality of first cache queues based on the data sending frequency of each of the plurality of first cache queues to obtain a merged queue includes: determining, based on a data sending frequency of each of the plurality of first cache queues and a time sensitivity of the first data, a matching degree between each of the first cache queues and the first data; Determining at least one third cache queue from the plurality of first cache queues based on a matching degree between each of the first cache queues and the first data; determining a merging order of the third cache queues based on a data sending frequency of the third cache queues; Based on the merging order of each of the third cache queues, each of the third cache queues is queue-merged to obtain a merged queue.

4. The method according to claim 1, wherein The determining the insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data includes: determining a ranking percentage of the first data based on a ratio between the comprehensive priority of the first data and a preset comprehensive priority upper limit; An insertion order of the first data is determined based on a product of a total amount of arranged data in the merge queue and a sorting percentage of the first data.

5. The method according to claim 1, wherein The determining, based on the data insertion frequency of each of the first cache queues, a target queue length of each of the first cache queues includes: determining an adjustment coefficient based on a data insertion frequency of the first cache queue; The target queue length of the first cache queue is determined based on the product of the data insertion frequency of the first cache queue and the adjustment coefficient, and a basic queue length corresponding to the first cache queue.

6. The method according to claim 1, characterized in that The merged queue after the data is inserted is split based on the start bit data and the end bit data of each of the first cache queues to obtain multiple split queues, including: Based on the start bit data and the end bit data of the first cache queue, determining the corresponding target start bit data and the target end bit data in the merge queue after the data is inserted; In the merged queue after the data is inserted, the queue from the target starting data to the target ending data is intercepted to obtain the split queue.

7. A data adaptive cache queue optimization device based on 104 protocol, characterized in that: include: a data attribute determination module, configured to determine the data type, time sensitivity, data priority, data structure, and data production method of the first data based on the 104 protocol; a comprehensive priority determination module, configured to determine the comprehensive priority of the first data based on the data type, time sensitivity, data priority, data structure, and data production method of the first data; a queue merging module, configured to merge the plurality of first cache queues based on a data sending frequency of each of the plurality of first cache queues to obtain a merged queue; an insertion order determination module, configured to determine an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; a data insertion module, configured to insert the first data into the merge queue based on an insertion order of the first data, to obtain the merge queue after the data is inserted; a queue splitting module, configured to split the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues; a queue updating module, configured to update each of the first cache queues based on each of the split queues to obtain each updated first cache queue; a data sending module, configured to send the data in each updated first cache queue based on the 104 protocol and the data sending frequency of each updated first cache queue; a target queue length determining module, configured to determine a target queue length of each of the first cache queues based on a data insertion frequency of each of the first cache queues; a data cleaning module, configured to, when a queue length of a fourth cache queue among the plurality of first cache queues is greater than a target queue length of the fourth cache queue, clean up data in the fourth cache queue so that the queue length of the fourth cache queue after data cleaning matches the target queue length; Wherein, the data cleaning module includes: a historical feedback data determining unit, configured to determine historical feedback data of the corresponding historical data based on the attribute information of each second data in each of the fourth cache queues; a comprehensive scoring unit, configured to determine a comprehensive score for each second data item based on a load score of the operating system, a feedback score of the historical feedback data corresponding to each second data item, and a dimension score of each information item in the attribute information of each second data item; A data cleaning unit is configured to clean up the second data in the fourth cache queue whose comprehensive scores do not meet a preset comprehensive scoring condition based on the comprehensive scores of the respective second data.

8. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions for being executed by the at least one processor, and the instructions are executed by the at least one processor so as to enable the at least one processor to perform the method according to any one of claims 1 to 6.

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