Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a substrate, a pixel circuit and a light-emitting unit, the pixel circuit and the light-emitting unit are located at one side of the substrate, the pixel circuit is provided with a first node and a second node, the first node is electrically connected with a first power line, and the second node is electrically connected with the light-emitting unit; the pixel circuit includes a first transistor coupled between a first node and a second node; the first transistor comprises a first electrode and a second electrode; the first electrode comprises a first part extending along a first direction, and the second electrode comprises a second part extending along a second direction; the first direction intersects with the second direction; the first part comprises a first sub-part and a second sub-part which are connected, and the orthographic projection of the second sub-part on the substrate is overlapped with the orthographic projection of the second part on the substrate; in the second direction, the width of the first sub-part is larger than that of the second sub-part. The driving delay problem of the first transistor can be improved, and the layout structure of the pixel circuit can be simplified.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In existing display panels, transistor devices with a large aspect ratio are usually set in the pixel circuit to meet the needs of high current driving light-emitting devices. However, the setting of these transistor devices will increase the difficulty of designing the pixel circuit layout, resulting in overlap between some electrodes of the transistors, which can easily cause the drive signal line connected to the transistor device to be overloaded, and then cause the drive signal to be delayed, affecting the display effect of the display panel. Therefore, a solution is urgently needed. Summary of the invention

[0003] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising a substrate, a pixel circuit and a light-emitting unit, wherein the pixel circuit and the light-emitting unit are located on one side of the substrate, the pixel circuit having a first node and a second node, the first node being electrically connected to a first power line, and the second node being electrically connected to the light-emitting unit; the pixel circuit comprising a first transistor, the first transistor being coupled between the first node and the second node; the first transistor comprising a first electrode and a second electrode; the first electrode comprising a first portion extending along a first direction, the second electrode comprising a second portion extending along a second direction; the first direction and the second direction intersect; the first portion comprising a first sub-portion and a second sub-portion connected, the orthographic projection of the second sub-portion on the substrate overlapping the orthographic projection of the second portion on the substrate; in the second direction, the width of the first sub-portion is greater than the width of the second sub-portion.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0006] In the embodiment of the present application, the width of the second sub-portion in the second direction is set to be smaller, so that the area of ​​the second sub-portion can be made smaller, which is beneficial to reducing the overlapping area between the second sub-portion and the second part in the direction perpendicular to the plane where the display panel is located, thereby helping to reduce the parasitic capacitance between the second sub-portion and the second part, and further helping to reduce the parasitic capacitance between the first electrode and the second electrode.

[0007] When driving the first transistor, the first electrode or the second electrode of the first transistor can receive the driving signal. Since the parasitic capacitance between the first electrode and the second electrode is reduced, the load of the driving signal can be reduced, which is beneficial to improving the driving delay problem of the first transistor and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0010] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0011] Figure 3 for Figure 2 A schematic diagram of a layout of a first transistor;

[0012] Figure 4 for Figure 2 A schematic diagram of another layout of the first transistor;

[0013] Figure 5 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0014] Figure 6 for Figure 5 A schematic diagram of a local layout of the pixel circuit shown;

[0015] Figure 7 A schematic diagram of a layout of a first transistor provided in an embodiment of the present application;

[0016] Figure 8 A schematic diagram of a local layout of a pixel circuit provided in an embodiment of the present application;

[0017] Fig. 9 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application;

[0018] Fig.10 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application;

[0019] Fig.11 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application;

[0020] Fig.12 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application;

[0021] Fig.13 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application;

[0022] Fig.14A A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application;

[0023] Fig. 14B for Fig.14A A cross-sectional schematic diagram of a first transistor;

[0024] Fig.15 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0025] Fig.16 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0026] Fig.17 A schematic diagram of a layout of a pixel circuit provided in an embodiment of the present application;

[0027] Fig.18 for Fig.17 A cross-sectional schematic diagram of a first capacitor;

[0028] Fig.19 An enlarged schematic diagram of a first capacitor provided in an embodiment of the present application;

[0029] Fig. 20A for Fig.17 A schematic diagram of a film layer of the first metal layer in the pixel circuit shown;

[0030] Fig. 20B for Fig.17 A schematic diagram of a film layer of an active layer in the pixel circuit shown;

[0031] Fig. 20C for Fig.17 A schematic diagram of a film layer of the second metal layer in the pixel circuit shown;

[0032] Fig.20D for Fig.17 A schematic diagram of a film layer of the third metal layer in the pixel circuit shown;

[0033] Fig.20E for Fig.17 A schematic diagram of a film layer of the fourth metal layer in the pixel circuit shown;

[0034] Fig.21 A comparative schematic diagram of a first transistor provided in an embodiment of the present application;

[0035] Fig. 22 A schematic diagram of a display device provided in an embodiment of the present application;

[0036] Fig.23 A schematic diagram of another display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0039] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application, Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 3 for Figure 2 A schematic diagram of a layout of the first transistor in FIG.

[0042] The present application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes a substrate 10, a pixel circuit 11 and a light-emitting unit 12. The pixel circuit 11 and the light-emitting unit 12 are located on one side of the substrate 10, and the pixel circuit 11 is used to drive the light-emitting unit 12 to emit light.

[0043] Exemplarily, the light emitting unit 12 is any one of a micro light emitting diode (Micro-LED), a sub-millimeter light emitting diode (Mini-LED), and an organic light emitting diode (OLED).

[0044] like Figure 2 As shown, the pixel circuit 11 has a first node N1 and a second node N2 , the first node N1 is electrically connected to the first power line PAM_VDD, and the second node N2 is electrically connected to the light emitting unit 12 .

[0045] Optionally, the second node N2 is electrically connected to the first electrode of the light emitting unit 12, and the second electrode of the light emitting unit 12 is electrically connected to the second power line PAM_VEE. Exemplarily, the first power line PAM_VDD transmits the power voltage PVDD, the second power line PAM_VEE transmits the power voltage PVEE, and the first electrode of the light emitting unit 12 is its anode.

[0046] The pixel circuit 11 includes a first transistor M1, and the first transistor M1 is coupled between the first node N1 and the second node N2. Figure 3 As shown, the first transistor M1 includes a first electrode 21 and a second electrode 22 . The first electrode 21 includes a first portion P1 extending along a first direction X, and the second electrode 22 includes a second portion P2 extending along a second direction Y. The first direction X intersects with the second direction Y.

[0047] Exemplarily, the first direction X is the row direction of the display panel 01 , and the second direction Y is the column direction of the display panel 01 .

[0048] The first portion P1 includes a first sub-portion P11 and a second sub-portion P12 that are connected, and an orthographic projection of the second sub-portion P12 on the substrate 10 overlaps with an orthographic projection of the second portion P2 on the substrate 10 .

[0049] In the second direction Y, the width of the first sub-portion P11 is greater than the width of the second sub-portion P12.

[0050] For example, Figure 3 As shown, in the second direction Y, the second sub-portion P12 is a continuous structure, the width of the first sub-portion P11 is S1, the width of the second sub-portion P12 is S2, S1>S2. Here, the second sub-portion P12 is a continuous structure, which means that the second sub-portion P12 does not include a hollow area in the second direction Y.

[0051] For example, Figure 4 As shown, Figure 4 for Figure 2 Another schematic layout diagram of the first transistor in the second direction Y, the second sub-portion P12 is a discontinuous structure. The second sub-portion P12 includes a first section P121 and a second section P122 arranged in the second direction Y, and a hollow area Q is included between the first section P121 and the second section P122, and the orthographic projection of the hollow area Q on the substrate 10 overlaps with the orthographic projection of the second portion P2 on the substrate 10. In the second direction Y, the width of the first sub-portion P11 is S1, the width of the first section P121 is S2, and the width of the second section P122 is S3, S1>S2+S3.

[0052] In the first direction X, the length of the hollow area Q may be greater than or equal to the length of the second portion P2.

[0053] After research, the inventors of the present application discovered that, in a direction perpendicular to the plane where the display panel 01 is located, when the first electrode and the second electrode of the first transistor M1 overlap, there is a parasitic capacitance between the first electrode and the second electrode, which may easily cause the load of the driving signal driving the first transistor M1 to increase, resulting in a problem of driving signal delay, thereby easily causing a delay in the opening or closing of the first transistor M1, affecting the display effect.

[0054] In view of this, in the embodiment of the present application, the width of the second sub-portion P12 in the second direction Y is set to be smaller, so that the area of ​​the second sub-portion P12 extending along the first direction X can be smaller, which is beneficial to reducing the overlapping area between the second sub-portion P12 and the second portion P2 in the direction perpendicular to the plane of the display panel 01, thereby helping to reduce the parasitic capacitance between the second sub-portion P12 and the second portion P2, and further helping to reduce the parasitic capacitance between the first electrode 21 and the second electrode 22.

[0055] When driving the first transistor M1, the first electrode 21 or the second electrode 22 of the first transistor M1 can receive the driving signal. Since the parasitic capacitance between the first electrode 21 and the second electrode 22 is reduced, the load of the driving signal can be reduced, which is beneficial to improving the response delay problem of the first transistor M1 and improving the display effect of the display panel 01.

[0056] Optional, such as Figure 3 and Figure 4 As shown, the first electrode 21 is a gate electrode, and the second electrode 22 is a source electrode or a drain electrode.

[0057] Since the width of the first sub-portion P11 in the second direction Y of the first electrode P1 is relatively large, the cross-sectional area of ​​the first sub-portion P11 can be increased, which is beneficial to reducing the resistance of the first sub-portion P11, thereby facilitating reducing the resistance of the first portion P1, and further facilitating reducing the resistance of the first electrode 21. Since the present application can also reduce the parasitic capacitance between the first electrode 21 and the second electrode 22, the present application can reduce the RC load on the first electrode 21.

[0058] The first electrode 21 is set as a gate. When the first transistor M1 is driven, the first electrode 21 receives a driving signal, which is beneficial to greatly reduce the RC load of the driving signal, thereby further improving the response delay problem of the first transistor M1.

[0059] For example, Figure 3 and Figure 4 As shown, the first transistor M1 further includes a channel GD. In the first electrode 21 , the orthographic projection of the first sub-portion P11 on the substrate 10 overlaps with the orthographic projection of the channel GD on the substrate 10 , and the orthographic projection of the second sub-portion P12 on the substrate 10 does not overlap with the orthographic projection of the channel GD on the substrate 10 .

[0060] Figure 5 A schematic diagram of another pixel circuit provided in an embodiment of the present application is shown. Figure 6 for Figure 5 A schematic diagram of a local layout of the pixel circuit shown.

[0061] In one embodiment of the present application, Figure 5 and Figure 6 As shown, the pixel circuit 11 includes a first light-emitting control transistor T1, a first driving transistor Td, and a second light-emitting control transistor T2. The first light-emitting control transistor T1 is coupled between the first node N1 and the first driving transistor Td, and the second light-emitting control transistor T2 is coupled between the first driving transistor Td and the second node N2. In this way, the light-emitting drive current generated by the pixel circuit 11 can be transmitted to the light-emitting unit 12 through the first light-emitting control transistor T1, the first driving transistor Td, and the second light-emitting control transistor T2 in sequence.

[0062] For example, Figure 5 and Figure 6 As shown, the source of the first light-emitting control transistor T1 is electrically connected to the first node N1 for receiving the first power supply voltage PVDD, the drain of the first light-emitting control transistor T1 is electrically connected to the source of the first driving transistor Td, the drain of the first driving transistor Td is electrically connected to the source of the second light-emitting control transistor T2, and the drain of the second light-emitting control transistor T2 is electrically connected to the second node N2. The first node N1 may be a position in the pixel circuit 11 where a hole is punched to connect the first power line DL1, and the second node N2 may be a position in the pixel circuit 11 where a hole is punched to connect the light-emitting unit 12.

[0063] At least one of the first light emission control transistor T1 , the first driving transistor Td and the second light emission control transistor T2 is the first transistor M1 .

[0064] That is to say, among the first light emitting control transistor T1, the first driving transistor Td and the second light emitting control transistor T2, the first electrode 21 and the second electrode 22 of at least one of them overlap in a direction perpendicular to the plane where the display panel 01 is located, and by setting the width of the second sub-portion P12 to be smaller, the parasitic capacitance between the first electrode 21 and the second electrode 22 is reduced.

[0065] Based on this setting method, it can be seen from the above analysis that it is beneficial to reduce the driving signal load of at least one of the first light-emitting control transistor T1, the first driving transistor Td and the second light-emitting control transistor T2, and improve the response delay problem of at least one of the first light-emitting control transistor T1, the first driving transistor Td and the second light-emitting control transistor T2.

[0066] Since the light-emitting driving current transmitted to the light-emitting unit 12 passes through the first light-emitting control transistor T1, the first driving transistor Td, and the second light-emitting control transistor T2, improving the response delay problem of at least one of the first light-emitting control transistor T1, the first driving transistor Td, and the second light-emitting control transistor T2 is beneficial to improving the timeliness of the light-emitting driving current being transmitted to the light-emitting unit 12, thereby facilitating improving the response speed of the light-emitting unit 12 and improving the display effect of the display panel.

[0067] Optional, such as Figure 5 and Figure 6 As shown, the first light-emitting control transistor T1 , the first driving transistor Td and the second light-emitting control transistor T2 are all first transistors M1 , so as to improve the response speed of the light-emitting unit 12 to a large extent.

[0068] For example, Figure 6 As shown, the first light emitting control transistor T1 and the second light emitting control transistor T2 are located on the same side of the first driving transistor Td, the first light emitting control transistor T1 and the second light emitting control transistor T2 are arranged along the first direction X, and the first light emitting control transistor T1 and the first driving transistor Td are arranged along the second direction Y.

[0069] Based on this arrangement, the connection lines between the first driving transistor Td and the first light-emitting control transistor T1, and the connection lines between the first driving transistor Td and the second light-emitting control transistor T2 can be arranged along the second direction Y, which is beneficial for making the connection lines relatively straight, which is beneficial for reducing the design difficulty of the pixel circuit 11 layout, and is beneficial for reducing the length of the connection lines and reducing impedance.

[0070] Furthermore, the first electrode 21 of the first light emission control transistor T1 is electrically connected to the first electrode 21 of the second light emission control transistor T2, that is, the gate of the first light emission control transistor T1 is electrically connected to the gate of the second light emission control transistor T2. In this way, the first light emission control transistor T1 and the second light emission control transistor T2 can have the same switching state, which is conducive to simplifying the control method of the first light emission control transistor T1 and the second light emission control transistor T2.

[0071] Furthermore, since the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are arranged along the first direction X, the connection line between the gate of the first light-emitting control transistor T1 and the gate of the second light-emitting control transistor T2 can be integrally formed with the gates of the two transistors, without the need to set a cross-line, which is also conducive to reducing the process difficulty of electrically connecting the gate of the first light-emitting control transistor T1 and the gate of the second light-emitting control transistor T2.

[0072] For example, Figure 6As shown, in the second direction Y, the second subsection P12 of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 is a continuous structure, and the second subsection P12 of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 forms a "neck" structure relative to the first subsection P11. In the second direction Y, the second subsection P12 of the first driving transistor Td is a discontinuous structure, and the second subsection P12 of the first driving transistor Td includes a first section P121 and a second section P122, and a hollow area Q is included between the first section P121 and the second section P122.

[0073] Figure 7 A schematic diagram of a layout of a first transistor provided in an embodiment of the present application.

[0074] In one embodiment of the present application, Figure 7 As shown, the first transistor M1 includes X sub-transistors M11, and the first electrodes, second electrodes, and third electrodes of the X sub-transistors M11 are connected. The first electrode can be the gate of the sub-transistor M11, the second electrode can be the source of the sub-transistor M11, and the third electrode can be the drain of the sub-transistor M11. Of course, the gate, source, and drain of the sub-transistor M11 can also be referred to as the gate, source, and drain of the first transistor M1, respectively.

[0075] Wherein, X≥2 and is an integer. That is, the first transistor M1 includes at least two sub-transistors M11, and the gates, sources, and drains of each sub-transistor M11 are connected to each other. Based on this connection mode, it can be known that in the first transistor M1, X sub-transistors M11 are arranged in parallel. That is, the first transistor M1 includes X sub-transistors M11 connected in parallel.

[0076] like Figure 7 As shown, in the first transistor M1, each sub-transistor M11 can be arranged along the first direction X. Of course, each sub-transistor M11 can also be arranged along the second direction Y. In addition, each sub-transistor M11 can also be arranged in an array along the first direction X and the second direction Y. The present application can flexibly set the arrangement of the sub-transistors M11 according to the layout space.

[0077] In the embodiment of the present application, the first transistor M1 is provided to include a plurality of sub-transistors M11, which is conducive to making the channel width-to-length ratio of the first transistor M1 (the sum of the channel width-to-length ratios of each sub-transistor) larger. Since the larger the channel width-to-length ratio of the transistor, the larger its saturation current, which is conducive to making the first transistor M1 have a larger driving capability. When the first transistor M1 is used as a transistor for the light-emitting driving current to flow in the pixel circuit 11, it is conducive to increasing the large current driving capability of the pixel circuit 11.

[0078] On this basis, since the capacitance of the first transistor M1 with a large channel width-to-length ratio is relatively large, reducing the parasitic capacitance between the first electrode 21 and the second electrode 22 of the first transistor M1 can more significantly improve the driving signal delay of the first transistor M1 and increase the response speed of the first transistor M1.

[0079] From the above analysis, it can be known that since at least one of the first light emission control transistor T1, the first driving transistor Td and the second light emission control transistor T2 can be the first transistor M1, at least one of the first light emission control transistor T1, the first driving transistor Td and the second light emission control transistor T2 can include a plurality of sub-transistors M11.

[0080] Optional, such as Figure 6 As shown, the first light-emitting control transistor T1 is a first transistor M1, and the first light-emitting control transistor T1 includes X1 first sub-transistors T11 connected in parallel, and the gates, sources, and drains of the X1 first sub-transistors T11 are connected. Among them, the X1 first sub-transistors T11 are arranged along the second direction Y, and X1 ≥ 2 and is an integer. It can be understood that the first sub-transistor T11 is a sub-transistor in the first light-emitting control transistor T1.

[0081] For example, in Figure 6 In the embodiment, the first light emission control transistor T1 may include three first sub-transistors T11 arranged along the second direction Y.

[0082] The second light-emitting control transistor T2 is the first transistor M1, and the second light-emitting control transistor T2 includes X2 second sub-transistors T21 connected in parallel, and the gates, sources, and drains of the X2 second sub-transistors T21 are connected. Among them, the X2 second sub-transistors T21 are arranged in an array along the first direction X and the second direction Y, and X2 ≥ 2 and is an integer. It can be understood that the second sub-transistor T21 is a sub-transistor in the second light-emitting control transistor T2.

[0083] Exemplarily, X1<X2.

[0084] For example, in Figure 6 In the embodiment, the second light emitting control transistor T2 includes six second sub-transistors T21, and the six second sub-transistors T21 are arranged in three rows and two columns. In the first direction X, two second sub-transistors T21 are arranged in sequence; in the second direction Y, three second sub-transistors T21 are arranged in sequence.

[0085] Since the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are arranged along the first direction X, the first sub-transistor T11 in the first light-emitting control transistor T1 is arranged along the second direction Y, and the second sub-transistor T21 in the second light-emitting control transistor T2 is arranged in an array along the first direction X and the second direction Y. On the one hand, it is beneficial to reasonably allocate the occupied space of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 in the first direction X and the second direction Y, and avoid the first light-emitting control transistor T1 and the second light-emitting control transistor T2 occupying too much space in the first direction X. On the other hand, it is beneficial to align the gate of the first sub-transistor T11 with the gate of the second sub-transistor T21. When the gate of the first light-emitting control transistor T1 and the gate of the second light-emitting control transistor T2 are electrically connected, it is beneficial to make the connection line between the two relatively straight, thereby reducing the difficulty of layout design of the pixel circuit 11.

[0086] Exemplarily, the channel width-to-length ratio of the first sub-transistor T11 is equal to the channel width-to-length ratio of the second sub-transistor T21. Based on this configuration, on the one hand, the structural complexity of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be reduced, which is conducive to reducing the difficulty of manufacturing the pixel circuit 11. On the other hand, it is conducive to better realizing the alignment of the first sub-transistor T11 and the second sub-transistor T21 in the first direction X.

[0087] The first driving transistor Td is a first transistor M1, and the first driving transistor Td includes X3 third sub-transistors Td1 connected in parallel, and the gates, sources, and drains of the X3 third sub-transistors Td1 are connected. The X3 third sub-transistors Td1 are arranged along the first direction X, and X3 ≥ 2 and is an integer. It can be understood that the third sub-transistor Td1 is a sub-transistor in the first driving transistor Td.

[0088] Based on this setting, the first driving transistor Td can have a larger channel width-to-length ratio. Since the larger the channel width-to-length ratio of the transistor, the larger its saturation current, it is beneficial for the first driving transistor Td to have a larger driving capability, which in turn is beneficial for increasing the high current driving capability of the pixel circuit 11.

[0089] Exemplarily, the channel width-to-length ratio of the third sub-transistor Td1 is smaller than the channel width-to-length ratio of the first sub-transistor T11. Since the channel width-to-length ratio of the second sub-transistor T21 can be equal to the channel width-to-length ratio of the first sub-transistor T11, the channel width-to-length ratio of the third sub-transistor Td1 can also be smaller than the channel width-to-length ratio of the second sub-transistor T21. Exemplarily, in Figure 6 In the embodiment, the first driving transistor Td includes four third sub-transistors Td1 arranged along the first direction X.

[0090] Since the first driving transistor Td and the first light-emitting control transistor T1 are arranged along the second direction Y, and the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are arranged along the first direction X, the third sub-transistor Td1 in the first driving transistor Td is arranged along the first direction X, which is beneficial to reasonably utilize the space of the pixel circuit 11 in the first direction X, improve the compactness of the first driving transistor Td and the first light-emitting control transistor T1 and the second light-emitting control transistor T2, and avoid a large area of ​​blank space in the layout of the pixel circuit 11.

[0091] Optional, such as Figure 6 As shown, the third electrode 23 (drain) connected to the second sub-transistor T21 is farther away from the first sub-transistor T11 than the second electrode 22 (source) connected thereto. Since the drain of the second light-emitting control transistor T2 is electrically connected to the second node N2, based on this arrangement, the second node N2 can be arranged on a side of the second light-emitting control transistor T2 away from the first light-emitting control transistor T1, which is beneficial to reducing the number of wirings between the first light-emitting control transistor T1 and the second light-emitting control transistor T2, and reducing the difficulty of layout design of the pixel circuit 01.

[0092] Optional, such as Figure 6 As shown, the third electrode 23 (drain) connected to the first sub-transistor T11 is farther away from the second sub-transistor T21 than the second electrode 22 (source) connected thereto.

[0093] Figure 8 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application.

[0094] In one embodiment of the present application, Figure 8 As shown, the first light emitting control transistor T1 and the second light emitting control transistor T2 can both be the first transistor M1, and the first electrode 21 of the first transistor M1 is electrically connected to the first light emitting control signal line EM1, that is, the gates of the first light emitting control transistor T1 and the second light emitting control transistor T2 are both electrically connected to the first light emitting control signal line EM1.

[0095] Exemplarily, the first light emission control signal line EM1 is in the same layer as the gates of the first light emission control transistor T1 and the second light emission control transistor T2 and can be manufactured using the same process and the same materials.

[0096] The first light emission control signal line EM1 includes a third portion P3 extending along the first direction X, and the third portion P3 is located at a side of the first light emission control transistor T1 away from the first driving transistor Td.

[0097] In the second direction Y, the width of the third portion P3 is greater than that of the first portion P1. Of course, in the second direction Y, the width D of the third portion P3 is greater than both the width S2 of the second sub-portion P12 in the first portion P1 and the width S1 of the first sub-portion P11 in the first portion P1.

[0098] It is understandable that the first light control signal line EM1 can be used to transmit a driving signal to the first light control transistor T1 and the second light control transistor T2, and the load on the first light control signal line EM1 will also affect the response speed of the first light control transistor T1 and the second light control transistor T2.

[0099] Moreover, in the display panel 01 , a plurality of pixel circuits 11 extending along the first direction X may be connected to the same first light emission control signal line EM1 , and the length of the first light emission control signal line EM1 in the first direction X is relatively large.

[0100] Therefore, in the embodiment of the present application, the third portion P3 is set to have a larger width in the second direction Y, which is beneficial to increase the cross-sectional area of ​​the first light-emitting control signal line EM1 and reduce the resistance of the first light-emitting control signal line EM1, thereby further reducing the load of the driving signal driving the first transistor and improving the response speed of the first transistor. In particular, in the pixel circuit 11 connected to the end of the first light-emitting control signal line EM1 (the end away from the receiving signal), by reducing the resistance of the first light-emitting control signal line EM1, the response speed of the first transistor can be significantly improved.

[0101] Optional, such as Figure 8 As shown, in the second direction Y, the width of the third portion P3 is D, 5.6 μm<D≤15 μm. In this way, while reducing the resistance of the first light-emitting control signal line EM1, it is helpful to avoid excessively increasing the occupied space of the pixel circuit 11 in the second direction Y, which is helpful to ensure that the number of pixel circuits arranged along the second direction Y in the display panel 01 is large, thereby ensuring that the display panel 01 has a high pixel density.

[0102] In one embodiment of the present application, please continue to refer to Figure 8 The display panel 01 includes a first metal trace ZX1. The first metal trace ZX1 may be in the same layer as the second electrode 22 of the first transistor M1. The first metal trace ZX1 includes a fourth portion P4 extending along the second direction Y.

[0103] The third portion P3 in the first light emission control signal line EM1 includes a third sub-portion P31 and a fourth sub-portion P32 that are connected, and an orthographic projection of the fourth sub-portion P32 on the substrate 10 overlaps with an orthographic projection of the fourth portion P4 on the substrate 10 .

[0104] The fourth sub-portion P32 includes a first connection portion P321 connected to the third sub-portion P31, and the width of the first connection portion P321 in the second direction Y is d1. The fourth sub-portion P32 includes a second connection portion P322 connected to the third sub-portion P31, and the width of the second connection portion P322 in the second direction Y is d2.

[0105] The width of the third portion P3 in the second direction Y is D, and d1+d2<D. That is, in the second direction Y, the width of the third portion P3 is greater than the sum of the widths of the first connection portion P321 and the second connection portion P322.

[0106] In the embodiment of the present application, the width of the fourth sub-portion P32 in the second direction Y is set to be smaller, so that the area of ​​the fourth sub-portion P32 can be smaller, which is beneficial to reducing the overlapping area of ​​the fourth sub-portion P32 and the fourth portion P4 in the direction perpendicular to the plane where the display panel 01 is located, thereby facilitating the reduction of the parasitic capacitance between the fourth sub-portion P32 and the fourth portion P4, and further facilitating the further reduction of the load on the first light-emitting control signal line EM1, and improving the response speed of the first transistor M1. For example, Figure 8 As shown, in the second direction Y, the fourth sub-section P32 is a continuous structure, the first connecting portion P321 is connected to the second connecting portion P322, and the fourth sub-section P32 is designed to be "shrinking" relative to the third sub-section P31. The sum of the widths of the first connecting portion P321 and the second connecting portion P322 in the second direction Y is the width of the fourth sub-section P32 in the second direction Y.

[0107] For example, Fig. 9 As shown, Fig. 9 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application, wherein the fourth sub-portion P32 may be a non-wired structure in the second direction Y. The first connection portion P321 and the second connection portion P322 are arranged along the second direction Y, and a first hollow portion QB1 is provided between the first connection portion P321 and the second connection portion P322. The orthographic projection of the first hollow portion QB1 on the substrate 10 overlaps with the orthographic projection of the fourth portion P4 on the substrate 10. The sum of the widths of the first connection portion P321 and the second connection portion P322 in the second direction Y is the width of the fourth sub-portion P32 in the second direction Y.

[0108] Optional, such as Fig. 9 As shown, along the first direction X, the length L1 of the first hollow portion QB1 is greater than or equal to the length L2 of the fourth portion P4. In this way, the first connection portion P321 and the second connection portion P322 can be prevented from connecting in the second direction Y, which is beneficial to greatly reduce the area of ​​the fourth sub-portion P32.

[0109] For example, Figure 8 and Fig. 9As shown, the display panel 01 includes a first data signal line PAM_Data, the first data signal line PAM_Data is used to transmit a first data voltage to the pixel circuit 11, and the first data signal line PAM_Data can be a first metal wiring ZX1.

[0110] For example, Figure 8 and Fig. 9 As shown, taking the second node N2 as the position of the hole in the pixel circuit 11 for connecting the light-emitting unit 12 as an example, a driving line An is provided between the third electrode 23 (drain) of the second light-emitting control transistor T2 and the second node N2, and the driving line An and the third electrode 23 of the second light-emitting control transistor T2 can be integrally formed. The driving line An can also be the first metal line ZX1.

[0111] In the embodiment of the present application, the display panel 01 may include multiple first metal traces ZX1, and the third portion P3 of the first light emitting control signal line EM1 may also include multiple fourth sub-portions P32. The multiple fourth sub-portions P32 may adopt the same design or different designs.

[0112] For example, Figure 8 As shown, the first data signal line PAM_Data and the driving line An are both first metal lines ZX1 , and in different fourth sub-portions P32 , the first connection portion P321 and the second connection portion P322 are both connected in the second direction Y.

[0113] For example, Fig. 9 As shown, the first data signal line PAM_Data and the driving line An are both first metal lines ZX1, and in different fourth sub-parts P32, the first connection part P321 and the second connection part P322 are both structures with a first hollow part QB1 disposed therebetween.

[0114] For example, Fig.10 As shown, Fig.10 A partial layout diagram of another pixel circuit provided in an embodiment of the present application, wherein the first data signal line PAM_Data and the driving line An are both first metal lines ZX1, and in a portion of the fourth sub-portion P32, the first connection portion P321 is connected to the second connection portion P322 in the second direction Y, and in a portion of the fourth sub-portion P32, a first hollow portion QB1 is included between the first connection portion P321 and the second connection portion P322.

[0115] For example Fig.10As shown, in the fourth sub-portion P32 overlapping with the first data signal line PAM_Data, the first connection portion P321 is connected to the second connection portion P322 in the second direction Y, and in the fourth sub-portion P32 overlapping with the driving line An, a first hollow portion QB1 is included between the first connection portion P321 and the second connection portion P322.

[0116] It should be noted that when the third part P3 includes a third sub-part P31 and a fourth sub-part P32 with different widths, in the above embodiment describing the width of the third part P3, the width D of the third part P3 in the second direction Y is the width D of the third sub-part P31 in the second direction Y in this embodiment.

[0117] Fig.11 A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application.

[0118] In one embodiment of the present application, Fig.11 As shown, the first metal trace ZX1 includes a fourth portion P4 extending along the second direction Y, the fourth portion P4 includes a fifth sub-portion P41 and a sixth sub-portion P42 connected to each other, and the orthographic projection of the sixth sub-portion P42 on the substrate 10 overlaps with the orthographic projection of the third portion P3 on the substrate 10 .

[0119] The sixth sub-section P42 includes a third connection portion P421 and a fourth connection portion P422 connected to the fifth sub-section P41. The width of the third connection portion P421 in the first direction X is w1, and the width of the fourth connection portion P422 in the first direction X is w2. The sum of the widths of the third connection portion P421 and the fourth connection portion P422 in the first direction X can be the width of the sixth sub-section P42 in the first direction X.

[0120] The width of the fifth sub-portion P41 in the first direction X is W, W>w1+w2. W may be the length L2 of the fourth portion P4 in the first direction X in the above embodiment.

[0121] Optional, such as Fig.11 As shown, the sixth sub-portion P42 is a continuous structure in the first direction X, the third connecting portion P421 is connected to the fourth connecting portion P422 in the first direction X, and the sixth sub-portion P42 is designed to be "neck-shrinking" relative to the fifth sub-portion P41.

[0122] Optional, such as Fig.12 As shown, Fig.12A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application, wherein the sixth sub-portion P42 is a non-continuous structure in the first direction X, the third connection portion P421 and the fourth connection portion P422 are arranged along the first direction X, a second hollow portion QB2 is provided between the third connection portion P421 and the fourth connection portion P422, and the orthographic projection of the second hollow portion QB2 on the substrate 10 overlaps with the orthographic projection of the third portion P3 on the substrate 10.

[0123] For example, Fig.12 As shown, in the second direction Y, the length of the second hollow portion QB2 is greater than the length of the third portion P3. In this way, the third connection portion P421 and the fourth connection portion P422 can be prevented from being connected in the first direction X, which is conducive to reducing the area of ​​the sixth sub-portion P42 to a large extent. Here, the length of the third portion P3 in the second direction Y may refer to the length of the portion of the third portion P3 that overlaps with the sixth sub-portion P42.

[0124] In the embodiment of the present application, the sixth sub-portion P42 is set to have a smaller width in the first direction X, which is beneficial to reducing the overlapping area between the sixth sub-portion P42 and the third portion P3 in a direction perpendicular to the plane of the display panel 01, thereby facilitating the reduction of the parasitic capacitance between the fourth portion P4 and the third portion P3 in the first light-emitting control signal line EM1, and further facilitating the further reduction of the load on the first light-emitting control signal line EM1, thereby improving the response speed of the first transistor M1.

[0125] Further, such as Fig.13 As shown, Fig.13 A partial layout schematic diagram of another pixel circuit provided in an embodiment of the present application, in a direction perpendicular to the plane where the display panel 01 is located, the fourth sub-portion P32 of the third portion P3 overlaps with the sixth sub-portion P42 of the fourth portion P4, and in the overlapping fourth sub-portion P32 and sixth sub-portion P42, the width of the fourth sub-portion P32 in the second direction Y and the width of the sixth sub-portion P42 in the first direction X can be reduced, so as to further reduce the parasitic capacitance between the fourth sub-portion P32 and the sixth sub-portion P42.

[0126] In addition, in the fourth sub-portion P32 and the sixth sub-portion P42 that overlap each other, the width of only one of them may be reduced to achieve the purpose of reducing the parasitic capacitance between the two.

[0127] For example, Fig.13As shown, the first data signal line PAM_Data and the driving wiring An are both the first metal wiring ZX1. At the overlapping position of the first data signal line PAM_Data and the third part P3 in the first light-emitting control signal line EM1, the width of the fourth sub-part P32 in the third part P3 in the second direction Y is reduced, and the width of the sixth sub-part P42 in the first data signal line PAM_Data in the first direction X is reduced.

[0128] At the overlapping position of the driving line An and the third portion P3 of the first light-emitting control signal line EM1, only the width of the fourth sub-portion P32 of the third portion P3 in the second direction Y can be reduced. In this way, while reducing the load on the first light-emitting control signal line EM1, the driving line An can be ensured to be wider, which is beneficial to avoid overheating of the driving line An when a large light-emitting driving current flows through the driving line An.

[0129] Please continue to refer to Figure 8-Figure 13 In one embodiment of the present application, the first light emission control transistor T1 and the second light emission control transistor T2 are both first transistors M1, and the first electrode 21 of the first light emission control transistor T1 is electrically connected to the first electrode 21 of the second light emission control transistor T2. That is, the gate of the first light emission control transistor T1 is electrically connected to the gate of the second light emission control transistor T2, and the first light emission control transistor T1 and the second light emission control transistor T2 can maintain the same switching state.

[0130] From the above analysis, it can be seen that the light-emitting driving current generated by the pixel circuit 11 will flow through the first light-emitting control transistor T1 and the second light-emitting control transistor T2, so that the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are both the first transistor M1, which can reduce the load of the driving signal required by the first light-emitting control transistor T1 and the second light-emitting control transistor T2, which is beneficial to improve the response speed of the first light-emitting control transistor T1 and the second light-emitting control transistor T2, and further improve the response speed of the light-emitting unit 12.

[0131] In addition, the first electrode 21 of the first light emission control transistor T1 is electrically connected to the first electrode 21 of the second light emission control transistor T2. The first light emission control transistor T1 and the second light emission control transistor T2 can receive the same driving signal, which is beneficial to reducing the number of driving signal lines required to drive the first light emission control transistor T1 and the second light emission control transistor T2, thereby reducing the complexity of the pixel circuit 11 layout and simplifying the design of the pixel circuit 11 layout.

[0132] Optional, such as Figure 8-Figure 13As shown, the first light emission control transistor T1 and the second light emission control transistor T2 are arranged along the first direction X, and the first electrode 21 of the first light emission control transistor T1 is electrically connected to the first light emission control signal line EN1. Of course, the first electrode 21 of the second light emission control transistor T2 is also electrically connected to the first light emission control signal line EM1. The first light emission control signal line EM1 is used to transmit a driving signal to the first light emission control transistor T1 and the second light emission control transistor T2.

[0133] The first light emission control signal line EM1 includes a third portion P3 extending along the first direction X, and the third portion P3 is located on a side of the first light emission control transistor T1 or the second light emission control transistor T2 away from the first driving transistor Td. That is, the third portion P3, the first light emission control transistor T1, and the first driving transistor Td can be arranged in sequence along the second direction Y, or the third portion P3, the second light emission control transistor T2, and the first driving transistor Td can be arranged in sequence along the second direction Y.

[0134] Since the first electrode 21 of the first light emitting control transistor T1 and the first electrode 21 of the second light emitting control transistor T2 may both include a first portion P1 extending along the first direction X, arranging the first light emitting control transistor T1 and the second light emitting control transistor T2 along the first direction X is beneficial for aligning the first portion P1 of the first light emitting control transistor T1 with the first portion P1 of the second light emitting control transistor T2, thereby facilitating electrical connection between the first portion P1 of the first light emitting control transistor T1 and the first portion P1 of the second light emitting control transistor T2, and further facilitating electrical connection between the first electrode 21 of the first light emitting control transistor T1 and the first electrode 21 of the second light emitting control transistor T2.

[0135] First driving transistor From the above analysis, it can be known that the first driving transistor Td is electrically connected to the first light-emitting control transistor T1 and the second light-emitting control transistor T2, and the third part P3 is also electrically connected to the first light-emitting control transistor T1 and the second light-emitting control transistor T2. The first driving transistor Td and the third part P3 are located on opposite sides of the first light-emitting control transistor T1 or on opposite sides of the second light-emitting control transistor T2, which is beneficial to reduce the mutual interference between the electrical connection between the two and the first light-emitting control transistor T1 and the second light-emitting control transistor T2.

[0136] Fig.14A A schematic diagram of a partial layout of another pixel circuit provided in an embodiment of the present application.

[0137] In one embodiment of the present application, as shown in FIG. 14 , the first electrode 21 of the first transistor M1 includes a plurality of first portions P1 arranged along the second direction Y. As shown in FIG.

[0138] The plurality of first portions P1 include an edge first portion P1A, and the edge first portion P1A is adjacent to the via hole Z. That is, the edge first portion P1A is located on a side of the first electrode 21 close to the via hole Z.

[0139] For example, Fig.14A As shown, the via Z includes a via Z1 between the first node N1 and the first power line PAM_VDD (not shown in the figure), and the via Z1 is located on the side of the first transistor M1 close to the first driving transistor Td. In addition, the via Z also includes a via Z2 located on the side of the first transistor M1 away from the first driving transistor Td, and the via Z2 includes a via Z21 and a via Z22. The first portion P1 adjacent to the via Z1 is the edge first portion P1A, and the first portion P1 adjacent to the via Z2 can also be the edge first portion P1A.

[0140] Combination Fig. 14B As shown, Fig. 14B for Fig.14A A cross-sectional schematic diagram of the first transistor in the embodiment of the present invention, the first electrode 21 includes a first sub-electrode 211 and a second sub-electrode 212, the first sub-electrode 211 is located on the side of the channel GD away from the substrate 10, the second sub-electrode 212 is located on the side of the channel GD close to the substrate 10, and the first sub-electrode 211 and the second sub-electrode 212 are electrically connected. That is, the first transistor M1 can be a top-bottom dual-gate structure, and its top gate and bottom gate receive the same signal. The via Z2 is a via hole used to realize the electrical connection between the first sub-electrode 211 and the second sub-electrode 212.

[0141] For the convenience of routing, for example, Fig.14A As shown, the first sub-electrode 211 is electrically connected to the connection line LJ1 through the via Z21, and the connection line LJ1 is electrically connected to the second sub-electrode 212 through the via Z22, thereby realizing the electrical connection between the first sub-electrode 211 and the second sub-electrode 212. The connection line LJ1 can be in the same layer as the second electrode 22 of the first transistor M1.

[0142] In the first edge portion P1A, the first sub-portion P11 includes a first side B1 and a second side B2 that are opposite to each other along the second direction Y, and the second side B2 is located on a side of the first side B1 close to the via Z. The second sub-portion P12 includes a third side B3 and a fourth side B4 that are opposite to each other along the second direction Y, and the fourth side B4 is located on a side of the third side B3 close to the via Z. It should be noted that the via Z here refers to a via adjacent to the first edge portion P1A.

[0143] Exemplarily, the second sub-portion P12 is a continuous structure in the second direction Y. That is, the second sub-portion P12 is designed to be “neck-shrink” relative to the first sub-portion P11.

[0144] In the second direction Y, the distance H1 between the fourth side B4 and the via Z is greater than the distance H2 between the second side B2 and the via Z. That is, in the first edge portion P1A, the second sub-portion P12 is retracted toward the side away from the via Z relative to the first sub-portion P11.

[0145] It can be understood that, in the second direction Y, the plurality of first portions P1 may include two edge first portions P1A.

[0146] In the embodiment of the present application, the second sub-portion P12 in the first edge portion P1A is set to be retracted, so that the via Z at the first edge portion P1A can be avoided, which is beneficial to reducing the mutual interference between the first edge portion P1A and the via Z.

[0147] For example, Fig.14A As shown, the first transistor M1 includes a first light-emitting control transistor T1 and a second light-emitting control transistor T2, so that the second sub-portion P12 in the first edge portion P1A is retracted to avoid the via Z1 and the via Z2, and reduce the overlap of the second sub-portion P12 in the first edge portion P1A with the via Z1 or the via Z2 at the different layers of material, which is beneficial to further reduce the load on the first portion P1 in the first transistor M1.

[0148] Optional, such as Fig.14A As shown, in the same first edge portion P1A, the first side B1 of the first sub-portion P11 and the third side B3 of the second sub-portion P12 are located in the same plane. Based on this arrangement, in the first edge portion P1A, when the width of the second sub-portion P12 is constant, it is beneficial to increase the degree of retraction of the second sub-portion P12, so as to better avoid the via Z at the first edge portion P1A.

[0149] Fig.15 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0150] In one embodiment of the present application, Fig.15 As shown, the pixel circuit 11 includes a pulse width adjustment module 111 and an amplitude adjustment module 112 which are electrically connected, and the amplitude adjustment module 112 includes a first transistor M1.

[0151] That is to say, the first light emission control transistor T1 , the first driving transistor Td, and the second light emission control transistor T2 in the aforementioned embodiment may all be located in the amplitude adjustment module 112 of the pixel circuit 11 . Fig.15 It is only illustrated that the first light emission control transistor T1 and the second light emission control transistor T2 are the first transistor M1 .

[0152] The amplitude adjustment module 112 is used to provide a light-emitting driving current to the light-emitting unit 12 , and to control the light-emitting efficiency of the light-emitting unit 12 by adjusting the amplitude of the light-emitting driving current.

[0153] Optionally, the light-emitting driving current may be a constant driving current, so as to drive the light-emitting unit 12 with a better light-emitting driving current to ensure that the light-emitting unit 12 works in an optimal state, which is conducive to achieving higher light-emitting efficiency and better display effect.

[0154] The pulse width regulation module 111 is used to control the duration of the amplitude regulation module 112 providing the light-emitting driving current to the light-emitting unit 12, thereby controlling the light-emitting duration of the light-emitting unit 12. It can be understood that by controlling the light-emitting duration of the light-emitting unit 12 (i.e., adjusting the light-emitting duty cycle of the light-emitting unit 12), the brightness of the light emitted by the light-emitting unit 12 can be controlled.

[0155] Since the amplitude adjustment module 112 is used to provide the light-emitting unit 12 with a light-emitting driving current, the speed at which the amplitude adjustment module 112 generates the light-emitting driving current or cuts off the light-emitting driving current will affect the response speed of the light-emitting unit 12. In the embodiment of the present application, the first transistor M1 is located in the amplitude adjustment module 112. As can be seen from the above analysis, it is beneficial to reduce the load of the driving signal of the transistor in the amplitude adjustment module 112, improve the response speed of the transistor in the amplitude adjustment module 112, and further improve the response speed of the light-emitting unit 12.

[0156] For example, Fig.16 As shown, Fig.16 The schematic diagram of a pixel circuit provided in an embodiment of the present application, the amplitude adjustment module 112 may include a first light-emitting control transistor T1, a first driving transistor Td, a second light-emitting control transistor T2, and an amplitude data writing transistor T3, an amplitude compensation transistor T4, an amplitude gate reset transistor T5, an amplitude reset transistor T6 and a first capacitor C1. Among them, the source of the first light-emitting control transistor T1 is electrically connected to the first power line PAM_VDD, and the drain is electrically connected to the source of the first driving transistor Td, the source of the second light-emitting control transistor T2 is electrically connected to the drain of the first driving transistor Td, and the drain is electrically connected to the first electrode of the light-emitting unit 12. The source of the amplitude data writing transistor T3 is electrically connected to the first data signal line PAM_Data, and the drain is electrically connected to the source of the first driving transistor Td. The source of the amplitude compensation transistor T4 is electrically connected to the drain of the first driving transistor Td, and the drain is electrically connected to the gate of the first driving transistor Td. The source of the amplitude gate reset transistor T5 is electrically connected to the first reset signal line PAM_REF, and the drain is electrically connected to the gate of the first driving transistor Td. The source of the amplitude reset transistor T6 is electrically connected to the second reset signal line PAM_INIT, and the drain is electrically connected to the first electrode of the light emitting unit 12.

[0157] The gate of the first light-emitting control transistor T1 and the gate of the second light-emitting control transistor T2 receive the first amplitude light-emitting control signal provided by the first light-emitting control signal line EM1, the gate of the amplitude gate reset transistor T5 receives the first scanning signal provided by the first scanning signal line PAM_S1, and the gates of the amplitude data writing transistor T3, the amplitude compensation transistor T4 and the amplitude reset transistor T6 receive the second scanning signal provided by the second scanning signal line PAM_S2.

[0158] The pulse width modulation module 111 may include a third light emission control transistor T10, a pulse width data writing transistor T11, a second driving transistor T12, a pulse width compensation transistor T13, a pulse width gate reset transistor T14, a third light emission control transistor T15 and a third capacitor C3.

[0159] Among them, the source of the third light-emitting control transistor T10 is electrically connected to the third power supply line PWM_VDD, and the drain is electrically connected to the source of the second driving transistor T12. The source of the fourth light-emitting control transistor T15 is electrically connected to the drain of the second driving transistor T12, and the drain is electrically connected to the gate of the first driving transistor Td in the amplitude adjustment module 111. The source of the pulse width data writing transistor T11 is electrically connected to the second data signal line PWM_Data, and the drain is electrically connected to the source of the second driving transistor T12. The source of the pulse width compensation transistor T13 is electrically connected to the drain of the second driving transistor T12, and the drain is electrically connected to the gate of the second driving transistor T12. The source of the pulse width gate reset transistor T14 is electrically connected to the third reset signal line PWM_REF, and the drain is electrically connected to the gate of the second driving transistor T12. One plate of the third capacitor C3 is electrically connected to the gate of the second driving transistor T12, and the other plate is electrically connected to the sweep signal line SWEEP.

[0160] The gates of the third light-emitting control transistor T10 and the fourth light-emitting control transistor T15 receive the first pulse width light-emitting control signal provided by the second light-emitting control signal line EM2, the gate of the pulse width gate reset transistor T14 receives the third scanning signal provided by the third scanning signal line PWM_S1, and the gates of the pulse width data writing transistor T11 and the pulse width compensation transistor T13 receive the fourth scanning signal provided by the fourth scanning signal line PWM_S2.

[0161] Optionally, the pulse width modulation module 111 also includes a sweeping transistor T16, which is connected in series between the sweeping constant voltage signal line SWEEP_GND and the third capacitor C3 (for example, the plate in the third capacitor C3 connected to the sweeping signal line SWEEP), and the gate of the sweeping transistor T16 receives the fourth scanning signal provided by the fourth scanning signal line PWM_S2. Under the control of the fourth scanning signal, the sweeping transistor T16 is turned on to transmit the sweeping constant voltage provided by the sweeping constant voltage signal line SWEEP_GND to the third capacitor C3, and the sweeping constant voltage can be the same as the high level of the sweeping signal, or the same as the low level of the sweeping signal. At this time, the sweeping constant voltage signal line SWEEP_GND and the sweeping signal line SWEEP both provide signals to one plate of the third capacitor C3 (for example, the plate in the third capacitor C3 connected to the sweeping signal line SWEEP), which can further ensure the stability of the plate potential of the third capacitor C3 and reduce the signal disturbance caused by the peripheral signal.

[0162] In addition, the amplitude adjustment module 112 may also include a seventh transistor T7, which is connected in series between the first capacitor C1 and the first power line PAM_VDD. The gate of the seventh transistor T7 receives a first pulse width light-emitting control signal provided by the second light-emitting control signal line EM2. Under the control of the first pulse width light-emitting control signal, the seventh transistor T7 is turned on to transmit the voltage provided by the first power line PAM_VDD to the first capacitor C1, thereby applying the voltage on the first power line PAM_VDD to the amplitude adjustment module 112 in the light-emitting stage, thereby providing a driving current to the light-emitting unit 12.

[0163] Optionally, the amplitude adjustment module 112 also includes an eighth transistor T8 and a ninth transistor T9, the eighth transistor T8 is connected in series between the third power line PWM_VDD and the first capacitor C1, the gate of the eighth transistor T8 receives the first scanning signal provided by the first scanning signal line PAM_S1, and under the control of the first scanning signal, the eighth transistor T8 is turned on to transmit the voltage provided by the third power line PWM_VDD to the first capacitor C1; the ninth transistor T9 is also connected in series between the third power line PWM_VDD and the first capacitor C1, the gate of the ninth transistor T9 receives the second scanning signal provided by the second scanning signal line PAM_S2, and under the control of the second scanning signal, the ninth transistor T9 is turned on to transmit the voltage provided by the third power line PWM_VDD to the first capacitor C1, so that the voltage on the third power line PWM_VDD is applied to the amplitude adjustment module 112 when the amplitude adjustment module 112 performs the reset phase and the data writing phase.

[0164] Furthermore, the amplitude adjustment module 112 further includes a second capacitor C2, which is connected in series between the second reset signal line PAM_INIT and the first capacitor C1, and can be used to stabilize the plate potential of the first capacitor C1.

[0165] In the pixel circuit 11, the essence of its working principle is to set a reference voltage (such as the voltage on the third power line PWM_VDD) at the source of the second driving transistor T12 of the pulse width modulation module 111, and form a changing potential at the gate of the second driving transistor T12 through the data voltage on the second data signal line PWM_Data and the sweep signal on the sweep signal line SWEEP. When the voltage difference between the gate and the source of the second driving transistor T12 is greater than the threshold voltage of the second driving transistor T12, the second driving transistor T12 is in a cut-off state. At this time, the pulse width modulation module 111 does not provide a control signal to the amplitude adjustment module 112, and the first driving transistor Td in the amplitude adjustment module 112 provides a light-emitting driving current to the light-emitting unit 12 according to the voltage on the first data signal line PAM_Data.

[0166] As the voltage of the frequency sweep signal changes, the potential of the gate of the second driving transistor T12 changes synchronously, until the voltage difference between the gate and the source of the second driving transistor T12 is equal to (or less than) the threshold voltage of the second driving transistor T12, the second driving transistor T12 is turned on, and the second driving transistor T12 transmits the voltage on the third power line PWM_VDD as the cut-off voltage to the amplitude adjustment module 112, so that the first driving transistor Td in the amplitude adjustment module 112 is cut off, thereby stopping the supply of the light-emitting driving current to the light-emitting element 12. Therefore, the pulse width adjustment module 111 actually provides a PWM control signal to the amplitude adjustment module 112, and controls the duration of the amplitude adjustment module 112 outputting the light-emitting driving current by adjusting the duty cycle of PWM, thereby changing the effective light-emitting duration of the light-emitting unit 12 in a frame time period, and controlling the light-emitting brightness of the light-emitting element 12.

[0167] It should be noted that Fig.16 The circuit structure of the pixel circuit 11 shown is only a schematic diagram, and the pixel circuit structure provided by the present invention is not limited thereto, and the present invention does not make any specific limitation thereto.

[0168] Optionally, in the pixel circuit 11, some transistors may be dual-gate transistors, wherein the dual-gate transistor may include two transistors connected in series, and two gates of the dual-gate transistor receive the same control signal.

[0169] Combination Fig.16 and Fig.17 As shown, Fig.17A schematic diagram of a pixel circuit provided in an embodiment of the present application, wherein the amplitude adjustment module 112 includes a first driving transistor Td and a first capacitor C1, wherein the first capacitor C1 is located between the pulse width adjustment module 111 and the first driving transistor Td, and the pulse width adjustment module 111 is electrically connected to the gate of the first driving transistor Td, and the pulse width adjustment module 111 is electrically connected to the first capacitor C1. In addition, the first capacitor C1 is also electrically connected to the gate of the first driving transistor Td.

[0170] For example, Fig.16 As shown, the fourth light emitting control transistor T15 in the pulse width modulation module 111 is electrically connected to the gate of the first driving transistor Td and one plate of the first capacitor C1.

[0171] Optional, such as Fig.17 As shown, the pulse width modulation module 111, the first capacitor C1 and the first driving transistor Td are arranged along the second direction Y. This is beneficial to improving the space utilization of the pixel circuit 11 and preventing the pixel circuit 11 from occupying too much space in the first direction X.

[0172] In the embodiment of the present application, the first capacitor C1 is arranged between the pulse width modulation module 111 and the first driving transistor Td, which is conducive to facilitating the electrical connection between the pulse width modulation module 111 and the first capacitor C1, and the pulse width modulation module 111 can also be electrically connected to the gate of the first driving transistor Td through the electrode plate of the first capacitor C1.

[0173] Fig.18 for Fig.17 A cross-sectional schematic diagram of the first capacitor in FIG.

[0174] In one embodiment of the present application, Fig.17 and Fig.18 As shown, the first capacitor C1 includes a first sub-capacitor C11 and a second sub-capacitor C12, the first sub-capacitor C11 includes a first plate F1 and a second plate F2, the second sub-capacitor C12 includes a second plate F2 and a third plate F3, the first plate F1 and the third plate F3 are connected through a via K1. The second plate F2 is located between the first plate F1 and the third plate F3.

[0175] Exemplarily, the first electrode plate F1 is in the same layer as the gate electrode of the first transistor M1 , and the third electrode plate F3 is in the same layer as the source electrode or the drain electrode of the first transistor M1 .

[0176] Based on this configuration, the first capacitor C1 forms a double-layer capacitor structure, which is beneficial to increasing the capacitance value of the first capacitor C1 and further beneficial to improving the voltage stabilizing capability of the first capacitor C1.

[0177] Optional, combined Fig.17 and Fig.19 As shown, Fig.19 This is an enlarged schematic diagram of a first capacitor provided in an embodiment of the present application, wherein the first plate F1 is electrically connected to the gate of the first driving transistor Td, and the pulse width modulation module 111 is electrically connected to the third plate F3. Since the third plate F3 is electrically connected to the first plate F1, the pulse width modulation module 111 can be electrically connected to the gate of the first driving transistor Td through the third plate F3 and the first plate F1.

[0178] Exemplary, combined Fig.17 and Fig.19 As shown, the pulse width modulation module 111 is connected to the third electrode plate F3 at the via K1, and the via K1 is located on the side of the first capacitor C1 close to the pulse width modulation module 111, so as to reduce the connection length between the pulse width modulation module 111 and the first capacitor C1.

[0179] Exemplary, combined Fig.17 and Fig.19 As shown, the second plate F2 can be connected to other devices through the via K2, and the via K2 can be located on the side of the first capacitor C1 close to the pulse width modulation module 111. For example, the second plate F2 can be connected to the seventh transistor T7 ( Fig.19 ), the eighth transistor T8 and the ninth transistor T9 are electrically connected.

[0180] In one embodiment of the present application, please continue to refer to Fig.17 The first light emitting control transistor T1 and the second light emitting control transistor T2 are arranged along the first direction X. The pixel circuit 11 further includes a first capacitor C1. The first capacitor C1 is electrically connected to the gate of the first driving transistor Td.

[0181] In the second direction Y, the first driving transistor Td is located between the first light emitting control transistor T1 and / or the second light emitting control transistor T2 and the first capacitor C1.

[0182] That is, the first capacitor C1 is located at a side of the first driving transistor Td away from the first light emission control transistor T1 and / or the second light emission control transistor T2.

[0183] From the above analysis, it can be known that the first light emission control transistor T1 and the second light emission control transistor T2 are both electrically connected to the first driving transistor Td, and the first capacitor C1 is electrically connected to both the first driving transistor Td and the pulse width modulation module 111. Therefore, by arranging the first capacitor C1 on the side of the first driving transistor Td away from the first light emission control transistor T1 and / or the second light emission control transistor T2, the connection between the first capacitor C1 and the pulse width modulation module 111 can be avoided, and the connection between the first light emission control transistor T1 and / or the second light emission control transistor T2 and the first driving transistor Td can be blocked, which is beneficial to reducing the number of cross-lines in the pixel circuit 11 and reducing the complexity of the layout of the pixel circuit 11.

[0184] Moreover, based on this setting method, the arrangement of the first light-emitting control transistor T1, the second light-emitting control transistor T2 and the first driving transistor Td can be made more compact, which is beneficial to shorten the path of the light-emitting driving current flowing through the first light-emitting control transistor T1, the second light-emitting control transistor T2 and the first driving transistor Td, thereby reducing the loss of the light-emitting driving current.

[0185] Please combine Fig.16 and Fig.17 In one embodiment of the present application, the first light-emitting control signal line EM1, the second light-emitting control signal line EM2, the first scan line PAM_S1, the second scan line PAM_S2, the third scan line PWM_S1, the fourth scan line PWM_S2, the second reset signal line PAM_I NIT, the third power line PWM_VDD, the sweep signal line SWEEP, and the sweep constant voltage signal line SWEEP_GND are arranged on the same layer and on the same layer as the first electrode 21 of the first transistor M1, that is, they can be prepared using the same process and the same material. In this way, it is helpful to simplify the preparation process of the pixel circuit and reduce the preparation cost.

[0186] The second light control signal line EM2 is located on the side of the third power line PWM_VDD close to the amplitude adjustment module 112. This arrangement facilitates the connection between the second light control signal line EM2 and the seventh transistor T7 in the amplitude adjustment module 112 and reduces crossovers.

[0187] Optionally, the first reset signal line PAM_REF and the third reset signal line PWM_REF are in the same layer, and are in the same layer as the second electrode plate F2 of the first capacitor C1 . This is beneficial to further simplify the manufacturing process of the pixel circuit 11 .

[0188] Optionally, the first data signal line PAM_Data and the second data signal line PWM_Data are in the same layer, and are in the same layer as the second electrode 22 of the first transistor M1 .

[0189] It should be noted that in Fig.17 In the figure, structures with the same fill pattern are located in the same film layer.

[0190] Fig. 20A for Fig.17 A schematic diagram of a film layer of the first metal layer in the pixel circuit shown in FIG. Fig. 20B for Fig.17 A schematic diagram of a film layer in the active layer of the pixel circuit shown. Fig. 20C for Fig.17 A schematic diagram of a film layer of the second metal layer in the pixel circuit shown, Fig.20D for Fig.17 A schematic diagram of a film layer of the third metal layer in the pixel circuit shown, Fig.20E for Fig.17 A schematic diagram of a film layer of the fourth metal layer in the pixel circuit shown.

[0191] For the convenience of Fig.17 The understanding of the pixel circuit film layer shown below is combined with Fig.17 and Figure 20A-Figure 20E The film layers of the pixel circuit 11 are briefly introduced. Along the thickness direction perpendicular to the plane where the display panel is located, the pixel circuit 11 includes a first metal layer U1, an active layer YU, a second metal layer U2, a third metal layer U3 and a fourth metal layer U4 arranged in sequence. The active layer YU includes the channel of the transistor as described above. The first metal layer U1 is located on the side of the active layer YU close to the substrate. The first metal layer U1 may include the second sub-electrode 212 (the bottom gate of the transistor) as described above. The second metal layer U2 is located on the side of the active layer YU away from the substrate. The second metal layer U2 may include the first sub-electrode 211 (the top gate of the transistor) as described above, and the first plate F1 of the capacitor. The third metal layer U3 is located on the side of the second metal layer U2 away from the substrate. The third metal layer U3 may include the second plate F2 of the capacitor as described above. The fourth metal layer U4 is located on the side of the third metal layer U3 away from the substrate. The fourth metal layer U4 may include the second electrode 22 (source or drain) of the first transistor M1 as described above, and the connecting line LJ1, etc.

[0192] It should be noted that, in the display panel 01, the first power line PAN_VDD may be disposed on a side of the fourth metal layer U4 away from the substrate.

[0193] Fig.21 A comparative schematic diagram of a first transistor provided in an embodiment of the present application.

[0194] like Fig.21 As shown, in one embodiment of the present application, the pixel circuit 11 includes a plurality of first transistors M1 , and the first transistors M1 include first-type transistors M1A and second-type transistors M1B.

[0195] In the second direction Y, in the first type of transistor M1A, the width of the first sub-portion P11 is D1, the width of the second sub-portion P12 is D2, and D1>D2; in the second type of transistor M1B, the width of the first sub-portion P11 is D3, the width of the second sub-portion P12 is D4, and D3>D4.

[0196] Among them, D1>D3, (D1-D2)>(D3-D4).

[0197] That is, the first sub-portion P11 in the first type transistor M1A is wider than the first sub-portion P11 in the second type transistor M1B, and the degree to which the width of the second sub-portion P12 in the first type transistor M1A is reduced relative to the first sub-portion P11 is greater than the degree to which the width of the second sub-portion P12 in the second type transistor M1B is reduced relative to the first sub-portion P11.

[0198] Based on this setting method, while increasing the diversity of the pixel circuit 11 layout, it is beneficial to significantly reduce the width of the second sub-portion P12 in the first type transistor M1A, thereby helping to significantly reduce the parasitic capacitance between the first electrode 21 and the second electrode 22 in the first type transistor M1A, and helping to make the parasitic capacitance between the first electrode 21 and the second electrode 22 in both the first type transistor M1A and the second type transistor M1B smaller.

[0199] Exemplarily, the first driving transistor Td may be a first type transistor M1A, and the first light emission control transistor T1 and / or the second light emission control transistor T2 may be a second type transistor M1B.

[0200] In addition, (D1-D2) / D1>(D3-D4) / D3 may be set to ensure that the parasitic capacitance between the first electrode 21 and the second electrode 22 in the first type transistor M1A and the second type transistor M1B is small.

[0201] Optional, such as Fig.21 As shown, D2<D3. This helps to ensure that the width of the second sub-portion P12 in the first type transistor M1A is small, and helps to further reduce the parasitic capacitance between the first electrode 21 and the second electrode 22 in the first type transistor M1A.

[0202] Optional, such as Fig.21 As shown, D2 = D4. Thus, the second sub-portion P12 in the first type transistor M1A and the second sub-portion P12 in the second type transistor M1B can have the same width, which is beneficial to reduce the structural complexity of the first transistor M1, thereby reducing the difficulty of layout design of the pixel circuit 11.

[0203] Exemplarily, in the second direction Y, the widths of the second sub-portion P12 in the first-type transistor M1A and the second sub-portion P12 in the second-type transistor M1B are both minimum values ​​allowed by the manufacturing process.

[0204] Fig. 22 A schematic diagram of a display device provided in an embodiment of the present application, Fig.23 A schematic diagram of another display device provided in an embodiment of the present application.

[0205] The present application embodiment provides a display device 02, such as Fig. 22 and Fig.23 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. The display device provided in the embodiment of the present invention may be a spliced ​​display device, such as a frameless spliced ​​display device, which includes at least two of the above display panels 01, so as to be applicable to a large-screen display device with display function.

[0206] The at least two display panels 01 may be arranged along the first direction X, or the at least two display panels 01 may be arranged along the second direction Y, but the present invention is not limited thereto and the present invention does not specifically limit this.

[0207] The display device 02 provided in the embodiment of the present invention can be Fig. 22 The mobile phone shown can also be Fig.23 The spliced ​​display device shown may also be any electronic product with a display function, including but not limited to the following categories: televisions, notebook computers, and desktop displays, which are not particularly limited in the embodiments of the present invention.

[0208] In the display device 02, by setting the width of the second sub-portion P12 in the second direction Y to be smaller, the area of ​​the second sub-portion P12 can be made smaller, which is beneficial to reducing the overlapping area between the second sub-portion P12 and the second portion P2 in the direction perpendicular to the plane of the display panel 01, thereby helping to reduce the parasitic capacitance between the second sub-portion P12 and the second portion P2, and further helping to reduce the parasitic capacitance between the first electrode 21 and the second electrode 22.

[0209] When driving the first transistor M1, the first electrode 21 or the second electrode 22 of the first transistor M1 can receive the driving signal. Since the parasitic capacitance between the first electrode 21 and the second electrode 22 is reduced, the load of the driving signal can be reduced, which is beneficial to improving the driving delay problem of the first transistor M1 and improving the display effect of the display panel 01.

[0210] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A pixel circuit and a light-emitting unit are located on one side of the substrate; The pixel circuit has a first node and a second node, the first node is electrically connected to the first power line, and the second node is electrically connected to the light emitting unit; The pixel circuit includes a first transistor coupled between the first node and the second node; The first transistor includes a first electrode and a second electrode; the first electrode includes a first portion extending along a first direction, and the second electrode includes a second portion extending along a second direction; the first direction and the second direction intersect; The first portion includes a first sub-portion and a second sub-portion connected, and an orthographic projection of the second sub-portion on the substrate overlaps with an orthographic projection of the second portion on the substrate; In the second direction, the width of the first sub-portion is greater than the width of the second sub-portion.

2. The display panel according to claim 1, characterized in that: The first electrode is a gate electrode, and the second electrode is a source electrode or a drain electrode.

3. The display panel according to claim 1, characterized in that: The pixel circuit includes a first light-emitting control transistor, a first driving transistor, and a second light-emitting control transistor; the first light-emitting control transistor is coupled between the first node and the first driving transistor, and the second light-emitting control transistor is coupled between the first driving transistor and the second node; At least one of the first light emission control transistor, the first driving transistor, and the second light emission control transistor is the first transistor.

4. The display panel according to claim 1, characterized in that: The first transistor includes X sub-transistors, the first electrodes of the X sub-transistors are connected, the second electrodes are connected, and the third electrodes are connected, and X is ≥ 2 and is an integer.

5. The display panel according to claim 1, characterized in that: The first electrode of the first transistor is electrically connected to a first light emitting control signal line, and the first light emitting control signal line includes a third portion extending along the first direction; In the second direction, a width of the third portion is greater than a width of the first portion.

6. The display panel according to claim 5, characterized in that: In the second direction, the width of the third portion is D, 5.6 μm<D≤15 μm.

7. The display panel according to claim 5, characterized in that: The display panel includes a first metal trace, and the first metal trace includes a fourth portion extending along the second direction; The third portion includes a third sub-portion and a fourth sub-portion connected to each other, and an orthographic projection of the fourth sub-portion on the substrate overlaps with an orthographic projection of the fourth portion on the substrate; The fourth sub-portion includes a first connecting portion connected to the third sub-portion, and the width of the first connecting portion in the second direction is d1; The fourth sub-section further includes a second connecting portion connected to the third sub-section, and the width of the second connecting portion in the second direction is d2; The width of the third sub-section in the second direction is D, where d1+d2 <D。 8. The display panel according to claim 7, characterized in that: The first connection portion and the second connection portion are arranged along the second direction, and a first hollow portion is provided between the first connection portion and the second connection portion; An orthographic projection of the first hollow portion on the substrate overlaps with an orthographic projection of the fourth portion on the substrate.

9. The display panel according to claim 8, characterized in that: Along the first direction, the length of the first hollow portion is greater than or equal to the length of the fourth portion.

10. The display panel according to claim 1, characterized in that: The pixel circuit includes a pulse width adjustment module and an amplitude adjustment module which are electrically connected, and the amplitude adjustment module includes the first transistor.

11. The display panel according to claim 10, characterized in that: The amplitude adjustment module includes a first driving transistor and a first capacitor, wherein the first capacitor is located between the pulse width adjustment module and the first driving transistor; the pulse width adjustment module is electrically connected to the gate of the first driving transistor, and the pulse width adjustment module is connected to the first capacitor.

12. The display panel according to claim 11, characterized in that: The first capacitor includes a first sub-capacitor and a second sub-capacitor; the first sub-capacitor includes a first electrode plate and a second electrode plate; the second sub-capacitor includes a second electrode plate and a third electrode plate; The first electrode plate and the third electrode plate are connected through a via.

13. The display panel according to claim 12, characterized in that: The first electrode plate is connected to the gate of the first driving transistor, and the pulse width modulation module is connected to the third electrode plate.

14. The display panel according to claim 3, characterized in that: The first light emission control transistor and the second light emission control transistor are arranged along the first direction; The pixel circuit further includes a first capacitor. In the second direction, the first driving transistor is located between the first light emission control transistor and / or the second light emission control transistor and the first capacitor.

15. The display panel according to claim 3, characterized in that: The first light emission control transistor includes X1 first sub-transistors connected in parallel, and the second light emission control transistor includes X2 second sub-transistors connected in parallel; X1≥2, X2≥2, and X1 and X2 are integers; X1<X2.

16. The display panel according to claim 15, characterized in that: The channel width-to-length ratio of the first sub-transistor is equal to the channel width-to-length ratio of the second sub-transistor.

17. The display panel according to claim 15, characterized in that: The first driving transistor includes X3 third sub-transistors connected in parallel, X3≥2 and X3 is an integer; X1 first sub-transistors are arranged along the second direction, X2 second sub-transistors are arranged in an array along the first direction and the second direction; and X3 third sub-transistors are arranged along the first direction.

18. The display panel according to claim 1, characterized in that: The first electrode of the first transistor includes a plurality of the first portions arranged along the second direction; The plurality of first portions include an edge first portion, the edge first portion being adjacent to the via hole; In the first portion of the edge, the first sub-portion includes a first side and a second side opposite to each other along the second direction, and the second side is located on a side of the first side close to the via hole; the second sub-portion includes a third side and a fourth side opposite to each other along the second direction, and the fourth side is located on a side of the third side close to the via hole; wherein, In the second direction, a distance from the fourth side to the via hole is greater than a distance from the second side to the via hole.

19. The display panel according to claim 3, characterized in that: The first light emission control transistor and the second light emission control transistor are both the first transistors, and a first electrode of the first light emission control transistor is electrically connected to a first electrode of the second light emission control transistor.

20. The display panel according to claim 19, characterized in that: The first light emission control transistor and the second light emission control transistor are arranged along the first direction; The first electrode of the first light emission control transistor is electrically connected to a first light emission control signal line, and the first light emission control signal line includes a third portion extending along the first direction; The third portion is located on a side of the first light emission control transistor or the second light emission control transistor away from the first driving transistor.

21. The display panel according to claim 1, characterized in that: The pixel circuit includes a plurality of the first transistors, wherein the plurality of the first transistors include first-type transistors and second-type transistors; In the second direction, in the first type of transistor, the width of the first sub-portion is D1, the width of the second sub-portion is D2, and D1>D2; in the second type of transistor, the width of the first sub-portion is D3, the width of the second sub-portion is D4, and D3>D4; Among them, D1>D3, (D1-D2)>(D3-D4).

22. The display panel according to claim 21, characterized in that: D2<D3.

23. The display panel according to claim 21, characterized in that: D2=D4.

24. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-23.

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