A low-noise silicon carbide NPN phototransistor and a method for manufacturing the same

Abstract

The application discloses a low-noise silicon carbide NPN photoelectric transistor, which comprises an n-type transition layer, an n+ buried layer, an n-buffer layer, a p-type base layer, an n-type collector layer and a SiO2 oxide layer covering a first isolation groove, the first isolation groove is located on both sides of the p-type base layer along a second direction perpendicular to a first direction, the n+ buried layer with high doping concentration is arranged in the n-type transition layer along the second direction, the n-buffer layer with low doping concentration is located on the upper surface of the n-type transition layer and the n+ buried layer, the p-type base layer is located on the upper surface of the n-buffer layer, the n-type collector layer is located on one side of the p-type base layer away from the n-buffer layer along the second direction, the width of the n-type collector layer is smaller than that of the p-type base layer along the second direction, and the n-type collector layer does not contact the SiO2 oxide layer located on the first isolation groove. The application can greatly reduce the leakage current of the sidewall, and improve the noise performance and the light-dark current ratio.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of photoelectric detection, and particularly relates to a low-noise silicon carbide NPN phototransistor and a preparation method thereof. BACKGROUND

[0002] SiC material has excellent characteristics such as wide band gap, high critical breakdown electric field, high electron saturation velocity and high thermal conductivity, which makes SiC power devices very suitable for high-temperature, high-voltage and high-power application scenarios. For compound semiconductor materials, there is an inverse proportional relationship between the band gap and the cut-off wavelength of the photovoltaic effect. For the 3.27eV band gap of SiC, the cut-off wavelength is near 280nm. Therefore, another important application field of wide band gap semiconductors represented by SiC is ultraviolet photoelectric detection. Compared with traditional silicon-based photoelectric detectors, photoelectric detectors made of SiC do not need additional optical filters and have very good selectivity and very high detection degree in the ultraviolet band; compared with other wide band gap semiconductor photoelectric materials such as aluminum gallium nitride, the preparation technology of SiC is more mature and the process is more advanced, which can be epitaxially grown, has high epitaxial quality, and can directly generate an oxide layer by thermal oxidation, and the process steps are simple. In nature, the ultraviolet waveband with a wavelength less than 280nm is called the solar blind waveband, in which the ultraviolet waveband from the sun is completely absorbed by the atmosphere, and the environmental interference is very low, so the photoelectric detection in the solar blind ultraviolet waveband has great significance. At present, ultraviolet photoelectric detectors prepared from SiC have been widely used in the fields of ultraviolet communication, environmental monitoring and biological detection.

[0003] Photoelectric detection devices mainly have structures such as phototransistors, NPN phototransistors and apd avalanche diodes. The traditional vertical structure SiC phototransistor is epitaxially grown, which is the most commonly used single crystal thin film growth technology for SiC preparation at present, and has the advantages of fast growth speed and good process stability. In the preparation process, the emitter emission region, the base region and the collector region are epitaxially grown on the N-type substrate in sequence, and then the preparation is completed through steps such as trench etching, electrode sputtering, thermal annealing and thermal oxidation to generate an oxide layer. Whether it is a vertical structure or a horizontal structure, the existing technology adopts a three-layer epitaxial growth method. The emitter region, the collector region and the sidewall oxide layer are in direct contact, forming a sharp current concentration point, and the carrier recombination is serious, which leads to large surface leakage current, large dark current, low photo-dark current ratio and low noise performance, thereby affecting the detection performance of the ultraviolet photoelectric detector. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a low-noise silicon carbide NPN phototransistor and a preparation method thereof.

[0005] The technical problem to be solved by the application is solved by the following technical scheme:

[0006] The application provides a low-noise silicon carbide NPN photo transistor, comprising: an n-type transition layer, an n+ buried layer, an n- buffer layer, a p-type base layer and an n-type collector layer arranged along a first direction, and a SiO2 oxide layer covering a first isolation groove located on both sides of the p-type base layer along a second direction perpendicular to the first direction;

[0007] The n+ buried layer has a high doping concentration, and is arranged at intervals along the second direction in the n-type transition layer;

[0008] The n- buffer layer has a low doping concentration and is located on the upper surface of the n-type transition layer and the n+ buried layer;

[0009] The p-type base layer is located on the upper surface of the n- buffer layer; wherein the first isolation groove extends downward from the upper surface of the p-type base layer to the upper surface of the n- buffer layer along the first direction;

[0010] The n-type collector layer is located on the side of the p-type base layer away from the n- buffer layer, and along the second direction, the width of the n-type collector layer is smaller than the width of the p-type base layer, and the n-type collector layer does not contact the SiO2 oxide layer located in the first isolation groove.

[0011] The application also provides a preparation method of a low-noise silicon carbide NPN photo transistor, comprising:

[0012] S1, preparing an n-type substrate, and forming an n-type emitter layer on the upper surface of the n-type substrate along a first direction;

[0013] S2, forming an n-type transition layer on the upper surface of the n-type emitter layer;

[0014] S3, forming an n+ buried layer with a high doping concentration and arranged at intervals along a second direction perpendicular to the first direction in the n-type transition layer;

[0015] S4, forming an n- buffer layer with a low doping concentration on the upper surface of the n-type transition layer;

[0016] S5, forming a p-type base layer on the upper surface of the n- buffer layer;

[0017] S6, etching a first isolation groove on both sides of the p-type base layer along the second direction, wherein the first groove extends downward from the upper surface of the p-type base layer to the upper surface of the n- buffer layer along the first direction;

[0018] S7, forming an n-type collector layer on the upper surface of the p-type base region layer, wherein the width of the n-type collector layer is less than the width of the p-type base region layer along the second direction;

[0019] S8, forming an n+ region in the n-type collector layer by ion implantation;

[0020] S9, forming n-type isolation regions on both sides of the n-type collector layer along the second direction, and the n-type isolation regions are distributed on both sides of the n-type collector layer and in contact with the p-type base region layer along the second direction;

[0021] S10, etching a second isolation groove in the middle of the n+ region, wherein the second isolation groove extends downward from the upper surface of the n-type collector layer to the inside of the n-type collector layer along the second direction;

[0022] S11, forming an emitter metal layer on the lower surface of the n-type substrate;

[0023] S12, forming a collector metal layer on the upper surface of each n+ region;

[0024] S13, forming a SiO2 oxide layer outside the device obtained in S12 to obtain the phototransistor, wherein the n-type collector layer is not in contact with the SiO2 oxide layer located in the first isolation groove.

[0025] Compared with the prior art, the present application has the following advantages:

[0026] Compared with the traditional NPN phototransistor, the NPN phototransistor provided by the present application has a low-doped n-buffer layer, so that the surface state in contact with the p-type base region layer is reduced, thereby reducing the current aggregation and making the current as uniformly distributed as possible. By arranging the high-doped n+ buried layer in the n-type transition layer and spacing the n+ buried layer, the uniform distribution and longitudinal transport of the current can be promoted, and the edge leakage current can be reduced. In addition, by arranging the n-type collector layer with a width smaller than that of the p-type base region layer in the p-type base region layer, and making the n-type collector layer not in contact with the SiO2 oxide layer covering the isolation grooves on both sides of the p-type base region layer, the n-type collector layer can be wrapped in the p-type base region layer, so that the pn junction interface can be wrapped in the p-type base region layer and not in contact with the SiO2 oxide layer of the side wall, thereby avoiding the horizontal transport of the current in the horizontal direction. Therefore, the present application can promote the longitudinal transport of the carrier, reduce the current aggregation, greatly reduce the leakage current of the side wall, improve the noise performance, improve the light-dark current ratio, and thus improve the normalized detectivity of the detector.

[0027] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a partial cross-sectional structure schematic diagram of a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present application;

[0029] Figure 2 is a cross-sectional structure schematic diagram of a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present application;

[0030] Figure 3 is a flowchart of a preparation method of a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present application;

[0031] Figures 4a to 4l is a cross-sectional structure schematic diagram of a device obtained in each preparation step in a preparation process of a low-noise silicon carbide NPN phototransistor provided by an embodiment of the present application;

[0032] Figure 5 is a comparison diagram of dark currents of a low-noise silicon carbide NPN phototransistor and an NPN phototransistor with a traditional structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.

[0034] In a phototransistor, a pn junction is a key area of carrier recombination, and a collector junction formed by a base region and a collector region is an area of carrier recombination concentration. Meanwhile, after SiO2 oxide layers are generated by SiC thermal oxidation, a large number of oxide layer defects exist at a SiO2 / SiC interface, and there is significant oxide layer leakage current at a side wall. These surface leakage currents constitute an important part of dark current, which can cause an increase in noise of the device, a decrease in a light-to-dark current ratio, and a decrease in a detection degree. It is of great significance to focus on and optimize the surface leakage for reducing the dark current of a photodetector. In a traditional three-layer epitaxial structure, a collector junction and an emitter junction directly contact a SiO2 oxide layer side wall in a horizontal direction, which causes a large amount of carrier recombination in a region of the collector junction close to the side wall oxide layer, induces current concentration, causes an increase in leakage current of the device, an increase in noise, and a decrease in a normalized detection degree of the device. Therefore, the present application combines an ion implantation method and designs a device structure under a feasible scheme of an existing process, which can significantly weaken current concentration and carrier recombination from a structure design, thereby reducing surface leakage, reducing dark current, and improving noise characteristics of the device.

[0035] The present application provides a low-noise silicon carbide NPN phototransistor, comprising: an n-type transition layer 3, an n+ buried layer 4, an n- buffer layer 5, a p-type base layer 6 and an n-type collector layer 7 arranged along a first direction, and a SiO2 oxide layer 12 covering a first isolation trench located on both sides of the p-type base layer 6 along a second direction perpendicular to the first direction.

[0036] The n+ buried layer 4 has a high doping concentration, and is arranged in the n-type transition layer 3 along the second direction;

[0037] The n- buffer layer 5 has a low doping concentration, and is located on the upper surface of the n-type transition layer 3 and the n+ buried layer 4;

[0038] The p-type base layer 6 is located on the upper surface of the n- buffer layer 5; wherein the first trench extends downward from the upper surface of the p-type base layer 6 to the upper surface of the n- buffer layer 5 along the first direction;

[0039] The n-type collector layer 7 is located on the side of the p-type base layer 6 away from the n- buffer layer 5, and along the second direction, the width of the n-type collector layer 7 is less than the width of the p-type base layer 6, and the n-type collector layer 7 does not contact the SiO2 oxide layer 12 located in the first isolation trench.

[0040] In some embodiments, the region where the n+ buried layer 4 is arranged is the central region of the n-type transition layer 3, and along the second direction, the width of the region where the n+ buried layer 4 is arranged is at least 1 / 3 of the width of the n-type transition layer 3.

[0041] In some embodiments, there are at least 3 n+ buried layers 4 arranged in the n-type transition layer 3 along the second direction. For example, Figure 1 A partial cross-sectional structure diagram of the low-noise silicon carbide NPN phototransistor provided by the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the first direction is A, and the second direction is B. There are 3 n+ buried layers 4 arranged in the n-type transition layer 3 along the second direction B.

[0042] In some embodiments, the thickness of the n-type transition layer 3 is 5 μm to 10 μm.

[0043] In some embodiments, along the second direction, the width of each n+ buried layer 4 ranges from 3 μm to 5 μm, the distance between every two adjacent n+ buried layers 4 ranges from 2 μm to 4 μm, and the junction depth (i.e. thickness) of the n+ buried layer 4 ranges from 2 μm to 4 μm.

[0044] In some embodiments, the doping element of each n+ buried layer 4 is N, and the doping concentration of each n+ buried layer 4 is greater than or equal to 7e 18 cm -3 . For example, the doping concentration of each n+ buried layer 4 ranges from 7e18 cm -3 ~1e 19 cm -3 .

[0045] In some embodiments, the doping element of the n-buffer layer 5 is N, and the doping concentration is less than or equal to 1e 17 cm -3 . For example, the doping concentration of the n-buffer layer 5 ranges from 5e 16 cm -3 ~1e 17 cm -3 .

[0046] In some embodiments, the thickness of the n-buffer layer 5 ranges from 2μm to 3μm.

[0047] Compared with the traditional NPN phototransistor, by setting the n-buffer layer 5 with a very low doping concentration, the surface state in contact with the p-type base layer can be reduced; by setting the n+ buried layer with high doping concentration and interval arrangement characteristics in the n-type transition layer, and making the width of each n+ buried layer range from 3μm to 5μm, the distance between each n+ buried layer range from 2μm to 4μm, and the area where the n+ buried layer is located is in the central 1 / 3 area of the entire n-type transition layer, the current uniform distribution and longitudinal transport can be promoted, and the edge leakage current can be reduced.

[0048] In some embodiments, as shown in the above Figure 1 , along the second direction B, the distance L1 between the n-type collector layer 7 and the sidewall of the p-type base layer 6 is at least 5μm, so as to further play the role of isolating the n-type collector layer and the SiO2 oxide layer.

[0049] In some embodiments, the thickness of the p-type base layer 6 ranges from 3μm to 10μm.

[0050] In some embodiments, the doping element of the p-type base layer 6 is Al, and the doping concentration ranges from 5e 15 cm -3 ~3e 16 cm -3 .

[0051] In some embodiments, along the second direction, the ratio of the width of each first isolation trench to the width of the p-type base layer 6 ranges from 0.1 to 0.2.

[0052] In some embodiments, along the second direction, the ratio of the width of the n-type collector layer 7 to the width of the p-type base layer 6 ranges from 0.7 to 0.8.

[0053] In some embodiments, the junction depth of the n-type collector layer 7 ranges from 0.5μm to 1μm, the doping element is N, and the doping concentration ranges from 5e17 cm -3 ~1e 18 cm -3 .

[0054] In some embodiments, the photo transistor provided by the present application further comprises: an n+ region 8, an n- isolation region 9 with low doping concentration, and two collector metal layers 11. The n+ region 8 and the n- isolation region 9 are both located on the side of the n-type collector layer 7 facing away from the p-type base layer 6, and the n- isolation region 9 is distributed on both sides of the n-type collector layer 7 and contacts the p-type base layer 6 along the second direction, and each collector metal layer 11 is located on the upper surface of the n+ region 8. Here, the n+ region is arranged to facilitate the longitudinal transport of carriers in the n-type collector layer; the n- isolation region is arranged to further isolate the sidewall of the n-type collector layer and the p-type base layer.

[0055] As shown in the above Figure 1 , the photo transistor further comprises two n+ regions 8, and each collector metal layer 11 is located on the upper surface of one n+ region 8; the two n+ regions 8 have a second isolation groove therebetween, which extends downward from the upper surface of the n-type collector layer 7 to the inside of the n-type collector layer 7 along the second direction B. The present application uses double collectors instead of a single electrode in the prior art, which can avoid the aggregation of current on one side and further facilitate the uniform distribution of current in the entire horizontal direction, and the etching groove between the electrodes can avoid interference. As an example, the width of the second isolation groove is greater than or equal to 2 μm along the second direction, which can effectively avoid interference.

[0056] In some embodiments, the metal forming the collector metal layer 11 is Ni.

[0057] In some embodiments, the photo transistor provided by the present application further comprises: an n-type substrate 1, an n-type emitter layer 2, and an emitter metal layer 10; the n-type emitter layer 2 is located on the upper surface of the n-type substrate 1; the emitter metal layer 10 is located on the lower surface of the n-type substrate 1; and the n-type transition layer 3 is located on the upper surface of the n-type emitter layer 2. As an example, Figure 2 is a schematic diagram of a cross-sectional structure of a low-noise silicon carbide NPN photo transistor provided by the present application.

[0058] In some embodiments, the thickness of the n-type emitter layer 2 is 4 μm to 10 μm.

[0059] In some embodiments, the material of the n-type substrate is 4H-SiC material, the doping element is N, the thickness is 200 μm to 500 μm, and the doping concentration range is 4e 18 cm -3 ~1e 19 cm -3 .

[0060] In some embodiments, the metal forming the emitter metal layer 10 is Ni.

[0061] In some embodiments, along the second direction, the SiO2 oxide layer 12 also covers the exposed upper surface of the p-type base layer 6, the n-type collector layer 7 and the n- isolation region 9. As shown in the above Figure 2 As shown, the SiO2 oxide layer 12 also covers the exposed upper surface of the p-type base layer 6, the n-type collector layer 7 and the n- isolation region 9, but does not cover the two collector metal layers 11. The present application further insulates the lateral transport of carriers and reduces the surface leakage current by providing the n+ region at the area where the electrode (i.e. the collector metal layer) contacts the n-type collector layer, and at the same time providing the n- isolation region at the interface between the pn junction and the side edge, keeping the n- isolation region low-doped and located at the junction between the n-type collector layer and the p-type base layer, and at the same time in contact with the SiO2 oxide layer.

[0062] The present application also provides a method for preparing the low-noise silicon carbide NPN phototransistor, for preparing the low-noise silicon carbide NPN phototransistor. As shown in the above Figure 3 The method comprises:

[0063] S1, preparing an n-type substrate 1, and forming an n-type emitter layer 2 on the upper surface of the n-type substrate 1 along a first direction.

[0064] Specifically, the n-type substrate material can be selected as 4H-SiC material, the doping element is N, the thickness is 200 μm-500 μm, and the doping concentration range is 4e18cm-3-1e19cm-3. The n-type emitter layer 2 can be formed on the upper surface of the n-type substrate by using a chemical vapor deposition device. As an example, a mixed gas of SiH4, CH4 and N2 can be used as a source gas, H2 is used as a dilution gas, the flow rate of SiH4 is 5 sccm, the flow rate of CH4 is 5 sccm-10 sccm, the flow rate of N2 is 0.01 sccm-0.1 sccm, and the radio frequency power is 10 W-30 W, and the annealing temperature is 900 °C-1200 °C. The obtained n-type emitter layer 2 has a thickness of 4 μm-10 μm, and the doping concentration range is 7e18cm-3-1e19cm-3. As an example, the cross-sectional structure diagram of the device prepared in step S1 is shown in the above Figure 4a

[0065] S2, forming an n-type transition layer 3 on the upper surface of the n-type emitter layer 2.

[0066] ​Specifically, the n-type transition layer can be prepared on the upper surface of the n-type emitter layer 2 by using a chemical vapor deposition device. For example, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the dilution gas, the flow rate of SiH4 can be 5 sccm, the flow rate of CH4 can be 5 sccm to 10 sccm, the flow rate of N2 can be 0.01 sccm to 0.1 sccm, the radio frequency power can be 10 W to 30 W, and the annealing temperature can be 900 °C to 1200 °C. The obtained n-type transition layer has a thickness of 5 μm to 10 μm, and the doping concentration ranges from 1e 18 cm -3 to 2e 18 cm -3 . For example, the cross-sectional structure of the device prepared in step S2 is shown in Figure 4b .

[0067] S3, forming n+buried layers 4 having high doping concentration and being arranged at intervals along a second direction perpendicular to the first direction in the n-type transition layer 3 by ion implantation.

[0068] Specifically, a photoetching process is performed on the upper surface of the n-type transition layer 3, and a window is set as the buried layer area when preparing the mask plate. After exposure, the window is exposed, ion implantation is performed, the width of each n+buried layer 4 ranges from 3 μm to 5 μm, the interval between two adjacent n+buried layers 4 ranges from 2 μm to 4 μm, the junction depth of each n+buried layer 4 ranges from 2 μm to 4 μm, the entire area where the n+buried layer 4 is located is located in the central 1 / 3 area of the entire n-type transition layer 3, the doping element is N, and the doping concentration ranges from 7e 18 cm -3 to 1e 19 cm -3 .

[0069] For example, the cross-sectional structure of the device prepared in step S3 is shown in Figure 4c .

[0070] S4, forming an n-buffer layer 5 having low doping concentration on the upper surface of the n-type transition layer 3.

[0071] Specifically, the n-buffer layer 5 can be prepared on the upper surface of the n-type transition layer 3 by using a chemical vapor deposition device. For example, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the dilution gas, the flow rate of SiH4 can be 5 sccm, the flow rate of CH4 can be 5 sccm to 10 sccm, the flow rate of N2 can be 0.1 sccm to 1 sccm, the radio frequency power can be 10 W to 30 W, and the annealing temperature can be 900 °C to 1200 °C. The obtained n-buffer layer 5 has a thickness of 2 μm to 3 μm, the doping element is N, and the doping concentration ranges from 5e 16 cm -3~1e 17 cm -3 An exemplary schematic diagram of the cross-sectional structure of the device prepared in step S4 is shown in FIG. 4. Figure 4d

[0072] S5, forming a p-type base region layer 6 on the upper surface of the n-buffer layer 5.

[0073] Specifically, the p-type base region layer 6 can be prepared on the upper surface of the n-buffer layer 5 by using a chemical vapor deposition device. Exemplarily, a mixed gas of SiH4, CH4 and N2 can be used as the source gas, H2 can be used as the dilution gas, the flow rate of SiH4 can be 5 sccm, the flow rate of CH4 can be 5 sccm-10 sccm, the flow rate of N2 can be 0.1 sccm-1 sccm, the radio frequency power can be 10 W-30 W, and the annealing temperature can be 900 °C-1200 °C. The obtained p-type base region layer has a thickness of 3 μm-10 μm, the doping element is Al, and the doping concentration ranges from 5e 15 cm -3 ~3e 16 cm -3 An exemplary schematic diagram of the cross-sectional structure of the device prepared in step S5 is shown in FIG. 5. Figure 4e

[0074] S6, etching a first isolation groove on both sides of the p-type base region layer 6 along the second direction, wherein the first groove extends downward from the upper surface of the p-type base region layer 6 to the upper surface of the n-buffer layer 5 along the first direction.

[0075] Specifically, photolithography can be performed on the p-type base region layer 6, a mask is used to protect the central region of the p-type base region layer 6 and leave the edges exposed, and then an inductively coupled plasma (ICP) dry etching process is used to form the first isolation groove on the side surface of the p-type base region layer 6. Exemplarily, the ratio of the width of the protected central region to the overall width of the p-type base region layer 6 along the second direction ranges from 0.8 to 0.9. An exemplary schematic diagram of the cross-sectional structure of the device prepared in step S6 is shown in FIG. 6. Figure 4f

[0076] S7, forming an n-type collector layer 7 on the upper surface of the p-type base region layer 6 by ion implantation, wherein the width of the n-type collector layer 7 along the second direction is less than the width of the p-type base region layer 6.

[0077] ​​​Specifically, on the upper surface of the p-type base region layer 6, a window is set as the n-type collector layer region by a photoetch process when a mask plate is prepared, the window is exposed after exposure, and ion implantation is performed. In the second direction, the width of the outer region of the n-type collector layer region on the p-type base region layer 6 is 0.2-0.3 times the overall width of the p-type base region layer 6, the n-type collector layer 7 is formed using an ion implantation process when a well region is implanted, the junction depth of the n-type collector layer 7 is 0.5-1 μm, the doping element is N, and the doping concentration is 5e17 cm-3-1e18 cm-3. An exemplary cross-sectional structure of the device prepared in step S7 is shown in FIG. 7. Figure 4g

[0078] S8, an n+ region 8 is formed in the n-type collector layer 7 by ion implantation.

[0079] Specifically, the n+ region 8 is formed by ion implantation after a window is set as the n+ region region by a photoetch process on the n-type collector layer 7 when a mask plate is prepared, the window is exposed after exposure. The width of the n+ region 8 is 2-5 μm, the junction depth of the n+ region 8 is 0.2-0.3 μm, the doping element is N, and the doping concentration is 5e 18 cm -3 -1e 19 cm -3 . An exemplary cross-sectional structure of the device prepared in step S8 is shown in FIG. 8. Figure 4h

[0080] S9, an n- isolation region 9 is formed on both sides of the n-type collector layer 7 in the second direction by ion implantation, and the n- isolation region 9 is distributed on both sides of the n-type collector layer 7 and contacts the p-type base region layer 6 in the second direction.

[0081] Specifically, the n- isolation region 9 is formed by ion implantation after a window is set as the n- isolation region region by a photoetch process on the n-type collector layer 7 when a mask plate is prepared, the window is exposed after exposure. The width of the n- isolation region 9 is 2-4 μm, the junction depth of the n- isolation region 9 is 0.2-0.3 μm, the doping element is N, and the doping concentration is 5e 16 cm -3 -1e 17 cm -3 . An exemplary cross-sectional structure of the device prepared in step S9 is shown in FIG. 9. Figure 4i

[0082] S10, a second isolation groove is etched in the middle of the n+ region 8, wherein the second isolation groove extends downward from the upper surface of the n-type collector layer 7 to the inside of the n-type collector layer 7 in the second direction.

[0083] ​​​Specifically, photolithography is performed on the n-type collector layer 7, and a mask is used to expose the region between the two n+ regions 8, wherein the exposed region has a width ranging from 2 μm to 4 μm in the second direction, and then a second isolation trench is formed in the exposed region by using an inductively coupled plasma (ICP) dry etching process, and the etching depth ranges from 0.4 μm to 0.6 μm. The cross-sectional structure of the device prepared in step S10 is shown in Fig. 2, for example. Figure 4j

[0084] S11, forming an emitter metal layer 10 on the lower surface of the n-type substrate 1.

[0085] Specifically, the emitter metal is sputtered on the lower surface of the n-type substrate by using a magnetron sputtering technique, and the metal used is Ni, the sputtering rate is 10 nm / min-15 nm / min, the sputtering power is 100 W-120 W, and the sputtering thickness is 200 nm-250 nm. The cross-sectional structure of the device prepared in step S11 is shown in Fig. 3, for example. Figure 4k

[0086] S12, forming a collector metal layer 11 on the upper surface of each n+ region 8.

[0087] Specifically, photolithography is performed on each n+ region 8, and a mask is used to expose the central region of each n+ region 8 while protecting other regions, and the ratio of the width of the exposed central region of each n+ region 8 to the width of the n+ region 8 ranges from 0.3 to 0.4 in the second direction, and then a collector metal is magnetron sputtered on the exposed region by using a magnetron sputtering technique, and the metal used is Ni, the sputtering rate is 10 nm / min-15 nm / min, the sputtering power is 100 W-120 W, and the sputtering thickness is 200 nm-250 nm. The cross-sectional structure of the device prepared in step S12 is shown in Fig. 4, for example. Figure 4l

[0088] S13, forming a SiO2 oxide layer on the outside of the device obtained in S12 to obtain a phototransistor, wherein the n-type collector layer 7 does not contact the SiO2 oxide layer 12 located in the first isolation trench.

[0089] Specifically, for the entire device prepared in step S12, a SiO2 layer is formed on the surface of the silicon carbide material by a thermal oxidation process. The thickness of the obtained SiO2 oxide layer 12 ranges from 0.5 μm to 1 μm, for example.

[0090] ​​​In the thermal oxidation process of the present application, the thermal oxidation temperature is controlled at a maximum temperature of 1400-1450 DEG C lower than the melting point of nickel, so that the annealing temperature can be as high as possible under the premise of not melting the metal nickel, thereby reducing the concentration of carbon antisite defects in the prepared oxide layer.

[0091] In the conventional SiC thermal oxidation process for generating SiO2 oxide layer, the oxygen flow rate and the argon flow rate are similar, and the oxygen is in a rich environment, however, in the rich oxygen environment, a large amount of carbon antisite defects are generated, the carbon antisite defects are various and have a large concentration, and are the main defects in the SiO2 / SiC interface defects. In the thermal oxidation process of the present application, the oxygen flow rate is less than 1 / 4 of the argon flow rate, for example, the oxygen flow rate is controlled at 50-100 sccm, and the argon flow rate is 500 sccm, so that the oxygen can be in a poor environment, thereby reducing the concentration of carbon antisite defects in the prepared oxide layer. That is, the high-temperature thermal oxidation and poor oxygen environment process adopted in the present application can greatly reduce the generation of carbon antisite defects from the chemical point of view, thereby reducing the leakage of the oxide layer of the device, reducing the carrier recombination, weakening the noise current, and improving the normalized detectivity of the detector.

[0092] For example, the cross-sectional structure of the device prepared by the step S13 is shown in the above Figure 2 .

[0093] For example, Figure 5 The dark current comparison chart of the low-noise silicon carbide NPN phototransistor provided by the present application and the NPN phototransistor with a conventional structure is shown in the above Figure 5 It is obvious that the dark current of the low-noise silicon carbide NPN phototransistor provided by the present application is much smaller than the dark current of the NPN phototransistor with a conventional structure.

[0094] It should be noted that the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0095] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.

[0096] In the specification, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0097] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A low-noise silicon carbide NPN phototransistor, characterized in that, include: The n-type substrate (1), n-type emitter layer (2), n-type transition layer (3), n+ buried layer (4), n- buffer layer (5), p-type base region layer (6) and n-type collector layer (7) are arranged along a first direction, and a SiO2 oxide layer (12) covering a first isolation trench is provided. The first isolation trench is located on both sides of the p-type base region layer (6) along a second direction perpendicular to the first direction. The n+ buried layer (4) has a high doping concentration and is spaced apart along the second direction in the n-type transition layer (3); The n-buffer layer (5) has a low doping concentration and is located on the upper surface of the n-type transition layer (3) and the n+ buried layer (4); The p-type base region layer (6) is located on the upper surface of the n-buffer layer (5); wherein, the first isolation trench extends downward from the upper surface of the p-type base region layer (6) to the upper surface of the n-buffer layer (5) along the first direction; The n-type current collector layer (7) is located on the side of the p-type base region layer (6) away from the n-buffer layer (5). Along the second direction, the width of the n-type current collector layer (7) is smaller than the width of the p-type base region layer (6), and the n-type current collector layer (7) does not contact the SiO2 oxide layer (12) located in the first isolation trench. The fabrication method of the low-noise silicon carbide NPN phototransistor includes: S1. Prepare the n-type substrate (1) and epitaxially grow the n-type emission layer (2) on the upper surface of the n-type substrate (1) along the first direction; S2. The n-type transition layer (3) is epitaxially grown on the upper surface of the n-type emission layer (2); S3. An n+ buried layer (4) with a high doping concentration and spaced apart along a second direction perpendicular to the first direction is formed in the n-type transition layer (3); S4. An n-buffer layer (5) with a low doping concentration is epitaxially grown on the upper surface of the n-type transition layer (3); S5. The p-type base region layer (6) is epitaxially grown on the upper surface of the n-buffer layer (5); S6. Along the second direction, the first isolation trench is etched on both sides of the p-type base layer (6), wherein the first isolation trench extends downward from the upper surface of the p-type base layer (6) to the upper surface of the n-buffer layer (5) along the first direction. S7. An n-type current collector layer (7) is formed on the upper surface of the p-type base layer (6) by ion implantation, wherein the width of the n-type current collector layer (7) is smaller than the width of the p-type base layer (6) along the second direction.

2. The low-noise silicon carbide NPN phototransistor according to claim 1, characterized in that, The area where the spaced-apart n+ buried layers (4) are located is the central area of ​​the n-type transition layer (3), and along the second direction, the width of the area where the spaced-apart n+ buried layers (4) are located is at least 1 / 3 of the width of the n-type transition layer (3).

3. The low-noise silicon carbide NPN phototransistor according to claim 1, characterized in that, Along the second direction, the width of each n+ buried layer (4) ranges from 3μm to 5μm, and the spacing between any two adjacent n+ buried layers (4) ranges from 2μm to 4μm.

4. The low-noise silicon carbide NPN phototransistor according to claim 1, characterized in that, Along the second direction, the distance between the sidewalls of the n-type current collector layer (7) and the p-type base layer (6) is at least 5 μm.

5. The low-noise silicon carbide NPN phototransistor according to claim 1, characterized in that, The phototransistor further includes: an n+ region (8), an n- isolation region with low doping concentration (9), and two collector metal layers (11); The n+ region (8) and the n- isolation region (9) are both located on the side of the n-type collector layer (7) away from the p-type base layer (6), and along the second direction, the n- isolation region (9) is distributed on both sides of the n-type collector layer (7) and contacts the p-type base layer (6); Each collector metal layer (11) is located on the upper surface of the n+ region (8).

6. The low-noise silicon carbide NPN phototransistor according to claim 5, characterized in that, The phototransistor further includes two n+ regions (8), each collector metal layer (11) located on the upper surface of one n+ region (8); a second isolation trench is provided between the two n+ regions (8), and along the second direction, the second isolation trench extends downward from the upper surface of the n-type collector layer (7) into the interior of the n-type collector layer (7).

7. The low-noise silicon carbide NPN phototransistor according to claim 6, characterized in that, Along the second direction, the width of the second isolation trench is greater than or equal to 2 μm.

8. The low-noise silicon carbide NPN phototransistor according to claim 6, characterized in that, Along the second direction, the SiO2 oxide layer (12) also covers the exposed upper surfaces of the p-type base region layer (6), the n-type current collector layer (7), and the n-isolation region (9).

9. The low-noise silicon carbide NPN phototransistor according to claim 1, characterized in that, The phototransistor further includes: an emitter metal layer (10); The emitter metal layer (10) is located on the lower surface of the n-type substrate (1).

10. The low-noise silicon carbide NPN phototransistor according to claim 1, characterized in that, The fabrication method of the low-noise silicon carbide NPN phototransistor further includes: S8. An n+ region (8) is formed in the n-type collector layer (7); S9. Along the second direction, n-isolation regions (9) are formed on both sides of the n-type collector layer (7), and along the second direction, the n-isolation regions (9) are distributed on both sides of the n-type collector layer (7) and contact the p-type base layer (6); S10. Etch a second isolation trench in the middle of the n+ region (8), wherein, along the second direction, the second isolation trench extends downward from the upper surface of the n-type current collector layer (7) to the interior of the n-type current collector layer (7); S11. An emitter metal layer (10) is formed on the lower surface of the n-type substrate (1); S12. A collector metal layer (11) is formed on the upper surface of each n+ region (8); S13. A SiO2 oxide layer is formed on the outside of the device obtained in S12 to obtain the phototransistor, wherein the n-type collector layer (7) does not contact the SiO2 oxide layer (12) located in the first isolation trench.

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