Display device

Abstract

A display device includes: a substrate including pixels; a light emitting diode disposed in the pixel; a first insulating layer disposed around the light emitting diode; a second insulating layer disposed on the first insulating layer; and a first bank disposed around the second insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device including a light emitting diode. Background Art

[0002] In addition to the display screen of a television or monitor, the display device is also widely used as a display screen for a laptop computer, a tablet computer, a smart phone, a portable display device, and a portable information device. Each of a liquid crystal display device and an organic light emitting display device uses a thin film transistor as a switching element to display an image. Due to the presence of a backlight unit, the liquid crystal display device has design limitations, as well as reduced brightness and response speed. Because the organic light emitting display device contains organic materials, the organic light emitting display device is susceptible to moisture, thereby reducing its reliability and lifespan.

[0003] Recently, research and development of light emitting diode display devices using micro light emitting diodes are being conducted. The light emitting diode display devices are receiving attention as next generation display devices because the light emitting diode display devices have high image quality and high reliability. Summary of the invention

[0004] The light-emitting diode display device may have stains on the display panel due to the difference between the brightness levels of the front surface and the side surface of the display panel. In addition, the P / N electrode structure of the light-emitting diode may cause asymmetry in the brightness levels in the left beam angle and the right beam angle. In addition, due to tolerances in the manufacturing process of the light-emitting diode, the non-uniformity of the viewing angle increases depending on the position of the light-emitting diode.

[0005] Therefore, an object of the present disclosure is to provide a display device with reduced luminance non-uniformity based on viewing angle to solve the above-mentioned problems.

[0006] The purpose according to the present disclosure is not limited to the purpose mentioned above. Other purposes and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved using the means shown in the claims or their combination.

[0007] To achieve this objective, a display device according to some embodiments of the present disclosure may include: a substrate including pixels; a light-emitting diode arranged in the pixel; a first insulating layer arranged around the light-emitting diode; a second insulating layer arranged on the first insulating layer; and a first dam arranged around the second insulating layer.

[0008] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0009] The technical solutions according to the embodiments of the present disclosure are not limited to the technical solutions mentioned above. According to the following description set forth below, those skilled in the art can clearly understand other technical solutions not mentioned above.

[0010] According to the present disclosure, a dam can be provided around a light emitting diode to absorb a light beam emitted from the light emitting diode that has a small emission direction angle relative to the upper surface of the substrate and is thus directed to the side surface of the display device, thereby reducing the visibility difference caused by the reflected light. Therefore, the brightness deviation based on the viewing angle of the display device can be reduced.

[0011] The effects of the present disclosure are not limited to the above-mentioned effects, but other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0012] In addition to the above-described effects, specific effects of the present disclosure are described together with specific details for implementing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a configuration diagram of a display device according to an embodiment of the present disclosure.

[0014] Figure 2 is a perspective view of a tiled display device according to an embodiment of the present disclosure.

[0015] Figure 3 is a plan view of a display device according to an embodiment of the present disclosure.

[0016] Figure 4 is a plan view of a display device according to an embodiment of the present disclosure.

[0017] Figure 5 is a plan view of a display device according to an embodiment of the present disclosure.

[0018] Figure 6 is a plan view of a display device according to another embodiment of the present disclosure.

[0019] Figure 7 is a plan view of a display device according to another embodiment of the present disclosure.

[0020] Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0021] Fig. 9 is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0022] Fig.10 is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0023] Fig.11 is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0024] Fig.12 is an enlarged cross-sectional view of a display device according to another embodiment of the present disclosure.

[0025] Figures 13 to 15 is a diagram showing a brightness level based on a viewing angle of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Refer to the attached Figure 1 The advantages and features of the present disclosure and the methods for achieving the advantages and features will become apparent from the detailed description of the embodiments. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. Therefore, these embodiments are only set forth to complete the present disclosure and fully inform the scope of the present disclosure to those of ordinary skill in the art to which the present disclosure belongs.

[0027] For simplicity and clarity of explanation, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements, and therefore perform similar functions. In addition, for simplicity of description, the description and details of known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other cases, known methods, processes, components and circuits are not described in detail to avoid unnecessarily blurring the various aspects of the present disclosure. The examples of various embodiments are further described and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, the description herein is intended to cover the alternatives, modifications and equivalents as may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0028] The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments of the present disclosure are illustrative, and the embodiments of the present disclosure are not limited thereto.

[0029] The terms used herein are only intended to describe the purpose of a particular embodiment, and are not intended to limit the present disclosure. As used herein, singular components "one" and "a" are intended to also include plural components, unless the context clearly indicates otherwise. It will also be understood that the terms "include", "include", "comprise" and "comprises" specify the presence of the features, integers, operations, elements and / or parts when used in this specification, but do not exclude the presence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Statements such as "at least one of" can modify the entire element list before the element list, and the individual elements in the list cannot be modified. When explaining numerical value, even if there is no clear description thereof, errors or tolerances therein can also occur.

[0030] In addition, it should also be understood that when a first element or layer is referred to as being present "on" a second element or layer, the first element may be directly disposed on the second element, or may be indirectly disposed on the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer. It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, the element or layer may be directly connected to or coupled to the other element or layer, or one or more intermediate elements or layers may be present. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0031] In addition, as used herein, when a layer, film, region, plate, etc. may be disposed "on" or "on top of" another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly "on" or "on top of" another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. may be disposed "under" or "below" another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly "under" or "below" another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter.

[0032] In the description of a time relationship such as a time priority relationship between two events, such as "after", "after", "before", etc., unless there is no indication of "directly after", "directly after", or "directly before", another event may occur between the two events.

[0033] When a certain embodiment can be implemented differently, the function or operation specified in the specific block can occur in an order different from the order specified in the flow chart. For example, two consecutive blocks can actually be executed substantially simultaneously, or the two blocks can be executed in reverse order according to the functions or operations involved.

[0034] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0035] When the embodiment can be implemented differently, the functions or operations specified in a particular block can be performed in an order different from the order specified in the flowchart. For example, two consecutive blocks can actually be performed substantially simultaneously, or the blocks can be performed in the reverse order according to the related functions or operations.

[0036] The features of various embodiments of the present disclosure may be partially or completely combined with each other, and may be technically associated with each other or operate with each other. These embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0037] When interpreting numerical values, unless otherwise expressly stated, the values ​​are interpreted as including the error range.

[0038] It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. In addition, it should be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0039] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such in this article.

[0040] As used herein, "embodiment," "example," "aspect," etc. should not be construed as preferring or advantageous over any aspect or design described over other aspects or designs.

[0041] Additionally, the term "or" is intended to mean an inclusive or rather than an exclusive or. That is, unless stated otherwise or clear from the context, the phrase "x employs a or b" means any of the natural inclusive permutations.

[0042] The terms used in the following description are selected to be general and common in the relevant technical field. However, other terms than the terms may exist according to the development and / or change of technology, convention, preference of technicians, etc. Therefore, the terms used in the following description should not be understood as limiting the technical concept, but should be understood as examples of terms used to illustrate the implementation mode.

[0043] In addition, in specific cases, the terms may be arbitrarily selected by the applicant, and in this case, their detailed meanings will be described in the corresponding description period. Therefore, the terms used in the following description should be understood not only based on the names of the terms, but also based on the meanings of the terms and the content throughout the specific implementation methods.

[0044] In the description of a signal flow, for example, when a signal is delivered from node A to node B, this may include a case where the signal is transmitted from node A to node B via another node unless the phrase “transmitted immediately” or “transmitted directly” is used.

[0045] Throughout this disclosure, unless otherwise stated, "A and / or B" means A, B, or A and B, and unless otherwise stated, "C to D" means C (inclusive) to D (inclusive).

[0046] “At least one” should be understood to include any combination of one or more of the listed components. For example, “at least one of a first component, a second component, and a third component” means not only the first component, the second component, or the third component, but also all combinations of two or more of the first component, the second component, and the third component.

[0047] Hereinafter, embodiments of the present disclosure will be described using the accompanying drawings. For convenience of explanation, the proportion of each of the components shown in the accompanying drawings is different from its actual proportion, and therefore, the present disclosure is not limited to the proportions shown in the accompanying drawings.

[0048] “At least one” should be understood to include any combination of one or more of the listed components. For example, “at least one of a first component, a second component, and a third component” means not only the first component, the second component, or the third component, but also all combinations of two or more of the first component, the second component, and the third component.

[0049] Hereinafter, the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 is a configuration diagram of a display device according to one embodiment of the present disclosure.

[0051] Reference Figure 1 The display device 10 may include a display panel PN including a plurality of sub-pixels SP, a data driver 40 and a gate driver 30 providing various signals to the display panel PN, and a timing controller 20 controlling the gate driver 30 and the data driver 40 .

[0052] The gate driver 30 provides a plurality of scanning signals to the plurality of gate lines 31 according to a plurality of gate control signals provided from the timing controller 20. Figure 1 , one gate driver 30 is shown to be disposed on and spaced apart from one side of the display panel PN. However, the number and arrangement of the gate drivers 30 are not limited thereto.

[0053] The data driver 40 converts the image data input from the timing controller 20 into data voltages using reference gamma voltages according to a plurality of data control signals provided from the timing controller 20. The data driver 40 may provide the converted data voltages to a plurality of data lines 41.

[0054] The timing controller 20 aligns the image data input from the external source and provides the aligned data to the data driver 40. The timing controller 20 may generate a gate control signal and a data control signal using synchronization signals (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the external source. The timing controller 20 may provide the generated gate control signal and the generated data control signal to the gate driver 30 and the data driver 40, respectively, to control the gate driver 30 and the data driver 40.

[0055] The display panel PN is a component for displaying an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of gate lines 31 and a plurality of data lines 41 intersect each other, and each of the plurality of sub-pixels SP is connected to the gate line 31 and the data line 41. Although not shown in the figure, each of the plurality of sub-pixels SP may be connected to a high potential voltage line, a low potential voltage line, a reference voltage line, etc.

[0056] A display area AA and a non-display area NA surrounding the display area AA may be defined in the display panel PN.

[0057] The display area AA is an area in which an image is displayed in the display device 10. Subpixels SP constituting each pixel PX of a plurality of pixels PX and a circuit for driving the plurality of subpixels SP may be provided in the display area AA. Each subpixel SP of the plurality of subpixels SP refers to the minimum unit constituting the display area AA, and n subpixels SP may constitute one pixel PX. A light-emitting element and a thin film transistor for driving the light-emitting element may be provided in each subpixel SP of the plurality of subpixels SP. The type of each of the plurality of light-emitting elements may vary according to the type of the display panel PN. For example, the light-emitting element may be embodied as a light-emitting diode (LED) or a micro-light-emitting diode (micro-LED).

[0058] In the display area AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines may include: a plurality of data lines 41 for providing a data voltage to each of the plurality of sub-pixels SP, and a plurality of gate lines 31 for providing a gate voltage to each of the plurality of sub-pixels SP. The plurality of gate lines 31 may extend in one direction in the display area AA and may be connected to the plurality of sub-pixels SP, and the plurality of data lines 41 may extend in a direction different from the one direction in the display area AA and may be connected to the plurality of sub-pixels SP. In addition, the second power line 230 (see Figure 8 ), the first power line 232 (see Figure 7 ) etc. may also be provided in the display area AA. However, the embodiments of the present disclosure are not limited thereto.

[0059] The non-display area NA is an area in which an image is not displayed, and may be defined as an area extending from the display area AA. In the non-display area NA, a link line and a pad electrode for transmitting a signal to the sub-pixel SP of the display area AA, or a driver IC such as a gate driver IC and a data driver IC may be provided. In one example, the non-display area NA may be located on the rear surface of the display panel PN (i.e., on the surface of the display panel PN where the sub-pixel SP does not exist), or may be omitted. However, the present disclosure is not limited to that shown in the drawings.

[0060] Drivers such as the gate driver 30, the data driver 40, and the timing controller 20 can be connected to the display panel PN in various schemes. For example, the gate driver 30 can be installed in the non-display area NA in a GIP (gate electrode in panel) scheme, or can be installed between a plurality of sub-pixels SP in the display area AA in a GIA (gate electrode in active area) scheme. For example, the data driver 40 and the timing controller 20 can be formed in a separate flexible film and a printed circuit board, and the flexible film and the printed circuit board can be bonded to a pad electrode formed in the non-display area NA of the display panel PN, and thus the data driver 40 and the timing controller 20 can be electrically connected to the display panel PN. When the gate driver 30 is implemented in a GIP scheme, and the data driver 40 and the timing controller 20 transmit signals to the display panel PN via the pad electrode in the non-display area NA, it is necessary to ensure the area of ​​the non-display area NA where the driver 30 and the pad electrode are set so that the frame size can be increased.

[0061] Alternatively, the gate driver 30 may be installed in the display area AA using the GIA scheme, and a side line connecting the signal line of the front surface of the display panel PN to the pad electrode of the rear surface of the display panel PN may be formed, and the flexible film and the printed circuit board are bonded to the rear surface of the display panel PN. In this case, the size of the non-display area NA of the front surface of the display panel PN can be reduced to a minimum size. In other words, when the gate driver 30, the data driver 40, and the timing controller 20 are connected to the display panel PN using the above scheme, a zero frame in which substantially no frame exists can be achieved.

[0062] Figure 2 is a perspective view of a tiled display device 50 according to an embodiment of the present disclosure.

[0063] Reference Figure 2 A light emitting diode may be provided in each pixel PX of the display device 10 according to an embodiment of the present disclosure. The pixel PX is a separate unit that emits light, and may include a plurality of light emitting elements and a plurality of pixel circuits for separately driving the plurality of light emitting elements.

[0064] Reference Figure 2 , a tiled display device 50 having a large screen can be realized by connecting a plurality of display devices 10 to each other. Figure 2 As shown in , when a tiled display device 50 is implemented using a display device 10 having a minimized bezel, a seam area between adjacent display devices 10 in which no image is displayed can be minimized, so that display quality can be improved.

[0065] For example, a plurality of sub-pixels SP may constitute one pixel PX, and an interval D1 between an outermost pixel PX of one display device 10 and an outermost pixel PX of another display device 10 adjacent thereto may be equal to an interval D1 between adjacent pixels PX within one display device 10. Therefore, the intervals between pixels PX of adjacent display devices 10 and the intervals between pixels PX in a display device 10 may be constant, thereby minimizing the seam area and thus realizing a seamless tiled display device 50.

[0066] However, Figure 2 This is just an example, and the display device 10 according to one embodiment of the present disclosure may be a general display device 10 having a bezel. However, embodiments of the present disclosure are not limited thereto.

[0067] Figures 3 to 5 is a plan view of a display device according to an embodiment of the present disclosure. Figure 6 and Figure 7 is a plan view of a display device according to another embodiment of the present disclosure. Figures 3 to 7 In the figure, for the convenience of explanation, only some components of the pixel PX in the components of the display device are shown. For example, Figures 3 to 7 is a plan view showing the light emitting diode 300 and the structure around the light emitting diode 300 .

[0068] Figure 4 and Figure 5 is a plan view of a state in which the light emitting diode 300 has been transferred onto the display panel of the display device according to the embodiment of the present disclosure. Figure 6 and Figure 7 3 is a plan view of a state where a light emitting diode 300 has been transferred to a display panel of a display device according to another embodiment of the present disclosure. Figures 4 to 7, the second bank 326 may be disposed on the top of the reflective layer 310. The second bank 326 may be disposed around the light emitting diode 300 including the n-type electrode 315 and the p-type electrode 319. The light emitting diode 300 may be disposed between the holes 323 defined in the second insulating layer. Even when the light emitting diode 300 has a transfer tolerance, the n-type electrode 315 and the p-type electrode 319 may be electrically connected to the first connection electrode 330 and the second connection electrode 332 via the holes 323 formed in the second insulating layer, respectively. The shape of the hole 323 defined in the second insulating layer may be symmetrical, asymmetrical, a single hole, etc. However, the embodiments of the present disclosure are not limited thereto.

[0069] Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 8 is along Figure 3 , Figure 4 and Figure 6 A cross-sectional view taken along the line AA′ shown in FIG.

[0070] Reference Figure 3 and Figure 8 , each of the multiple sub-pixels SP of the display panel of the display device according to an embodiment of the present disclosure may include a substrate 110, a driving transistor 200, and a light emitting diode 300. The substrate 110 is a component for supporting various components included in the display device 10, and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. In addition, the substrate 110 may be made of a polymer or plastic and may be made of a material having flexibility. The display device according to an embodiment of the present disclosure can operate in a top emission mode in which the emitted light is emitted toward the top of the display device. Therefore, the substrate 110 may be made of an opaque material as well as a transparent material.

[0071] The light blocking layer 210 may be disposed on the substrate 110 and in each of the plurality of sub-pixels SP. The light blocking layer 210 may prevent light incident from a position below the substrate 110 from intruding into the semiconductor layer 214 of the driving transistor 200, which will be described later. The light blocking layer 210 may prevent light from being incident on the semiconductor layer 214 of the driving transistor 200, thereby minimizing leakage current.

[0072] A buffer layer 112 may be disposed on the substrate 110 and the light blocking layer 210. The buffer layer 112 may reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 112 may include, for example, a layer made of silicon oxide (SiO x ) or silicon nitride (SiN x) is a single layer or a multilayer made of. However, the embodiments of the present disclosure are not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 112 may be omitted. However, the embodiments of the present disclosure are not limited thereto.

[0073] The driving transistor 200 may be disposed on the buffer layer 112. The driving transistor 200 includes a semiconductor layer 214, a gate electrode 220, a source electrode 218, and a drain electrode 216.

[0074] A semiconductor layer 214 may be disposed on the buffer layer 112. The semiconductor layer 214 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, embodiments of the present disclosure are not limited thereto.

[0075] The gate insulating layer 114 may be disposed on the semiconductor layer 214. The gate insulating layer 114 is an insulating layer for insulating the semiconductor layer 214 and the gate electrode 220 from each other, and may include a silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or multiple layers. However, the embodiments of the present disclosure are not limited thereto.

[0076] The gate electrode 220 may be disposed on the gate insulating layer 114. The gate electrode 220 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0077] The first interlayer insulating layer 116 and the second interlayer insulating layer 118 are disposed on the gate electrode 220. The first interlayer insulating layer 116 and the second interlayer insulating layer 118 may have a second contact hole 224 and a third contact hole 226 defined therein for connecting the source electrode 218 and the drain electrode 216 to the semiconductor layer 214, respectively. Each of the first interlayer insulating layer 116 and the second interlayer insulating layer 118 serves as an insulating layer for protecting components below the first interlayer insulating layer 116 and the second interlayer insulating layer 118, and may include a silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or a double layer. However, the embodiments of the present disclosure are not limited thereto.

[0078] A source electrode 218 and a drain electrode 216 electrically connected to the semiconductor layer 214 may be disposed on the second interlayer insulating layer 118. Each of the source electrode 218 and the drain electrode 216 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0079] The present disclosure describes an example in which the first interlayer insulating layer 116 and the second interlayer insulating layer 118 (i.e., multiple insulating layers) are disposed between the gate electrode 220 and the source electrode 218 and the drain electrode 216. However, the embodiments of the present disclosure are not limited thereto. Only one insulating layer may be disposed between the gate electrode 220 and the source electrode 218 and the drain electrode 216.

[0080] Furthermore, as shown in the figure, when a plurality of insulating layers such as the first interlayer insulating layer 116 and the second interlayer insulating layer 118 are provided between the gate electrode 220 and the source and drain electrodes 218 and 216, an electrode may be additionally formed between the first interlayer insulating layer 116 and the second interlayer insulating layer 118. The additionally formed electrode and another component provided under the first interlayer insulating layer 116 or on top of the second interlayer insulating layer 118 may constitute a capacitor.

[0081] The auxiliary electrode 212 may be disposed on the gate insulating layer 114. The auxiliary electrode 21 serves as an electrode that electrically connects the light blocking layer 210 disposed under the buffer layer 112 to one of the source electrode 218 and the drain electrode 216 disposed on the second interlayer insulating layer 118. For example, since the light blocking layer 210 is electrically connected to the source electrode 218 or the drain electrode 216 via the auxiliary electrode 212 and does not operate as a floating gate, a change in the threshold voltage of the driving transistor 200 caused by the floating light blocking layer 210 may be minimized. Although the light blocking layer 210 is shown in the drawings to be connected to the drain electrode 216 via the first contact hole 222 extending through the buffer layer 112 and the gate insulating layer 114 and the fourth contact hole 228 extending through the first interlayer insulating layer 116 and the second interlayer insulating film 118, the embodiments of the present disclosure are not limited thereto. The light blocking layer 210 may be connected to the source electrode 218. However, the embodiments of the present disclosure are not limited thereto. For example, the light blocking layer 210 may overlap at least one of the gate electrode 220, the semiconductor layer 214, the source electrode 218, and the drain electrode 216. For example, the light blocking layer 210 may extend to overlap one side and the other side of the semiconductor layer 214.

[0082] The source electrode 218, the drain electrode 216, the first power line 232 and the second power line 230 may be disposed on the second interlayer insulating layer 118. The first power line 232 may be electrically connected to the light emitting diode 300 and the driving transistor 200 so that the light emitting diode 300 emits light. Each of the first power line 232 and the second power line 230 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto. The first power line 232 may be spaced apart from the second power line 230.

[0083] The third interlayer insulating layer 120 may be disposed on the driving transistor 200, the first power line 232, and the second power line 230. The third interlayer insulating layer 120 may be disposed on the source electrode 218 and the drain electrode 216. The third interlayer insulating layer 120 may be an insulating layer for protecting a structure below the third interlayer insulating layer 120. The third interlayer insulating layer 120 may include silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or multiple layers. However, the embodiments of the present disclosure are not limited thereto.

[0084] A planarization layer 124 may be disposed on the third interlayer insulating layer 120. The planarization layer 124 may planarize the top of the portion of the substrate 110 on which the driving transistor 200 is disposed. In the example of the present disclosure, the planarization layer 124 includes a single layer. However, the embodiments of the present disclosure are not limited thereto. For example, the planarization layer 124 may include a plurality of planarization layers. When the planarization layer 124 includes a plurality of planarization layers, at least one of the plurality of planarization layers may include a single layer or a double layer. The planarization layer 124 may be made of, for example, a photoresist or an acrylic-based organic material. However, the embodiments of the present disclosure are not limited thereto. The planarization layer 124 may be a protective layer. However, the embodiments of the present disclosure are not limited thereto.

[0085] A plurality of reflective electrodes 234 and 236 spaced apart from each other may be provided on the planarization layer 124. The plurality of reflective electrodes 234 and 236 electrically connect the light emitting diode 300 to the first power line 232 and the driving transistor 200, and light emitted from the light emitting diode 300 may be reflected from the plurality of reflective electrodes 234 and 236 to guide the light above the light emitting diode 300. Each of the plurality of reflective electrodes 234 and 236 may be made of a conductive material having excellent reflective properties, and light emitted from the light emitting diode 300 may be reflected from the plurality of reflective electrodes 234 and 236 to guide the light above the light emitting diode 300.

[0086] The plurality of reflective electrodes 234 and 236 may include a first reflective electrode 234 and a second reflective electrode 236. The first reflective electrode 234 may electrically connect the driving transistor 200 and the light emitting diode 300 to each other. The first reflective electrode 234 may be connected to the source electrode 218 or the drain electrode 216 of the driving transistor 200 via a sixth contact hole 238 extending through the planarization layer 124. The first reflective electrode 234 may be electrically connected to the p-type electrode 319 and the semiconductor layer 214 of the light emitting diode 300 via a first connection electrode 330, which will be described later. The first reflective electrode 234 may extend to overlap one side and the other side of the light emitting diode 300. For example, the first reflective electrode 234 may be arranged to overlap a portion of the second bank 326. The first reflective electrode 234 may overlap the second power line 230.

[0087] The second reflective electrode 236 may electrically connect the first power line 232 and the light emitting diode 300 to each other. The second reflective electrode 236 may be connected to the first power line 232 via a seventh contact hole 240 extending through the planarization layer 124, and may be electrically connected to the n-type electrode 315 of the light emitting diode 300 via a second connection electrode 332, which will be described later.

[0088] The reflective layer 310 may be disposed on the plurality of reflective electrodes 234 and 236. The reflective layer 310 may overlap a portion of the first reflective electrode 234.

[0089] The fourth interlayer insulating layer 122 may be disposed on the reflective layer 310. The fourth interlayer insulating layer 122 may be an insulating layer for protecting a structure below the fourth interlayer insulating layer 122. The fourth interlayer insulating layer 122 may include silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or multiple layers. However, the embodiments of the present disclosure are not limited thereto.

[0090] The adhesive layer 312 may be disposed on the fourth interlayer insulating layer 122. The adhesive layer 312 may adhere or fix the light emitting diode 300 disposed on the adhesive layer 312. The adhesive layer 312 may be made of, for example, an adhesive polymer, epoxy resin, UV resin, polyimide, acrylic acid, urethane, or polydimethylsiloxane (PDMS). However, embodiments of the present disclosure are not limited thereto.

[0091] A plurality of light emitting diodes 300 can be disposed on the adhesive layer 312 in a manner corresponding to the plurality of sub-pixels SP. Each of the plurality of light emitting diodes 300 refers to a light emitting element that emits light using current. The plurality of light emitting diodes 300 can respectively emit light beams of various colors including red light, green light, and blue light and combinations thereof as white light. However, the embodiments of the present disclosure are not limited thereto.

[0092] The light emitting diode 300 may include an n-type semiconductor layer 314 , a light emitting layer 316 , a p-type semiconductor layer 318 , an n-type electrode 315 , and a p-type electrode 319 .

[0093] The n-type semiconductor layer 314 may be disposed on the adhesive layer 312, and the p-type semiconductor layer 318 may be disposed on the n-type semiconductor layer 314. The n-type conductor layer 314 and the p-type semiconductor layer 318 may be layers formed by doping n-type impurities and p-type impurities into specific materials, respectively. For example, each of the n-type semiconductor layer 314 and the p-type semiconductor layer 318 may be each layer doped with each of n-type impurities and p-type impurities into a matrix made of gallium nitride (GaN), indium aluminum phosphide (InAlP) or gallium arsenide (GaAs). In this regard, the p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc. However, the embodiments of the present disclosure are not limited thereto.

[0094] The light emitting layer 316 may be disposed between the n-type semiconductor layer 314 and the p-type semiconductor layer 318. The light emitting layer 316 may receive holes and electrons from the n-type semiconductor layer 314 and the p-type semiconductor layer 318, and may emit light under the recombination of the holes and the electrons. The light emitting layer 316 may include a single layer or a multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN). However, embodiments of the present disclosure are not limited thereto.

[0095] The n-type electrode 315 may be disposed on the n-type semiconductor layer 314. The n-type electrode 315 may be an electrode for electrically connecting the driving transistor 200 and the n-type semiconductor layer 314 to each other. The n-type electrode 315 may be disposed on an exposed portion of the upper surface of the n-type semiconductor layer 314 that is not covered by the light emitting layer 316 and the p-type semiconductor layer 318. For example, the n-type electrode 315 may be disposed along an edge region of the upper surface of the n-type semiconductor layer 314, and may have a circular shape in its plan view. However, embodiments of the present disclosure are not limited thereto. The n-type electrode 315 may be made of a conductive material, for example, a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0096] The p-type electrode 319 may be disposed on the p-type semiconductor layer 318. The p-type electrode 319 may be disposed on the upper surface of the p-type semiconductor layer 318. The p-type electrode 319 may be an electrode for electrically connecting the first power line 232 and the p-type semiconductor layer 318 to each other. The p-type electrode 319 may be made of a conductive material, for example, a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0097] According to an embodiment of the present disclosure, the display device 10 may include: a substrate 110, the substrate 110 includes pixels; a light-emitting diode 300, the light-emitting diode 300 is arranged in the pixel; a first insulating layer 320, the first insulating layer 320 is arranged around the light-emitting diode 300; a second insulating layer 322, the second insulating layer 322 is arranged on the first insulating layer 320; and a first embankment 324, the first embankment 324 is arranged around the second insulating layer 322.

[0098] According to another embodiment of the present disclosure, the light emitting diode 300 may have a structure different from that of the lateral type light emitting diode 300. The first insulating layer 320 may be located on the side surfaces of the plurality of light emitting diodes 300. The second insulating layer 322 and the third insulating layer 328 may be provided to cover the plurality of light emitting diodes 300 and may fix and / or protect the plurality of light emitting diodes 300. Each of the first insulating layer 320, the second insulating layer 322, and the third insulating layer 328 may include a silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or a multi-layer stack. However, the embodiments of the present disclosure are not limited thereto.

[0099] The first bank 324 may be disposed on the first insulating layer 320. The second insulating layer 322 may be disposed on a side surface of the first bank 324. The third insulating layer 328 may be disposed on the first bank 324 and the second insulating layer 322.

[0100] The second bank 326 may be disposed on the first insulating layer 320. The second insulating layer 322 may be disposed on a side surface of the second bank 326. The third insulating layer 328 may be disposed on the second bank 326 and the second insulating layer 322.

[0101] After forming or depositing the second insulating layer 322 , a plurality of connection electrodes may be formed. The plurality of connection electrodes may include a first connection electrode 330 and a second connection electrode 332 .

[0102] The first connection electrode 330 may be an electrode provided in each of the plurality of sub-pixels SP, and may electrically connect the light emitting diode 300 and the driving transistor 200 to each other. The first connection electrode 330 may be connected to the first reflective electrode 234 via an eighth contact hole 242 extending through the fourth interlayer insulating layer 122, the first insulating layer 320, and the second insulating layer 322. The first connection electrode 330 may be formed along a side surface of the second insulating layer 322.

[0103] The first connection electrode 330 may be electrically connected to one of the source electrode 218 and the drain electrode 216 of the driving transistor 200 via the first reflective electrode 234. The first connection electrode 330 may be connected to the p-type electrode 319 of each of the plurality of light emitting diodes 300. Therefore, the first connection electrode 330 may electrically connect the driving transistor 200 to the p-type semiconductor layer 318 and the p-type electrode 319 of each of the plurality of light emitting diodes 300.

[0104] The second connection electrode 332 may be an electrode for electrically connecting the light emitting diode 300 and the first power line 232 to each other. The second connection electrode 332 may be connected to the second reflective electrode 236 via a ninth contact hole 244 extending through the fourth interlayer insulating layer 122, the first insulating layer 320, and the second insulating layer 322. The second connection electrode 332 may be formed along a side surface of the second insulating layer 322.

[0105] The second connection electrode 332 may be electrically connected to the first power line 232 via the second reflective electrode 236. The second connection electrode 332 may be connected to the n-type electrode 315 of each of the plurality of light emitting diodes 300. Thus, the second connection electrode 332 may electrically connect the first power line 232 to the n-type semiconductor layer 314 and the n-type electrode 315 of each of the plurality of light emitting diodes 300.

[0106] The first connection electrode 330 provided in each of the plurality of sub-pixels SP to connect the driving transistor 200 and the light emitting diode 300 to each other may be provided individually in each of the plurality of sub-pixels SP. The second connection electrode 332 may be provided in each of the plurality of sub-pixels SP to connect the first power line 232 and the light emitting diode 300 to each other. In this regard, the second connection electrodes 332 respectively provided in adjacent sub-pixels SP of the plurality of sub-pixels SP may be connected to each other. For example, since the power voltage of the first power line 232 is commonly applied to all the light emitting diodes 300 of the plurality of light emitting diodes 300 of the plurality of sub-pixels SP, a single integrated second connection electrode 332 may be provided throughout the plurality of sub-pixels SP.

[0107] A first bank 324 and a second bank 326 may be formed on the first connection electrode 330 and the second connection electrode 332 .

[0108] The first bank 324 may be disposed on the top of the driving transistor 200. The first bank 324 may cover at least a portion of the first connection electrode 330 and at least a portion of the second connection electrode 332. The vertical height of the upper surface SS2 of the first bank 324 may be lower than the vertical height of the upper surface SS1 of the light emitting diode 300. For example, the vertical height of the upper surface SS2 of the first bank 324 may be lower than the vertical height of the top of the first connection electrode 330.

[0109] Light emitted from light emitting diode 300 may be emitted from light emitting layer 316 in all directions and may therefore include top directional light 8a, reflected top directional light 8a', side directional light 8b and 8b', first reflected side directional light 8c and 8c', and second reflected side directional light 8d and 8d'.

[0110] The top directional light 8a may be light output from the light emitting diode 300 in an upward direction to the top of the display device. The reflected top directional light 8a' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output to the top of the display device in an upward direction. The side directional lights 8b and 8b' may be light output from the light emitting diode 300 in an upper left direction and an upper right direction, respectively. The first reflected side directional lights 8c and 8c' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output in an upper left direction and an upper right direction, respectively. The second reflected side directional lights 8d and 8d' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output in an upper left direction and an upper right direction, respectively, and then may be absorbed by the second embankment 326.

[0111] exist Figure 8 , the light emitted from the light emitting diode 300 includes: top directional light 8a represented by one or more arrows, reflected top directional light 8a', side directional light 8b and 8b', first reflected side directional light 8c and 8c', and second reflected side directional light 8d and 8d'. However, the embodiments of the present disclosure are not limited to this. However, the embodiments of the present disclosure are not limited to this. The light emitted from the light emitting diode 300 may include a light beam having a propagation direction other than the direction represented by one or more arrows.

[0112] The reflective layer 310 may be formed to extend to overlap one side and the other side of the light emitting diode 300. The reflective layer 310 may overlap a portion of the second bank 326.

[0113] The second bank 326 may be disposed around the light emitting diode 300. For example, the second bank 326 may be disposed around the light emitting diode 300 so that the light emitting region of the light emitting diode 300 is open. Therefore, the second bank 326 may absorb the second reflective side directional light 8d and 8d' reflected from the reflective layer 310. Therefore, since the loss of light output from the light emitting diode 300 is small, the brightness of light in the forward direction of the display device may be improved.

[0114] The vertical height of the top of the second bank 326 may be equal to or different from the vertical height of the top of each of the first connection electrode 330 or the second connection electrode 332. In one example, the vertical height of the top of the second bank 326 may be lower than the vertical height of the top of each of the first connection electrode 330 or the second connection electrode 332.

[0115] The second bank 326 may be disposed in the fifth contact hole 229 defined in the second insulating layer 322. The second bank 326 may be disposed on the first connection electrode 330 or the second connection electrode 332 formed along the bottom surface and the side surface of the fifth contact hole 229. The second bank 326 may be configured to fill at least a portion of the fifth contact hole 229. Therefore, the second reflected side directional light 8d and 8d' in the light of the light emitting diode 300 may be absorbed by the second bank 326.

[0116] Each of the first bank 324 and the second bank 326 may be made of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. However, the embodiments of the present disclosure are not limited thereto. Each of the first bank 324 and the second bank 326 may include a black material that absorbs light. Therefore, the light emitted from the light emitting diode 300 disposed in each sub-pixel SP may be absorbed by the first bank 324 and the second bank 326, and may not be emitted to the outside in the region in which the first bank 324 and the second bank 326 are formed. Therefore, the region in which the first bank 324 and the second bank 326 are formed may correspond to a non-light emitting region. The first bank 324 and the second bank 326 prevent the light emitted from the light emitting diode 300 in one sub-pixel SP from propagating to another sub-pixel SP adjacent to the sub-pixel SP. Therefore, color mixing between light beams from the sub-pixels SP may be prevented. For example, the first bank 324 may be a first black layer or a first light blocking layer. However, the embodiments of the present disclosure are not limited thereto. For example, the second bank 326 may be a second black layer or a second light blocking layer. However, the embodiments of the present disclosure are not limited thereto.

[0117] In the display device according to the embodiment of the present disclosure, the second bank 326 may be located at the side of the light emitting diode 300, and may absorb the second reflected side directional light beams 8d and 8d' among the light beams emitted from the light emitting diode 300. Therefore, the display device according to the embodiment of the present disclosure may minimize the visibility difference caused by the reflected light.

[0118] Fig. 9 is a cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 9 The description of the substrate 110, the driving transistor 200 and the light emitting diode 300 is the same as that of the above reference Figure 8 The descriptions are the same as those given above, so the components are given the same Figure 8 The same figure numbers as in the figure are used, and their repeated descriptions are omitted or simplified.

[0119] Reference Fig. 9 , the light emitted from the light emitting diode 300 may include: top directional light 9a, reflected top directional light 9a', side directional light 9b and 9b', first reflected side directional light 9c and 9c', and second reflected side directional light 9d and 9d'.

[0120] The top directional light 9a may be light output from the light emitting diode 300 in an upward direction to the top of the display device. The reflected top directional light 9a' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output to the top of the display device in an upward direction. The side directional lights 9b and 9b' may be light output from the light emitting diode 300 in an upper left direction and an upper right direction, respectively. The first reflected side directional lights 9c and 9c' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output in an upper left direction and an upper right direction, respectively. The second reflected side directional lights 9d and 9d' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output in an upper left direction and an upper right direction, respectively, and then may be absorbed by the second embankment 326.

[0121] like Fig. 9 As shown, the fifth contact hole 229 extends through the second insulating layer 322, and extends through a portion of the first insulating layer 320. A second bank 326 may be provided on the first connection electrode 330 or the second connection electrode 332 provided in the fifth contact hole 229. The second bank 326 may be configured to fill at least a portion of the fifth contact hole 229. Therefore, the second reflected side directional light beams 9d and 9d' in the light beam of the light emitting diode 300 may be absorbed by the second bank 326.

[0122] Fig.10 and Fig.11is a cross-sectional view of a display device according to another different embodiment of the present disclosure. Fig.10 and Fig.11 The description of the substrate 110, the driving transistor 200 and the light emitting diode 300 in each of the above reference Figure 8 The descriptions are the same as those given above, so the components are given the same Figure 8 The same figure numbers as in the figure are used, and their repeated descriptions are omitted or simplified.

[0123] Reference Fig.10 , the first bank 324 may be formed around the side surface of the light emitting diode 300. The first bank 324 may be provided to cover at least a portion of each of the first connection electrode 330 and the second connection electrode 332. For example, the first bank 324 may be provided on the top of the driving transistor 200. The first bank 324 may be provided on the second connection electrode 330. The vertical height of the top surface SS2 of the first bank may be lower than the vertical height of the top surface SS1 of the light emitting diode 300.

[0124] The light output from the light emitting diode 300 may include: top directional light 10a, reflected top directional light 10a', side directional lights 10b and 10b', and bottom directional lights 10c and 10c'. The top directional light 10a may be light output from the light emitting diode 300 to the top of the display device in an upward direction. The reflected top directional light 10a' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output to the top of the display device in an upward direction. The side directional lights 10b and 10b' may be light output from the light emitting diode 300 in an upper left direction and an upper right direction, respectively. The bottom directional lights 10c and 10c' may be light output from the light emitting diode 300 in a downward direction.

[0125] exist Fig.10 , the light emitted from the light emitting diode 300 includes: top directional light 10a represented by one or more arrows, reflected top directional light 10a', side directional light 10b and 10b', and bottom directional light 10c and 10c'. However, the embodiments of the present disclosure are not limited thereto. The light emitted from the light emitting diode 300 may include a light beam having a propagation direction other than the direction represented by one or more arrows.

[0126] The fourth interlayer insulating layer 122 and the adhesive layer 312 may be disposed on the reflective layer 310. The second bank 326 may be disposed on the fourth interlayer insulating layer 122. The second bank 326 may overlap the reflective layer 310. For example, in a plan view, the area size of the reflective layer 310 may be larger than the area size of the second bank 326. The second bank 326 may overlap the second reflective electrode 234. For example, in a plan view, the area size of the second bank 326 may be smaller than the area size of the second reflective electrode 234. The second bank 326 may overlap a portion of the first bank 324. For example, the second bank 326 may extend to overlap with an outer area of ​​the light emitting diode 300. Each of the two opposite ends of the second bank 326 may overlap a portion of the first bank 324. Therefore, the bottom directional beams 10c and 10c' in the light beam emitted from the light emitting diode 300 may be absorbed by the second bank 326, and thus the brightness difference or deviation according to the viewing angle may be reduced.

[0127] Reference Fig.11 , the side surface of the light emitting diode 300 may contact the first insulating layer 320, the second dam 326, the first connection electrode 330 and the second connection electrode 332. The fourth interlayer insulating layer 122 and the adhesive layer 312 may be disposed on the reflective layer 310. The reflective layer 310 may overlap with the light emitting diode 300 and may overlap with a portion of the second dam 326. The first dam 324 may be disposed on the second insulating layer 322. The first dam 324 may be disposed on the first connection electrode 330. The vertical height of the upper surface SS2 of the first dam 324 may be lower than the vertical height of the upper surface SS1 of the light emitting diode 300. The first connection electrode 330 may be connected to the first reflective electrode 234 via the eighth contact hole 242 extending through the fourth interlayer insulating layer 122 and the second insulating layer 322. The first connection electrode 330 may be formed along the side surface of the second insulating layer 322.

[0128] The second bank 326 may be disposed on the first insulating layer 320 .

[0129] Reference Fig.11 , the light emitted from the light emitting diode 300 may include: top directional light 11a, reflected top directional light 11a', side directional lights 11b and 11b', and reflected side directional lights 11c and 11c'.

[0130] The top directional light 11a may be light output from the light emitting diode 300 in an upward direction to the top of the display device. The reflected top directional light 11a' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output to the top of the display device in an upward direction. The side directional lights 11b and 11b' may be light output from the light emitting diode 300 in an upper left direction and an upper right direction, respectively. The reflected side directional lights 11c and 11c' may be light output from the light emitting diode 300 in a downward direction, then reflected from the reflective layer 310, and output in an upper left direction and an upper right direction, respectively, and then may be absorbed by the second bank 326.

[0131] Fig.12 According to another embodiment of the present disclosure Fig.11 An enlarged cross-sectional view of part B.

[0132] Reference Fig.12 The second bank 326 may be disposed between an end of the upper surface SS1 of the light emitting diode 300 and an end of the lower surface BS of the light emitting diode 300. For example, an upper end of the second bank 326 may be disposed between an end of the upper surface SS1 of the light emitting diode 300 and an end of the lower surface BS of the light emitting diode 300.

[0133] Reference Fig.12 , a distance between an upper end portion of one side of the second bank 326 and an end portion of one side of the upper surface SS1 of the light emitting diode 300 may be smaller than a distance between an upper end portion of one side of the second bank 326 and an end portion of one side of the lower surface BS of the light emitting diode 300. An upper end portion of a portion of the second bank 326 adjacent to one side of the light emitting diode 300 may be located at a higher vertical height than a vertical height of an upper end portion of a portion of the second bank 326 adjacent to the other side of the light emitting diode 300.

[0134] The second bank 326 may include an inclined surface PS and a flat surface FS. The interval between the inclined surface PS of the second bank 326 and the side surface of the light emitting diode 300 may vary as the inclined surface PS of the second bank 326 extends from the upper end to the lower end of the inclined surface PS of the second bank 326. For example, the interval between the inclined surface PS of the second bank 326 and the side surface of the light emitting diode 300 may increase as the inclined surface PS of the second bank 326 extends from the upper end to the lower end of the inclined surface PS of the second bank 326.

[0135] Therefore, the reflected side directional light beams 11c and 11c' in the light beam emitted from the light emitting diode 300 can be absorbed by the inclined surface PS of the second bank 326, and thus the brightness difference or deviation according to the viewing angle can be reduced. For example, the reflected side directional light beams 11c and 11c' in the light beam emitted from the light emitting diode 300 can propagate downward and then be reflected from the reflective layer 310, and can propagate upward on the left or right side, and then can be absorbed by the inclined surface PS of the second bank 326, and thus the brightness difference or deviation according to the viewing angle can be reduced.

[0136] According to one embodiment of the present disclosure, the flat surface FS of the second bank 326 may overlap the first bank 324 in a vertical direction. A first width L1 of the first bank 324 overlapping the flat surface FS of a portion of the second bank 326 disposed on one side of the light emitting diode 300 may be equal to or different from a second width L2 of the first bank 324 overlapping the flat surface FS of a portion of the second bank 326 disposed on the other side of the light emitting diode 300.

[0137] According to one embodiment of the present disclosure, a width (or length) of the inclined surface PS on one side of the second bank 326 and a width (or length) of the inclined surface PS on the other side of the second bank 326 may be different from each other.

[0138] For example, when the second bank 326 is disposed on the top of the light emitting diode 300, a defect may occur when the diode is connected to the second connection electrode 322, or a contact defect between the diode and the pad electrode may occur. Therefore, according to an embodiment of the present disclosure, the second bank 326 is not disposed on the top of the light emitting diode 300. Therefore, a defect may not occur when the diode is connected to the second connection electrode 322, and / or a contact defect between the diode and the pad electrode may be suppressed.

[0139] Figures 13 to 15 is a graph showing the brightness based on the viewing angle of the display device according to the embodiment of the present disclosure. For example, Figures 13 to 15 are shown based on Figure 8 , Fig.10 and Fig.11 The curve diagram of the brightness simulation result of the display device with respect to the viewing angle is shown in FIG. Figures 13 to 15 , assuming that the brightness of the light in the forward direction at a 0-degree viewing angle is 100%. The brightness of the light at a 60-degree viewing angle can be compared with the 100% brightness of the light in the forward direction at a 0-degree viewing angle. Therefore, the brightness deviation between the brightness of the light at a 60-degree viewing angle and the 100% brightness of the light in the forward direction at a 0-degree viewing angle can be obtained.

[0140] Reference Fig.13, the brightness deviation between the brightness of the light at a viewing angle of 60 degrees and the 100% brightness of the light in the forward direction at a viewing angle of 0 degrees is 35%.

[0141] Reference Fig.14 , the brightness deviation between the brightness of the light at a 60-degree viewing angle and the 100% brightness of the light in the forward direction at a 0-degree viewing angle is 10%. Figure 8 Compared with the display device, Fig.10 The display device in may have a reduced brightness deviation between the brightness of light at a viewing angle of 60 degrees and 100% brightness of light in a forward direction at a viewing angle of 0 degrees.

[0142] Reference Fig.15 , the brightness deviation between the brightness of the light at a 60-degree viewing angle and the 100% brightness of the light in the forward direction at a 0-degree viewing angle is 5%. Fig.10 Compared with the display device, Fig.11 The display device in may have a reduced brightness deviation between the brightness of light at a viewing angle of 60 degrees and 100% brightness of light in a forward direction at a viewing angle of 0 degrees.

[0143] According to one embodiment of the present disclosure, a bank may be provided around a light emitting diode so that a brightness deviation according to a viewing angle of a display device may be reduced.

[0144] A display device according to various aspects and embodiments of the present disclosure may be described as follows.

[0145] One aspect of the present disclosure provides a display device including: a substrate including pixels; a light emitting diode disposed in the pixel; a first insulating layer disposed around the light emitting diode; a second insulating layer disposed on the first insulating layer; and a first dam disposed around the second insulating layer.

[0146] According to some embodiments of the display device of the present disclosure, the display device further includes: a thin film transistor disposed on the substrate, wherein the first bank covers at least a portion of the thin film transistor.

[0147] According to some embodiments of the display device of the present disclosure, the display device further includes: a connection electrode disposed on the first insulating layer; and a second bank disposed on the connection electrode.

[0148] According to some embodiments of the display device of the present disclosure, the display device further includes: a reflective layer disposed below the light emitting diode.

[0149] According to some embodiments of the display device of the present disclosure, the display device further includes a hole defined in the second insulating layer, wherein the second bank is disposed in the hole.

[0150] According to some embodiments of the display device of the present disclosure, the display device further includes: a hole extending through a portion of the first insulating layer, wherein the second bank is disposed in the hole.

[0151] According to some embodiments of the display device of the present disclosure, a vertical height of a top surface of the first bank is lower than a vertical height of a top surface of the light emitting diode.

[0152] According to some embodiments of the display device of the present disclosure, the second bank is located at a side of the light emitting diode.

[0153] According to some embodiments of the display device of the present disclosure, the display device further includes: a connection electrode disposed on the first insulating layer, wherein the first bank is disposed on the connection electrode.

[0154] According to some embodiments of the display device of the present disclosure, the display device further includes: a thin film transistor disposed on the substrate, wherein the first bank covers the thin film transistor.

[0155] According to some embodiments of the display device of the present disclosure, the display device further includes: a second bank disposed below the light emitting diode, wherein the first bank overlaps two opposite ends of the second bank in an up-and-down direction.

[0156] According to some embodiments of the display device of the present disclosure, the second bank extends to the outside of the light emitting diode.

[0157] According to some embodiments of the display device of the present disclosure, the display device further includes: a second bank disposed on the first insulating layer, wherein the second bank is disposed on a portion of a side surface of the light emitting diode.

[0158] According to some embodiments of the display device of the present disclosure, the first bank overlaps with a side end portion of the second bank in the up-down direction.

[0159] According to some embodiments of the display device of the present disclosure, an upper end portion of the second bank is disposed between an end portion of an upper surface of the light emitting diode and an end portion of a lower surface of the light emitting diode.

[0160] According to some embodiments of the display device of the present disclosure, a gap between an upper end of the second bank and an end of an upper surface of the LED is smaller than a gap between an upper end of the second bank and an end of a lower surface of the LED.

[0161] According to some embodiments of the display device of the present disclosure, a vertical height of an upper end portion of the second bank adjacent to one side of the LED is higher than a vertical height of an upper end portion of the second bank adjacent to the other side of the LED.

[0162] According to some embodiments of the display device of the present disclosure, the display device further includes: a connection electrode disposed on the first insulating layer, wherein a side surface of the light emitting diode contacts the first insulating layer, the second bank and the connection electrode.

[0163] According to some embodiments of the display device of the present disclosure, the second bank includes an inclined surface and a flat surface connected to each other, wherein a horizontal interval between the inclined surface and a side surface of the light emitting diode varies as the inclined surface extends from an upper end to a lower end thereof.

[0164] According to some embodiments of the display device of the present disclosure, the first bank is disposed on the second insulating layer, wherein the second bank is disposed on the first insulating layer.

[0165] According to some embodiments of the display device of the present disclosure, the display device further includes: a reflective layer disposed below the light emitting diode.

[0166] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above embodiments are not restrictive in all aspects, but illustrative.

Claims

1. A display device, comprising: a substrate, the substrate comprising pixels; a light emitting diode, wherein the light emitting diode is arranged in the pixel; a first insulating layer, wherein the first insulating layer is disposed around the light emitting diode; a second insulating layer, the second insulating layer being disposed on the first insulating layer; as well as A first bank is disposed around the second insulating layer.

2. The display device according to claim 1, wherein: The display device further includes a thin film transistor disposed on the substrate. Wherein, the first embankment covers at least a portion of the thin film transistor.

3. The display device according to claim 1, wherein: The display device further includes: a connecting electrode, the connecting electrode being disposed on the first insulating layer; and A second bank is provided on the connection electrode.

4. The display device according to claim 1, wherein: The display device further includes a reflective layer disposed below the light emitting diode.

5. The display device according to claim 3, wherein: The display device further includes a hole defined in the second insulating layer, Wherein, the second dam is arranged in the hole.

6. The display device according to claim 3, wherein: The display device further includes a hole extending through the second insulating layer and extending through a portion of the first insulating layer, Wherein, the second dam is arranged in the hole.

7. The display device according to claim 1, wherein: A vertical height of a top surface of the first bank is lower than a vertical height of a top surface of the light emitting diode.

8. The display device according to claim 3, wherein: The second bank is located on a side of the light emitting diode.

9. The display device according to claim 1, wherein: The display device further includes a connecting electrode disposed on the first insulating layer. Wherein, the first embankment is arranged on the connecting electrode.

10. The display device according to claim 9, wherein: The display device further includes a thin film transistor disposed on the substrate. Wherein, the first embankment covers the thin film transistor.

11. The display device according to claim 9, wherein: The display device further includes a second bank disposed below the light emitting diode, The first bank overlaps with two opposite ends of the second bank in the up-down direction.

12. The display device according to claim 11, wherein: The second bank extends to the outside of the light emitting diode.

13. The display device according to claim 1, wherein: The display device further includes a second bank disposed on the first insulating layer, Wherein, the second bank is arranged on a portion of a side surface of the light emitting diode.

14. The display device according to claim 13, wherein: The first bank overlaps with a side end portion of the second bank in a vertical direction.

15. The display device according to claim 13, wherein: An upper end portion of the second bank is disposed between an end portion of an upper surface of the light emitting diode and an end portion of a lower surface of the light emitting diode.

16. The display device according to claim 13, wherein: A distance between an upper end portion of the second bank and an end portion of an upper surface of the light emitting diode is smaller than a distance between an upper end portion of the second bank and an end portion of a lower surface of the light emitting diode.

17. The display device according to claim 13, wherein: A vertical height of an upper end portion of a portion of the second bank adjacent to one side of the light emitting diode is higher than a vertical height of an upper end portion of a portion of the second bank adjacent to the other side of the light emitting diode.

18. The display device according to claim 13, wherein: The display device further includes a connecting electrode disposed on the first insulating layer. The side surface of the light emitting diode is in contact with the first insulating layer, the second bank and the connecting electrode.

19. The display device according to claim 13, wherein: The second bank includes an inclined surface and a flat surface connected to each other, The horizontal interval between the inclined surface and the side surface of the light emitting diode varies as the inclined surface extends from the upper end to the lower end thereof.

20. The display device according to claim 13, wherein: The first bank is disposed on the second insulating layer, Wherein, the second bank is arranged on the first insulating layer.

21. The display device according to claim 13, wherein: The display device further includes a reflective layer disposed below the light emitting diode.

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