Display device having moisture barrier structure and method for manufacturing display device

Abstract

Embodiments of the present disclosure disclose a display device having a moisture barrier structure and a method for manufacturing the display device. The display device includes a first thin film transistor on a substrate, an isolation layer disposed on the first thin film transistor and including an organic material, an inorganic insulating layer on the isolation layer, a buffer layer on the inorganic insulating layer, a second thin film transistor on the buffer layer, and a display element connected to any one of the first thin film transistor and the second thin film transistor, in which the isolation layer has a recess having an opening in a direction toward the inorganic insulating layer, and the inorganic insulating layer is not disposed in the opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to Korean Patent Application No. 10-2023-0134199, filed on October 10, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device having a moisture barrier structure and which can effectively block moisture penetration, and a method of manufacturing the display device. Background Art

[0004] Recently, flat panel display devices or flexible display devices are widely used as display devices. Among display devices, organic light-emitting display devices, which are self-luminous display devices, have the advantages of wide viewing angle, excellent contrast characteristics, and fast response characteristics. In addition, organic light-emitting display devices have the advantage of being easy to use as flexible display devices.

[0005] An organic light emitting display device includes a plurality of organic light emitting diodes. The organic light emitting diode includes an anode electrode, a light emitting layer, and a cathode electrode. When a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, holes from the anode electrode and electrons from the cathode electrode move to the light emitting layer, respectively. When holes and electrons combine in the light emitting layer, excitons are formed during the excitation process, and light is generated due to the energy from the excitons. The organic light emitting display device displays an image by electrically controlling the amount of light generated from the light emitting layers of the plurality of organic light emitting diodes.

[0006] Organic light-emitting display devices have various advantages, but have the disadvantage of being susceptible to moisture and oxygen. In order to solve this problem, methods for blocking moisture and oxygen from penetrating from the outside into the organic light-emitting display device are being studied. In particular, when the through hole is located inside the display area, moisture and oxygen can easily penetrate through the through hole, and therefore, it is necessary to block moisture and oxygen from penetrating from around the through hole into the organic light-emitting display device. Summary of the invention

[0007] The present disclosure has been made in view of the above-mentioned problems, and an aspect of an embodiment of the present disclosure is to provide a display device which has a moisture barrier structure and can effectively block moisture penetration.

[0008] An aspect of another embodiment of the present disclosure is to provide a display device that can effectively block moisture penetration by having a moisture barrier structure provided around a through hole even if a through hole for placing various components such as a camera module or an optical sensor is provided in a display region.

[0009] An aspect of another embodiment of the present disclosure is to provide a display device that can effectively block moisture penetration by having a moisture barrier structure provided at an edge of a display panel.

[0010] An aspect of another embodiment of the present disclosure is to provide a method of manufacturing a display device having a moisture barrier structure.

[0011] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a display device, which includes a first thin film transistor on a substrate, an isolation layer arranged on the first thin film transistor and including an organic material, an inorganic insulating layer on the isolation layer, a buffer layer on the inorganic insulating layer, a second thin film transistor on the buffer layer, and a display element connected to any one of the first thin film transistor and the second thin film transistor, wherein the isolation layer has a recess, and wherein the recess has an opening in a direction toward the inorganic insulating layer, and the inorganic insulating layer is not arranged in the opening.

[0012] The isolation layer may have a higher etching rate than the inorganic insulating layer.

[0013] The width of the concave portion may be greater than the width of the opening. Here, the width of the concave portion is a width measured at a middle height of the concave portion, and the width of the opening is a width measured at a bottom of the inorganic insulating layer.

[0014] The width of the recess may be at least twice the width of the opening.

[0015] The isolation layer may have two or more recesses.

[0016] The buffer layer may be disposed on a sidewall of the recess.

[0017] The display element may include an organic light emitting layer, and wherein the organic light emitting layer loses continuity in the concave portion.

[0018] The isolation layer may have a thickness of 1 μm to 4 μm.

[0019] The substrate may have a through hole.

[0020] The display device may further include an optical element disposed overlapping the through hole formed in the substrate. The first thin film transistor, the second thin film transistor, and the display element are not disposed in the through hole, and wherein the recess surrounds the through hole.

[0021] The optical element may include at least one of a camera, an infrared sensor, a proximity sensor, an illumination sensor, and a fingerprint sensor.

[0022] The display device may further include an encapsulation layer on the display element, wherein the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, wherein the first inorganic encapsulation layer is disposed on a buffer layer disposed on a side wall of the recess.

[0023] The recess may be provided along an edge of the substrate.

[0024] Another embodiment of the present disclosure provides a method for manufacturing a display device, including: forming a first thin film transistor on a substrate, forming an isolation layer including an organic material on the first thin film transistor, forming an inorganic insulating layer on the isolation layer, removing a portion of the inorganic insulating layer and a portion of the isolation layer to form a hole passing through the inorganic insulating layer and the isolation layer, expanding the hole formed in the isolation layer to form a recess in the isolation layer, forming a buffer layer on the inorganic insulating layer, forming a second thin film transistor on the buffer layer, and forming a display element connected to any one of the first thin film transistor and the second thin film transistor.

[0025] The etching rate of the isolation layer may be greater than the etching rate of the inorganic insulating layer.

[0026] Forming a hole passing through the inorganic insulating layer and the isolation layer may further include forming a contact hole connecting the first thin film transistor and the second thin film transistor.

[0027] The method of manufacturing a display device may further include forming a first bridge electrode on the inorganic insulating layer, wherein the first bridge electrode is connected to the first thin film transistor through a contact hole.

[0028] When forming the buffer layer, the buffer layer forming material may be disposed on the sidewall of the recess.

[0029] Forming the display element may include forming an organic light emitting layer, and wherein the organic light emitting layer loses continuity in the concave portion.

[0030] A hole may be formed along the edge of the substrate through the inorganic insulating layer and the isolation layer so that a recess is formed along the edge of the substrate.

[0031] Technical effects of the present disclosure

[0032] According to an embodiment of the present disclosure, a display panel of a display device is provided with a moisture barrier structure to prevent moisture or oxygen from entering the display panel from the outside. Therefore, display elements, especially organic light-emitting elements, provided on the display panel can be protected from moisture or oxygen.

[0033] Meanwhile, among the components of the organic light-emitting device, the organic light-emitting layer is very susceptible to moisture or oxygen. Therefore, according to an embodiment of the present disclosure, when the display panel of the display device is provided with a moisture barrier structure, moisture or oxygen from the outside is prevented from flowing into the display panel, thereby protecting the organic light-emitting layer of the organic light-emitting device from moisture or oxygen. Therefore, the life of the organic light-emitting device can be extended, and thus the life of the display panel can also be extended.

[0034] According to another embodiment of the present disclosure, even if a through hole for arranging various components or optical elements such as a camera module or an optical sensor is provided in the display area, a moisture barrier structure is provided around the through hole so that external moisture or oxygen can be prevented from flowing into the display panel of the display device.

[0035] In addition, according to another embodiment of the present disclosure, a moisture barrier structure is provided at an edge of a display panel to prevent moisture or oxygen from entering the display panel of a display device from the outside.

[0036] In addition to the above-mentioned effects, other features and advantages of the present disclosure are described below and those skilled in the art can clearly understand the other features and advantages of the present disclosure from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application, illustrate embodiments of the present disclosure and are used together with the specification to illustrate the principles of the present disclosure. The above and other purposes, features and other advantages of the present disclosure will be more clearly understood according to the detailed description below in conjunction with the accompanying drawings.

[0038] Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0039] Figure 2 yes Figure 1 Circuit diagram of a pixel.

[0040] Figure 3 is a schematic diagram of an embodiment of a display panel.

[0041] Figure 4 yes Figure 3 An enlarged plan view of the portion indicated by HA in FIG.

[0042] Figure 5 It is along Figure 4 Cross-sectional view along line II′.

[0043] Figure 6 yes Figure 5 A partial enlarged view of the dam part and the concave part.

[0044] Figure 7 is a partial cross-sectional view of a display device according to another embodiment of the present disclosure.

[0045] Figure 8 is a schematic diagram of a display panel of a display device according to another embodiment of the present disclosure.

[0046] Fig. 9 It is along Figure 8 Cross-sectional view along line II-II′.

[0047] Fig.10 is a circuit diagram of a pixel of a display device according to another embodiment of the present disclosure.

[0048] Fig.11 is a circuit diagram of a pixel of a display device according to another embodiment of the present disclosure.

[0049] FIG. 12A to FIG. 12G is a schematic diagram of a manufacturing process of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The advantages and features of the present disclosure and methods for implementing the same will be illustrated by the embodiments described below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully illustrate the present disclosure to those skilled in the art.

[0051] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings used to describe the embodiments of the present disclosure are examples only, and therefore, the present disclosure is not limited to the details shown. Throughout the specification, similar reference numerals refer to similar elements. In the following description, when the detailed description of the relevant known functions or configurations is determined to be unnecessary to obscure the focus of the present disclosure, the detailed description will be omitted.

[0052] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may be added unless “only” is used. Unless mentioned otherwise, a term in the singular form may include a plural form.

[0053] In interpreting an element, although not explicitly described, the element is interpreted to include an error range.

[0054] When describing a positional relationship, for example, when the positional relationship is described as "on", "above", "below", and "beside", unless "just" or "directly" is used, one or more parts may be arranged between two other parts.

[0055] Spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to easily describe the relationship of one or more elements to another one or more elements as shown in the accompanying drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device shown in the accompanying drawings is reversed, a device described as being disposed "below" or "under" another device may be disposed "above" the other device. Thus, the exemplary term "below or below" may include both "below or below" and "above" orientations. Similarly, the exemplary term "above" or "upper" may include both "above" and "below or below" orientations.

[0056] When describing a time relationship, for example, when a time sequence is described as "after," "afterwards," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0057] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present invention.

[0058] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first, second, and third items" means all combinations of items listed from two or more of the first, second, and third items as well as the first, second, or third item.

[0059] As those skilled in the art can fully understand, the features of various embodiments of the present disclosure can be coupled or combined with each other in part or in whole, and can interoperate with each other and be technically driven in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0060] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

[0061] Hereinafter, examples or embodiments of the present disclosure will be described with reference to the accompanying drawings. For ease of description, the scale of components shown in the drawings may be different from the actual scale, and therefore are not limited to the scale shown in the drawings.

[0062] Figure 1 is a schematic diagram of a display device 100 according to an embodiment of the present disclosure.

[0063] like Figure 1 As shown in , the display device 100 according to an embodiment of the present disclosure may include a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0064] The gate lines GL and the data lines DL are disposed in the display panel 310 , and pixels P are disposed at intersections of the gate lines GL and the data lines DL. By driving the pixels P, an image is displayed.

[0065] The controller 340 controls the gate driver 320 and the data driver 330 .

[0066] The controller 340 generates a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using, for example, a signal supplied from an external system (not shown). In addition, the controller 340 samples the input image data input from the external system, rearranges it, and supplies the rearranged digital image data RGB to the data driver 330.

[0067] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, the gate control signal GCS may include a control signal for controlling the shift register 350.

[0068] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0069] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. In detail, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0070] The gate driver 320 may include a shift register 350 .

[0071] The shift register 350 sequentially supplies gate pulses to the gate lines GL within one frame using a start signal and a gate clock transmitted from the controller 340. In this case, one frame means a period during which one image is output through the display panel 310. The gate pulse has a turn-on voltage that can turn on a switching element (thin film transistor) provided in the pixel P.

[0072] In addition, the shift register 350 supplies a gate-off signal that turns off the switching element to the gate line GL during the remaining period of one frame when no gate pulse is supplied. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal (SS or Scan).

[0073] According to an embodiment of the present disclosure, the gate driver 320 may be installed in the display panel 310. As such, a structure in which the gate driver 320 is directly installed in the display panel 310 is referred to as a gate-in-panel (GIP) structure.

[0074] The gate driver 320 may include a plurality of thin film transistors. The plurality of thin film transistors may be provided in the shift register 350.

[0075] Figure 2 yes Figure 1 Circuit diagram of pixel P.

[0076] Figure 2 The circuit diagram of FIG. 1 is an equivalent circuit diagram of a pixel P of the display device 100 including an organic light emitting diode OLED as a display element 710. The pixel P includes the display element 710 and a pixel driving circuit PDC driving the display element 710.

[0077] Reference Figure 2 , the display device 100 according to an embodiment of the present disclosure includes a pixel driving circuit PDC and a display element 710 connected to the pixel driving circuit PDC. The pixel driving circuit PDC may include a first thin film transistor TR1 and a second thin film transistor TR2.

[0078] Figure 2 A pixel driving circuit PDC is shown in which the first thin film transistor TR1 is a switching transistor and the second thin film transistor TR2 is a driving transistor.

[0079] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

[0080] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0081] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the second thin film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED as the display element 710 .

[0082] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied from the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2. Figure 2 The capacitor C1 is a storage capacitor formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0083] Reference Figure 2 , the gate electrode of the second thin film transistor TR2 is connected to the drain electrode of the first thin film transistor TR1. Therefore, Figure 2 The capacitor C1 may be referred to as being formed between the drain electrode of the first thin film transistor TR1 and the source electrode of the second thin film transistor TR2.

[0084] The amount of current supplied to the organic light emitting diode OLED as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray level of light emitted from the display element 710 may be controlled.

[0085] Figure 3 is a schematic diagram of an embodiment of a display panel 310 . Figure 3 A display panel 310 applied to the display device 100 is shown, for example, an organic light emitting panel. Figure 1 The display device 100 including the organic light emitting panel as the display panel 310 may be referred to as an organic light emitting display device.

[0086] Reference Figure 3 , the display panel 310 includes a substrate 110 and pixels P on the substrate 110 .

[0087] A glass substrate or a plastic substrate may be used as the substrate 110. The substrate 110 may include a display area AA and a non-display area IA.

[0088] The display area AA is an area where an image is displayed, and may be referred to as a pixel array area, an active area, a pixel array unit, a display area, or a screen. The display area AA includes pixels P. A plurality of pixels P may be arranged in the display area AA.

[0089] A plurality of pixels P may be arranged along each of a first direction and a second direction intersecting the first direction. For example, the first direction may be referred to as a first longitudinal direction or a horizontal direction of the substrate 110. The second direction may be referred to as a second longitudinal direction or a vertical direction of the substrate 110.

[0090] The pixel P can be said to be a unit area that actually emits light.

[0091] The non-display area IA is an area where no image is displayed. For example, the non-display area IA may be arranged around the display area AA. The non-display area IA may be configured to surround the display area AA.

[0092] The non-display area IA may include at least one of a peripheral circuit area, a signal supply area, a non-active area, and a frame area. The non-display area IA may be referred to as, for example, a peripheral area, a peripheral circuit area, a signal supply area, a non-active area, or a frame area.

[0093] The display panel 310 may further include a peripheral circuit portion disposed in the non-display area IA. The peripheral circuit portion may include a gate driver 320 connected to the plurality of pixels P. Figure 1 and Figure 3 A configuration in which the gate driver 320 is provided on the substrate 110 as a peripheral circuit portion is shown.

[0094] Figure 4 yes Figure 3 An enlarged plan view of the portion indicated by HA in FIG.

[0095] Figure 4 1 is an enlarged plan view illustrating a through hole TH and a surrounding area thereof provided in the display area AA of the display device 100 according to an embodiment of the present disclosure.

[0096] According to the embodiments of the present disclosure, Figure 4 As shown in FIG. 1 , the through hole TH may be disposed in the display area AA. The pixel P may be disposed around the through hole TH. Figure 4 As indicated in , among the pixels P, a series of pixels P arranged closest to the through hole TH may be defined as a neighboring pixel P′. A region between the neighboring pixel P′ and the through hole TH may be defined as a hole boundary portion THB.

[0097] According to an embodiment of the present disclosure, the moisture barrier structure is provided at the hole boundary portion THB. Therefore, according to an embodiment of the present disclosure, the hole boundary portion THB may be referred to as a moisture barrier region.

[0098] The dam portions DM1 , DM2 and the recesses RE1 , RE2 may be provided at the hole boundary portion THB.

[0099] The dam portions DM1 and DM2 may include a first dam DM1 and a second dam DM2. Figure 4 , the first dam DM1 and the second dam DM2 may be disposed between the through hole TH and the adjacent pixel P′.

[0100] The first dam DM1 may have a closed curved shape surrounding the through hole TH. The first dam DM1 may have a closed curved shape corresponding to the shape of the through hole TH, but may also have a closed curved shape different from the shape of the through hole TH. Figure 4 In FIG. 5 , for example, the first dam DM1 is shown to have a closed curved shape having the same shape as the through hole TH and having a different size. Figure 4 , the first dam DM1 and the through hole TH have a concentric circle shape, and a region of the through hole TH may be defined by the first dam DM1. According to an embodiment of the present disclosure, a sidewall of the through hole TH defining the region of the through hole TH may be the first dam DM1.

[0101] According to an embodiment of the present disclosure, the second dam DM2 may be disposed between the first dam DM1 and the adjacent pixel P′.

[0102] The second dam DM2 is spaced apart from the first dam DM1 and may have a closed curved shape surrounding the first dam DM1. The second dam DM2 may have a closed curved shape corresponding to the shape of the first dam DM1, but may also have a closed curved shape different from the shape of the through hole TH. Figure 4 , the second dam DM2 and the first dam DM1 may have concentric circle shapes.

[0103] The recesses RE1, RE2 may be disposed between the through hole TH and the adjacent pixel P'. The recesses RE1, RE2 may have a closed curved shape corresponding to the shape of the through hole TH and surround the through hole TH. The recesses RE1, RE2 may have a closed curved shape different from the shape of the through hole TH, or may have the same closed curved shape but different sizes.

[0104] The recesses RE1, RE2 may include a first recess RE1 and a second recess RE2. Reference Figure 4 , the first recess RE1 and the second recess RE2 may be disposed between the through hole TH and the adjacent pixel P′.

[0105] According to an embodiment of the present disclosure, the first recess RE1 may be disposed between the first dam DM1 and the adjacent pixel P′. In more detail, the first recess RE1 may be disposed between the first dam DM1 and the second dam DM2.

[0106] According to an embodiment of the present disclosure, the second recess RE2 may be disposed between the second dam DM2 and the adjacent pixel P′.

[0107] The first recess RE1 and the second recess RE2 have concentric circle shapes and may be arranged to be spaced apart from each other. The first recess RE1 and the second recess RE2 may be spaced apart from each other with the second dam DM2 therebetween.

[0108] According to the embodiments of the present disclosure, Figure 4 As shown in FIG, the first dam DM1, the first recess RE1, the second dam DM2, and the second recess RE2 are sequentially arranged.

[0109] Figure 5 It is along Figure 4 Cross-sectional view along line II′.

[0110] Reference Figure 5 , the display device 100 according to an embodiment of the present disclosure includes a substrate 110 , a first buffer layer 120 , a first thin film transistor TR1 , an isolation layer 180 , an inorganic insulating layer 210 , a second thin film transistor TR2 , and a display element 710 .

[0111] In detail, the display device 100 according to an embodiment of the present disclosure includes a first thin film transistor TR1 on a substrate 110, an isolation layer 180 on the first thin film transistor TR1, an inorganic insulating layer 210 on the isolation layer 180, a second thin film transistor TR2 on the inorganic insulating layer 210, and a display element 710 connected to one of the first thin film transistor TR1 and the second thin film transistor TR2.

[0112] The substrate 110 may include a display area AA and a non-display area IA surrounding the display area AA. The substrate 110 is a base layer and may include a plastic material or a glass material. As a plastic substrate, for example, a transparent or colored polyimide substrate may be used. The substrate 110 may be a flexible substrate or a rigid substrate.

[0113] The first buffer layer 120 may be disposed on the substrate 110. The first buffer layer 120 may be arranged to cover the entire surface of the substrate 110. The first buffer layer 120 may be used to block moisture or oxygen. For example, the first buffer layer 120 may include a single inorganic layer or a plurality of stacked inorganic layers. For example, the first buffer layer 120 may include at least one of a silicon oxide SiOx layer, a silicon nitride SiNx layer, and a silicon oxynitride SiON layer.

[0114] The first buffer layer 120 may also be referred to as a lower buffer layer. In some embodiments, the first buffer layer 120 may be omitted.

[0115] The first thin film transistor TR1 may be disposed on the first buffer layer 120 .

[0116] The first thin film transistor TR1 includes a semiconductor layer A1, a gate electrode G1, a source electrode S1, and a drain electrode D1 disposed on the substrate 110 or the first buffer layer 120. A gate insulating layer 140 may be disposed between the semiconductor layer A1 and the gate electrode G1.

[0117] exist Figure 5 , a thin film transistor having a top gate structure in which the gate electrode G1 is disposed on the top of the semiconductor layer A1 is shown, but the embodiments of the present disclosure are not limited thereto. As another example, the first thin film transistor TR1 may have a bottom gate structure in which the gate electrode G1 is disposed below the semiconductor layer A1 or a double gate structure in which the gate electrode G1 is disposed both on the top of the semiconductor layer A1 and below the semiconductor layer A1.

[0118] The semiconductor layer A1 may be disposed on the substrate 110 or on the first buffer layer 120. The semiconductor layer A1 may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic-based semiconductor material, and may have a single-layer structure or a multi-layer structure. A light shielding layer may be additionally disposed between the first buffer layer 120 and the substrate 110 to block external light from being incident on the semiconductor layer A1.

[0119] The gate insulating layer 140 insulates the semiconductor layer A1 from the gate electrode G1. The gate insulating layer 140 may be disposed on the entire surface of the substrate 110 to cover the semiconductor layer A1, or may be disposed only in a region where the semiconductor layer A1 and the gate electrode G1 overlap.

[0120] The gate insulating layer 140 may include, for example, at least one of a silicon oxide SiOx layer and a silicon nitride SiNx layer, or may have a multi-layer structure including both the silicon oxide SiOx layer and the silicon nitride SiNx layer.

[0121] The gate electrode G1 is disposed on the gate insulating layer 140 to overlap at least a portion of the semiconductor layer A1. The gate electrode G1 may be formed together with the gate line GL. According to an embodiment of the present disclosure, the gate electrode G1 may include at least one of molybdenum Mo, aluminum Al, chromium Cr, gold Au, titanium Ti, nickel Ni, neodymium Nd, and copper Cu. The gate electrode G1 may have a single-layer structure or a multi-layer structure.

[0122] An interlayer insulating layer 150 may be disposed on the gate electrode G1 . The interlayer insulating layer 150 may be formed on the entire surface of the substrate 110 to cover the gate electrode G1 and the gate insulating layer 140 .

[0123] The source electrode S1 and the drain electrode D1 may be disposed on the interlayer insulating layer 150. For example, the source electrode S1 and the drain electrode D1 may be formed together with the data line DL or the driving power line PL.

[0124] Each of the source electrode S1 and the drain electrode D1 may be connected to the semiconductor layer A1 through an electrode contact hole penetrating the interlayer insulating layer 150 and the gate insulating layer 140. The source electrode S1 and the drain electrode D1 may include at least one of molybdenum Mo, aluminum Al, chromium Cr, gold Au, titanium Ti, nickel Ni, neodymium Nd, and copper Cu.

[0125] As described above, the first thin film transistor TR1 included in the pixel driving circuit PDC may be disposed on the substrate 110. In addition, the gate driver 320 disposed on the substrate 110 may include a thin film transistor that is the same as or similar to the first thin film transistor TR1 disposed in the pixel P.

[0126] The isolation layer 180 is disposed on the first thin film transistor TR1 .

[0127] The isolation layer 180 may be disposed, for example, on the entire surface of the substrate 110 to cover the first thin film transistor TR1. The isolation layer 180 provides a flat surface over the first thin film transistor TR1. In addition, the isolation layer 180 serves to isolate the first thin film transistor TR1 and the second thin film transistor TR2 from each other.

[0128] The isolation layer 180 may include an organic material. For example, the isolation layer 180 may be an organic layer including an organic material. The isolation layer 180 may be made of an organic material. According to an embodiment of the present disclosure, the isolation layer 180 may be referred to as an organic isolation layer.

[0129] According to an embodiment of the present disclosure, the isolation layer 180 may include at least one of acrylic resin, epoxy resin, phenolic resin, polyurethane resin, polyamide resin, polycarbonate resin, and polyimide resin.

[0130] In order to sufficiently space the first thin film transistor TR1 and the second thin film transistor TR2 to obtain electrical stability and to sufficiently flatten the surface above the first thin film transistor TR1, the isolation layer 180 has a thickness of 1 μm to 4 μm. When the isolation layer 180 has a thickness of 1 μm or more, the first thin film transistor TR1 and the second thin film transistor TR2 are sufficiently spaced apart to ensure electrical stability from each other. In addition, when the isolation layer 180 has a thickness of 4 μm or less, the display device 100 can be prevented from becoming thicker than necessary.

[0131] In detail, the isolation layer 180 may have a thickness of 1 μm to 3 μm, and may also have a thickness of 1.5 μm to 2.5 μm.

[0132] According to an embodiment of the present disclosure, a portion of the isolation layer 180 is removed to form the recesses RE1, RE2. The structure and method of forming the recesses RE1, RE2 will be described later.

[0133] The inorganic insulating layer 210 may be disposed on the isolation layer 180 . The inorganic insulating layer 210 protects an upper portion of the isolation layer 180 .

[0134] The inorganic insulating layer 210 includes an inorganic material. For example, the inorganic insulating layer 210 may include at least one of silicon oxide, aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, and tantalum nitride.

[0135] The inorganic insulating layer 210 has an etching rate different from that of the isolation layer 180. According to an embodiment of the present disclosure, the etching rate of the isolation layer 180 is greater than that of the inorganic insulating layer 210. In detail, in the dry etching condition, the etching rate of the isolation layer 180 is greater than that of the inorganic insulating layer 210. In addition, with respect to an etching solution for etching an organic material, the etching rate of the isolation layer 180 is greater than that of the inorganic insulating layer 210.

[0136] According to an embodiment of the present disclosure, the etching rate of the isolation layer 180 is designed to be greater than that of the inorganic insulating layer 210. Since the etching rate of the isolation layer 180 is greater than that of the inorganic insulating layer 210, pot-shaped recesses RE1, RE2 may be formed.

[0137] According to an embodiment of the present disclosure, the recesses RE1, RE2 and the dam portions DM1, DM2 may be formed after patterning the inorganic insulating layer 210 and the isolation layer 180 and then additionally etching or over-etching the patterned isolation layer 180. The structure and manufacturing method of the dam portions DM1, DM2 will be described later.

[0138] Reference Figure 5 , a contact hole CH1 penetrating the inorganic insulating layer 210 and the isolation layer 180 may be formed. The contact hole CH1 may be formed by patterning the inorganic insulating layer 210 and the isolation layer 180 .

[0139] A first bridge electrode BR1 may be formed on the inorganic insulating layer 210. The first bridge electrode BR1 may be connected to the first thin film transistor TR1 through a contact hole CH1. In detail, the first bridge electrode BR1 may be connected to the drain electrode D1 of the first thin film transistor TR1 through the contact hole CH1. However, embodiments of the present disclosure are not limited thereto, and the first bridge electrode BR1 may be connected to the source electrode S1 of the first thin film transistor TR1 through the contact hole CH1.

[0140] In addition, a first capacitor electrode CE1 may be formed on the inorganic insulating layer 210. The first capacitor electrode CE1 is one electrode constituting the capacitor C1.

[0141] The first capacitor electrode CE1 may be integrally formed with the first bridge electrode BR1 .

[0142] Reference Figure 5 A buffer layer 220 is disposed on the inorganic insulating layer 210, the first bridge electrode BR1, and the first capacitor electrode CE1. According to an embodiment of the present disclosure, the buffer layer 220 disposed on the inorganic insulating layer 210 may be referred to as a second buffer layer or an upper buffer layer.

[0143] The buffer layer 220 may be used to block moisture or oxygen. The buffer layer 220 may be arranged to cover the entire surface of the substrate 110.

[0144] The buffer layer 220 has an insulating property and may include an inorganic material. The buffer layer 220 may be made of a single inorganic layer, or may include a plurality of stacked inorganic layers. For example, the buffer layer 220 may include at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON.

[0145] The second thin film transistor TR2 may be disposed on the buffer layer 220 .

[0146] The second thin film transistor TR2 includes a semiconductor layer A2, a gate electrode G2, a source electrode S2, and a drain electrode D2 disposed on the buffer layer 220. A gate insulating layer 240 may be disposed between the semiconductor layer A2 and the gate electrode G2.

[0147] exist Figure 5 , a second thin film transistor TR2 having a top gate structure in which the gate electrode G2 is disposed on top of the semiconductor layer A2 is shown, but the embodiments of the present disclosure are not limited thereto. As another example, the second thin film transistor TR2 may have a bottom gate structure in which the gate electrode G2 is disposed below the semiconductor layer A2, or may have a dual gate structure in which the gate electrode G2 is disposed both on top of the semiconductor layer A2 and below the semiconductor layer A2.

[0148] The semiconductor layer A2 is disposed on the buffer layer 220. The semiconductor layer A2 may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

[0149] The gate insulating layer 240 insulates the semiconductor layer A2 from the gate electrode G2. The gate insulating layer 240 may be disposed on the entire surface of the substrate 110 to cover the semiconductor layer A2, or may be disposed only in a region where the semiconductor layer A2 and the gate electrode G2 overlap.

[0150] The gate insulating layer 240 may include, for example, at least one of silicon oxide SiOx and silicon nitride SiNx, and may have a single-layer structure or a multi-layer structure.

[0151] The gate electrode G2 is disposed on the gate insulating layer 240 to overlap at least a portion of the semiconductor layer A2. The gate electrode G2 may be formed together with the gate line GL. According to an embodiment of the present disclosure, the gate electrode G2 may include at least one of molybdenum Mo, aluminum Al, chromium Cr, gold Au, titanium Ti, nickel Ni, neodymium Nd, and copper Cu. The gate electrode G2 may have a single-layer structure or a multi-layer structure.

[0152] According to an embodiment of the present disclosure, a second bridge electrode BR2 may be disposed on the gate insulating layer 240 .

[0153] Reference Figure 5 , the contact hole CH2 may be formed to penetrate the gate insulating layer 240 and the buffer layer 220. The contact hole CH2 may be formed by patterning the gate insulating layer 240 and the buffer layer 220. The second bridge electrode BR2 may be disposed on the gate insulating layer 240. The second bridge electrode BR2 may be connected to the first bridge electrode BR1 on the inorganic insulating layer 210 through the contact hole CH2.

[0154] In addition, the second bridge electrode BR2 may be connected to the gate electrode G2 of the second thin film transistor TR2. Figure 5 The path of the II′ cutting surface shown in FIG. 1 is connected to the gate electrode G2 of the second thin film transistor TR2 .

[0155] As described, the first bridge electrode BR1 may be connected to the drain electrode D1 of the first thin film transistor TR1 through the contact hole CH1. The second bridge electrode BR2 may be connected to the first bridge electrode BR1 and simultaneously connected to the gate electrode G2 of the second thin film transistor TR2. Therefore, the drain electrode D1 of the first thin film transistor TR1 may be connected to the gate electrode G2 of the second thin film transistor TR2 through the first bridge electrode BR1 and the second bridge electrode BR2. Figure 2 As shown in the circuit diagram of , the first thin film transistor TR1 and the second thin film transistor TR2 may be electrically connected.

[0156] According to an embodiment of the present disclosure, the gate electrode G2 of the second thin film transistor TR2 may be connected to the drain electrode D1 of the first thin film transistor TR1 through the first bridge electrode BR1 and the second bridge electrode BR2. Also, when the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL may be supplied to the gate electrode G2 of the second thin film transistor TR2.

[0157] Reference Figure 5 , an interlayer insulating film 250 may be disposed on the gate electrode G2 of the second thin film transistor TR2. The interlayer insulating film 250 may be disposed on the entire surface of the substrate 110 to cover the gate electrode G2 and the gate insulating layer 240.

[0158] The source electrode S2 and the drain electrode D2 may be disposed on the interlayer insulating film 250. The source electrode S2 and the drain electrode D2 may be formed together with, for example, the data line DL or the driving power line PL.

[0159] Each of the source electrode S2 and the drain electrode D2 may be connected to the semiconductor layer A2 through an electrode contact hole penetrating the interlayer insulating film 250 and the gate insulating layer 240. The source electrode S2 and the drain electrode D2 may include at least one of molybdenum Mo, aluminum Al, chromium Cr, gold Au, titanium Ti, nickel Ni, neodymium Nd, and copper Cu.

[0160] In addition, a second capacitor electrode CE2 may be disposed on the interlayer insulating film 250. The second capacitor electrode CE2 may be connected to the source electrode S2 of the second thin film transistor TR2. According to an embodiment of the present disclosure, the second capacitor electrode CE2 may be integrally formed with the source electrode S2 of the second thin film transistor TR2.

[0161] The second capacitor electrode CE2 is disposed to overlap the first capacitor electrode CE1. The capacitor C1 of the pixel P is formed by the overlap of the first capacitor electrode CE1 and the second capacitor electrode CE2.

[0162] The capacitor C1 formed by overlapping the first capacitor electrode CE1 and the second capacitor electrode CE2 may serve as a storage capacitor of the pixel P (see Figure 2 ).

[0163] As described above, the second thin film transistor TR2 included in the pixel driving circuit PDC may be disposed on the isolation layer 180 and the inorganic insulating layer 210. The gate driver 320 disposed on the substrate 110 may include a thin film transistor that is the same as or similar to the second thin film transistor TR2 disposed in the pixel P.

[0164] According to an embodiment of the present disclosure, the first thin film transistor TR1 and the second thin film transistor TR2 are arranged in a stacked state. When the first thin film transistor TR1 and the second thin film transistor TR2 are not arranged on the same plane but stacked on each other, the arrangement efficiency of the thin film transistors TR1 and TR2 can be increased and the arrangement area can be reduced.

[0165] According to the embodiments of the present disclosure, Figure 5As shown in , when the first thin film transistor TR1 and the second thin film transistor TR2 are arranged in a stacked state, a large number of thin film transistors can be arranged in a small area, and therefore, the area of ​​the capacitor C1 in the pixel P can be easily secured.

[0166] Since a high-resolution display device has a large number of pixels P arranged in a limited area, a small area is allocated to each pixel P. According to an embodiment of the present disclosure, since thin film transistors can be efficiently arranged in a small area, the display device 100 according to an embodiment of the present disclosure is conducive to realizing a high-resolution display device.

[0167] Reference Figure 5 A planarization layer 270 is disposed on the second thin film transistor TR2.

[0168] The planarization layer 270 is disposed on the entire surface of the substrate 110 to cover the thin film transistors TR1 and TR2. The planarization layer 270 provides a flat surface over the thin film transistors TR1 and TR2. The planarization layer 270 may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0169] The planarization layer 270 may include a pixel contact hole for exposing a source electrode or a drain electrode of a driving thin film transistor provided in the pixel P.

[0170] A first electrode 711 of the display element 710 is disposed on the planarization layer 270. The first electrode 711 is connected to the source electrode S2 of the second thin film transistor TR2 through a contact hole formed in the planarization layer 270. Therefore, the display element 710 may be connected to the second thin film transistor TR2.

[0171] In addition, since the first electrode 711 is connected to the source electrode S2 of the second thin film transistor TR2 , the display element 710 may be connected to the capacitor C1 .

[0172] The first electrode 711 of the display element 710 may be referred to as a pixel electrode or an anode.

[0173] According to an embodiment of the present disclosure, the first electrode 711 may include a metal material with high reflectivity. For example, the first electrode 711 may have a stacked structure of aluminum Al and titanium Ti (Ti / Al / Ti), a stacked structure of aluminum Al and indium tin oxide ITO (ITO / Al / ITO), a silver palladium copper APC (Ag / Pd / Cu) alloy, or a multilayer structure such as an APC alloy and an ITO laminated structure (ITO / APC / ITO). In addition, the first electrode 711 may include a layer containing one or more materials selected from silver Ag, aluminum Al, molybdenum Mo, gold Au, magnesium Mg, calcium Ca, and barium Ba.

[0174] A bank layer 750 may be provided at the edge of the first electrode 711. The bank layer 750 defines the light emitting region of the display element 710. The bank layer 750 is provided on the planarization layer 270 and defines an opening region or a light emitting region of a pixel P provided in the display region AA. The bank layer 750 may also be referred to as a pixel defining layer.

[0175] At the first electrode 711 , an edge portion except a middle portion of the first electrode 711 overlapping the opening region of the pixel P may be covered by the bank layer 750 .

[0176] An organic light emitting layer 712 is disposed on the first electrode 711. According to an embodiment of the present disclosure, the organic light emitting layer 712 may be disposed on the entire display area AA of the substrate 110 to cover the first electrode 711 and the bank layer 750.

[0177] The organic light-emitting layer 712 may include, for example, two or more light-emitting units stacked vertically to emit white light. According to an embodiment of the present disclosure, the organic light-emitting layer 712 may include a first light-emitting unit and a second light-emitting unit for emitting white light by mixing the first light and the second light. Here, the first light-emitting unit emits the first light and may include any one of a blue light-emitting portion, a green light-emitting portion, a red light-emitting portion, a yellow light-emitting portion, and a yellow-green light-emitting portion. The second light-emitting unit may include a light-emitting portion that emits a second light, and the second light has a complementary color relationship with the first light. When the organic light-emitting layer 712 emits white light, the display device 100 may further include a color filter layer (not shown). The color filter layer may be arranged in the direction in which light is emitted from the display element 710.

[0178] According to an embodiment of the present disclosure, the organic light emitting layer 712 may include any one of a blue light emitting portion, a green light emitting portion, and a red light emitting portion for emitting light having a color corresponding to a color set in the pixel P.

[0179] A second electrode 713 is disposed on the organic light emitting layer 712. The second electrode 713 may also be referred to as a common electrode.

[0180] The second electrode 713 may contact the organic light emitting layer 712. The second electrode 713 may be disposed throughout the display area AA of the substrate 110 to connect each organic light emitting layer 712 disposed in each pixel P in common.

[0181] According to an embodiment of the present disclosure, the second electrode 713 may include a transparent conductive material or a transmissive reflective conductive material that can transmit light. When the second electrode 713 is formed of a transmissive reflective conductive material, the emission efficiency of light emitted from the light-emitting device as the display element 710 may be increased by the microcavity structure. The transmissive reflective conductive material may include, for example, magnesium Mg, silver Ag, or an alloy of magnesium Mg and silver Ag.

[0182] Although not shown, a capping layer may be further disposed on the second electrode 713 to improve light emission efficiency by adjusting the refractive index of a layer through which light emitted from the display element 710 passes. In addition, an encapsulation layer including at least one inorganic layer and at least one organic layer may be disposed on the second electrode 713.

[0183] The display element 710 is formed by the first electrode 711 , the organic light emitting layer 712 , and the second electrode 713 . Figure 5 The display element 710 shown in FIG. 7 is an organic light emitting diode OLED. Therefore, the display device 100 according to an embodiment of the present disclosure may be referred to as an organic light emitting display device.

[0184] In the following, reference will be made to Figure 6 The recessed portions RE1 , RE2 and the dam portions DM1 , DM2 of the display device 100 according to an embodiment of the present disclosure are described in more detail.

[0185] Figure 6 yes Figure 5 A partial enlarged view of the dam portions DM1, DM2 and the recesses RE1, RE2.

[0186] Reference Figure 4 and Figure 5 , the recesses RE1 and RE2 are disposed between the through hole TH and the adjacent pixel P′. Figure 5 and Figure 6 , the recessed portions RE1, RE2 may be formed in the isolation layer 180. The recessed portions RE1, RE2 may be formed by selectively removing a material constituting the isolation layer 180.

[0187] According to the embodiment of the present disclosure, it can be said that isolation layer 180 has recessed portions RE1 , RE2 .

[0188] Reference Figure 6 The inorganic insulating layer 210 has openings OP1 and OP2 , and the material constituting the isolation layer 180 may be selectively removed from the bottoms of the openings OP1 and OP2 of the inorganic insulating layer 210 to form recessed portions RE1 and RE2 .

[0189] The recessed portions RE1, RE2 may be defined by the dam portions DM1, DM2 and the isolation layer 180. In detail, the recessed portions RE1, RE2 may be defined as a region or space surrounded by the dam portions DM1, DM2 and the isolation layer 180.

[0190] For example, the first recess RE1 may be defined by the first dam DM1 and the second dam DM2 , and the second recess RE2 may be defined by the second dam DM2 and the isolation layer 180 .

[0191] Reference Figure 5 and Figure 6 , the dam portions DM1, DM2 include an isolation layer 180 and an inorganic insulating layer 210 on the isolation layer 180. The isolation layer 180 and the inorganic insulating layer 210 may be patterned to form the dam portions DM1, DM2.

[0192] The isolation layer 180 and the inorganic insulating layer 210 may be selectively patterned to form the recesses RE1 , RE2 . For example, the isolation layer 180 and the inorganic insulating layer 210 are patterned to form a through hole penetrating the inorganic insulating layer 210 , and the isolation layer 180 is also etched to form the recesses RE1 , RE2 .

[0193] The recessed portions RE1 and RE2 may have openings OP1 and OP2 in a direction toward the inorganic insulating layer 210. The inorganic insulating layer 210 is not provided in the openings OP1 and OP2.

[0194] The openings OP1 and OP2 may be defined by the inorganic insulating layer 210. In detail, the openings OP1 and OP2 may be formed by patterning the inorganic insulating layer 210. For example, the first opening OP1 of the first recess RE1 and the second opening OP2 of the second recess RE2 may be defined by the patterned inorganic insulating layer 210 and spaced apart from each other.

[0195] According to the embodiments of the present disclosure, Figure 5 and Figure 6 As shown in FIG. 1 , the isolation layer 180 may have two or more recesses RE1, RE2. The two or more recesses RE1, RE2 may be spaced apart from each other with a second dam DM2 therebetween.

[0196] According to an embodiment of the present disclosure, the isolation layer 180 has an etch rate greater than that of the inorganic insulating layer 210 .

[0197] In detail, under dry etching conditions, the etching rate of the isolation layer 180 may be greater than the etching rate of the inorganic insulating layer 210. In addition, with respect to an etching solution for etching organic materials, the etching rate of the isolation layer 180 is greater than the etching rate of the inorganic insulating layer 210. Since the etching rate of the isolation layer 180 is greater than the etching rate of the inorganic insulating layer 210, Figure 6 As shown in FIG. 8 , pot-shaped recesses RE1 , RE2 can be formed.

[0198] Since the etching rate of the isolation layer 180 is greater than the etching rate of the inorganic insulating layer 210, after forming the hole penetrating the isolation layer 180 and the inorganic insulating layer 210, additional etching is then performed on the isolation layer 180. Therefore, the width of the recesses RE1, RE2 formed in the isolation layer 180 can be formed to be greater than the width of the openings OP1, OP2 defined by the inorganic insulating film 210. Therefore, according to an embodiment of the present disclosure, the width of the recesses RE1, RE2 is greater than the width of the openings OP1, OP2. In detail, the width WR1 of the first recess RE1 is greater than the width WO1 of the first opening OP1, and the width WR2 of the second recess RE2 is greater than the width WO1 of the first opening OP1.

[0199] According to an embodiment of the present disclosure, the width WR1 , WR2 of the recesses RE1 , RE2 is defined as the width at the middle height of the recesses RE1 , RE2 , and the width WO1 , WO2 of the openings OP1 , OP2 is defined as the width measured at the bottom of the inorganic insulating layer 210 .

[0200] Reference Figure 5 and Figure 6 , the inorganic insulating layer 210 is disposed on the buffer layer 220. According to an embodiment of the present disclosure, the buffer layer 220 may also be disposed on the sidewalls SW of the recesses RE1 and RE2. In detail, during the process of forming the buffer layer 220, the material for forming the buffer layer 220 is attached to the sidewalls SW of the recesses RE1 and RE2, and therefore, the buffer layer 220 may also be formed at the sidewalls SW of the recesses RE1 and RE2.

[0201] The buffer layer 220 has insulating properties and may include an inorganic material. For example, the buffer layer 220 may include at least one of silicon oxide SiOx, silicon nitride SiNx, and silicon oxynitride SiON. Compared with organic materials, the buffer layer 220 including an inorganic material has excellent moisture and oxygen barrier properties. Since the buffer layer 220 is disposed on the sidewalls SW of the recesses RE1 and RE2 made of an organic material, the penetration of moisture or oxygen through the sidewalls SW of the recesses RE1 and RE2 can be effectively prevented. Therefore, the display device 100 according to an embodiment of the present disclosure may have excellent moisture barrier properties and have excellent oxygen barrier properties.

[0202] According to an embodiment of the present disclosure, the display element 710 includes an organic light emitting layer 712. The organic light emitting layer 712 including an organic material is susceptible to moisture and oxygen, and the organic light emitting layer 712 itself and the interface between the organic light emitting layer 712 and other layers may be a path for moisture or oxygen migration.

[0203] In particular, if Figure 5 and Figure 6 As shown in , when a portion of the display panel 310 is cut to form the through hole TH, moisture or oxygen can easily penetrate through the cut surface. In particular, when the organic light emitting layer 712 is exposed on the cut surface, moisture or oxygen can easily penetrate through the organic light emitting layer 712, and the organic light emitting layer 712 may be easily damaged.

[0204] According to an embodiment of the present disclosure, the continuity of the organic light emitting layer 712 may be interrupted by the recesses RE1 and RE2. Figure 5 and Figure 6 , the organic light emitting layer 712 is discontinuously formed in the regions of the recesses RE1 and RE2, and the continuity of the organic light emitting layer 712 may be destroyed. According to an embodiment of the present disclosure, the organic light emitting layer 712 loses continuity in the recesses RE1 and RE2.

[0205] For example, even if the organic light emitting material is deposited on the entire surface above the substrate 110 to form the organic light emitting layer 712, the organic light emitting layer 712 may be discontinuously formed in the region of the pot-shaped recesses RE1, RE2. Therefore, the continuity of the organic light emitting layer 712 may be destroyed by the recesses RE1, RE2.

[0206] When the continuity of the organic light emitting layer 712 is interrupted, the permeation path of moisture and oxygen is cut off, thereby preventing or suppressing the permeation of moisture and oxygen through the organic light emitting layer 712 .

[0207] In particular, if Figure 5 and Figure 6 As shown in FIG, even if a portion of the display panel 310 is cut to form the through hole TH and a portion of the organic light emitting layer 712 is exposed, the continuity of the organic light emitting layer 712 is destroyed by the recesses RE1 and RE2, so that the penetration of moisture and oxygen can be easily prevented or suppressed.

[0208] According to the embodiments of the present disclosure, Figure 5 and Figure 6 As shown in FIG. 1 , the organic light emitting layer 712 may be disposed on the bottom surface of the recesses RE1 and RE2. However, the organic light emitting layer 712 disposed on the bottom surface of the recesses RE1 and RE2 is not connected to the organic light emitting layer 712 disposed on the upper portion of the buffer layer 220. Therefore, the continuity of the organic light emitting layer 712 may be easily destroyed.

[0209] According to an embodiment of the present disclosure, the isolation layer 180 may have a thickness of 1 μm to 4 μm. When the isolation layer 180 has a thickness of 1 μm to 4 μm, the first thin film transistor TR1 and the second thin film transistor TR2 are sufficiently spaced apart to ensure electrical stability from each other, and at the same time, the display device 100 may be prevented from becoming unnecessarily thick.

[0210] The recesses RE1, RE2 may have a height of 1 μm or more due to the thickness of the isolation layer 180. Due to the height of the recesses RE1, RE2, the thin organic light emitting layer 712 may not be connected between the bottom surface of the recesses RE1, RE2 and the top of the buffer layer 220. Therefore, the continuity of the organic light emitting layer 712 may be easily destroyed.

[0211] In addition, when the recesses RE1, RE2 have a height of 1 μm or more, overetching of the isolation layer 180 for forming the recesses RE1, RE2 can be easily achieved. And therefore, the width of the recesses RE1, RE2 can be increased. The width of the recesses RE1, RE2 can be more than twice the width of the openings OP1, OP2.

[0212] For example, the width WR1 of the first recess RE1 may be more than twice the width WO1 of the first opening OP1 , and the width WR2 of the second recess RE2 may be more than twice the width WO2 of the second opening OP2 .

[0213] According to an embodiment of the present disclosure, a through hole TH may be formed in the substrate 110. Figure 4 As described in the description, the substrate 110 has the through hole TH, and the first thin film transistor TR1, the second thin film transistor TR2 and the display element 710 are not disposed in the through hole TH. The recesses RE1 and RE2 may be arranged to surround the through hole TH. In addition, the dam portions DM1 and DM2 may also be arranged to surround the through hole TH.

[0214] According to an embodiment of the present disclosure, the first thin film transistor TR1, the second thin film transistor TR2, and the display element 710 are disposed on the substrate 110 to form the display panel 310, and then a portion of the panel 310 is cut or removed to form the through hole TH. A portion of the panel 310 is cut or removed into the shape of the through hole. Therefore, the display panel 310 having the through hole TH can be manufactured.

[0215] The display device 100 according to an embodiment of the present disclosure may further include an optical member 410 disposed to overlap with the through hole TH formed in the substrate 110 .

[0216] The optical element 410 may include, for example, any one of a camera, an infrared sensor, a proximity sensor, an illumination sensor, a fingerprint sensor, and the like.

[0217] Figure 7 is a partial cross-sectional view of a display device 200 according to another embodiment of the present disclosure.

[0218] The display device 200 according to another embodiment of the present disclosure has a through hole TH which is disposed in the display area AA and penetrates the display panel 310. According to another embodiment of the present disclosure, various components or modules may be installed or arranged in the through hole TH. For example, the optical element 410 may be disposed in the through hole TH.

[0219] The display device 200 according to another embodiment of the present disclosure may include an optical element 410 disposed to overlap the through hole TH. As the optical element 410, for example, at least one of a camera, an infrared sensor, a proximity sensor, an illumination sensor, and a fingerprint sensor may be used.

[0220] Figure 7 For example, a configuration is shown in which an image pickup device as the optical element 410 is provided in the through hole TH.

[0221] When a camera is used as the optical element 410, the camera is located behind the display panel 310 and may be arranged so that the center of the camera lens LE coincides with the center of the through hole TH. When a camera is used as the optical element 410, the through hole TH may not have a completely circular shape.

[0222] For example, Figure 7 As shown in FIG. 1 , a display device 200 according to another embodiment of the present disclosure includes an encapsulation layer 510 and a cover window 612. The cover window 612 may be attached to the encapsulation layer 510 by using a light-transmitting adhesive layer 611.

[0223] The encapsulation layer 510 may be formed on the display element 710 above the substrate 110 to surround the display area AA. The encapsulation layer 510 may be disposed on the second electrode 713 of the display element 710. The encapsulation layer 510 protects the display element 710. In detail, the encapsulation layer 510 protects the thin film transistors TR1, TR2 and the organic light emitting layer 712 from external impacts, and prevents oxygen, moisture or foreign particles from penetrating into the organic light emitting layer 712.

[0224] According to an embodiment of the present disclosure, the encapsulation layer 510 may include a plurality of inorganic encapsulation layers 511 , 513 and at least one organic encapsulation layer 512 interposed between the plurality of inorganic encapsulation layers 511 , 513 .

[0225] For example, the encapsulation layer 510 includes a first inorganic encapsulation layer 511 , an organic encapsulation layer 512 on the first inorganic encapsulation layer 511 , and a second inorganic encapsulation layer 513 on the organic encapsulation layer 512 .

[0226] The first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 513 are used to block the penetration of moisture or oxygen. Each of the first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 513 may include, for example, at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and titanium oxide. The first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 513 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0227] According to an embodiment of the present disclosure, the first inorganic encapsulating layer 511 may be disposed on the sidewalls SW of the recesses RE1 , RE2 In detail, the first inorganic encapsulating layer 511 may be disposed on the buffer layer 220 disposed on the sidewalls SW of the recesses RE1 , RE2 .

[0228] The organic encapsulation layer 512 may have a structure sealed or encapsulated by the first and second inorganic encapsulation layers 511 and 513. The organic encapsulation layer 512 may have a relatively large thickness compared to the first and second inorganic encapsulation layers 511 and 513. The organic encapsulation layer 512 may include an organic material.

[0229] Reference Figure 7 , a light-transmitting adhesive layer 611 may be disposed on the encapsulation layer 510 , and a cover window 612 may be disposed on the light-transmitting adhesive layer 611 .

[0230] exist Figure 7 In the display device 200 shown in FIG. 1 , the through hole TH may be opened only on the side facing the optical element 410, and may be blocked on the upper side facing the user by the cover window 612. Since most of the components of the display panel 310 except the cover window 612 on the front surface of the optical element 410 have been removed through the through hole TH, there may be no optical interference with the optical element 410.

[0231] Although not shown, a component or module performing a mechanical or physical function may be disposed in the through hole TH in addition to the optical element 410. For example, a vibration device, a locking device, a rotation shaft, etc. may be disposed in the through hole TH.

[0232] Figure 8 is a schematic diagram of a display panel 310 of a display device 300 according to another embodiment of the present disclosure, and Fig. 9 It is along Figure 8 Cross-sectional view along line II-II′.

[0233] According to the display device 300 according to another embodiment of the present disclosure, the recesses RE1 and RE2 may be provided along the edge of the substrate 110. Figure 8 and Fig. 9 , the recesses RE1 and RE2 may be disposed in the non-display area IA surrounding the display area AA. The organic light emitting layer 712 may not be disposed in the recesses RE1 and RE2, or the continuity of the organic light emitting layer 712 may be destroyed by the recesses RE1 and RE2.

[0234] Since the recesses RE1 and RE2 are provided in the non-display area IA corresponding to the edge of the substrate 110, the penetration path of moisture and oxygen from the outside into the display area AA of the display panel 310 becomes longer. Therefore, the display area AA can be effectively protected from moisture and oxygen.

[0235] Fig.10 is a circuit diagram of one pixel P of a display device 400 according to another embodiment of the present disclosure. Fig.10 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0236] Fig.10 The pixel P of the display device 400 shown in FIG. 4 includes an organic light emitting diode OLED as a display element 710 and a pixel driving circuit PDC driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0237] In the pixel P, signal lines DL, GL, PL, RL, and SCL that supply signals to the pixel driving circuit PDC are provided.

[0238] Data voltage Vdata is supplied to data line DL, scan signal SS is supplied to gate line GL, and driving voltage Vdd for driving pixels is supplied to driving power line PL. Reference voltage Vref is supplied to reference line RL, and sensing control signal SCS is supplied to sensing control line SCL.

[0239] The pixel driving circuit PDC, for example, includes a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the amplitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1, and a third thin film transistor TR3 (sensing transistor) for sensing the characteristics of the first thin film transistor TR1.

[0240] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710 .

[0241] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2 .

[0242] The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710 and to the reference line RL. The third thin film transistor TR3 is turned on or off by the sensing control signal SCS and senses the characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0243] The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The storage capacitor Cst is formed between the second node n2 and the first node n1.

[0244] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0245] When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 through the second thin film transistor TR2 by the driving voltage Vdd that drives the pixel, and light is emitted from the display element 710 .

[0246] According to another embodiment of the present disclosure, the first thin film transistor TR1 , the second thin film transistor TR2 , and the third thin film transistor TR3 may be disposed to be stacked.

[0247] In detail, at least one of the first, second, and third thin film transistors TR1 , TR2 , and TR3 may be disposed under the isolation layer 180 , and at least one of the first, second, and third thin film transistors TR1 , TR2 , and TR3 may be disposed on the isolation layer 180 .

[0248] For example, the first thin film transistor TR1 and the third thin film transistor TR3 may be disposed below the isolation layer 180, and the second thin film transistor TR2 may be disposed above the isolation layer 180. Conversely, the first thin film transistor TR1 and the third thin film transistor TR3 may be disposed above the isolation layer 180, and the second thin film transistor TR2 may be disposed below the isolation layer 180. Alternatively, only the first thin film transistor TR1 may be disposed below the isolation layer 180, and the second thin film transistor TR2 and the third thin film transistor TR3 may be disposed above the isolation layer 180.

[0249] Fig.11is a circuit diagram of a pixel of a display device 500 according to another embodiment of the present disclosure.

[0250] Fig.11 The pixel P of the display device 500 shown in FIG. 5 includes an organic light emitting diode OLED as a display element 710 and a pixel driving circuit PDC driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0251] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0252] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL that supply signals to the pixel driving circuit PDC are provided.

[0253] and Fig.10 Compared with the pixel P in Fig.11 The pixel P in FIG. 4 further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL.

[0254] In addition, Fig.10 Compared with the pixel driving circuit PDC, Fig.11 The pixel driving circuit PDC further includes a fourth thin film transistor TR4 which is a light emission control transistor for controlling the timing of light emission by controlling the second thin film transistor TR2.

[0255] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710 .

[0256] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2 .

[0257] The third thin film transistor TR3 connected to the reference line RL is turned on or off by the sensing control signal SCS, and senses characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0258] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2, thereby emitting light from the display element 710.

[0259] Fig.11 One or more of the thin film transistors TR1 , TR2 , TR3 , and TR4 shown in FIG. 1 may be disposed under the isolation layer 180 , and another one or more may be disposed over the isolation layer 180 .

[0260] The pixel driving circuit PDC according to another embodiment of the present disclosure may be formed in various structures other than the above-described structures. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0261] FIG. 12A to FIG. 12G is a schematic diagram of a manufacturing process of the display device 100 according to an embodiment of the present disclosure.

[0262] Reference Fig. 12A , a first thin film transistor TR1 is formed on a substrate 110. In detail, a first buffer layer 120 is formed on the substrate 110, a semiconductor layer A1 is formed on the first buffer layer 120, a gate insulating layer 140 is formed on the semiconductor layer A1, a gate electrode G1 is formed on the gate insulating layer 140, an interlayer insulating layer 150 is formed on the gate electrode G1, and a source electrode S1 and a drain electrode D1 are formed on the interlayer insulating layer 150.

[0263] Reference Fig. 12B An isolation layer 180 including an organic material is formed on the first thin film transistor TR1. In addition, an inorganic insulating layer 210 is formed on the isolation layer 180.

[0264] The isolation layer 180 may include or may be made of an organic material. To form the isolation layer 180, a material having an etching rate greater than that of the inorganic insulating layer 210 is used. The isolation layer 180 has an etching rate higher than that of the inorganic insulating layer 210.

[0265] Reference Fig. 12C , a portion of the inorganic insulating layer 210 and the isolation layer 180 is removed to form holes HR1 and HR2 that pass through the inorganic insulating layer 210 and the isolation layer 180. Optionally, the holes HR1 and HR2 are formed along the edge of the substrate 110. At this time, the contact hole CH1 may be formed to connect the first thin film transistor TR1 and the second thin film transistor TR2. The first thin film transistor TR1 and the second thin film transistor TR2 may be connected by Fig. 12C The contact hole CH1 shown in FIG.

[0266] In addition, refer to Fig. 12C , a first bridge electrode BR1 may be formed on the inorganic insulating layer 210. The first bridge electrode BR1 is connected to the first thin film transistor TR1 through the contact hole CH1. The contact hole CH1 is filled or protected by the first bridge electrode BR1.

[0267] Reference Fig.12D, the holes HR1, HR2 formed in the isolation layer 180 are expanded to form recesses RE1, RE2 in the isolation layer 180. Alternatively, in the case where the holes HR1, HR2 are formed along the edge of the substrate 110, the recesses RE1, RE2 are also formed along the edge of the substrate 110.

[0268] According to an embodiment of the present disclosure, the inorganic insulating layer 210 and the isolation layer 180 are patterned to form holes HR1 and HR2 (see FIG. Fig. 12C ), and further etches a portion of the holes HR1, HR2 formed in the isolation layer 180 to form recesses RE1, RE2 in the isolation layer 180. The process of further etching the holes HR1, HR2 formed in the isolation layer 180 may be referred to as an over-etching process for the isolation layer 180. According to an embodiment of the present disclosure, a portion of the holes HR1, HR2 formed in the inorganic insulating layer 210 may become openings OP1, OP2.

[0269] In the process of further etching the holes HR1 and HR2 formed in the isolation layer 180, the inorganic insulating layer 210 is not further etched or is hardly further etched. Therefore, the width of the recesses RE1 and RE2 formed in the isolation layer 180 can be made larger than the width of the openings OP1 and OP2 defined by the inorganic insulating layer 210.

[0270] According to an embodiment of the present disclosure, the first opening OP1 of the first recess RE1 may be defined by the inorganic insulating layer 210 of the first dam DM1 and the inorganic insulating layer 210 of the second dam DM2, which are formed by patterning and are spaced apart from each other. The second opening OP2 of the second recess RE2 may be defined by the inorganic insulating layer 210 of the second dam DM2 and the inorganic insulating layer 210 of the adjacent pixel P′. According to an embodiment of the present disclosure, the width WR1 of the first recess RE1 may be formed to be greater than the width WO1 of the first opening OP1, and the width WR2 of the second recess RE2 may be formed to be greater than the width WO2 of the second opening OP2.

[0271] Reference Fig.12E , a buffer layer 220 is formed on the inorganic insulating layer 210. The buffer layer 220 has insulating properties and may include an inorganic material.

[0272] According to an embodiment of the present disclosure, in the step of forming the buffer layer 220, the material for forming the buffer layer 220 is applied into the recesses RE1, RE2 and disposed on the sidewalls SW of the recesses RE1, RE2. Fig.12EAs shown in FIG. 2 , a buffer layer 220 may be formed on the sidewalls SW of the recesses RE1 , RE2 . Since the buffer layer 220 is disposed on the sidewalls SW of the recesses RE1 , RE2 , penetration of moisture or oxygen through the sidewalls SW of the recesses RE1 , RE2 may be easily prevented.

[0273] Reference Fig.12F , a second thin film transistor TR2 is formed on the buffer layer 220. In addition, a display element 710 is formed on the second thin film transistor TR2. The display element 710 may be connected to any one of the first thin film transistor TR1 and the second thin film transistor TR2. Fig.12F A structure in which the display element 710 is connected to the second thin film transistor TR2 is shown.

[0274] According to an embodiment of the present disclosure, the display element 710 is an organic light emitting diode OLED including an organic light emitting layer 712. Forming the display element 710 includes forming the organic light emitting layer 712.

[0275] Reference Fig.12F , the continuity of the organic light emitting layer 712 is destroyed in the recesses RE1, RE2. In detail, the organic light emitting layer 712 is discontinuously formed in the regions of the recesses RE1, RE2, and the continuity of the organic light emitting layer 712 may be destroyed. When the continuity of the organic light emitting layer 712 is interrupted or destroyed, the permeation path of moisture and oxygen is cut off, thereby preventing or inhibiting the permeation of moisture and oxygen through the organic light emitting layer 712.

[0276] although Fig.12F Although not shown in the figure, an encapsulation layer 510 may be provided on the display element 710 .

[0277] After forming the display element 710, the through hole TH may be formed. According to an embodiment of the present disclosure, the through hole TH may be formed by cutting a portion of the display panel 310 into a hole shape. Laser may be used to cut a portion of the display panel 310 to form the through hole TH.

[0278] Reference Figure 12G , the through holes TH are formed by using laser cutting, thereby manufacturing the display device 100 according to the embodiment of the present disclosure.

[0279] The present disclosure described above is not limited to the above-described embodiments and drawings, and it is well known to those skilled in the art that various substitutions, modifications, and changes are possible within the scope of the technical details of the present disclosure.

Claims

1. A display device, comprising: a first thin film transistor on a substrate; An isolation layer disposed on the first thin film transistor and comprising an organic material; an inorganic insulating layer on the isolation layer; a buffer layer on the inorganic insulating layer; a second thin film transistor on the buffer layer; as well as a display element connected to any one of the first thin film transistor and the second thin film transistor, Wherein, the isolation layer has a concave portion, and The recess has an opening in a direction toward the inorganic insulating layer, and the inorganic insulating layer is not disposed in the opening.

2. The display device according to claim 1, in, The isolation layer has a higher etching rate than the inorganic insulating layer.

3. The display device according to claim 1, in, The width of the recess is greater than the width of the opening: The width of the recess is a width measured at a middle height of the recess, and the width of the opening is a width measured at a bottom of the inorganic insulating layer.

4. The display device according to claim 1, in, The width of the recess is at least twice the width of the opening.

5. The display device according to claim 1, in, The isolation layer has two or more recesses.

6. The display device according to claim 1, in, The buffer layer is disposed on a sidewall of the recess.

7. The display device according to claim 1, in, The display element includes an organic light emitting layer, and The organic light-emitting layer loses continuity in the concave portion.

8. The display device according to claim 1, in, The isolation layer has a thickness of 1 μm to 4 μm.

9. The display device according to claim 1, Also included is an optical element arranged to overlap with the through hole formed in the substrate, in, The first thin film transistor, the second thin film transistor and the display element are not arranged in the through hole, and Wherein, the recess surrounds the through hole.

10. The display device according to claim 1, Also includes an encapsulation layer on the display element, in, The encapsulation layer comprises: a first inorganic encapsulation layer; an organic encapsulation layer on the first inorganic encapsulation layer; as well as a second inorganic encapsulation layer on the organic encapsulation layer, Wherein, the first inorganic encapsulation layer is disposed on the buffer layer disposed on the sidewall of the concave portion.

11. The display device according to claim 1, wherein: The recess is disposed along an edge of the substrate.

12. A method for manufacturing a display device, comprising: forming a first thin film transistor on a substrate; forming an isolation layer including an organic material on the first thin film transistor; forming an inorganic insulating layer on the isolation layer; removing a portion of the inorganic insulating layer and a portion of the isolation layer to form a hole passing through the inorganic insulating layer and the isolation layer; expanding the hole formed in the isolation layer to form a recess in the isolation layer; forming a buffer layer on the inorganic insulating layer; forming a second thin film transistor on the buffer layer; as well as A display element connected to any one of the first thin film transistor and the second thin film transistor is formed.

13. The method for manufacturing a display device according to claim 12, in, The etching rate of the isolation layer is greater than the etching rate of the inorganic insulating layer.

14. The method for manufacturing a display device according to claim 12, in, Forming the hole through the inorganic insulating layer and the isolation layer further includes forming a contact hole connecting the first thin film transistor and the second thin film transistor.

15. The method for manufacturing a display device according to claim 14, The method further includes forming a first bridge electrode on the inorganic insulating layer, in, The first bridge electrode is connected to the first thin film transistor through the contact hole.

16. The method for manufacturing a display device according to claim 12, in, When forming the buffer layer, a buffer layer forming material is disposed on a side wall of the recess.

17. The method for manufacturing a display device according to claim 16, in, Forming the display element includes forming an organic light emitting layer, and The organic light-emitting layer loses continuity in the concave portion.

18. The method for manufacturing a display device according to claim 12, wherein: The hole is formed through the inorganic insulating layer and the isolation layer along an edge of the substrate so that the concave portion is formed along the edge of the substrate.

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