Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel comprises a substrate, and a shading layer, a first semiconductor layer and a second semiconductor layer which are arranged on the substrate, the first semiconductor layer is provided with a first active part of a driving transistor, and the second semiconductor layer is provided with a second active part of a driving transistor; a third active part of the compensation transistor and a fourth active part of the first initialization transistor are formed on the second semiconductor layer, and the light shielding layer comprises a first light shielding part arranged corresponding to the first active part, a second light shielding part arranged corresponding to the third active part and a third light shielding part arranged corresponding to the fourth active part. The second shading part can shade the third active part, and the third shading part can shade the fourth active part, so that the third active part of the compensation transistor and the fourth active part of the first initialization transistor are prevented from being influenced by light, and the photosensitivity and the electrical property of the compensation transistor and the first initialization transistor are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, the requirements for power consumption and screen-to-body ratio of existing display devices are getting higher and higher. In order to reduce power consumption and increase screen-to-body ratio, existing display devices will use low-temperature polysilicon oxide (LTPO) technology. LTPO technology refers to the simultaneous use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current.

[0003] Existing display devices using LTPO technology have a large number of film layers, and the corresponding number of mask plates required is large, resulting in a complex process and high cost. In order to reduce the number of mask plates, existing display devices will remove some gate layers and insulating layers, but this will result in the loss of the bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor will deteriorate.

[0004] Therefore, existing display devices using LTPO technology have technical problems such as poor photosensitivity and electrical properties caused by the absence of the bottom gate of the oxide thin film transistor. Summary of the invention

[0005] The present application provides a display panel and a display device to alleviate the technical problem of poor photosensitivity and electrical properties caused by the bottom gate loss of oxide thin film transistors in existing display devices using LTPO technology.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] In a first aspect, an embodiment of the present application provides a display panel, comprising a substrate and a plurality of sub-pixels arranged on the substrate, each of the sub-pixels comprising a driving transistor, a switching transistor, a compensation transistor and a first initialization transistor, the switching transistor and the driving transistor are connected to a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, and another electrode of the compensation transistor and the driving transistor are connected to a third node; the display panel further comprises:

[0008] A light shielding layer, disposed on one side of the substrate;

[0009] A first semiconductor layer, disposed on a side of the light shielding layer away from the substrate, the first semiconductor layer comprising a first active portion of the driving transistor and a second active portion of the switching transistor;

[0010] a second semiconductor layer, disposed on a side of the first semiconductor layer away from the substrate, the second semiconductor layer comprising a third active portion of the compensation transistor and a fourth active portion of the first initialization transistor;

[0011] Among them, the light-shielding layer includes a first light-shielding portion arranged corresponding to the first active portion, a second light-shielding portion arranged corresponding to the third active portion, and a third light-shielding portion arranged corresponding to the fourth active portion; the light-shielding layer also includes a first connecting line extending along a first direction and a second connecting line extending along a second direction, the first direction and the second direction are different, the first connecting line is connected to two first light-shielding portions arranged adjacent to each other in the first direction, and the second connecting line is connected to two first light-shielding portions arranged adjacent to each other in the second direction.

[0012] In a second aspect, an embodiment of the present application further provides a display device, which includes a display panel as described in one of the aforementioned embodiments.

[0013] The beneficial effects of the present application are as follows: in the display panel and the display device provided by the present application, the display panel includes a substrate and a light-shielding layer, a first semiconductor layer, and a second semiconductor layer arranged on the substrate, the first semiconductor layer forms a first active part of a driving transistor, the second semiconductor layer forms a third active part of a compensation transistor and a fourth active part of a first initialization transistor, the light-shielding layer includes a first light-shielding part arranged corresponding to the first active part, a second light-shielding part arranged corresponding to the third active part, and a third light-shielding part arranged corresponding to the fourth active part, the second light-shielding part can shield the third active part, and the third light-shielding part can shield the fourth active part, so as to prevent the third active part of the compensation transistor and the fourth active part of the first initialization transistor from being affected by light, thereby improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor, so as to improve the problem of poor photosensitivity and electrical properties caused by the bottom gate loss of oxide thin film transistors in existing display devices using LTPO technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application.

[0016] Figure 2A schematic diagram of a second comparative display device provided in an embodiment of the present application.

[0017] Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application.

[0018] Figure 4 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application.

[0019] Figure 5 A circuit diagram of a sub-pixel of a display panel provided in an embodiment of the present application.

[0020] Figure 6 This is a first stacking diagram of various film layers of the display panel provided in an embodiment of the present application.

[0021] Figure 7 This is a second stacking diagram of the film layers of the display panel provided in the embodiment of the present application.

[0022] Figure 8 for Figure 6 Exploded view of the light shielding layer of the display panel.

[0023] Fig. 9 for Figure 7 Exploded view of the light shielding layer of the display panel.

[0024] Fig.10 for Figure 6 An exploded view of the first semiconductor layer of the display panel in FIG.

[0025] Fig.11 for Figure 6 An exploded view of the first gate layer of the display panel in FIG.

[0026] Fig.12 for Figure 6 An exploded view of the second semiconductor layer of the display panel in FIG.

[0027] Fig.13 for Figure 6 An exploded view of the second gate layer of the display panel in FIG.

[0028] Fig.14 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG.

[0029] Fig.15 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG.

[0030] Fig.16 for Figure 6 Exploded view of the first via hole of the display panel.

[0031] Fig.17 for Figure 6 Exploded view of the second via hole of the display panel.

[0032] Fig.18 for Figure 6 An exploded view of the third via hole of the display panel in FIG.

[0033] Fig.19 for Figure 6 An exploded view of the fourth via hole of the display panel in FIG. DETAILED DESCRIPTION

[0034] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0035] Please refer to Figures 1 to 3 As an introduction to the embodiments of the present application, some comparative display devices are provided. Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application, Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application, Figure 3 This is a schematic diagram of a third comparative display device provided in an embodiment of the present application. Figure 1 A comparative display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarizing film 117, a second source-drain film 118, a second planarizing film 119, a third source-drain film 121, a third planarizing film 122, an anode film 123, a pixel definition film 124, and a support film 125. Figure 1 It can be seen that the comparative display device includes three layers of source and drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, the process is relatively complex and the cost is relatively high.

[0036] In order to solve the problem of complex process of the comparative display device, another comparative display device removes one layer of the gate film and the insulating film, such as Figure 2 As shown, it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the comparative display device, so that the number of mask plates can be reduced to 14, but there are still problems such as a large number of mask plates, a complex process, and a high cost.

[0037] In order to solve the problem of complex process of the comparative display device, another comparative display device further removes a layer of source and drain film and insulating film, such as Figure 3 As shown in FIG. 1 , by removing the third source-drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13; Figure 2 , Figure 3 It can be seen that there is no shielding under the oxide semiconductor film 112, resulting in the missing bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor are deteriorated.

[0038] To this end, the present application provides a display panel and a display device, please refer to Figures 1 to 19 , Figure 4 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application. Figure 5 A circuit diagram of a sub-pixel of a display panel provided in an embodiment of the present application. Figure 6 This is a first stacking diagram of various film layers of the display panel provided in an embodiment of the present application. Figure 7 A second stacking diagram of the display panel provided in an embodiment of the present application. Figure 8 for Figure 6 Exploded view of the light shielding layer of the display panel. Fig. 9 for Figure 7 Exploded view of the light shielding layer of the display panel. Fig.10 for Figure 6 An exploded view of the first semiconductor layer of the display panel in FIG. Fig.11 for Figure 6 An exploded view of the first gate layer of the display panel in FIG. Fig.12 for Figure 6 An exploded view of the second semiconductor layer of the display panel in FIG. Fig.13 for Figure 6 An exploded view of the second gate layer of the display panel in FIG. Fig.14 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG. Fig.15 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG. Fig.16 for Figure 6 Exploded view of the first via hole of the display panel. Fig.17 for Figure 6 Exploded view of the second via hole of the display panel. Fig.18 for Figure 6 An exploded view of the third via hole of the display panel in FIG. Fig.19 for Figure 6 An exploded view of the fourth via hole of the display panel in FIG.

[0039] It should be noted that the embodiments of the present application Figure 6 The display panel and Figure 7 The difference between the display panels in FIG. 1 and FIG. 2 is that the design of the light shielding layer is different, and the design of other film layers on the display panel can be the same. Therefore, the following Figure 6 In the decomposition diagram, except for the different light-shielding layers, the decomposition diagrams of other film layers can also be used as Figure 7 An exploded view of the corresponding film layers of the display panel in FIG. Figure 7 The exploded diagram of the light shielding layer of the display panel in FIG. Fig. 9 As shown, other film layers can be similarly referred to in other exploded views and will not be described in detail here.

[0040] The present application embodiment provides a display panel, such as Figures 4 to 19 As shown, the display panel 2 includes a substrate 201 and a plurality of sub-pixels 31 arranged on the substrate 201, each sub-pixel 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the switching transistor T2 and the driving transistor T1 are connected to a first node A; one electrode of the compensation transistor T3, one electrode of the first initialization transistor T4 and the driving transistor T1 are connected to a second node Q, and the other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B.

[0041] The display panel 2 further includes a light shielding layer 202 , a first semiconductor layer 207 and a second semiconductor layer 212 disposed on the substrate 201 . The light shielding layer 202 is disposed between the substrate 201 and the first semiconductor layer 207 , and the first semiconductor layer 207 is disposed between the light shielding layer 202 and the second semiconductor layer 212 .

[0042] The first semiconductor layer 207 is disposed on a side of the light shielding layer 202 away from the substrate 201 . The first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1 and a second active portion T2A of the switching transistor T2 .

[0043] The second semiconductor layer 212 is disposed on a side of the first semiconductor layer 207 away from the substrate 201 , and the second semiconductor layer 212 includes a third active portion T3A of the compensation transistor T3 and a fourth active portion T4A of the first initialization transistor T4 .

[0044] The light shielding layer 202 includes a first light shielding portion 202a provided corresponding to the first active portion T1A, a second light shielding portion 202b provided corresponding to the third active portion T3A, and a third light shielding portion 202c provided corresponding to the fourth active portion T4A; the light shielding layer 202 also includes a first connecting line 202e extending along the first direction X and a second connecting line 202d extending along the second direction Y, the first connecting line 202e is connected to two first light shielding portions 202a provided adjacent to each other in the first direction X, and the second connecting line 202d is connected to two first light shielding portions 202a provided adjacent to each other in the second direction Y, so that the light shielding layer 202 forms a grid structure. The second light shielding portion 202b and the third light shielding portion 202c are both located in the area enclosed by the two adjacent first connecting lines 202e, the two adjacent second connecting lines 202d, and the four first light shielding portions 202a, that is, the second light shielding portion 202b and the third light shielding portion 202c are located in part of the meshes of the grid structure formed by the light shielding layer 202. The first direction X and the second direction Y are different. For example, the first direction X is a horizontal direction, and the second direction Y is a vertical direction. That is, the first direction X is a row direction, and the second direction Y is a column direction. Of course, the present application is not limited thereto. In the present application, the first direction X and the second direction Y may also be at other angles.

[0045] An embodiment of the present application provides a display panel, which includes a substrate and a light-shielding layer, a first semiconductor layer, and a second semiconductor layer arranged on the substrate, wherein the first semiconductor layer forms a first active portion of a driving transistor, and the second semiconductor layer forms a third active portion of a compensation transistor and a fourth active portion of a first initialization transistor. The light-shielding layer includes a first light-shielding portion arranged corresponding to the first active portion, a second light-shielding portion arranged corresponding to the third active portion, and a third light-shielding portion arranged corresponding to the fourth active portion. The second light-shielding portion can shield the third active portion, and the third light-shielding portion can shield the fourth active portion, so as to prevent the third active portion of the compensation transistor and the fourth active portion of the first initialization transistor from being affected by light, thereby improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor, so as to improve the problem of poor photosensitivity and electrical properties caused by the bottom gate loss of the oxide thin film transistor in the display device using LTPO technology.

[0046] Specifically, in the embodiment of the present application, the light-shielding portion formed by the light-shielding layer is arranged corresponding to the active portion of the transistor, which means that the light-shielding portion is at least arranged corresponding to the channel portion of the active portion of the transistor, and the projection of the light-shielding portion on the substrate overlaps with the projection of the channel portion of the transistor on the substrate. It can be understood that the active portion of each transistor includes a doping portion and a channel portion, and the channel portion is easily affected by light and causes performance changes. Therefore, the light-shielding portion can be arranged corresponding to the channel portion of the transistor. Specifically, for example, the second light-shielding portion is arranged corresponding to the third active portion of the compensation transistor, which means that the second light-shielding portion is at least arranged corresponding to the third channel portion of the compensation transistor.

[0047] In some embodiments, Figure 6 and Figure 8 As shown, the light shielding layer 202 includes a first light shielding portion 202a, a second light shielding portion 202b and a third light shielding portion 202c. The first light shielding portion 202a is arranged corresponding to the first active portion T1A of the driving transistor T1, the second light shielding portion 202b is arranged corresponding to the third active portion T3A of the compensation transistor T3, and the third light shielding portion 202c is arranged corresponding to the fourth active portion T4A of the first initialization transistor T4.

[0048] Specifically, the orthographic projection of the first active portion of the driving transistor on the substrate is located within the orthographic projection of the first light-shielding portion on the substrate, the orthographic projection of the third active portion of the compensation transistor on the substrate is located within the orthographic projection of the second light-shielding portion on the substrate, and the orthographic projection of the fourth active portion of the first initialization transistor on the substrate is located within the orthographic projection of the third light-shielding portion on the substrate, thereby preventing light from irradiating to the first active portion of the driving transistor, the third active portion of the compensation transistor and the fourth active portion of the first initialization transistor, thereby improving the electrical properties and photosensitivity of the driving transistor, the compensation transistor and the first initialization transistor.

[0049] Specifically, the area of ​​the first light-shielding portion can be greater than or equal to the area of ​​the first active portion of the driving transistor, the area of ​​the second light-shielding portion can be greater than or equal to the area of ​​the third active portion of the compensation transistor, and the area of ​​the third light-shielding portion can be greater than or equal to the area of ​​the fourth active portion of the first initialization transistor.

[0050] In some embodiments, Figure 4 , Figure 6 , Figure 8 As shown, the display panel includes a plurality of repeating units 30 arranged on an array substrate, each repeating unit 30 includes two sub-pixels 31 arranged in mirror symmetry, and in the repeating unit 30, the light shielding layer 202 includes two first light shielding portions 202a, two second light shielding portions 202b, two third light shielding portions 202c, and a first connecting line 202e and a second connecting line 202d connecting two adjacent first light shielding portions 202a, which are symmetrically arranged in the corresponding areas of the two sub-pixels 31. The second light shielding portion 202b is located between the third light shielding portion 202c and the first light shielding portion 202a, and the second light shielding portion 202b is also arranged corresponding to the gap between the two adjacent first light shielding portions 202a, and the two first light shielding portions 202a are mirror symmetric with respect to the two second light shielding portions 202b. Moreover, in the first direction X, the second light shielding portion 202b partially overlaps with the first light shielding portion 202a. The third light shielding portion 202c is located between two adjacent second connecting lines 202d. In the second direction Y, the third light shielding portion 202c partially overlaps with the first light shielding portion 202a.

[0051] The first connecting line 202e is arranged along the first direction X, the second connecting line 202d is arranged along the second direction Y, the first light shielding portion 202a is provided with a notch on the side away from the second light shielding portion 202b, and the first connecting line 202e is arranged at the notch. Two adjacent first connecting lines 202e overlap in the first direction X. The second connecting line 202d is located on the side where the center line of the first light shielding portion 202a in the second direction Y is close to the second light shielding portion 202b, and two adjacent second connecting lines 202d overlap in the second direction Y. There is a gap between the second light shielding portion 202b and the first light shielding portion 202a, the first connecting line 202e and the second connecting line 202d, so that the second light shielding portion 202b is insulated from the first light shielding portion 202a. There is a gap between the third light shielding portion 202c and the first light shielding portion 202a, the first connecting line 202e and the second connecting line 202d, so that the third light shielding portion 202c is insulated from the first light shielding portion 202a. Optionally, there is a gap between adjacent second light shielding portions 202b, there is a gap between adjacent third light shielding portions 202c, and there is also a gap between adjacent second light shielding portions 202b and third light shielding portions 202c. The second light shielding portion 202b and / or the third light shielding portion 202c are in a floating state, that is, the second light shielding portion 202b and / or the third light shielding portion 202c are not connected to an electrical signal, and the second light shielding portion 202b and / or the third light shielding portion 202c will not be applied with an electrical signal. At least one of the first light shielding portion 202a, the first connecting line 202e, and the second connecting line 202d is connected to a high potential power line.

[0052] Specifically, it can be understood that the display panel may include a plurality of repeating units arranged in an array, and the sub-pixels in each repeating unit may refer to the design in a repeating unit in the embodiment of the present application.

[0053] Specifically, it can be understood that in the display panel, two adjacent sub-pixels are symmetrically arranged to increase the aperture ratio. The embodiment of the present application realizes a mesh structure of the first light-shielding portion by symmetrically arranging the light-shielding portions and connecting the first light-shielding portions of each row and column by setting the first connecting line and the second connecting line. When a signal is input, the voltage drops of various parts of the first light-shielding portion are similar or even the same, thereby improving the uniformity of the signal and improving the display effect.

[0054] Specifically, Figure 8As shown, it can be seen that the first connecting line 202e connects the plurality of first light shielding portions 202a in the first direction X, and the second connecting line 202d connects the plurality of first light shielding portions 202a in the second direction Y. The second connecting line 202d connects the first light shielding portion 202a in the sub-pixel 31 of the current row with the first light shielding portion 202a in the sub-pixel 31 of the previous row, and the adjacent second connecting line 202d connects the first light shielding portion 202a in the sub-pixel 31 of the current row with the first light shielding portion 202a in the sub-pixel 31 of the next row, and the two first light shielding portions 202a in the repeating unit 30 are connected to each other (not shown in the figure, because the two first light shielding portions 202a in some repeating units are connected to each other to achieve a grid-like design), thereby achieving the connection of the first light shielding portions 202a in each row and column, so that the light shielding layer 202 forms a mesh structure, thereby achieving uniformity during signal transmission.

[0055] In some embodiments, Figure 4 , Figure 7 , Fig. 9 As shown, Figure 8 The difference of the illustrated embodiment is that the light shielding layer 202 further includes a third connecting line (such as Fig. 9 202f1, 202f2), in a repeating unit, at least one of the second light shielding portion 202b and the third light shielding portion 202c is connected to at least one of the first light shielding portion 202a, the first connection line 202e, and the second connection line 202d through a third connection line, such as Fig. 9 As shown, the second light shielding portion 202b is connected to the first light shielding portion 202a and the second connection line 202d through the third connection line 202f1, and the third light shielding portion 202c is connected to the second connection line 202d through the third connection line 202f2. Adjacent second light shielding portions 202b and / or adjacent third light shielding portions 202c are connected through the fourth connection line 202g, so that the second light shielding portion 202b, the third light shielding portion 202c, the third connection lines 202f1, 202f2, and the fourth connection line 202g cooperate with the first light shielding portion 202a, the first connection line 202e, and the second connection line 202d to form a grid structure, further achieving uniformity during signal transmission; and can also replace the first connection line 202e connecting two adjacent first light shielding portions 202a in the repeating unit, thereby reducing the number of first connection lines 202e. At the same time, in the second direction Y, the line widths of the second light shielding portion 202b, the third light shielding portion 202c, the third connecting lines 202f1, 202f2, and the fourth connecting line 202g are all greater than the line width of the first connecting line 202e, which can further reduce the overall impedance of the light shielding layer 202 and further improve the uniformity of the signal.

[0056] Optionally, at least one of the first light shielding portion 202a, the second light shielding portion 202b, the third light shielding portion 202c, the first connection line 202e, the second connection line 202d, and the third connection lines 202f1 and 202f2 is connected to a high potential power line.

[0057] In some embodiments, Figure 5 As shown, the gate of the switch transistor T2 is connected to the first scan signal line Pscan, the first electrode of the switch transistor T2 is connected to the data line DATA, and the second electrode of the switch transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node B; the sub-pixel 31 also includes:

[0058] A first light emitting control transistor T5, wherein a gate of the first light emitting control transistor T5 is connected to the light emitting control signal line EM, a first electrode of the first light emitting control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emitting control transistor T5 is connected to the first electrode of the driving transistor T1 to the first node A;

[0059] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0060] a second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan2, a first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and a second electrode of the second initialization transistor T7 is connected to the second electrode of the second light emission control transistor T6 to a fourth node C;

[0061] a third initialization transistor T8, wherein the gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 to the first node A;

[0062] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at the second node Q;

[0063] A boost capacitor Cboost, one plate of the boost capacitor Cboost is connected to the first scan signal line Pscan, and the other plate of the boost capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0064] Specifically, Figure 4 , Figure 5 As shown, the display panel 2 further includes a light emitting layer 23, which includes a light emitting device LED, whose anode is connected to the second electrode of the second initialization transistor T7, and whose cathode is connected to the low potential power line VSS.

[0065] In some embodiments, Figure 4 As shown, the display panel 2 further includes a first gate layer 209, a second gate layer 214, a first source-drain electrode layer 216, and a second source-drain electrode layer 218. The first gate layer 209 is disposed between the first semiconductor layer 207 and the second semiconductor layer 212, the second gate layer 214 is disposed between the second semiconductor layer 212 and the first source-drain electrode layer 216, and the first source-drain electrode layer 216 is disposed between the second gate layer 214 and the second source-drain electrode layer 218. By making the display panel include the first gate layer, the second gate layer, the first source-drain electrode layer, and the second source-drain electrode layer, the process steps of the display panel can be reduced, and the mask plates required to form the display panel can be reduced.

[0066] In some embodiments, Figures 4 to 6 , Fig.10As shown, the first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1, a second active portion T2A of the switching transistor T2, a fifth active portion T5A of the first light emission control transistor T5, a sixth active portion T6A of the second light emission control transistor T6, a seventh active portion T7A of the second initialization transistor T7, and an eighth active portion T8A of the third initialization transistor T8, the first active portion T1A of the driving transistor T1 is arranged along the first direction X, and the first active portion T1A of the driving transistor T1 is connected to the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light emission control transistor T5, and the sixth active portion T6A of the second light emission control transistor T6, the second active portion T2 of the switching transistor T2 T2A and the fifth active portion T5A of the first light emission control transistor T5 are arranged along the second direction Y, the sixth active portion T6A of the second light emission control transistor T6 and the seventh active portion T7A of the second initialization transistor T7 are arranged along the second direction Y, and the sixth active portion T6A of the second light emission control transistor T6 is connected to the seventh active portion T7A of the second initialization transistor T7, and the eighth active portion T8A of the third initialization transistor T8 is spaced apart from the first active portion T1A of the driving transistor T1, the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light emission control transistor T5, the sixth active portion T6A of the second light emission control transistor T6, and the seventh active portion T7A of the second initialization transistor T7.

[0067] Specifically, it can be seen that within one repeating unit, the seventh active portions T7A of the second initialization transistors T7 of two adjacent sub-pixels 31 are connected.

[0068] In some embodiments, Figures 4 to 7 , Fig.11 As shown, the first gate layer 209 includes a first initialization signal line VI-G, a first scanning signal line Pscan, a light-emitting control signal line EM, a fourth scanning signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light-emitting control transistor T5, a gate T6G of a second light-emitting control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8 and a first electrode Cst1 of a storage capacitor Cst. The first initialization signal line VI-G, the first scanning signal line Pscan, the first electrode Cst1 of the storage capacitor Cst, the light-emitting control signal line EM and the fourth scanning signal line Pscan2 are sequentially arranged along the second direction Y at intervals.

[0069] Specifically, from Fig.11It can be seen that the gate T2G of the switch transistor T2 is a part of the first scan signal line Pscan. It can be understood that since the gates T2G of all the switch transistors T2 in a row of sub-pixels are connected to the same first scan signal line Pscan, when the first scan signal line Pscan is formed, the part of the channel of the switch transistor T2 of each sub-pixel corresponding to the first scan signal line Pscan serves as the gate of the switch transistor T2 of each pixel unit. Therefore, two reference numerals are used to identify the same structure. Similarly, the gate T1G of the drive transistor T1 serves as both the gate and the storage capacitor Cst. The first electrode Cst1, the portion of the channel of the first light-emitting control transistor T5 corresponding to the light-emitting control signal line EM serves as the gate T5G of the first light-emitting control transistor T5, the portion of the channel of the second light-emitting control transistor T6 corresponding to the light-emitting control signal line EM serves as the gate T6G of the second light-emitting control transistor T6, the portion of the channel of the fourth scanning signal line Pscan2 corresponding to the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the portion of the channel of the third initialization transistor T8 corresponding to the fourth scanning signal line Pscan2 serves as the gate T8G of the third initialization transistor T8.

[0070] In some embodiments, Figures 4 to 7 , Fig.12 As shown, the second semiconductor layer 212 includes the third active portion T3A of the compensation transistor T3, the fourth active portion T4A of the first initialization transistor T4, and the second plate Cst2 of the storage capacitor Cst, the third active portion T3A of the compensation transistor T3 is connected to the fourth active portion T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is arranged on one side of the third active portion T3A of the compensation transistor T3 along the first direction X, and the second plate Cst of the storage capacitor Cst is provided with a through hole 331. By forming the second plate of the storage capacitor in the second semiconductor layer, the storage capacitor can be provided in the sub-pixel 31, and the second plate of the storage capacitor is provided with a through hole, so that the first electrode of the compensation transistor can be normally connected to the gate of the driving transistor.

[0071] Specifically, it can be understood that the second semiconductor layer forms the second electrode plate of the storage capacitor. Therefore, it is necessary to make the second electrode plate of the storage capacitor have better electrical properties. The second electrode plate of the storage capacitor can be doped to keep the electrical properties of the second electrode plate of the storage capacitor consistent with or even higher than the electrical properties of the doped part of the active part, so that the electrical properties of the storage capacitor are better.

[0072] Specifically, by providing a through hole on the second electrode plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second electrode plate of the storage capacitor and be connected to the gate of the driving transistor, so that the sub-pixel 31 works normally.

[0073] Specifically, Fig.11 , Fig.12 As shown, the first gate layer 209 also includes a first plate Cboost1 of the boost capacitor Cboost, the second semiconductor layer 212 also includes a second plate Cboost2 of the boost capacitor Cboost, the overlapping portion of the first scanning signal line Pscan and the fourth active portion T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the fourth active portion T4A of the first initialization transistor T4 and the first scanning signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0074] In some embodiments, Figures 4 to 7 , Fig.13 As shown, the second gate layer 214 includes a second scan signal line Nscan1, a third scan signal line Nscan2, a third initialization signal line VI3, a gate T3G of the compensation transistor T3 and a gate T4G of the first initialization transistor T4, and the third scan signal line Nscan2, the second scan signal line Nscan1 and the third initialization signal line VI3 are arranged in sequence along the second direction Y.

[0075] In some embodiments, Figures 4 to 7 , Fig.14 As shown, the first source-drain layer 216 includes a first data connection line L1, a first electrode T2S of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a second electrode T3D of a compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of a first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T5D of a first light-emitting control transistor T5, a first electrode T6S of a second light-emitting control transistor T6, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of a second initialization transistor T7, a first electrode T8S of a third initialization transistor T8, a second electrode T8D of a third initialization transistor T8, and a second initialization signal line VI-ANO.

[0076] Specifically, Fig.14 As shown, it can be understood that since the electrodes of each transistor are connected together, in order to improve the aperture ratio in actual design, the electrodes of each transistor share the same structure. Fig.14 In the figure, multiple reference numerals are used to identify the same structure. For example, a structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. Figure 5As can be seen in , this is the location where the second node Q is connected. Similarly, other structures can also serve as multiple electrodes, and the location of each node can be determined accordingly.

[0077] Specifically, Fig.11 , Fig.14 As shown, the first initialization signal line VI-G is connected to the first electrode T4S of the first initialization transistor T4 through the first connection terminal K1. In view of the small spacing between the projections of the first initialization signal line VI-G and the third scanning signal line Nscan2 on the substrate, a via hole is directly formed in the region corresponding to the first electrode of the first initialization transistor to connect the first initialization signal line, which may cause the via hole to be formed on the third scanning signal line Nscan2. Therefore, the first connection terminal K1 may be arranged on the first source-drain layer, and the first electrode of the first initialization transistor T4 may be connected through the first connection terminal K1. At the same time, a via hole is formed in the region corresponding to the first connection terminal K1, so that the first connection terminal K1 is connected to the first initialization signal line VI-G, thereby realizing the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. The first connection terminal K1 is arranged on the symmetry axis of the two symmetrically arranged sub-pixels 31, so that the first electrode of the first initialization transistor T4 in the two symmetrically arranged sub-pixels 31 can be connected to the first initialization signal line through the same first connection terminal K1, thereby reducing the number of via holes and improving the yield.

[0078] Specifically, Figure 6 , Figure 7 , Fig.14 , Fig.15 As shown, since the high potential power line VDD has no overlap with the first electrode T5S of the first light emitting control transistor T5, and the high potential power line VDD will be connected to one plate of the storage capacitor, it is necessary to set a second connection terminal K2 so that the second connection terminal K2 is connected to the high potential power line VDD, so that the signal of the high potential power line VDD can be transmitted to the first electrode T5S of the first light emitting control transistor T5, and a third connection terminal K3 can be set so that the third connection terminal K3 is connected to the second plate Cst2 of the storage capacitor Cst, thereby realizing the connection between one plate of the storage capacitor Cst, the first light emitting control transistor T5 and the high potential power line VDD.

[0079] Specifically, Figures 6 to 14 As shown, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a fourth connection terminal K4 can be set on the first source and drain layer. The fourth connection terminal K4 passes through the through hole 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0080] In some embodiments, Figures 4 to 15As shown, within the repeating unit 30, the second source-drain layer 218 includes two data lines DATA, an initialization signal connection line L3, two high-potential power lines VDD and a second data connection line L2. The two data lines DATA are arranged in a mirror-symmetrical manner, the two high-potential power lines VDD are arranged in a mirror-symmetrical manner, and the initialization signal connection line L3 and the second data connection line L2 are arranged in a mirror-symmetrical manner.

[0081] Specifically, the high potential power line VDD may be connected to the second connection terminal K2 through the via hole, and the data line may be connected to the first electrode T2S of the switch transistor T2 through the via hole.

[0082] Specifically, Fig.15 As shown, the second source-drain electrode layer 218 further includes a fifth connection terminal K5 , and the fifth connection terminal K5 is connected to the second electrode T6D of the second light emitting control transistor T6 and an electrode of the light emitting device.

[0083] Specifically, it can be understood that due to the design of the sub-pixel 31 in the display area shown in the embodiment of the present application, the connection points of some routing lines are located in the non-display area. Therefore, some routing lines may not be connected together, but in fact, they will be connected. For example, in order to adopt the technology of setting the fan-out line in the display area (Fanout In AA, FIAA), the data line DATA will be set along the first direction. The first data connection line L1 set along the second direction and the second data connection line L2 set along the second direction will be connected, and will be connected to the data line outside the display area. However, the embodiment of the present application shows the design of the sub-pixel 31, and therefore, its connection points are not shown, but in fact, they will be connected.

[0084] At the same time, in order to realize the mesh structure design of the initialization signal line, the embodiment of the present application will set the initialization signal connection line L3, and the initialization signal connection line L3 can realize the mesh structure design of at least one of the first initialization signal line, the second initialization signal line and the third initialization signal line. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0085] For example, the first initialization signal line will be connected to the initialization signal connection line outside the display area, thereby realizing the mesh structure design of the first initialization signal line. Similarly, the mesh structure design of the second initialization signal line and the third initialization signal line can be realized. However, the embodiments of the present application are not limited to this. Some initialization signal connection lines can be connected to one of the first initialization signal line, the second initialization signal line and the third initialization signal line, and some initialization signal connection lines can be connected to another one of the first initialization signal line, the second initialization signal line and the third initialization signal line. Some initialization signal connection lines can also be connected to another one of the first initialization signal line, the second initialization signal line and the third initialization signal line, thereby realizing the mesh structure design of each initialization signal line.

[0086] In some embodiments, Fig.16 As shown, Fig.16 The arrangement position of the first via hole 341 is shown. The first via hole 341 refers to a via hole etched from the first source and drain electrode layer to the first semiconductor layer or the first gate layer.

[0087] In some embodiments, Fig.17 As shown, Fig.17 The configuration position of the second via hole 342 is shown. The second via hole 342 refers to a via hole etched from the first source and drain electrode layer to the second semiconductor layer or the second gate layer.

[0088] In some embodiments, Fig.18 As shown, Fig.18 The configuration position of the third via hole 343 is shown. The third via hole 343 refers to a via hole etched from the second source and drain electrode layer to the first source and drain electrode layer.

[0089] In some embodiments, Fig.19 As shown, Fig.19 The fourth via hole 344 is shown as a location where the fourth via hole 344 is etched from the anode of the light emitting layer to the second source and drain layer.

[0090] Specifically, Figure 4 As shown, the display panel 2 further includes a first barrier layer 203 , a second barrier layer 205 , a buffer layer 206 , a first gate insulating layer 208 , a first interlayer insulating layer 211 , a second gate insulating layer 213 , a second interlayer insulating layer 215 , a first planarizing layer 217 and a second planarizing layer 219 .

[0091] Specifically, Figure 4 As shown, the display panel 2 further includes a light-emitting layer 23 , and the light-emitting layer 23 includes a pixel electrode layer 221 , a pixel definition layer 222 , a light-emitting material layer, a common electrode layer and a support column 223 .

[0092] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0093] Specifically, the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2 and the light-emitting control signal line EM can be respectively connected to different gate driving circuits. Specifically, five groups of gate driving circuits can be used to output signals to the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2 and the light-emitting control signal line EM, respectively. Among them, the gate driving circuit connected to the first scanning signal line Pscan can adopt bilateral driving, and the other gate driving circuits adopt unilateral driving.

[0094] Specifically, the material of the first semiconductor layer includes silicon semiconductor material, and specifically may be low temperature polysilicon.

[0095] Specifically, the material of the second semiconductor layer includes an oxide semiconductor material, specifically a metal oxide semiconductor material, more specifically, indium gallium zinc oxide.

[0096] Specifically, the material of the light shielding layer includes metal material.

[0097] Specifically, the driving transistor, the switching transistor, the first light emitting transistor, the second light emitting transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0098] Specifically, the above embodiments respectively describe the display panel in detail from the sub-pixel structure, film layer structure, specific structure, materials, and potential of each layer in the display panel. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined.

[0099] Meanwhile, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0100] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: A plurality of sub-pixels are included, each sub-pixel includes a driving transistor, a compensation transistor, a first initialization transistor and a storage capacitor, the first active portion of the driving transistor is located in a first semiconductor layer, the third active portion of the compensation transistor, the fourth active portion of the first initialization transistor and one plate of the storage capacitor are all located in a second semiconductor layer, the other plate of the storage capacitor is located in a first gate layer, and the first semiconductor layer, the second semiconductor layer and the first gate layer are all arranged in different layers; The display panel also includes a light-shielding layer, which includes a first light-shielding portion arranged corresponding to the first active portion, a second light-shielding portion arranged corresponding to the third active portion, and a third light-shielding portion arranged corresponding to the fourth active portion; the light-shielding layer also includes a first connecting line and a second connecting line, and at least some adjacent first light-shielding portions are connected via the first connecting line or the second connecting line.

2. The display panel according to claim 1, characterized in that: The first connecting line extends along a first direction, and the second connecting line extends along a second direction, the first direction and the second direction are different, the first connecting line is connected to two first light-shielding portions adjacently arranged in the first direction, and the second connecting line is connected to two first light-shielding portions adjacently arranged in the second direction; the second light-shielding portion and the third light-shielding portion are both located in an area surrounded by two adjacent first connecting lines, two adjacent second connecting lines and four first light-shielding portions.

3. The display panel according to claim 1, characterized in that: There are gaps between the second light shielding portion and the first light shielding portion, the first connecting line and the second connecting line, there are gaps between the third light shielding portion and the first light shielding portion, the first connecting line and the second connecting line, and the second light shielding portion and / or the third light shielding portion are in a floating state.

4. The display panel according to claim 1, characterized in that: The light shielding layer further includes a third connecting line, and at least one of the second light shielding portion and the third light shielding portion is connected to at least one of the first light shielding portion, the first connecting line, and the second connecting line through the third connecting line.

5. The display panel according to claim 4, characterized in that: At least one of the first light shielding portion, the second light shielding portion, the third light shielding portion, the first connection line, the second connection line, and the third connection line is connected to a high potential power line.

6. The display panel according to claim 4, characterized in that: The second light-shielding portion is connected to the first light-shielding portion and the second light-shielding portion through the third connecting line, and the third light-shielding portion is connected to the second light-shielding portion through the third connecting line; the light-shielding layer also includes a fourth connecting line, and adjacent second light-shielding portions and / or adjacent third light-shielding portions are connected through the fourth connecting line.

7. The display panel according to claim 2, characterized in that: The second light shielding portion partially overlaps with the first light shielding portion in the first direction, the third light shielding portion is located between two adjacent second connecting lines, and the third light shielding portion partially overlaps with the first light shielding portion in the second direction.

8. The display panel according to claim 7, characterized in that: The first light shielding portion is provided with a notch at a side away from the second light shielding portion, and the first connecting line is provided at the notch.

9. The display panel according to any one of claims 1 to 8, characterized in that: The display panel includes a plurality of repeating units arranged in an array, each of the repeating units includes two sub-pixels arranged in mirror symmetry, and within the repeating unit, the light-shielding layer includes two first light-shielding portions, two second light-shielding portions, two third light-shielding portions, and the first connecting line and the second connecting line connecting two adjacent first light-shielding portions, which are symmetrically arranged in areas corresponding to the two sub-pixels, the second light-shielding portion is located between the third light-shielding portion and the first light-shielding portion, and the second light-shielding portion is also arranged corresponding to a gap between two adjacent first light-shielding portions, and the two first light-shielding portions are mirror symmetric with respect to the two second light-shielding portions.

10. The display panel according to claim 9, characterized in that: Each of the sub-pixels further comprises: a switching transistor, wherein the switching transistor is connected to the driving transistor at a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, another electrode of the compensation transistor and the driving transistor are connected to a third node, a gate of the switching transistor is connected to a first scanning signal line, a first electrode of the switching transistor is connected to a data line, and a second electrode of the switching transistor and a first electrode of the driving transistor are connected to a first node; a gate of the compensation transistor is connected to a second scanning signal line, a first electrode of the compensation transistor and a gate of the driving transistor are connected to a second node, and a second electrode of the compensation transistor is connected to a second electrode of the driving transistor; a gate of the first initialization transistor is connected to a third scanning signal line, a first electrode of the first initialization transistor is connected to a first initialization signal line, and a second electrode of the first initialization transistor and a gate of the driving transistor are connected to a second node; a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode of the first light emission control transistor is connected to a high potential power supply line, and a second electrode of the first light emission control transistor is connected to a first node with a first electrode of the driving transistor; a second light emission control transistor, wherein a gate of the second light emission control transistor is connected to the light emission control signal line, and a first electrode of the second light emission control transistor and a second electrode of the driving transistor are connected to a third node; a second initialization transistor, wherein a gate of the second initialization transistor is connected to a fourth scanning signal line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emission control transistor are connected to a fourth node; a third initialization transistor, wherein a gate of the third initialization transistor is connected to the fourth scanning signal line, a first electrode of the third initialization transistor is connected to the third initialization signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor at a first node; One plate of the storage capacitor is connected to the high potential power line, the other plate of the storage capacitor is connected to the gate of the driving transistor at a second node, and a through hole is provided on the plate connected to the high potential power line; A boost capacitor, one plate of the boost capacitor is connected to the first scanning signal line, and the other plate of the boost capacitor is connected to the second electrode of the first initialization transistor.

11. The display panel according to claim 10, characterized in that: The first semiconductor layer further includes a fifth active portion of the first light emission control transistor, a sixth active portion of the second light emission control transistor, a seventh active portion of the second initialization transistor, and an eighth active portion of the third initialization transistor, the first active portion is arranged along a first direction, and the first active portion connects the second active portion, the fifth active portion, and the sixth active portion, the second active portion and the fifth active portion are arranged along a second direction, the sixth active portion and the seventh active portion are arranged along the second direction, and the sixth active portion is connected to the seventh active portion, and the eighth active portion is arranged at intervals with the first active portion, the third active portion, the fifth active portion, the sixth active portion, and the seventh active portion; the display panel further includes: The first gate layer is arranged between the first semiconductor layer and the second semiconductor layer, the first gate layer includes the first initialization signal line, the first scan signal line, the light emission control signal line, the fourth scan signal line, the gate of the driving transistor, the gate of the switch transistor, the gate of the first light emission control transistor, the gate of the second light emission control transistor, the gate of the second initialization transistor, the gate of the third initialization transistor and the first plate of the storage capacitor, the first initialization signal line, the first scan signal line, the first plate of the storage capacitor, the light emission control signal line and the fourth scan signal line are sequentially arranged along the second direction; a second gate layer, arranged at a side of the second semiconductor layer away from the first gate layer, the second gate layer comprising the second scanning signal line, the third scanning signal line, the third initialization signal line, the gate of the compensation transistor and the gate of the first initialization transistor, the third scanning signal line, the second scanning signal line and the third initialization signal line being arranged in sequence along the second direction; A first source-drain electrode layer is arranged on a side of the second gate layer away from the second semiconductor layer, the first source-drain electrode layer comprising a first data connection line, a first electrode of the switch transistor, a first electrode and a second electrode of the compensation transistor, a first electrode and a second electrode of the first initialization transistor, a first electrode and a second electrode of the first light emission control transistor, a first electrode and a second electrode of the second light emission control transistor, a first electrode and a second electrode of the second initialization transistor, a first electrode and a second electrode of the third initialization transistor, and a second initialization signal line; A second source-drain electrode layer is arranged on a side of the first source-drain electrode layer away from the second gate layer, the second source-drain electrode layer comprising the data line, the high potential power line, the second data connection line and the initialization signal connection line extending along the second direction; Wherein, each of the repeating units also includes two mirror-symmetrical data lines, two mirror-symmetrical high-potential power lines, and mirror-symmetrical second data connection lines and initialization signal connection lines. In the repeating unit, the high-potential power line is located between the second data connection line and the initialization signal connection line, and the second data connection line and the initialization signal connection line are both located between the high-potential power line and the data line.

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