Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a substrate and at least one first pixel circuit, the substrate comprises a display area, and the display area comprises a first display area; at least one first pixel circuit is arranged on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit comprises at least one first transistor, the first transistor comprises a transparent first active layer and a first grid electrode arranged on the side, away from the substrate, of the first active layer in an insulating mode, and the first grid electrode comprises a first light-transmitting conductive layer.

Description

Technical Field

[0001] The present invention relates to display technology, and more particularly to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] The transmittance of the circuit structure layer of the display substrate is low. Although it will not affect the efficiency of the upper light-emitting structure layer, it will cause a great loss in the signal required by components such as under-screen sensors and cameras. Summary of the invention

[0004] The present application provides a display substrate, including: A substrate, comprising a display area, wherein the display area comprises a first display area; At least one first pixel circuit is disposed on the substrate, and an orthographic projection of the first pixel circuit on the substrate is located in the first display area; The first pixel circuit includes at least one first transistor, the first transistor includes a transparent first active layer, and a first gate insulated and arranged on a side of the first active layer away from the substrate, the first gate includes a first light-transmitting conductive layer.

[0005] In some exemplary embodiments, the first transistor further includes a first bottom gate, the first bottom gate is insulated and disposed on a side of the first active layer close to the substrate, and the first bottom gate includes a second light-transmitting conductive layer.

[0006] In some exemplary embodiments, the first transistor further includes a first source and a first drain, and the first source and / or the first drain includes a third light-transmitting conductive layer.

[0007] In some exemplary embodiments, the first pixel circuit includes at least one second transistor, the second transistor including a second gate and a transparent second active layer; The second gate is located on a side of the second active layer away from the substrate, the second gate comprises a first metal layer and a fourth light-transmitting conductive layer, and the fourth light-transmitting conductive layer is located on a side of the first metal layer close to the substrate; The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate.

[0008] In some exemplary embodiments, the fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0009] In some exemplary embodiments, the second transistor further includes a second bottom gate, the second bottom gate is located on a side of the second active layer close to the substrate, the second bottom gate includes a second metal layer and a fifth light-transmitting conductive layer, the fifth light-transmitting conductive layer is located on a side of the second metal layer close to the substrate; The orthographic projection of the second metal layer on the substrate is located within the orthographic projection of the fifth light-transmitting conductive layer on the substrate, and the fifth light-transmitting conductive layer and the second light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0010] In some exemplary embodiments, the second active layer includes a first region, a channel region, and a second region sequentially arranged in a first direction, and the first direction is parallel to the substrate; The fourth light-transmitting conductive layer and the first metal layer are both configured to extend along a second direction, the first metal layer is centrally arranged on the fourth light-transmitting conductive layer in the first direction, two ends of the fourth light-transmitting conductive layer in the first direction respectively protrude from two ends of the first metal layer in the first direction, and the second direction is parallel to the substrate and perpendicular to the first direction.

[0011] In some exemplary embodiments, the channel region includes a first auxiliary channel region, a main channel region, and a second auxiliary channel region sequentially arranged in the first direction; The orthographic projection of the first metal layer on the substrate is arranged to overlap with the orthographic projection of the main channel region on the substrate, and not overlap with the orthographic projections of the first auxiliary channel region and the second auxiliary channel region on the substrate; Orthographic projections of the main channel region, the first auxiliary channel region, and the second auxiliary channel region on the substrate all overlap with an orthographic projection of the fourth light-transmitting conductive layer on the substrate.

[0012] In some exemplary embodiments, the first gate further includes a third metal layer, the third metal layer is located on a side of the first light-transmitting conductive layer away from the substrate, and an orthographic projection of the third metal layer on the substrate is located within an orthographic projection of the first light-transmitting conductive layer on the substrate; The orthographic projection area of ​​the first metal layer on the substrate is S1, and the orthographic projection area of ​​the third metal layer on the substrate is S2, where S1>S2.

[0013] In some exemplary embodiments, the width of the first metal layer is set to D1, the width of the third metal layer is set to D2, D1>D2, D1-D2≤0.5 μm.

[0014] In some exemplary embodiments, the first active layer and the second active layer are configured to extend along a first direction, the first gate and the second gate are configured to extend along a second direction, and the first direction and the second direction are parallel to the substrate and perpendicular to each other; The size of the third metal layer in the second direction is L1, the size of the first light-transmitting conductive layer in the second direction is L2, and L1<L2; The third metal layer is centrally arranged on the first light-transmitting conductive layer in the second direction, and two ends of the first light-transmitting conductive layer in the second direction respectively protrude from two ends of the third metal layer in the second direction.

[0015] In some exemplary embodiments, one end of the first light-transmitting conductive layer in the second direction is a first end, one end of the third metal layer in the second direction close to the first end is a second end, and a distance between the first end and the second end in the second direction is set to L3, L3 ≥ 1 μm.

[0016] In some exemplary embodiments, the first pixel circuit includes at least one third transistor, the third transistor including a third gate and a third active layer; The material of the third active layer includes polysilicon; The third gate is located on a side of the third active layer away from the substrate, the third gate includes a fourth metal layer and a sixth light-transmitting conductive layer, the sixth light-transmitting conductive layer is located on a side of the fourth metal layer close to the substrate, and the orthographic projection of the fourth metal layer on the substrate is located within the orthographic projection of the sixth light-transmitting conductive layer on the substrate.

[0017] In some exemplary embodiments, the first active layer includes a first region, a channel region, and a second region sequentially arranged along a first direction, the channel region includes a third end close to the first region and a fourth end close to the second region in the first direction, and the first direction is parallel to the substrate; The first bottom gate further includes a fifth metal layer, the fifth metal layer is located on a side of the second light-transmitting conductive layer away from the substrate, and an orthographic projection of the fifth metal layer on the substrate is located within an orthographic projection of the second light-transmitting conductive layer on the substrate; The fifth metal layer is located between the third end and the fourth end in the first direction, the distance between the fifth metal layer and the third end in the first direction is greater than 0, and the distance between the fifth metal layer and the fourth end in the first direction is greater than 0.

[0018] In some exemplary embodiments, the first display area includes at least one sub-pixel area, the sub-pixel area includes a main display area, a high-transmittance wiring area and a high-transmittance display area, the high-transmittance display area is located on at least one side of the main display area, the high-transmittance wiring area is located between the high-transmittance display area and the main display area, and the orthographic projection of the first transistor on the substrate is located in the high-transmittance display area.

[0019] In some exemplary embodiments, the first pixel circuit further includes a plurality of signal lines, the plurality of signal lines include at least one transparent first signal line, and an orthographic projection of the first signal line on the substrate is located in the high-transmittance wiring area.

[0020] In some exemplary embodiments, the plurality of signal lines include at least one second signal line, the second signal line includes a first routing layer and a transparent second routing layer, the first routing layer is located on a side of the second routing layer away from the substrate, and the orthographic projection of the second signal line on the substrate is located in the high-transparency routing area.

[0021] In some exemplary embodiments, a light emitting structure layer is further included, wherein the light emitting structure layer includes a plurality of first light emitting devices and a pixel definition layer; The pixel definition layer is provided with a plurality of first pixel openings for arranging a plurality of the first light emitting devices, and the first light emitting devices are arranged to be electrically connected to the first pixel circuits in a one-to-one correspondence; The orthographic projection of the first pixel opening on the substrate is arranged to overlap with the main display area and the high-transmittance display area; Alternatively, the orthographic projection of the first pixel opening on the substrate is arranged to overlap with the main display area and not overlap with the high-transmittance display area.

[0022] In some exemplary embodiments, a material of the first light-transmitting conductive layer includes a transparent conductive oxide, and the transparent conductive oxide includes indium tin oxide.

[0023] The present application provides a method for preparing a display substrate, comprising: At least one first pixel circuit is formed on a substrate, the substrate includes a display area, and the display area includes a first display area; at least one first pixel circuit is arranged on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit includes at least one first transistor, the first transistor includes a transparent first active layer, and a first gate insulated and arranged on a side of the first active layer away from the substrate, the first gate includes a first light-transmitting conductive layer.

[0024] In some exemplary embodiments, forming at least one first pixel circuit on a substrate includes: The first transistor and the second transistor are formed synchronously on the substrate, the second transistor includes a second gate, the second gate includes a first metal layer and a fourth light-transmitting conductive layer, the fourth light-transmitting conductive layer is located on a side of the first metal layer close to the substrate, the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate, and the fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0025] An embodiment of the present application provides a display device, including the above-mentioned display substrate.

[0026] The display substrate of the embodiment of the present application replaces the gate of the oxide thin-film transistor with a transparent conductive material, which can improve the transmittance of the local under-screen recognition area, reduce the loss of the signal required by components such as under-screen sensors and cameras, and can adapt to the integration of under-screen camera modules and under-screen sensor modules. The display substrate of the embodiment of the present application also uses transparent conductive materials for the source and drain of the oxide thin-film transistor to make the entire oxide thin-film transistor transparent, further improving the transmittance. The display substrate of the embodiment of the present application may reduce the size of the metal part of the gate of the oxide thin-film transistor, while minimizing the number of polysilicon thin-film transistors and increasing the number of oxide thin-film transistors, which also further improves the transmittance.

[0027] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0029] Figure 1 is a structural schematic diagram of a display device; Figure 2 It is a schematic diagram of a planar structure of a display substrate; Figure 3 is a schematic diagram of a cross-sectional structure of a display device; Figure 4 is a schematic diagram of a display substrate of this exemplary embodiment; Figure 5 for Figure 4 A schematic cross-sectional view of a circuit structure layer of a display substrate; Figure 6 is a schematic diagram of an equivalent circuit of a first pixel circuit of this exemplary embodiment; Figure 7 for Figure 5 A local enlarged schematic diagram of point a in FIG. Figure 8 for Figure 7 Schematic diagram of the second gate in FIG. Fig. 9 is a first schematic diagram of another first transistor of this exemplary embodiment; Fig.10 is a second schematic diagram of another first transistor of this exemplary embodiment; Fig.11 is a first schematic diagram of yet another first transistor according to this exemplary embodiment; Fig.12 is a second schematic diagram of yet another first transistor according to this exemplary embodiment; Fig.13 for Figure 5 A local enlarged schematic diagram of point b in FIG. Fig.14 is a first preparation schematic diagram of a display substrate of this exemplary embodiment; Fig.15 is a second schematic diagram of preparing a display substrate according to the exemplary embodiment; Fig.16 is a third schematic diagram of preparing a display substrate of this exemplary embodiment; Fig.17 is a fourth schematic diagram of preparing a display substrate according to the exemplary embodiment; Fig.18 is a fifth schematic diagram of preparing a display substrate according to this exemplary embodiment; Fig.19 is a sixth schematic diagram of manufacturing a display substrate according to the exemplary embodiment; Fig. 20 is a seventh preparation schematic diagram of a display substrate of this exemplary embodiment; Fig.21 is an eighth preparation schematic diagram of a display substrate of this exemplary embodiment; Fig. 22 is a ninth schematic diagram of preparing a display substrate according to the exemplary embodiment; Fig.23 is a tenth schematic diagram of manufacturing a display substrate of the exemplary embodiment; Fig.24 is an eleventh preparation schematic diagram of a display substrate of this exemplary embodiment; Fig.25 is a twelfth preparation schematic diagram of a display substrate of the exemplary embodiment; Fig.26 is a thirteenth preparation schematic diagram of a display substrate of the exemplary embodiment; Fig. 27 This is a fourteenth preparation schematic diagram of a display substrate according to the exemplary embodiment. DETAILED DESCRIPTION

[0030] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0031] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0032] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0033] This exemplary embodiment provides a display substrate, including: A substrate, comprising a display area, wherein the display area comprises a first display area; At least one first pixel circuit is disposed on the substrate, and an orthographic projection of the first pixel circuit on the substrate is located in the first display area; The first pixel circuit includes at least one first transistor, the first transistor includes a transparent first active layer, and a first gate insulated and arranged on a side of the first active layer away from the substrate, the first gate includes a first light-transmitting conductive layer.

[0034] In some exemplary embodiments, the first transistor further includes a first bottom gate, the first bottom gate is insulated and disposed on a side of the first active layer close to the substrate, and the first bottom gate includes a second light-transmitting conductive layer.

[0035] In some exemplary embodiments, the first transistor further includes a first source and a first drain, and the first source and / or the first drain includes a third light-transmitting conductive layer.

[0036] In some exemplary embodiments, the first pixel circuit includes at least one second transistor, the second transistor including a second gate and a transparent second active layer; The second gate is located on a side of the second active layer away from the substrate, the second gate comprises a first metal layer and a fourth light-transmitting conductive layer, and the fourth light-transmitting conductive layer is located on a side of the first metal layer close to the substrate; The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate.

[0037] In some exemplary embodiments, the fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0038] In some exemplary embodiments, the second transistor further includes a second bottom gate, the second bottom gate is located on a side of the second active layer close to the substrate, the second bottom gate includes a second metal layer and a fifth light-transmitting conductive layer, the fifth light-transmitting conductive layer is located on a side of the second metal layer close to the substrate; The orthographic projection of the second metal layer on the substrate is located within the orthographic projection of the fifth light-transmitting conductive layer on the substrate, and the fifth light-transmitting conductive layer and the second light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0039] In some exemplary embodiments, the second active layer includes a first region, a channel region, and a second region sequentially arranged in a first direction, and the first direction is parallel to the substrate; The fourth light-transmitting conductive layer and the first metal layer are both configured to extend along a second direction, the first metal layer is centrally arranged on the fourth light-transmitting conductive layer in the first direction, two ends of the fourth light-transmitting conductive layer in the first direction respectively protrude from two ends of the first metal layer in the first direction, and the second direction is parallel to the substrate and perpendicular to the first direction.

[0040] In some exemplary embodiments, the channel region includes a first auxiliary channel region, a main channel region, and a second auxiliary channel region sequentially arranged in the first direction; The orthographic projection of the first metal layer on the substrate is arranged to overlap with the orthographic projection of the main channel region on the substrate, and not overlap with the orthographic projections of the first auxiliary channel region and the second auxiliary channel region on the substrate; Orthographic projections of the main channel region, the first auxiliary channel region, and the second auxiliary channel region on the substrate all overlap with an orthographic projection of the fourth light-transmitting conductive layer on the substrate.

[0041] In some exemplary embodiments, the first gate further includes a third metal layer, the third metal layer is located on a side of the first light-transmitting conductive layer away from the substrate, and an orthographic projection of the third metal layer on the substrate is located within an orthographic projection of the first light-transmitting conductive layer on the substrate; The orthographic projection area of ​​the first metal layer on the substrate is S1, and the orthographic projection area of ​​the third metal layer on the substrate is S2, where S1>S2.

[0042] In some exemplary embodiments, the width of the first metal layer is set to D1, the width of the third metal layer is set to D2, D1>D2, D1-D2≤0.5 μm.

[0043] In some exemplary embodiments, the first active layer and the second active layer are configured to extend along a first direction, the first gate and the second gate are configured to extend along a second direction, and the first direction and the second direction are parallel to the substrate and perpendicular to each other; The size of the third metal layer in the second direction is L1, the size of the first light-transmitting conductive layer in the second direction is L2, and L1<L2; The third metal layer is centrally arranged on the first light-transmitting conductive layer in the second direction, and two ends of the first light-transmitting conductive layer in the second direction respectively protrude from two ends of the third metal layer in the second direction.

[0044] In some exemplary embodiments, one end of the first light-transmitting conductive layer in the second direction is a first end, one end of the third metal layer in the second direction close to the first end is a second end, and a distance between the first end and the second end in the second direction is set to L3, L3 ≥ 1 μm.

[0045] In some exemplary embodiments, the first pixel circuit includes at least one third transistor, the third transistor including a third gate and a third active layer; The material of the third active layer includes polysilicon; The third gate is located on a side of the third active layer away from the substrate, the third gate includes a fourth metal layer and a sixth light-transmitting conductive layer, the sixth light-transmitting conductive layer is located on a side of the fourth metal layer close to the substrate, and the orthographic projection of the fourth metal layer on the substrate is located within the orthographic projection of the sixth light-transmitting conductive layer on the substrate.

[0046] In some exemplary embodiments, the first active layer includes a first region, a channel region, and a second region sequentially arranged along a first direction, the channel region includes a third end close to the first region and a fourth end close to the second region in the first direction, and the first direction is parallel to the substrate; The first bottom gate further includes a fifth metal layer, the fifth metal layer is located on a side of the second light-transmitting conductive layer away from the substrate, and an orthographic projection of the fifth metal layer on the substrate is located within an orthographic projection of the second light-transmitting conductive layer on the substrate; The fifth metal layer is located between the third end and the fourth end in the first direction, the distance between the fifth metal layer and the third end in the first direction is greater than 0, and the distance between the fifth metal layer and the fourth end in the first direction is greater than 0.

[0047] In some exemplary embodiments, the first display area includes at least one sub-pixel area, the sub-pixel area includes a main display area, a high-transmittance wiring area and a high-transmittance display area, the high-transmittance display area is located on at least one side of the main display area, the high-transmittance wiring area is located between the high-transmittance display area and the main display area, and the orthographic projection of the first transistor on the substrate is located in the high-transmittance display area.

[0048] In some exemplary embodiments, the first pixel circuit further includes a plurality of signal lines, the plurality of signal lines include at least one transparent first signal line, and an orthographic projection of the first signal line on the substrate is located in the high-transmittance wiring area.

[0049] In some exemplary embodiments, a material of the first light-transmitting conductive layer includes a transparent conductive oxide, and the transparent conductive oxide includes indium tin oxide.

[0050] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels ij, i and j may be natural numbers, at least one sub-pixel ij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel circuit, and the pixel circuit is connected to the scan signal line, the light emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of unit lines, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0051] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device, and the circuit unit may include at least a pixel circuit, and the pixel circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line, and the pixel circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0052] In some exemplary embodiments, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a square shape, etc., which is not limited in the present disclosure. In some exemplary embodiments, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged along a straight line, but are not limited thereto. For example, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged in a non-linear manner such as a square shape. In some exemplary embodiments, the pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square shape, etc., which is not limited in the present disclosure.

[0053] Figure 3 This is a schematic diagram of a cross-sectional structure of a display device, illustrating a structure that uses white light combined with a color film to achieve full color. Figure 3 As shown, the display device may include: a substrate 100, a circuit structure layer 200 disposed on the substrate 100, a light emitting structure layer 300 disposed on a side of the circuit structure layer 200 away from the substrate 100, a first encapsulation layer 400 disposed on a side of the light emitting structure layer 300 away from the substrate 100, a color film structure layer 500 disposed on a side of the first encapsulation layer 400 away from the substrate 100, a second encapsulation layer 600 disposed on a side of the color film structure layer 500 away from the substrate 100, and a cover layer 700 disposed on a side of the second encapsulation layer 600 away from the substrate 100. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in the present disclosure.

[0054] In some exemplary embodiments, the substrate 100 may be a polyimide (PI) substrate, but is not limited thereto, and may be, for example, a glass substrate. The circuit structure layer 200 may be prepared on the substrate 100 by a silicon semiconductor process (such as a CMOS process), and the circuit structure layer 200 may include a plurality of circuit units, and the circuit units may include at least a pixel circuit, and the pixel circuit is connected to the scanning signal line and the data signal line respectively, and the pixel circuit may include a plurality of transistors and a storage capacitor, Figure 3 Only one transistor is used as an example. The transistor may include a gate electrode, a first electrode S, and a second electrode. The gate electrode, the first electrode, and the second electrode may be connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0055] In an exemplary embodiment, the light emitting structure layer 300 may include a plurality of light emitting devices, and the light emitting devices may include at least an anode, an organic light emitting layer, and a cathode. The anode may be connected to the second electrode of the transistor through a connecting electrode, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the cathode is connected to the second power line. The organic light emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0056] In an exemplary embodiment, the first encapsulation layer 400 and the second encapsulation layer 600 may be formed by thin film encapsulation (TFE) to ensure that external water vapor cannot enter the light-emitting structure layer. The cover layer 700 may be made of glass or a flexible plastic such as colorless polyimide.

[0057] In an exemplary embodiment, the color film structure layer 500 may include a black matrix (BM) and a color filter (CF), the color filters are respectively arranged in the red sub-pixel, the green sub-pixel and the blue sub-pixel, and the white light emitted by the light-emitting device is filtered into red (R) light, green (G) light and blue (B) light, and the black matrix may be located between adjacent color filters.

[0058] The applicant found that the display device with under-screen sensor devices and under-screen camera devices cannot completely solve the fundamental problem of low transmittance of the circuit structure layer. Among the various film layer structures of the display substrate, the transmittance of the circuit structure layer is the lowest, only about 10%. Although it will not affect the efficiency of the light-emitting structure layer, its low transmittance will cause a great loss of the signal required by components such as under-screen sensors and cameras. Although some display products will use external or internal pixel solutions to alleviate the above problems, both will greatly reduce the display quality and affect the display effect of the under-screen recognition area.

[0059] The technical solution of the embodiment of the present invention is described in detail below through specific embodiments.

[0060] Figure 4 is a schematic diagram of a display substrate of this exemplary embodiment, Figure 5 for Figure 4 The schematic cross-sectional view of the circuit structure layer of the display substrate in FIG. 1 , the present exemplary embodiment provides a display substrate such as Figure 4 and Figure 5 As shown, the display substrate may include a substrate 100 and at least one first pixel circuit 800. The substrate 100 may include a display area AA, and the display area AA may include a first display area A1. At least one first pixel circuit 800 may be arranged on the substrate 100, and the orthographic projection of the first pixel circuit 800 on the substrate 100 is located in the first display area A1. The first pixel circuit 800 includes at least one first transistor 201, and the first transistor 201 includes a transparent first active layer 213, and a first gate 214 insulated and arranged on the side of the first active layer 213 away from the substrate 100, and the first gate 214 includes a first light-transmitting conductive layer 229. Therefore, in the display substrate of this example, the material of the first gate 214 of the oxide thin film transistor (first transistor 201) is a transparent conductive material, which can improve the transmittance of the local under-screen recognition area (i.e., the first display area A1), reduce the loss of the signal required by the under-screen sensing and camera components, and can adapt to the solution of integrating the under-screen camera module and the under-screen sensor module.

[0061] In some exemplary embodiments, Figure 4 and Figure 5As shown, the substrate 100 may include a display area AA and a frame area BB surrounding the periphery of the display area AA. The display area AA may include a first display area A1 and a second display area A0. The second display area A0 may surround the first display area A1, but is not limited thereto. For example, the first display area A1 may be located on one side of the second display area A0. The display substrate may have an under-screen sensor device or an under-screen camera device, or a device integrating sensing and camera functions. The orthographic projection of the above device on the substrate 100 may be located in the first display area A1. Light needs to pass through the portion of the display substrate in the first display area A1. Therefore, improving the transmittance of the portion of the display substrate in the first display area A1 can allow more light to reach the under-screen sensing and camera components, thereby reducing the loss of the signal required by the under-screen sensing and camera components.

[0062] In some exemplary embodiments, Figure 4 and Figure 5 As shown, the display area AA may include a plurality of sub-pixel areas arranged in an array, and the sub-pixels in the display substrate are arranged one by one corresponding to the sub-pixel areas. The plurality of sub-pixel areas may be evenly distributed in the first display area A1 and the second display area A0, and the sub-pixel area in the first display area A1 may be the first sub-pixel area A1. The display area AA may be a flat area, and the display substrate may have a plurality of sub-pixels constituting a pixel array in the display area AA, and the plurality of sub-pixels may be configured to display dynamic pictures or still images. The display area AA may be referred to as an active area (Active Area). In some examples, the display area AA may be a rectangle, but is not limited thereto. For example, the display area AA may be other shapes such as a circle or an ellipse.

[0063] In some exemplary embodiments, Figure 3 , Figure 4 and Figure 5 As shown, the sub-pixel may include an electrically connected light-emitting device 301 and a pixel circuit 800, the light-emitting structure layer 300 may be provided with a plurality of light-emitting devices 301 and a pixel definition layer 302, and the pixel definition layer 302 has a pixel opening. The light-emitting device 301 of the sub-pixel located in the first display area A1 may be a first light-emitting device (not shown in the figure), the pixel circuit 800 of the sub-pixel located in the first display area A1 may be a first pixel circuit 801, the pixel opening located in the first display area A1 may be a first pixel opening, the first light-emitting device may be arranged corresponding to the first pixel opening, and the first light-emitting device may be connected to the first pixel circuit 801 in a one-to-one correspondence.

[0064] Figure 6 is a schematic diagram of an equivalent circuit of a first pixel circuit of this exemplary embodiment. In some exemplary embodiments, as Figure 6As shown, the first pixel circuit 801 may include 7 transistors (transistors T1, T2 to T7), a storage capacitor C and multiple signal lines (data signal line D, a first scan signal line S1, a second scan signal line S2, an initial signal line INIT, a first power line VDD, a second power line VSS and a light emitting control signal line E).

[0065] In some exemplary embodiments, Figure 6 As shown, the gate electrode of transistor T1 is connected to the second scanning signal line S2, the first electrode of transistor T1 is connected to the initial signal line INIT, and the second electrode of transistor T1 is connected to the first node N1. The gate electrode of transistor T2 is connected to the first scanning signal line S1, the first electrode of transistor T2 is connected to the third node N3, and the second electrode of transistor T2 is connected to the first node N1. The gate electrode of transistor T3 is connected to the first node N1, the first electrode of transistor T3 is connected to the second node N2, and the second electrode of transistor T3 is connected to the third node N3. The gate electrode of transistor T4 is connected to the first scanning signal line S1, the first electrode of transistor T4 is connected to the data signal line D, and the second electrode of transistor T4 is connected to the second node N2. The gate electrode of transistor T5 is connected to the light emitting control signal line E, the first electrode of transistor T5 is connected to the first power supply line VDD, and the second electrode of transistor T5 is connected to the second node N2. The gate electrode of transistor T6 is connected to the light emitting control signal line E, the first electrode of transistor T6 is connected to the third node N3, and the second electrode of transistor T6 is connected to the fourth node N4 (i.e., the first electrode of the light emitting element). The gate electrode of transistor T7 is connected to the first scanning signal line S1 or the reset control signal line Reset, the first electrode of transistor T7 is connected to the initial signal line INIT, and the second electrode of transistor T7 is connected to the fourth node N4. The first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the first node N1.

[0066] In some exemplary embodiments, Figure 4 and Figure 6 As shown, the seven transistors (T1 to T7) can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, transistors T1 to transistor T7 can include P-type transistors and N-type transistors.

[0067] In some exemplary embodiments, the seven transistors (T1 to T7) may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate, that is, LTPS+Oxide (referred to as LTPO) display substrate, can take advantage of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality. The display substrate of this example can use LTPO technology.

[0068] In some exemplary embodiments, Figure 5 and Figure 6 As shown, the seven transistors (T1 to T7) can be divided into a first transistor 201, a second transistor 202 and a third transistor 203 according to different materials, wherein the first transistor 201 and the second transistor 202 are both oxide thin film transistors, and the third transistor 203 can be a low temperature polysilicon thin film transistor. In this example, the transistor T3 can be the third transistor 203, that is, it can be a low temperature polysilicon thin film transistor, and the other transistors (T1, T2, T4, T5, T6 and T7) can be the first transistor 201 or the second transistor 202, that is, the transistors (T1, T2, T4, T5, T6 and T7) can be oxide thin film transistors. However, it is not limited to this, for example, the seven transistors (T1 to T7) are all oxide thin film transistors, and the seven transistors (T1 to T7) can be divided into the first transistor 201 and the second transistor 202 according to different materials, or the seven transistors (T1 to T7) can all be the first transistor 201, or all be the second transistor 202.

[0069] In some exemplary embodiments, Figure 5As shown, the first active layer 213 of the first transistor 201 serves as the active layer of the transistor, and the material of the first active layer 213 may include an oxide semiconductor material. The first gate electrode 214 of the first transistor 201 may serve as the gate electrode of the transistor, and the first gate electrode 214 may be a first light-transmitting conductive layer 229, and the material of the first light-transmitting conductive layer 229 may include a transparent conductive oxide (Transparent Conducting Oxide, referred to as TCO). In this example, the material of the first light-transmitting conductive layer 229 may be indium tin oxide (Indium Tin Oxide, referred to as ITO), but is not limited thereto, and may be, for example, indium zinc oxide (Indium Zinc Oxide, full name IZO) and other conductive transparent oxides. The first transistor 201 also includes a first source 216, a first drain 217 and a first bottom gate 215. The first source 216 and the first drain 217 are electrically connected to the first active layer 213 through vias, respectively. The first source 216 can be used as the first electrode of the transistor, and the first drain 217 can be used as the second electrode of the transistor. The material of the first source 216 and / or the first drain 217 includes a transparent conductive material. In this example, the first source 216 and the first drain 217 both include a third light-transmitting conductive layer 253. The material of the third light-transmitting conductive layer 253 can be consistent with the material of the first light-transmitting conductive layer 229, but is not limited thereto. For example, the material of the third light-transmitting conductive layer 253 of the first source 216 and the first drain 217 can be inconsistent with the material of the first light-transmitting conductive layer 229. The first bottom gate 215 may be transparent, and the first bottom gate 215 may include a second light-transmitting conductive layer 215-1. The material of the second light-transmitting conductive layer 215-1 may be consistent with the material of the first light-transmitting conductive layer 229, and may be indium tin oxide, but is not limited thereto, and may be other conductive transparent oxides. The first bottom gate 215 is insulated and arranged on the side of the first active layer 213 close to the substrate 100, and the first bottom gate 215 may serve as another gate of the transistor. Thus, the first gate 214, the first source 216, the first drain 217 and the first bottom gate 215 are all made of transparent materials, so that the entire first transistor 201 has no structure that blocks light, and the transmittance of the first transistor 201 is high.

[0070] Figure 7 for Figure 5 In the locally enlarged schematic diagram of a in FIG. , in some exemplary embodiments, as Figure 5 and Figure 7As shown, the second transistor 202 may include a transparent second active layer 217, a second gate 218, a second bottom gate 219, a second source 220, and a second drain 221. The second active layer 217 serves as the active layer of the transistor, and the material of the second active layer 217 may include an oxide semiconductor material. The material of the second active layer 217 may be the same as the material of the first active layer 213 and arranged in the same city. The second gate 218 may be located on the side of the second active layer 217 away from the substrate 100, and the second gate 218 may serve as the gate electrode of the transistor. The second source electrode 220 and the second drain electrode 221 can be electrically connected to the second active layer 217 through vias, respectively. The second source electrode 220 can serve as the first electrode of the transistor, and the second drain electrode 221 can serve as the second electrode of the transistor. The materials of the second source electrode 220 and the second drain electrode 221 can both include metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb).

[0071] In some exemplary embodiments, Figure 5 and Figure 7 As shown, the second gate 218 may include a first metal layer 231 and a fourth light-transmitting conductive layer 232 arranged in a stacked manner, the fourth light-transmitting conductive layer 232 is located on a side of the first metal layer 231 close to the substrate 100, and the orthographic projection of the first metal layer 231 on the substrate 100 is located within the orthographic projection of the fourth light-transmitting conductive layer 232 on the substrate 100. The fourth light-transmitting conductive layer 232 and the first light-transmitting conductive layer 229 are made of the same material and are arranged in the same layer, and the material of the first metal layer 231 may include a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0072] Figure 8 for Figure 7 Schematic diagram of the second gate in some exemplary embodiments, such as Figure 5 , Figure 7 and Figure 8As shown, the second active layer 217 may include a first region 217-2, a channel region 217-1, and a second region 217-3 arranged in sequence in the first direction, the first metal layer 231 and the fourth light-transmitting conductive layer 232 both extend along the second direction, the first direction and the second direction are both parallel to the substrate 100, the first direction is perpendicular to the second direction, and the third direction is perpendicular to the substrate 100. The second source electrode 220 may be connected to the first region 217-2 of the second active layer 217 through a via hole, and the second drain electrode 221 may be connected to the second region 217-3 of the second active layer 217 through a via hole. Both ends of the fourth light-transmitting conductive layer 232 in the first direction are flush with both ends of the channel region 217-1 in the first direction, that is, the width of the fourth light-transmitting conductive layer 232 is equal to the size of the channel region 217-1 in the first direction, the length of the fourth light-transmitting conductive layer 232 may be the size of the fourth light-transmitting conductive layer 232 in the second direction, and the width of the fourth light-transmitting conductive layer 232 may be the size of the fourth light-transmitting conductive layer 232 in the first direction. The orthographic projection of the first metal layer 231 on the substrate 100 is located within the orthographic projection of the fourth light-transmitting conductive layer 232 on the substrate 100 .

[0073] In some exemplary embodiments, Figure 5 , Figure 7 and Figure 8As shown, the channel region 217-1 may include a first auxiliary channel region 217-5, a main channel region 217-4, and a second auxiliary channel region 217-6 arranged in sequence in the first direction, and the orthographic projections of the first auxiliary channel region 217-5, the main channel region 217-4, and the second auxiliary channel region 217-6 on the substrate 100 overlap with the orthographic projection of the fourth light-transmitting conductive layer 232 on the substrate 100; the orthographic projection of the first metal layer 231 on the substrate 100 overlaps with the orthographic projection of the main channel region 217-4 on the substrate 100, and does not overlap with the orthographic projections of the first auxiliary channel region 217-5 and the second auxiliary channel region 217-6 on the substrate 100. The width of the fourth light-transmitting conductive layer 232 may be greater than the width of the first metal layer 231, the width of the first metal layer 231 may be the size of the first metal layer 231 in the first direction, and the first metal layer 231 is centrally arranged on the fourth light-transmitting conductive layer 232 in the first direction. The two ends of the fourth light-transmitting conductive layer 232 in the first direction protrude from the two ends of the first metal layer 231 in the first direction, for example, the fourth light-transmitting conductive layer 232 includes two ends in the first direction set as the sixth end 235 and the second end 239, one end of the first metal layer 231 in the first direction may be the fifth end 237, the sixth end 235 protrudes from the fifth end 237, and the distance between the sixth end 235 and the fifth end 237 in the first direction may be D5, D5>0. Thus, the second gate 218 composed of the fourth light-transmitting conductive layer 232 and the first metal layer 231 can improve the control capability of the channel region 217-1 without losing transmittance, and the fourth light-transmitting conductive layer 232 can prevent further diffusion of ions into the channel region 217-2 when doping and conducting the first region 217-2 and the second region 217-3, so that the channel region 217-2 has a strong control compensation capability.

[0074] In some exemplary embodiments, Figure 5 , Figure 7 and Figure 8 As shown, the second bottom gate 219 may be located on the side of the second active layer 217 close to the substrate 100, and the second bottom gate 219 may include a second metal layer 233 and a fifth light-transmitting conductive layer 234 arranged in a stacked manner, and the fifth light-transmitting conductive layer 234 is located on the side of the second metal layer 233 close to the substrate 100. The fifth light-transmitting conductive layer 234 and the first bottom gate 215 are made of the same material and arranged in the same layer, and the material of the second metal layer 233 may include a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). The orthographic projection of the second metal layer 233 on the substrate 100 is located within the orthographic projection of the fifth light-transmitting conductive layer 234 on the substrate 100.

[0075] Fig. 9is a first schematic diagram of another first transistor of this exemplary embodiment, Fig.10 is a second schematic diagram of another first transistor of this exemplary embodiment. In some exemplary embodiments, as Fig. 9 and Fig.10 As shown, the first gate 214 includes a third metal layer 238 and a first light-transmitting conductive layer 229 arranged in a stacked manner, the third metal layer 238 is located on the side of the first light-transmitting conductive layer 229 away from the substrate 100, and the orthographic projection of the third metal layer 238 on the substrate 100 is located within the orthographic projection of the first light-transmitting conductive layer 229 on the substrate 100. The material of the third metal layer 238 may include a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first gate 214 of the first transistor is added with the third metal layer 238, which can enhance the driving capability of the first transistor.

[0076] In some exemplary embodiments, Fig. 9 and Fig.10 As shown, the third metal layer 238 and the first light-transmitting conductive layer 229 both extend in the second direction, the length of the third metal layer 238 may be the dimension L1 of the third metal layer 238 in the second direction, the length of the first light-transmitting conductive layer 229 may be the dimension L2 of the first light-transmitting conductive layer 229 in the second direction, and the length of the third metal layer 238 is less than the length of the first light-transmitting conductive layer 229, that is, L1<L2. The third metal layer 238 is centrally arranged on the first light-transmitting conductive layer 229 in the second direction, and the two ends of the first light-transmitting conductive layer 229 in the second direction protrude from the two ends of the third metal layer 238 in the second direction respectively.

[0077] In some exemplary embodiments, Fig. 9 and Fig.10 As shown, the width of the third metal layer 238 may be the dimension D2 of the third metal layer 238 in the first direction, the width of the first light-transmitting conductive layer 229 may be the dimension D4 of the first light-transmitting conductive layer 229 in the first direction, and the width of the third metal layer 238 is less than the width of the first light-transmitting conductive layer 229, that is, D2<D4. In this example, the third metal layer 238 is centrally arranged on the first light-transmitting conductive layer 229 in the first direction, so that the two ends of the first light-transmitting conductive layer 229 in the first direction protrude respectively from the two ends of the third metal layer 238 in the first direction.

[0078] In some exemplary embodiments, Figures 7 to 10As shown, the orthographic projection area of ​​the first metal layer 231 on the substrate 100 is S1, and the orthographic projection area of ​​the first metal layer 231 of the third metal layer 238 on the substrate 100 is S2, S1>S2. The width of the first metal layer 231 is set to D1, and the width of the third metal layer 238 is set to D2, D1>D2, D1-D2≤0.5μm. The size (L4) of the first metal layer 231 in the second direction is greater than the size (L1) of the third metal layer 238 in the second direction. One end of the first light-transmitting conductive layer 229 in the second direction is the first end 240, and the end of the third metal layer 238 in the second direction close to the first end 240 is the second end 239. The distance between the first end 240 and the second end 239 in the second direction is set to L3, L3≥1μm, and the edge of the first light-transmitting conductive layer 229 can form an edge relative to the first metal layer 231.

[0079] Fig.11 is a first schematic diagram of yet another first transistor according to this exemplary embodiment, Fig.12 is a second schematic diagram of another first transistor of this exemplary embodiment. In some exemplary embodiments, as Figure 5 , Fig.11 and Fig.12 As shown, the first active layer 213 includes a first region 213-2, a channel region 213-1, and a second region 213-2 sequentially arranged along the first direction, and the two ends of the channel region 213-1 in the first direction are respectively flush with the two ends of the first light-transmitting conductive layer 229 in the first direction. The channel region 213-1 includes a third end 213-4 close to the first region 213-2 and a fourth end 213-5 close to the second region 213-3 in the first direction. The first bottom gate 215 also includes a fifth metal layer 215-2, and the fifth metal layer 215-2 is located on the side of the second light-transmitting conductive layer 215-1 away from the substrate 100, and the orthographic projection of the fifth metal layer 215-2 on the substrate 100 is located within the orthographic projection of the second light-transmitting conductive layer on the substrate 100.

[0080] In some exemplary embodiments, Fig.11 and Fig.12 As shown, the fifth metal layer 215-2 is located between the third end 213-4 and the fourth end 213-5 in the first direction, that is, the width (D6) of the fifth metal layer 215-2 is less than the length (D7) of the channel region 213-1. The distance between the fifth metal layer 215-2 and the third end 213-4 in the first direction is greater than 0, that is, D8>0; the distance between the fifth metal layer 215-2 and the fourth end 213-5 in the first direction is greater than 0, that is, D9>0. As a result, the fifth metal layer 215-2 is inwardly contracted relative to the channel region 213-1, so that the stress performance of the transistor is guaranteed without losing transmittance.

[0081] Fig.13for Figure 5 The local enlarged schematic diagram of point b in FIG. Figure 5 and Fig.13 As shown, in some exemplary embodiments, the third transistor 203 may include a third gate 223, a third active layer 222, a third bottom gate 224, a third source 225, and a third drain 226. The material of the third active layer 222 includes polysilicon, the third gate 223 is located on the side of the third active layer 222 away from the third active layer 222, the third gate 223 may include a fourth metal layer 241 and a sixth light-transmitting conductive layer 242 arranged in a stacked manner, the sixth light-transmitting conductive layer 242 may be made of a transparent material, and the material of the sixth light-transmitting conductive layer 242 may be consistent with the material of the first light-transmitting conductive layer 229. The sixth light-transmitting conductive layer 242 is located on the side of the fourth metal layer 241 close to the substrate 100. The third bottom gate 224 may be a metal material, and the third bottom gate 224 is located on the side of the third active layer 222 close to the substrate 100.

[0082] In some exemplary embodiments, Figure 5 As shown, the first pixel circuit 800 also includes a plurality of signal lines 230, and the plurality of signal lines 230 include at least one transparent first signal line 227, and at least one second signal line 228. The second signal line 228 includes a first routing layer 228-1 and a transparent second routing layer 228-2, the first routing layer 228-1 is located on the side of the second routing layer 228-2 away from the substrate 100, and the materials of the first signal line 227 and the second routing layer 228-2 can be transparent conductive materials. Some of the plurality of signal lines (data signal line D, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power line VDD, second power line VSS and light emitting control signal line E) can be the first signal line 227, and the other part can be the second signal line 228.

[0083] In some exemplary embodiments, Figure 4 and Figure 5 As shown, each sub-pixel area A2 includes a main display area A3, a high-transmittance wiring area A5 and a high-transmittance display area A4, and the high-transmittance display area A4 is located on at least one side of the main display area A3. In this example, the high-transmittance display area A4 is located on one side of the main display area A3 in the first direction, and the high-transmittance wiring area A5 is located between the high-transmittance display area A4 and the main display area A3. The positive projection of the first transistor 201 on the substrate 100 is located in the high-transmittance display area A4 to improve the transmittance of the high-transmittance display area A4. The positive projections of the plurality of signal lines 230 on the substrate 100 are located in the high-transmittance wiring area A5, for example, the positive projection of the first signal line 227 on the substrate 100 is located in the high-transmittance wiring area A5.

[0084] In some exemplary embodiments, Figure 4 and Figure 5As shown, the display substrate has at least two third transistors 203, at least one third transistor 203 has an orthographic projection on the substrate 100 located in the high-transmittance display area A4, and at least one third transistor 203 has an orthographic projection on the substrate 100 located in the main display area A3. The third transistor 203 whose orthographic projection on the substrate 100 is located in the high-transmittance display area A4 may be a fourth transistor 203-1, and the third transistor 203 whose orthographic projection on the substrate 100 is located in the main display area A3 may be a fifth transistor 203-2.

[0085] In some exemplary embodiments, Figure 4 and Figure 5 As shown, the circuit structure layer 200 further includes a first connection layer 243, a second connection layer 244, a third connection layer 245 and a fourth connection layer 246. The first connection layer 243 can be connected to the third drain 226 of the fourth transistor 203-1 through a via hole; the second connection layer 244 can be connected to a signal line 230 through a via hole; the third connection layer 245 and the fourth connection layer 246 can be connected to the third source 225 and the third drain 226 of the fifth transistor 203-2 through via holes. The materials of the first connection layer 243 and the second connection layer 244 can be metal materials, and the materials of the first connection layer 243 and the second connection layer 244 are the same and arranged in the same layer; the materials of the third connection layer 245 and the fourth connection layer 246 are the same and are transparent conductive materials, and the third connection layer 245 and the fourth connection layer 246 can be arranged in the same layer as the first source 216 and the first drain 217 of the first transistor 201.

[0086] In some exemplary embodiments, Figure 3 , Figure 4 and Figure 5 As shown, the display substrate also includes a light emitting structure layer 300, and the light emitting structure layer 300 may include a plurality of first light emitting devices (not shown in the figure) and a pixel definition layer 302. The pixel definition layer 302 is provided with a plurality of first pixel openings (not shown in the figure) for arranging a plurality of first light emitting devices (not shown in the figure), and the plurality of first light emitting devices are arranged to be electrically connected to the first pixel circuit 800 in a one-to-one correspondence. The orthographic projection of the first pixel opening on the substrate 100 is arranged to overlap with the main display area A3 and the high-transmittance display area A4, forming a built-in pixel. Alternatively, the orthographic projection of the first pixel opening on the substrate 100 is arranged to overlap with the main display area A3 and not overlap with the high-transmittance display area A4, forming an external pixel.

[0087] In some exemplary embodiments, Figure 5 , Figure 7 and Fig.13As shown, the circuit structure layer 200 of the display area may include: a first conductive layer disposed on the substrate 100, and a first semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, and a tenth conductive layer arranged in sequence away from the substrate 100. The first conductive layer may include a third bottom gate 224 of the third transistor 203. The first semiconductor layer may include a third active layer 222 of the third transistor 203. The second conductive layer may include a sixth light-transmitting conductive layer 242 of the third transistor 203, and a first signal line 227-1. The third conductive layer may include a fourth metal layer 241 of the third transistor 203. The fourth conductive layer may include a second light-transmitting conductive layer 215-1 of the first transistor 201, a fifth light-transmitting conductive layer 234 of the second transistor 202, and a second wiring layer 228-2 of the second signal line 228. The fifth conductive layer may include a second metal layer 233 of the second transistor 202, and a first wiring layer 228-1 of the second signal line 228. The second semiconductor layer may include a first active layer 213 of the first transistor 201 and a second active layer 217 of the second transistor 202. The sixth conductive layer may include a first light-transmitting conductive layer 229 of the first transistor 201 and a fourth light-transmitting conductive layer 232 of the second transistor 202, and a first signal line 227-2. The seventh conductive layer may include a first metal layer 231 of the second transistor 202. The eighth conductive layer may include a second source 220 and a second drain 221 of the second transistor 202, and a third source 225 and a third drain 226 of the third transistor 203. The ninth conductive layer may include a first drain 216 and a second drain 217 of the first transistor 201, and a third connection portion 245, a fourth connection portion 246, and a first signal line 227-3. The tenth conductive layer may include a first connection portion 243 and a second connection portion 244. A first insulating layer 204 is provided between the first conductive layer and the first semiconductor layer; a second insulating layer 205 is provided between the first semiconductor layer and the second conductive layer; a third insulating layer 206 is provided between the third conductive layer and the fourth conductive layer; a fourth insulating layer 207 is provided between the fifth conductive layer and the second semiconductor layer; a fifth insulating layer 208 is provided between the second semiconductor layer and the sixth conductive layer; a sixth insulating layer 209 is provided between the seventh conductive layer and the eighth conductive layer; a seventh insulating layer 210 is provided between the eighth conductive layer and the ninth conductive layer; an eighth insulating layer 211 is provided between the ninth conductive layer and the tenth conductive layer; and a side of the tenth conductive layer away from the substrate 100 is provided on the ninth insulating layer 212. The above insulating layers may be inorganic insulating layers or organic insulating layers. The material of the inorganic insulating layer may include inorganic film layers such as silicon oxide (SiO) and silicon nitride (SiN); and the material of the organic insulating layer may include resin materials.

[0088] The following is an exemplary description of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate 100100 of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0089] In some exemplary embodiments, the preparation process of the display substrate can be obtained as follows Figure 5 The display substrate shown in the figure specifically includes the following steps.

[0090] Step 1: forming a first conductive layer pattern.

[0091] Fig.14 is a first schematic diagram of preparing a display substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 5 and Fig.14 As shown, forming the first conductive layer pattern may include: A first metal film is deposited on the substrate 100 and patterned to form a first conductive layer pattern. The first conductive layer pattern includes a third bottom gate 224 of the third transistor 203. The third bottom gate 224 can be connected to a fixed point signal in the peripheral area to ensure that the hysteresis characteristics of the third transistor 203 are maintained within an acceptable range of the pixel circuit.

[0092] Step 2: forming a first semiconductor layer pattern.

[0093] Fig.15 is a second schematic diagram of preparing a display substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 5 , Fig.14 and Fig.15 As shown, forming the first semiconductor layer pattern may include: An insulating material is deposited on the pattern formed in the previous step to form a first insulating layer 204, and then an amorphous silicon film is deposited on the first insulating layer 204. The amorphous silicon film is crystallized by excimer laser annealing (ELA) to form a polycrystalline silicon film, and then the polycrystalline silicon film is subjected to a patterning process to form a first semiconductor layer pattern. The first semiconductor layer pattern may include the undoped third active layer 222 in the third transistor 203.

[0094] Step 3: forming a second conductive layer pattern and a third conductive layer pattern.

[0095] Fig.16 is a third schematic diagram of preparing a display substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 5 , Fig.15 and Fig.16 As shown, forming the second semiconductor layer pattern and the third conductor layer pattern may include: An insulating material is deposited on the pattern formed in the above step to form a second insulating layer 205, and then an oxide film is deposited and patterned to form a second conductive layer pattern. Subsequently, a second metal film is deposited and patterned to form a third conductive layer pattern. Next, the first and second regions of the undoped third active layer 222 are conductorized using the second semiconductor layer pattern and the third conductor layer pattern as masks. The second conductive layer pattern may include the sixth light-transmitting conductive layer 242 of the third transistor 203, and the first signal line 227-1, and the third conductive layer pattern may include the fourth metal layer 241 of the third transistor 203, and the sixth light-transmitting conductive layer 242 and the fourth metal layer 241 may constitute the third gate 223 of the third transistor 203.

[0096] Step 4: forming a fourth conductive layer pattern and a fifth conductive layer pattern.

[0097] Fig.17 is a fourth schematic diagram of manufacturing a display substrate of this exemplary embodiment. In some exemplary embodiments, Figure 5 , Fig.16 and Fig.17 As shown, forming the fourth conductive layer pattern and the fifth conductive layer pattern may include: An insulating material is deposited on the pattern formed in the above step to form a third insulating layer 206, and then an oxide film is deposited and the oxide film is patterned to form a fourth conductive layer pattern. Subsequently, a third metal film is deposited and the third metal film is patterned to form a fifth conductive layer pattern. The fourth conductive layer pattern may include a second light-transmitting conductive layer 215-1 of the first transistor 201, a fifth light-transmitting conductive layer 234 of the second transistor 202, and a second wiring layer 228-2 of the second signal line 228. The fifth conductive layer pattern may include a second metal layer 233 of the second transistor 202, and a first wiring layer 228-1 of the second signal line 228. The fifth light-transmitting conductive layer 234 and the second metal layer 233 constitute the second bottom gate 219 of the second transistor 202, the first wiring layer 228-1 and the second wiring layer 228-2 constitute the second signal line 228, and the second light-transmitting conductive layer 215-1 constitutes the first bottom gate 215 of the first transistor 201.

[0098] Step 5: Forming a second semiconductor layer pattern.

[0099] Fig.18 is a fifth schematic diagram of manufacturing a display substrate of this exemplary embodiment. In some exemplary embodiments, Figure 5 , Fig.17 and Fig.18 As shown, forming the second semiconductor layer pattern may include: An insulating material is deposited on the pattern formed in the previous step to form a fourth insulating layer 207 , and then an oxide film is deposited and patterned to form a second semiconductor layer pattern. The second semiconductor layer pattern may include an undoped first active layer 213 in the first transistor 201 and an undoped second active layer 217 in the second transistor 202 .

[0100] Step 6: forming a sixth conductive layer pattern and a seventh conductive layer pattern.

[0101] Fig.19 is a sixth schematic diagram of manufacturing a display substrate of this exemplary embodiment. In some exemplary embodiments, Figure 5 , Fig.18 and Fig.19 As shown, forming the sixth conductive layer pattern and the seventh conductive layer pattern may include: An insulating material is deposited on the pattern formed in the above step to form a fifth insulating layer 208, and then an oxide film is deposited and patterned to form a sixth conductive layer pattern. Subsequently, a fourth metal film is deposited and patterned to form a seventh conductive layer pattern. Next, the first and second regions of the undoped first active layer 213 and the second active layer 217 are conductorized using the sixth conductive layer pattern and the seventh conductive layer pattern as masks. The sixth conductive layer pattern may include a first light-transmitting conductive layer 229 of the first transistor 201, a fourth light-transmitting conductive layer 232 of the second transistor 202, and a first signal line 227-2, and the seventh conductive layer pattern may include a first metal layer 231 of the second transistor 202. The fourth light-transmitting conductive layer 232 and the first metal layer 231 constitute the second gate 218 of the second transistor 202, and the first light-transmitting conductive layer 229 constitutes the first bottom gate 214 of the first transistor 201.

[0102] Fig. 20 is a seventh schematic diagram of manufacturing a display substrate of this exemplary embodiment, Fig.21 is an eighth schematic diagram of manufacturing a display substrate according to the exemplary embodiment. Fig. 22 is a ninth schematic diagram of manufacturing a display substrate of the present exemplary embodiment. In some exemplary embodiments, Figure 20 to Figure 22 As shown, in the process of forming the sixth conductive layer pattern and the seventh conductive layer pattern, the sixth conductive layer pattern is formed first. In this process, as shown in FIG. Fig. 20 As shown in FIG. 1 , the first light-transmitting conductive layer 229 of the first transistor 201 and the fourth light-transmitting conductive layer 232 of the second transistor 202 are formed simultaneously. A fourth metal film is then deposited, and the fourth metal film is coated, exposed, developed, and etched to form a first pattern. Fig.21 As shown, the first pattern includes the first metal layer 231 of the second transistor 202, and the first covering layer 247, the first covering layer 247 covers the side of the first light-transmitting conductive layer 229 away from the substrate, and the second gate of the second transistor and the first gate of the first transistor are formed. Fig. 22 As shown, the first active layer 213 and the second active layer 217 are doped and implanted with conductors using the second gate and the first gate as masks. Finally, a second covering layer 248 is formed through a patterning process. The second covering layer 248 covers the second gate of the second transistor but does not cover the first gate of the first transistor, thereby forming a photoresist protection for the second gate of the second transistor. The first covering layer 247 is then etched away.

[0103] Fig.23 is a tenth schematic diagram of manufacturing a display substrate of this exemplary embodiment, Fig.24is an eleventh preparation schematic diagram of a display substrate of the present exemplary embodiment. In some exemplary embodiments, during the formation of the sixth conductive layer pattern and the seventh conductive layer pattern, first, Fig.23 As shown, a first oxide film 249 and a fourth metal film 250 are deposited on the fifth insulating layer 208, and after an etching process, a first oxide film 249 and a fourth metal film 250 are formed. Fig.21 As shown, the second gate of the second transistor 202 (ie, the first metal layer 231 and the fourth light-transmitting conductive layer 231), the first covering layer 247, and the first light-transmitting conductive layer 229 covered by the first covering layer 247 are formed. Fig. 22 As shown, the first active layer 213 and the second active layer 217 are doped and implanted as conductors using the second gate and the first gate as masks; or Fig.24 As shown, a third covering layer 251 is covered on the second gate and the first covering layer 247, and the third covering layer 251 is used as a mask to dope the first active layer 213 and the second active layer 217, and implant conductors. Finally, a second covering layer 248 is formed through a patterning process, and the second covering layer 248 covers the second gate of the second transistor, but does not cover the first gate of the first transistor, forming a photoresist protection for the second gate of the second transistor, and then the first covering layer 247 is removed by etching.

[0104] Fig.25 is a twelfth preparation schematic diagram of a display substrate of the present exemplary embodiment. In some exemplary embodiments, during the formation of the sixth conductive layer pattern and the seventh conductive layer pattern, first, Fig. 20 As shown, the first light-transmitting conductive layer 229 and the fourth light-transmitting conductive layer 232 are formed simultaneously. Fig.25 As shown, a fourth covering layer 252 is formed on the first light-transmitting conductive layer 229 and the fourth light-transmitting conductive layer 232 by a patterning process, and the fourth covering layer 252 covers the end surfaces of the first light-transmitting conductive layer 229 and the fourth light-transmitting conductive layer 232 away from the substrate 100. The fourth covering layer 252 is used as a mask to dope the first active layer 213 and the second active layer 217, and inject conductors. Finally, a second covering layer 248 is formed by a patterning process, and the second covering layer 248 covers the second gate of the second transistor, but does not cover the first gate of the first transistor, forming a photoresist protection for the second gate of the second transistor, and then etching to remove the first covering layer 247. Finally, a fourth metal film is deposited, and the fourth metal film is coated, exposed, developed, and etched to form the first metal layer 231 of the second transistor 202.

[0105] Step 7: Forming an eighth conductive layer pattern.

[0106] Fig.26 is a thirteenth schematic diagram of manufacturing a display substrate of the present exemplary embodiment. In some exemplary embodiments, as Figure 5 , Fig.19 and Fig.26 As shown, forming the eighth conductive layer pattern may include: An insulating material is deposited on the pattern formed in the previous step to form a sixth insulating layer 209, and then a fifth metal film is deposited and patterned to form an eighth conductive layer pattern. The eighth conductive layer pattern may include the second source 220 and the second drain 221 of the second transistor 202, and the third source 225 and the third drain 226 of the third transistor 203.

[0107] Step 8: forming a ninth conductive layer pattern.

[0108] Fig. 27 is a fourteenth schematic diagram of manufacturing a display substrate of the present exemplary embodiment. In some exemplary embodiments, as Figure 5 , Fig.26 and Fig. 27 As shown, forming the ninth conductive layer pattern may include: An insulating material is deposited on the pattern formed in the previous step to form a seventh insulating layer 210, and then an oxide film is deposited and patterned to form a ninth conductive layer pattern. The ninth conductive layer pattern may include the first drain 216 and the second drain 217 of the first transistor 201, as well as the third connection portion 245, the fourth connection portion 246, and the first signal line 227-3.

[0109] Step 9: forming a tenth conductive layer pattern.

[0110] In some exemplary embodiments, Figure 5 and Fig. 27 As shown, forming the tenth conductive layer pattern may include: An insulating material is deposited on the pattern formed in the previous step to form an eighth insulating layer 211 , and then a sixth metal film is deposited and patterned to form a tenth conductive layer pattern. The tenth conductive layer pattern may include a first connection portion 243 and a second connection portion 244 .

[0111] At this point, after the circuit structure layer is prepared, the light emitting structure layer, the packaging structure layer, the optical structure layer and the cover plate are subsequently formed to obtain the above-mentioned display substrate.

[0112] In some exemplary embodiments, a display device includes the above-mentioned display substrate. The display device provided by the embodiments of the present disclosure can be applied to electronic devices, which can be mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, car displays, wearable devices, and any products or components with display functions, such as smart watches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc.

[0113] In some exemplary embodiments, a method for preparing a display substrate includes: At least one first pixel circuit is formed on a substrate, the substrate includes a display area, and the display area includes a first display area; at least one first pixel circuit is arranged on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit includes at least one first transistor, the first transistor includes a transparent first active layer, and a first gate insulated and arranged on a side of the first active layer away from the substrate, the first gate includes a first light-transmitting conductive layer.

[0114] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0115] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include at least one of the features.

[0116] In the description of the present application, “plurality” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0117] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0118] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0119] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0120] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area, wherein the display area comprises a first display area; At least one first pixel circuit is disposed on the substrate, and an orthographic projection of the first pixel circuit on the substrate is located in the first display area; The first pixel circuit includes at least one first transistor, the first transistor includes a transparent first active layer, and a first gate insulated and arranged on a side of the first active layer away from the substrate, the first gate includes a first light-transmitting conductive layer.

2. The display substrate according to claim 1, characterized in that: The first transistor further includes a first bottom gate, which is insulated and arranged on a side of the first active layer close to the substrate, and includes a second light-transmitting conductive layer.

3. The display substrate according to claim 1, characterized in that: The first transistor further includes a first source and a first drain, and the first source and / or the first drain includes a third light-transmitting conductive layer.

4. The display substrate according to claim 2, characterized in that: The first pixel circuit includes at least one second transistor, wherein the second transistor includes a second gate and a transparent second active layer; The second gate is located on a side of the second active layer away from the substrate, the second gate comprises a first metal layer and a fourth light-transmitting conductive layer, and the fourth light-transmitting conductive layer is located on a side of the first metal layer close to the substrate; The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate.

5. The display substrate according to claim 4, characterized in that: The fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

6. The display substrate according to claim 4, characterized in that: The second transistor further includes a second bottom gate, the second bottom gate is located on a side of the second active layer close to the substrate, the second bottom gate includes a second metal layer and a fifth light-transmitting conductive layer, the fifth light-transmitting conductive layer is located on a side of the second metal layer close to the substrate; The orthographic projection of the second metal layer on the substrate is located within the orthographic projection of the fifth light-transmitting conductive layer on the substrate, and the fifth light-transmitting conductive layer and the second light-transmitting conductive layer are made of the same material and are arranged in the same layer.

7. The display substrate according to claim 4, characterized in that: The second active layer includes a first region, a channel region, and a second region sequentially arranged in a first direction, wherein the first direction is parallel to the substrate; The fourth light-transmitting conductive layer and the first metal layer are both configured to extend along a second direction, the first metal layer is centrally arranged on the fourth light-transmitting conductive layer in the first direction, two ends of the fourth light-transmitting conductive layer in the first direction respectively protrude from two ends of the first metal layer in the first direction, and the second direction is parallel to the substrate and perpendicular to the first direction.

8. The display substrate according to claim 7, characterized in that: The channel region includes a first auxiliary channel region, a main channel region, and a second auxiliary channel region sequentially arranged in the first direction; The orthographic projection of the first metal layer on the substrate is arranged to overlap with the orthographic projection of the main channel region on the substrate, and not overlap with the orthographic projections of the first auxiliary channel region and the second auxiliary channel region on the substrate; Orthographic projections of the main channel region, the first auxiliary channel region, and the second auxiliary channel region on the substrate all overlap with an orthographic projection of the fourth light-transmitting conductive layer on the substrate.

9. The display substrate according to claim 4, characterized in that: The first gate further includes a third metal layer, the third metal layer is located on a side of the first light-transmitting conductive layer away from the substrate, and an orthographic projection of the third metal layer on the substrate is located within an orthographic projection of the first light-transmitting conductive layer on the substrate; The orthographic projection area of ​​the first metal layer on the substrate is S1, and the orthographic projection area of ​​the third metal layer on the substrate is S2, where S1>S2.

10. The display substrate according to claim 9, characterized in that: The width of the first metal layer is set to D1, the width of the third metal layer is set to D2, D1>D2, D1-D2≤0.5μm.

11. The display substrate according to claim 9, characterized in that: The first active layer and the second active layer are arranged to extend along a first direction, the first gate and the second gate are arranged to extend along a second direction, and the first direction and the second direction are parallel to the substrate and perpendicular to each other; The size of the third metal layer in the second direction is L1, the size of the first light-transmitting conductive layer in the second direction is L2, and L1<L2; The third metal layer is centrally arranged on the first light-transmitting conductive layer in the second direction, and two ends of the first light-transmitting conductive layer in the second direction respectively protrude from two ends of the third metal layer in the second direction.

12. The display substrate according to claim 11, characterized in that: One end of the first light-transmitting conductive layer in the second direction is a first end, one end of the third metal layer in the second direction close to the first end is a second end, and a distance between the first end and the second end in the second direction is set to L3, L3 ≥ 1 μm.

13. The display substrate according to claim 1, characterized in that: The first pixel circuit includes at least one third transistor, and the third transistor includes a third gate and a third active layer; The material of the third active layer includes polysilicon; The third gate is located on a side of the third active layer away from the substrate, the third gate includes a fourth metal layer and a sixth light-transmitting conductive layer, the sixth light-transmitting conductive layer is located on a side of the fourth metal layer close to the substrate, and the orthographic projection of the fourth metal layer on the substrate is located within the orthographic projection of the sixth light-transmitting conductive layer on the substrate.

14. The display substrate according to claim 2, characterized in that: The first active layer includes a first region, a channel region, and a second region sequentially arranged along a first direction, the channel region includes a third end close to the first region and a fourth end close to the second region in the first direction, and the first direction is parallel to the substrate; The first bottom gate further includes a fifth metal layer, the fifth metal layer is located on a side of the second light-transmitting conductive layer away from the substrate, and an orthographic projection of the fifth metal layer on the substrate is located within an orthographic projection of the second light-transmitting conductive layer on the substrate; The fifth metal layer is located between the third end and the fourth end in the first direction, the distance between the fifth metal layer and the third end in the first direction is greater than 0, and the distance between the fifth metal layer and the fourth end in the first direction is greater than 0.

15. The display substrate according to claim 1, characterized in that: The first display area includes at least one sub-pixel area, the sub-pixel area includes a main display area, a high-transmittance wiring area and a high-transmittance display area, the high-transmittance display area is located on at least one side of the main display area, the high-transmittance wiring area is located between the high-transmittance display area and the main display area, and the orthographic projection of the first transistor on the substrate is located in the high-transmittance display area.

16. The display substrate according to claim 15, characterized in that: The first pixel circuit further includes a plurality of signal lines, the plurality of signal lines include at least one transparent first signal line, and the orthographic projection of the first signal line on the substrate is located in the high-transparency wiring area.

17. The display substrate according to claim 16, characterized in that: The plurality of signal lines include at least one second signal line, the second signal line includes a first routing layer and a transparent second routing layer, the first routing layer is located on a side of the second routing layer away from the substrate, and the orthographic projection of the second signal line on the substrate is located in the high-transparency routing area.

18. The display substrate according to claim 15, characterized in that: Also included is a light emitting structure layer, the light emitting structure layer including a plurality of first light emitting devices and a pixel definition layer; The pixel definition layer is provided with a plurality of first pixel openings for arranging a plurality of the first light emitting devices, and the first light emitting devices are arranged to be electrically connected to the first pixel circuits in a one-to-one correspondence; The orthographic projection of the first pixel opening on the substrate is arranged to overlap with the main display area and the high-transmittance display area; Alternatively, the orthographic projection of the first pixel opening on the substrate is arranged to overlap with the main display area and not overlap with the high-transmittance display area.

19. The display substrate according to any one of claims 1 to 18, characterized in that: The material of the first light-transmitting conductive layer includes a transparent conductive oxide, and the transparent conductive oxide includes indium tin oxide.

20. A method for preparing a display substrate, characterized in that: include: At least one first pixel circuit is formed on a substrate, the substrate includes a display area, and the display area includes a first display area; at least one first pixel circuit is arranged on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit includes at least one first transistor, the first transistor includes a transparent first active layer, and a first gate insulated and arranged on a side of the first active layer away from the substrate, the first gate includes a first light-transmitting conductive layer.

21. The method for preparing a display substrate according to claim 20, characterized in that: The forming of at least one first pixel circuit on a substrate comprises: The first transistor and the second transistor are formed synchronously on the substrate, the second transistor includes a second gate, the second gate includes a first metal layer and a fourth light-transmitting conductive layer, the fourth light-transmitting conductive layer is located on a side of the first metal layer close to the substrate, the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate, and the fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

22. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 19.

Images