Display panel and display device

Abstract

The display panel comprises a first thin film transistor and a capacitor which are located in a pixel opening area, the capacitor comprises at least three electrode plates which are stacked and arranged at intervals, and the first thin film transistor and the capacitor are arranged on the basis of the face, close to an anode, of a substrate. The difference between the height of the first thin film transistor and the height of the capacitor is smaller than 4500 angstroms. Through the arrangement of the at least three layers of polar plates, the capacitance is improved, the terrain of the capacitance area is raised, the terrain of the first thin film transistor and the terrain of the capacitor tend to be similar, and the flatness of the pixel opening area is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the organic light-emitting display panel under inkjet printing, the flatness of the terrain of the pixel opening area of ​​the driving backplane will determine the uniformity of the film layer after the ink is cured; in addition, based on the improvement of the resolution of the display panel, the area of ​​the compensation capacitor is compressed, thereby reducing the capacitance of the compensation capacitor; secondly, based on the improvement of the resolution of the display panel, the driving thin film transistor and the compensation capacitor are set in the pixel opening area, so the terrain of the driving thin film transistor and the compensation capacitor will affect the flatness of the pixel opening area. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display device, which can improve the capacitance of a capacitor and the topographic flatness of a pixel opening area.

[0004] An embodiment of the present application provides a display panel, comprising:

[0005] substrate;

[0006] A first thin film transistor, disposed on the substrate;

[0007] A capacitor, disposed on the substrate and located on one side of the first thin film transistor;

[0008] an anode, disposed on a side of the first thin film transistor and the capacitor away from the substrate; and

[0009] A pixel definition layer is arranged on a side of the anode away from the substrate, the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode;

[0010] The first thin film transistor and the capacitor overlap with parts of the anode respectively, the capacitor comprises at least three stacked and spaced-apart plates, and with one side of the substrate close to the anode as a reference, the difference between the height of the first thin film transistor and the height of the capacitor is less than 4500 angstroms.

[0011] Optionally, in some embodiments of the present application, the display panel further includes a light shielding portion, a buffer layer, and an interlayer dielectric layer, the first thin film transistor includes a first active portion, a first gate insulating portion, a first gate, a first electrode, and a second electrode, and the capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate;

[0012] The first electrode plate is arranged in the same layer as the light shielding portion, the buffer layer covers the first electrode plate and the light shielding portion, the second electrode plate is arranged in the same layer as the first active portion, the first gate insulating portion is arranged on a side of the first active portion away from the substrate, the first gate is arranged on a side of the first gate insulating portion away from the substrate, the interlayer dielectric layer covers the first gate and the capacitor, and the first electrode and the second electrode are arranged on a side of the interlayer dielectric layer away from the substrate;

[0013] In the thickness direction of the display panel, the third electrode plate is located at one side of the first electrode plate, and the one of the first electrode plate and the second electrode plate which is farther from the third electrode plate is electrically connected to the third electrode plate.

[0014] Optionally, in some embodiments of the present application, the display panel also includes a first insulating layer and a transition portion, the first insulating layer covers the first gate and the second electrode, the third electrode is arranged on a side of the first insulating layer away from the substrate, the interlayer dielectric layer covers the first insulating layer and the third electrode, the transition portion, the first electrode and the second electrode are arranged in the same layer, and the transition portion connects the first electrode and the third electrode.

[0015] Optionally, in some embodiments of the present application, in the display panel viewed from above, the shading portion is connected to the first electrode plate, the second electrode plate is spaced apart from the first active portion, the second electrode plate includes a first sub-portion and a second sub-portion that are connected, the first sub-portion extends along a first direction, the second sub-portion extends along a second direction intersecting the first direction, the first sub-portion is located on one side of the first active portion in the second direction, the second sub-portion is located on one side of the first active portion in the first direction, and the first sub-portion and the second sub-portion are both overlapped with the first electrode plate.

[0016] Optionally, in some embodiments of the present application, in the display panel viewed from above, the third electrode plate includes a third sub-portion and a fourth sub-portion that are connected, the third sub-portion extends along a first direction, the fourth sub-portion extends along a second direction intersecting the first direction, the third sub-portion overlaps with the first sub-portion, and the fourth sub-portion overlaps with the second sub-portion.

[0017] Optionally, in some embodiments of the present application, in the display panel viewed from above, the transition portion covers part of the fourth sub-portion and at least covers part of the third sub-portion, and the transition portion is connected to the second electrode.

[0018] Optionally, in some embodiments of the present application, the display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the second active portion is arranged on a side of the buffer layer away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially cover the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate;

[0019] The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

[0020] Optionally, in some embodiments of the present application, the first gate insulating portion includes a first sublayer and a second sublayer that are stacked;

[0021] The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a protection portion, a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the protection portion is arranged on a side of the buffer layer away from the substrate, the second active portion is arranged on a side of the protection portion away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially cover the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate;

[0022] The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

[0023] Optionally, in some embodiments of the present application, the display panel also includes a first insulating layer and a transition portion, the third electrode is arranged on a side of the first electrode close to the substrate, the first insulating layer covers the third electrode and the substrate, the buffer layer covers the first insulating layer, the transition portion is arranged in the same layer as the first electrode on a side of the interlayer dielectric layer away from the substrate, and the transition portion connects the second electrode and the third electrode.

[0024] Optionally, in some embodiments of the present application, the display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the second active portion is arranged on a side of the buffer layer away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the interlayer dielectric layer sequentially covers the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate;

[0025] The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

[0026] Optionally, in some embodiments of the present application, the first gate insulating portion includes a first sublayer and a second sublayer that are stacked;

[0027] The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a protection portion, a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the protection portion is arranged on a side of the buffer layer away from the substrate, the second active portion is arranged on a side of the protection portion away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the interlayer dielectric layer covers the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate;

[0028] The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

[0029] Optionally, in some embodiments of the present application, the display panel further includes a first planar layer and a second planar layer sequentially covering the first thin film transistor and the capacitor, and the anode is arranged on a side of the second planar layer away from the substrate.

[0030] Correspondingly, an embodiment of the present application further provides a display device, which includes a display panel as described in any one of the above embodiments.

[0031] The display panel and display device of the embodiment of the present application include a first thin film transistor and a capacitor located in the pixel opening area, the capacitor includes at least three stacked and spaced electrodes, and the difference between the height of the first thin film transistor and the height of the capacitor is less than 4500 angstroms based on the side of the substrate close to the anode. The present application not only increases the capacitance but also raises the terrain of the capacitor area by setting at least three layers of electrodes, so that the terrain of the first thin film transistor and the capacitor tends to be similar, thereby improving the flatness of the pixel opening area. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0033] Figure 2 is a partial top plan schematic diagram of a display panel provided in an embodiment of the present application;

[0034] Figure 3 yes Figure 2 A schematic plan view of the film layer where the middle light shielding portion and the first electrode plate are located;

[0035] Figure 4 is based on Figure 3 Add a plan view of the film layer where the first active part and the second electrode plate are located;

[0036] Figure 5 is based on Figure 4 Add a planar schematic diagram of the film layer where the first gate is located;

[0037] Figure 6 is based on Figure 5 Add a planar schematic diagram of the membrane layer where the third electrode plate is located;

[0038] Figure 7 is based on Figure 6 Add a planar schematic diagram of the film layer where the first electrode, the second electrode and the transition portion are located;

[0039] Figure 8 is another structural schematic diagram of a display panel provided in an embodiment of the present application;

[0040] Fig. 9 is another structural schematic diagram of a display panel provided in an embodiment of the present application;

[0041] Fig.10 is another structural schematic diagram of a display panel provided in an embodiment of the present application;

[0042] Fig.11 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the various embodiments can be combined with each other but will not be repeated one by one, and in the absence of contrary instructions, the directional words used, such as "upper" and "lower", usually refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements or order are imposed.

[0044] The embodiments of the present application provide a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0045] Please refer to Figure 1 and Figure 2 The embodiment of the present application provides a display panel 100 , which includes a substrate 101 , a first thin film transistor t1 , a capacitor c1 , an anode 201 and a pixel definition layer 202 .

[0046] The first thin film transistor t1 is disposed on the substrate 101. The capacitor c1 is disposed on the substrate 101 and is located on one side of the first thin film transistor t1. The anode 201 is disposed on a side of the first thin film transistor t1 and the capacitor c1 away from the substrate 101. The pixel definition layer 202 is disposed on a side of the anode 201 away from the substrate 101, and the pixel definition layer 202 is provided with a pixel opening 2a, and the pixel opening 2a exposes the anode 201.

[0047] The first thin film transistor t1 and the capacitor c1 overlap with a portion of the anode 201. The capacitor c1 includes at least three stacked and spaced electrodes. Based on the side of the substrate 101 close to the anode 201, the height difference gd between the first thin film transistor t1 and the capacitor c1 is less than 4500 angstroms.

[0048] The display panel 100 of the embodiment of the present application includes a first thin film transistor t1 and a capacitor c1 located in the pixel opening 2a area. The present application not only increases the capacitance but also raises the terrain of the capacitor c1 area by setting at least three layers of electrodes, so that the terrain difference between the first thin film transistor t1 and the capacitor c1 is less than 4500 angstroms, and the two tend to be close, thereby improving the flatness of the pixel opening 2a area.

[0049] It can be understood that, in the thickness direction of the display panel 100, the difference gd between the height of the first thin film transistor t1 and the height of the capacitor c1 is less than 4500 angstroms, for example, the height difference between the two is 4400 angstroms, 4300 angstroms, 4200 angstroms, 4100 angstroms, 4000 angstroms, 3900 angstroms, 3800 angstroms, 3700 angstroms, 3600 angstroms, 3500 angstroms, 3400 angstroms, 3300 angstroms, 3200 angstroms, 3100 angstroms, 3000 angstroms, 2900 angstroms, 2800 angstroms, 2700 angstroms, 2600 angstroms, 2500 angstroms, 2900 angstroms, 2800 angstroms, 2700 angstroms, 2600 angstroms, 2500 angstroms, 2900 angstroms, 2800 angstroms, 2700 angstroms, 28 ... , 100 angstroms, 90 angstroms, 80 angstroms, 70 angstroms, 60 angstroms, 50 angstroms, 40 angstroms, 30 angstroms, 20 angstroms, 10 angstroms, or 0 angstroms.

[0050] It can be understood that the more plate layers the capacitor c1 has, the higher its terrain is, and the closer it is to the terrain height of the first thin film transistor t1, so that the flatness of the pixel opening 2a area is higher.

[0051] The first thin film transistor t1 is used as a driving thin film transistor and is located in the display area. The first thin film transistor t1 is connected to the anode 201 .

[0052] Optionally, the display panel 100 further includes a light-emitting functional layer, which is disposed on the anode 201. The light-emitting functional layer is formed by a plurality of layers including one or more emission layers, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In the case where the light-emitting functional layer includes all of the above layers, the hole injection layer may be located on the anode 201, and the hole transport layer, the emission layer, the electron transport layer, and the electron injection layer may be sequentially laminated on the hole injection layer.

[0053] Optionally, in some embodiments of the present application, the display panel 100 further includes a light shielding portion 102, a buffer layer 103 and an interlayer dielectric layer 109. The first thin film transistor t1 includes a first active portion 104, a first gate insulating portion 105, a first gate 106, a first electrode 107 and a second electrode 108. The capacitor c1 includes a first plate c01, a second plate c02 and a third plate c03.

[0054] The first electrode plate c01 is disposed in the same layer as the light shielding portion 102. The buffer layer 103 covers the first electrode plate c01 and the light shielding portion 102. The second electrode plate c02 is disposed in the same layer as the first active portion 104. The first gate insulating portion 105 is disposed on a side of the first active portion 104 away from the substrate 101. The first gate 106 is disposed on a side of the first gate insulating portion 105 away from the substrate 101. The interlayer dielectric layer 109 covers the first gate 106 and the capacitor c1. The first electrode 107 and the second electrode 108 are disposed on a side of the interlayer dielectric layer 109 away from the substrate 101.

[0055] In the thickness direction of the display panel 100 , the third electrode plate c03 is located on one side of the first electrode plate c01 , and the one of the first electrode plate c01 and the second electrode plate c02 that is farther from the third electrode plate c03 is electrically connected to the third electrode plate c03 .

[0056] It can be understood that the thickness of the conductive film layer of the first thin film transistor t1 is relatively large, so the conductive film layer has a greater impact on the topography of the first thin film transistor t1. Based on this, the first electrode c01 is set in the same layer as the light shielding portion 102, and the second electrode c02 is set in the same layer as the first active portion 104 to offset the topographic difference between the two conductive film layers. Secondly, the capacitor c1 is provided with a third electrode c03 to offset the topographic difference of the first gate 106 of the first thin film transistor t1, thereby reducing the topographic height difference between the first thin film transistor t1 and the capacitor c1 to improve flatness.

[0057] Optionally, in some embodiments of the present application, the display panel 100 further includes a first planar layer 111 and a second planar layer 112 sequentially covering the first thin film transistor t1 and the capacitor c1 , and the anode 201 is disposed on a side of the second planar layer 112 away from the substrate 101 .

[0058] It is understandable that the flat layer has a certain leveling property, and based on the process limitations of existing equipment, a flat layer has an upper limit on the leveling of the terrain. Therefore, based on the fact that the terrain height difference between the first thin film transistor t1 and the capacitor c1 is less than 4500 angstroms, the embodiment of the present application improves the flatness of the pixel opening 2a area by providing the first flat layer 111 and the second flat layer 112 to compensate for the terrain height difference between the first thin film transistor t1 and the capacitor c1, thereby improving the flatness of the anode 201.

[0059] Optionally, in some embodiments, based on the terrain height difference gd between the first thin film transistor t1 and the capacitor c1 being less than or equal to 2600 angstroms, the embodiments of the present application improve the flatness of the pixel opening 2a area by setting a first flat layer 111 and a second flat layer 112 to completely level the terrain height difference between the first thin film transistor t1 and the capacitor c1, thereby improving the flatness of the anode 201.

[0060] In some embodiments, the display panel 100 further includes a third flat layer 113, which is disposed on a side of the second flat layer 112 away from the substrate 101. It is understood that in the pixel opening 2a region, in addition to the terrain of the first thin film transistor t1 and the capacitor c1, a terrain formed by stacking inorganic insulating layers is also disposed, wherein the inorganic stacking terrain formed by the stacking of inorganic insulating layers is lower than the terrain of the first thin film transistor t1, so that the first flat layer 111 and the second flat layer 112 cannot completely compensate for the height difference between the first thin film transistor t1 and the inorganic stacking terrain. Therefore, the embodiment of the present application further compensates for the height difference between the first thin film transistor t1 and the inorganic stacking terrain by disposing the third flat layer 113, thereby improving the flatness of the pixel opening 2a region, and further improving the flatness of the anode 201.

[0061] Optionally, the inorganic stacked topography includes a buffer layer 103 and an interlayer dielectric layer 109 .

[0062] Optionally, in some embodiments of the present application, the display panel 100 further includes a first insulating layer 114 and a transition portion 115. The first insulating layer 114 covers the first gate electrode 106 and the second electrode plate c02. The third electrode plate c03 is arranged on a side of the first insulating layer 114 away from the substrate 101. The interlayer dielectric layer 109 covers the first insulating layer 114 and the third electrode plate c03, and the transition portion 115, the first electrode 107 and the second electrode 108 are arranged in the same layer, and the transition portion 115 connects the first electrode plate c01 and the third electrode plate c03.

[0063] It can be understood that the third electrode plate c03 is disposed on a side of the second electrode plate c02 away from the substrate 101 so that the transition portion 115 is closer to the third electrode plate c03 to reduce the depth of the via hole.

[0064] Optionally, the transition portion 115 is connected to the third electrode plate c03 through a first via hole g1, and the second electrode 108 is connected to the first active portion 104 through another first via hole g1. The transition portion 115 is connected to the first electrode plate c01 through a second via hole g2.

[0065] Optionally, the first gate 106 and the third plate c03 have the same thickness, the first active portion 104 and the second plate c02 have the same thickness, and the light shielding portion 102 and the first plate c01 have the same thickness, but the invention is not limited thereto. For example, the thickness of the first gate 106 may be less than the thickness of the third plate c03, the first active portion 104 and the second plate c02 have the same thickness, and the light shielding portion 102 and the first plate c01 have the same thickness, so as to further reduce the terrain height difference between the first thin film transistor t1 and the capacitor c1.

[0066] Optionally, in some embodiments, the light shielding portion 102 and the first electrode plate c01 are formed by using the same photomask, and the second electrode plate c02 and the first active portion 104 are formed by using the same photomask.

[0067] Optional, see Figures 2 to 7 In some embodiments of the present application, in the display panel 100 viewed from above, the light shielding portion 102 is connected to the first electrode plate c01, and the second electrode plate c02 is spaced apart from the first active portion 104. The second electrode plate c02 includes a first sub-portion c21 and a second sub-portion c22 connected to each other. The first sub-portion c21 extends along the first direction F1, and the second sub-portion c22 extends along the second direction F2 intersecting the first direction F1. The first sub-portion c21 is located on one side of the first active portion 104 in the second direction F2, and the second sub-portion c22 is located on one side of the first active portion 104 in the first direction F1. The first sub-portion c21 and the second sub-portion c22 are both arranged to overlap with the first electrode plate c01.

[0068] Optionally, the first direction F1 is perpendicular to the second direction F2, but is not limited thereto, for example, the first direction F1 and the second direction F2 do not intersect perpendicularly. Optionally, the second direction F2 is an extending direction of the data line d1.

[0069] It can be understood that the light shielding portion 102 and the first electrode plate c01 are connected to form a whole, which not only reduces the difficulty of preparation, but also is equivalent to increasing the layout area of ​​the first electrode plate c01.

[0070] Secondly, the first sub-portion c21 and the second sub-portion c22 are connected to form a shape that semi-surrounds the first active portion 104, thereby increasing the overlapping area of ​​the second electrode plate c02 and the first electrode plate c01 within a limited space, thereby increasing the capacitance of the capacitor c1 and raising the area of ​​the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0071] Optionally, in some embodiments of the present application, in the display panel 100 viewed from above, the third electrode plate c03 includes a third sub-portion c33 and a fourth sub-portion c34 connected to each other, the third sub-portion c33 extends along the first direction F1, and the fourth sub-portion c34 extends along the second direction F2 intersecting the first direction F1. The third sub-portion c33 overlaps with the first sub-portion c21, and the fourth sub-portion c34 overlaps with the second sub-portion c22.

[0072] It can be understood that the third sub-portion c33 of the third electrode c03 overlaps with the first sub-portion c21, and the fourth sub-portion c34 of the third electrode c03 overlaps with the second sub-portion c22, so that the overlapping area of ​​the second electrode c02 and the third electrode c03 is increased within a limited space, thereby increasing the capacitance of the capacitor c1 and raising the area of ​​the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0073] Optionally, in some embodiments of the present application, in the display panel 100 in a plan view, the transition portion 115 covers a portion of the fourth sub-portion c34 and at least a portion of the third sub-portion c33 . The transition portion 115 is connected to the second electrode 108 .

[0074] It is understandable that the transition portion 115 covers the portion of the third electrode plate c03, which can reduce the influence of the signal line on the side of the capacitor c1 away from the substrate 101. Secondly, the transition portion 115 covers the third electrode plate c03 to increase the topography of the capacitor c1 area, thereby reducing the height difference between the first thin film transistor t1 area and the capacitor c1 and improving the flatness.

[0075] Optionally, in some embodiments of the present application, the transition portion 115 partially extends beyond the third electrode plate c03 and the second electrode plate c02. The extended portion 15a of the transition portion 115 is connected to the second electrode 108. The extended portion 15a of the transition portion 115 is connected to the second electrode 108 to form a compensation plate c04, and the compensation plate c04 and the light shielding portion 102 are partially overlapped to form a compensation capacitor.

[0076] It can be understood that the compensation plate c04 and the light shielding portion 102 form a compensation capacitor, which can not only increase the capacitance of the capacitor c1, but also increase the area of ​​the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0077] Optionally, in some embodiments of the present application, the second electrode plate c02 further includes a first convex portion c23 connecting the intersection of the first sub-portion c21 and the second sub-portion c22 and close to the first active portion 104, and the first convex portion c23 is overlapped with the first electrode plate c01. The third electrode plate c03 further includes a second convex portion c35 connecting the intersection of the third sub-portion c33 and the fourth sub-portion c34 and close to the first active portion 104, and the second convex portion c35 is overlapped with the first convex portion c23.

[0078] It can be understood that the provision of the first convex portion c23 and the second convex portion c35 can not only increase the capacitance of the capacitor c1, but also increase the area of ​​the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0079] Optionally, in some embodiments, the display panel 100 further includes a connecting portion 116 which is disposed in the same layer and spaced apart from the transition portion 115. The connecting portion 116 is connected to the first gate 106 and the second electrode plate c02 through the third via hole g3.

[0080] Optionally, in some embodiments of the present application, the display panel 100 further includes a second thin film transistor t2 located in the gate driving circuit area, and the second thin film transistor t2 includes a second active portion 121, a second gate insulating portion 122, a second gate electrode 123, a third electrode 124, and a fourth electrode 125. The second active portion 121 is disposed on a side of the buffer layer 103 away from the substrate 101. The second gate insulating portion 122 is disposed on a side of the second active portion 121 away from the substrate 101. The second gate electrode 123 is disposed on a side of the second gate insulating portion 122 away from the substrate 101. The first insulating layer 114 and the interlayer dielectric layer 109 sequentially cover the second gate electrode 123. The third electrode 124 and the fourth electrode 125 are disposed on a side of the interlayer dielectric layer 109 away from the substrate 101.

[0081] Optionally, the second active portion 121 and the first active portion 104 are arranged in the same layer and are made by the same photomask. The second gate insulating portion 122 and the first gate insulating portion 105 are arranged in the same layer and are made by the same photomask. The second gate 123 and the first gate 106 are arranged in the same layer and are made by the same photomask. The third electrode 124, the fourth electrode 125, the first electrode 107 and the second electrode 108 are arranged in the same layer and are made by the same photomask.

[0082] The display panel 100 further includes a peripheral wiring 131 located in the gate driving circuit region. The peripheral wiring 131 is located on a side of the second thin film transistor t2 away from the substrate 101. The peripheral wiring 131 is electrically connected to the second thin film transistor t2.

[0083] Optionally, the display panel 100 further includes a passivation layer 110 covering the first electrode 107, the second electrode 108, the third electrode 124 and the fourth electrode 125, and the first flat layer 111 covers the passivation layer 110. The peripheral wiring 131 is arranged on a side of the first flat layer 111 away from the substrate 101. The second flat layer 112 covers the peripheral wiring 131 and the first flat layer 111.

[0084] The gate driving circuit area is provided with the peripheral wiring 131 to reduce the frame width. One peripheral wiring 131 is connected to the second gate electrode 123 , and another peripheral wiring 131 is connected to the fourth electrode 125 .

[0085] Optionally, the peripheral wiring 131 connected to the second gate 123 is a clock signal line, and the peripheral wiring connected to the fourth electrode 125 is a power line or a reset signal line.

[0086] Optionally, the display panel 100 further includes a line switching portion 132 located in the display area, which is disposed in the same layer as the peripheral wiring 131 on a side of the first planar layer 111 away from the substrate 101. The second electrode 108 of the first thin film transistor t1 is connected to the anode 201 through the line switching portion 132.

[0087] Figure 8 Another structural schematic diagram of the display panel 100 according to an embodiment of the present application is shown. Figure 8 Parts that are different from those of the above-mentioned embodiments will be described in detail to avoid redundancy.

[0088] exist Figure 8 In some embodiments of the present application, the first gate insulating portion 105 includes a first sub-layer 051 and a second sub-layer 052 which are stacked.

[0089] The display panel 100 further includes a second thin film transistor t2 located in the gate driving circuit area, and the second thin film transistor t2 includes a protection portion 120, a second active portion 121, a second gate insulating portion 122, a second gate electrode 123, a third electrode 124, and a fourth electrode 125. The protection portion 120 is disposed on a side of the buffer layer 103 away from the substrate 101. The second active portion 121 is disposed on a side of the protection portion 120 away from the substrate 101, the second gate insulating portion 122 is disposed on a side of the second active portion 121 away from the substrate 101, the second gate electrode 123 is disposed on a side of the second gate insulating portion 122 away from the substrate 101, the first insulating layer 114 and the interlayer dielectric layer 109 sequentially cover the second gate electrode 123, and the third electrode 124 and the fourth electrode 125 are disposed on a side of the interlayer dielectric layer 109 away from the substrate 101.

[0090] It should be noted that Figure 8 The display panel 100 of the corresponding embodiment is different from the above embodiment in that the first gate insulating portion 105 includes a first sublayer 051 and a second sublayer 052 stacked, and the second thin film transistor t2 further includes a protective portion 120. The carrier mobility of the first thin film transistor t1 is smaller than the carrier mobility of the second thin film transistor t2.

[0091] Optionally, the first sub-layer 051 and the protection portion 120 are formed by the same photomask process, and the materials and thicknesses of the two are the same. The second sub-layer 052 and the second gate insulating portion 122 are formed by the same photomask process, and the materials and thicknesses of the two are the same.

[0092] in, Figure 8 The planar layout structure of the display panel 100 of the corresponding embodiment is similar to or the same as the planar layout structure of the display panel 100 of the above embodiment. Figures 2 to 7 The explanation will not be repeated here.

[0093] Fig. 9 FIG. 1 is another schematic diagram of the structure of the display panel 100 according to an embodiment of the present application. Fig. 9 Parts that are different from those of the above-mentioned embodiments will be described in detail to avoid redundancy.

[0094] exist Fig. 9 In some embodiments of the present application, the display panel 100 further includes a first insulating layer 114 and a transition portion 115. The third electrode c03 is disposed on a side of the first electrode c01 close to the substrate 101. The first insulating layer 114 covers the third electrode c03 and the substrate 101. The buffer layer 103 covers the first insulating layer 114. The transition portion 115 is disposed on the same layer as the first electrode 107 on a side of the interlayer dielectric layer 109 away from the substrate 101, and the transition portion 115 connects the second electrode c02 and the third electrode c03.

[0095] Optionally, the transition portion 115 is connected to the second electrode plate c02 through the first via hole g1, and the transition portion 115 is connected to the third electrode plate c03 through the second via hole g2.

[0096] Compared with the display panel 100 of the above embodiments, Fig. 9 The display panel 100 of the corresponding embodiment arranges the third electrode plate c03 on the side of the first electrode plate c01 close to the substrate 101 to save wiring space above and facilitate wiring. Figure 1 The film layer where the third electrode c03 is located is transferred to the side of the film layer where the light shielding portion 102 is located close to the substrate 101.

[0097] Optionally, in some embodiments of the present application, the display panel 100 further includes a second thin film transistor t2 located in the gate driving circuit area, and the second thin film transistor t2 includes a second active portion 121, a second gate insulating portion 122, a second gate electrode 123, a third electrode 124, and a fourth electrode 125. The second active portion 121 is disposed on a side of the buffer layer 103 away from the substrate 101. The second gate insulating portion 122 is disposed on a side of the second active portion 121 away from the substrate 101. The second gate electrode 123 is disposed on a side of the second gate insulating portion 122 away from the substrate 101. The interlayer dielectric layer 109 sequentially covers the second gate electrode 123, and the third electrode 124 and the fourth electrode 125 are disposed on a side of the interlayer dielectric layer 109 away from the substrate 101.

[0098] Optionally, the second active portion 121, the second electrode plate c02 and the first active portion 104 are arranged in the same layer and are made by the same photomask. The second gate insulating portion 122 and the first gate insulating portion 105 are arranged in the same layer and are made by the same photomask. The second gate 123 and the first gate 106 are arranged in the same layer and are made by the same photomask. The third electrode 124, the fourth electrode 125, the first electrode 107 and the second electrode 108 are arranged in the same layer and are made by the same photomask.

[0099] The display panel 100 further includes a peripheral wiring 131 located in the gate driving circuit region. The peripheral wiring 131 is located at a side of the second thin film transistor t2 away from the substrate 101 . The peripheral wiring 131 is electrically connected to the second thin film transistor t2 .

[0100] The gate drive circuit area is provided with the peripheral wiring 131 to reduce the frame width. One peripheral wiring 131 is connected to the second gate electrode 123, and another peripheral wiring 131 is connected to the fourth electrode 125. Optionally, the peripheral wiring 131 connected to the second gate electrode 123 is a clock signal line, and the peripheral wiring connected to the fourth electrode 125 is a power line or a reset signal line.

[0101] Optionally, the third electrode plate c03 is a black electrode plate to enhance the integrated black effect.

[0102] It should be noted that Fig. 9 The planar structure of the shading portion 102, the first electrode plate c01, the second electrode plate c02, the third electrode plate c03 and the transition portion 115 of the corresponding embodiment is similar to or identical to the planar structure of the shading portion 102, the first electrode plate c01, the second electrode plate c02, the third electrode plate c03 and the transition portion 115 corresponding to the display panel 100 of the above-mentioned embodiment. The difference is that the first electrode plate c01 is spaced between the third electrode plate c03 and the second electrode plate c02, and the third electrode plate c03 and the second electrode plate c02 overlap with the first electrode plate c01 respectively to form a capacitor c1. Secondly, the transition portion 115 connects the second electrode plate c02 and the third electrode plate c03. Based on the fact that the third electrode plate c03 is below the first electrode plate c01, compared with the above-mentioned embodiment, Fig. 9 In the corresponding embodiment, the third electrode plate c03 further extends a contact portion beyond the first electrode plate c01 , and the contact portion is connected to the transition portion 115 . The first electrode plate c01 is electrically connected to the first grid 106 .

[0103] Fig.10 FIG. 1 is another schematic diagram of the structure of the display panel 100 according to an embodiment of the present application. Fig.10 Parts that are different from those of the above-mentioned embodiments will be described in detail to avoid redundancy.

[0104] exist Fig.10 In some embodiments of the present application, the first gate insulating portion 105 includes a first sub-layer 051 and a second sub-layer 052 which are stacked.

[0105] The display panel 100 further includes a second thin film transistor t2 located in the gate driving circuit region, and the second thin film transistor t2 includes a protection portion 120, a second active portion 121, a second gate insulating portion 122, a second gate electrode 123, a third electrode 124, and a fourth electrode 125. The protection portion 120 is disposed on a side of the buffer layer 103 away from the substrate 101. The second active portion 121 is disposed on a side of the protection portion 120 away from the substrate 101. The second gate insulating portion 122 is disposed on a side of the second active portion 121 away from the substrate 101. The second gate electrode 123 is disposed on a side of the second gate insulating portion 122 away from the substrate 101, the interlayer dielectric layer 109 covers the second gate electrode 123, and the third electrode 124 and the fourth electrode 125 are disposed on a side of the interlayer dielectric layer 109 away from the substrate 101.

[0106] Optionally, the first sub-layer 051 and the protection portion 120 are formed by the same photomask process, and the materials and thicknesses of the two are the same. The second sub-layer 152 and the second gate insulating portion 122 are formed by the same photomask process, and the materials and thicknesses of the two are the same.

[0107] The display panel 100 further includes a peripheral wiring 131 located in the gate driving circuit region. The peripheral wiring 131 is located at a side of the second thin film transistor t2 away from the substrate 101 . The peripheral wiring 131 is electrically connected to the second thin film transistor t2 .

[0108] Please refer to Fig.11 Accordingly, an embodiment of the present application further provides a display device 1000, which includes the display panel 100 as described in any one of the above embodiments.

[0109] The display device 1000 of the embodiment of the present application includes a first thin film transistor t1 and a capacitor c1 located in the pixel opening 2a area, and the capacitor c1 includes at least three stacked and spaced electrodes. With the side of the substrate 101 close to the anode 201 as a reference, the difference between the height of the first thin film transistor t1 and the height of the capacitor c1 is less than 4500 angstroms. The present application not only increases the capacitance but also raises the terrain of the capacitor c1 area by setting at least three layers of electrodes, so that the terrain of the first thin film transistor t1 and the capacitor c1 tends to be similar, thereby improving the flatness of the pixel opening 2a area.

[0110] It should be noted that the structure of the display panel 100 of the display device 1000 of the embodiment of the present application is similar to or the same as the structure of the display panel 100 described in the above embodiments. Figures 1 to 10 , so I will not repeat it here.

[0111] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: substrate; A first thin film transistor, disposed on the substrate; A capacitor, disposed on the substrate and located on one side of the first thin film transistor; an anode, arranged on a side of the first thin film transistor and the capacitor away from the substrate; as well as A pixel definition layer is arranged on a side of the anode away from the substrate, the pixel definition layer is provided with a pixel opening, and the pixel opening exposes the anode; The first thin film transistor and the capacitor overlap with parts of the anode respectively, the capacitor comprises at least three stacked and spaced-apart plates, and with one side of the substrate close to the anode as a reference, the difference between the height of the first thin film transistor and the height of the capacitor is less than 4500 angstroms.

2. The display panel according to claim 1, characterized in that: The display panel further includes a light shielding portion, a buffer layer and an interlayer dielectric layer, the first thin film transistor includes a first active portion, a first gate insulating portion, a first gate, a first electrode and a second electrode, and the capacitor includes a first plate, a second plate and a third plate; The first electrode plate is arranged in the same layer as the light shielding portion, the buffer layer covers the first electrode plate and the light shielding portion, the second electrode plate is arranged in the same layer as the first active portion, the first gate insulating portion is arranged on a side of the first active portion away from the substrate, the first gate is arranged on a side of the first gate insulating portion away from the substrate, the interlayer dielectric layer covers the first gate and the capacitor, and the first electrode and the second electrode are arranged on a side of the interlayer dielectric layer away from the substrate; In the thickness direction of the display panel, the third electrode plate is located at one side of the first electrode plate, and the one of the first electrode plate and the second electrode plate which is farther from the third electrode plate is electrically connected to the third electrode plate.

3. The display panel according to claim 2, characterized in that: The display panel also includes a first insulating layer and a transition portion, the first insulating layer covers the first gate and the second electrode, the third electrode is arranged on a side of the first insulating layer away from the substrate, the interlayer dielectric layer covers the first insulating layer and the third electrode, the transition portion, the first electrode and the second electrode are arranged in the same layer, and the transition portion connects the first electrode and the third electrode.

4. The display panel according to claim 3, characterized in that: In the display panel viewed from above, the shading portion is connected to the first electrode plate, the second electrode plate is spaced apart from the first active portion, the second electrode plate includes a first sub-portion and a second sub-portion that are connected, the first sub-portion extends along a first direction, the second sub-portion extends along a second direction intersecting the first direction, the first sub-portion is located on one side of the first active portion in the second direction, the second sub-portion is located on one side of the first active portion in the first direction, and the first sub-portion and the second sub-portion are both overlapped with the first electrode plate.

5. The display panel according to claim 4, characterized in that: In the display panel viewed from above, the third electrode plate includes a third sub-portion and a fourth sub-portion connected to each other, the third sub-portion extends along a first direction, the fourth sub-portion extends along a second direction intersecting the first direction, the third sub-portion overlaps with the first sub-portion, and the fourth sub-portion overlaps with the second sub-portion.

6. The display panel according to claim 5, characterized in that: In the display panel viewed from above, the transition portion covers a portion of the fourth sub-portion and at least a portion of the third sub-portion, and the transition portion is connected to the second electrode.

7. The display panel according to claim 3, characterized in that: The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor including a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the second active portion is arranged on a side of the buffer layer away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially cover the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate; The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

8. The display panel according to claim 3, characterized in that: The first gate insulating portion includes a first sublayer and a second sublayer that are stacked; The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a protection portion, a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the protection portion is arranged on a side of the buffer layer away from the substrate, the second active portion is arranged on a side of the protection portion away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially cover the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate; The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

9. The display panel according to claim 2, characterized in that: The display panel also includes a first insulating layer and a transition portion, the third electrode plate is arranged on a side of the first electrode plate close to the substrate, the first insulating layer covers the third electrode plate and the substrate, the buffer layer covers the first insulating layer, the transition portion is arranged in the same layer as the first electrode on a side of the interlayer dielectric layer away from the substrate, and the transition portion connects the second electrode plate and the third electrode plate.

10. The display panel according to claim 9, characterized in that: The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the second active portion is arranged on a side of the buffer layer away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the interlayer dielectric layer sequentially covers the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate; The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

11. The display panel according to claim 9, characterized in that: The first gate insulating portion includes a first sublayer and a second sublayer that are stacked; The display panel further includes a second thin film transistor located in the gate driving circuit area, the second thin film transistor includes a protection portion, a second active portion, a second gate insulating portion, a second gate, a third electrode and a fourth electrode, the protection portion is arranged on a side of the buffer layer away from the substrate, the second active portion is arranged on a side of the protection portion away from the substrate, the second gate insulating portion is arranged on a side of the second active portion away from the substrate, the second gate is arranged on a side of the second gate insulating portion away from the substrate, the interlayer dielectric layer covers the second gate, and the third electrode and the fourth electrode are arranged on a side of the interlayer dielectric layer away from the substrate; The display panel further includes a peripheral routing line located in the gate driving circuit area, the peripheral routing line is located on a side of the second thin film transistor away from the substrate, and the peripheral routing line is electrically connected to the second thin film transistor.

12. The display panel according to any one of claims 1 to 11, characterized in that: The display panel further includes a first planar layer and a second planar layer which sequentially cover the first thin film transistor and the capacitor, and the anode is arranged on a side of the second planar layer away from the substrate.

13. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-12.

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