Display device

Abstract

A display device includes a base layer, a circuit layer, and an element layer. The circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; and a readout wiring connected to the sensor driving circuit. First pixel driving circuits among the pixel driving circuits are continuously arranged in a direction parallel to the readout wiring, and the first pixel driving circuits are connected to first light emitting elements among the light emitting elements. The circuit layer further includes a first pixel connection electrode connecting the first pixel driving circuit to the first light emitting element, and the first pixel connection electrode does not intersect the readout wiring in a plan view.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to a display device having a biometric information recognition function. Background Art

[0002] The display device provides various functions capable of organically communicating with the user, such as providing information to the user by displaying an image or sensing the user's input. Recent display devices also include a function for sensing biometric information of the user.

[0003] Bio-information recognition methods include a capacitive method that senses a change in capacitance formed between electrodes, an optical method that senses incident light using an optical sensor, and an ultrasonic method that senses vibration using a piezoelectric material.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Embodiments of the present disclosure provide a display device with improved biometric information recognition performance.

[0006] In one or more embodiments of the present disclosure, a display device includes: a base layer; a circuit layer located on the base layer; and an element layer located on the circuit layer and including a light emitting element and a light receiving element.

[0007] The circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; and a readout wiring connected to the sensor driving circuit.

[0008] Among the pixel driving circuits, a first pixel driving circuit is continuously arranged in a direction parallel to the readout wiring, and the first pixel driving circuit is connected to a first light-emitting element among the light-emitting elements. The circuit layer also includes a first pixel connection electrode that connects the first pixel driving circuit to the first light-emitting element, and the first pixel connection electrode does not cross the readout wiring in a plan view.

[0009] In one or more embodiments of the present disclosure, a display device includes: a base layer; a circuit layer located on the base layer; and an element layer located on the circuit layer and including a light emitting element and a light receiving element.

[0010] The circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a readout wiring connected to the sensor driving circuit; and a shielding electrode overlapping the readout wiring and the sensor driving circuit in a plan view.

[0011] A first pixel driving circuit among the pixel driving circuits is continuously arranged in a direction parallel to the readout wiring, and the first pixel driving circuit is connected to a first light emitting element among the light emitting elements. The circuit layer also includes a first pixel connection electrode connecting the first pixel driving circuit to the first light emitting element, and the first pixel connection electrode is located at a layer different from the layer on which the shielding electrode is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0013] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0014] Figure 2A is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0015] Figure 2B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0016] Figure 3 is a block diagram of a display device according to one or more embodiments of the present disclosure;

[0017] Figure 4A is a circuit diagram showing a pixel and a sensor according to one or more embodiments of the present disclosure;

[0018] Figure 4B It is shown Figure 4A Waveform diagrams of the operation of the pixel and sensor shown in ;

[0019] Figure 5A is a schematic plan view showing the arrangement of a pixel driving circuit and a sensor driving circuit according to one or more embodiments of the present disclosure;

[0020] Figure 5B is a plan view showing the arrangement of light emitting elements and light receiving elements according to one or more embodiments of the present disclosure;

[0021] Figure 5C is a plan view showing a connection relationship between a light emitting element and a pixel driving circuit and a connection relationship between a light receiving element and a sensor driving circuit according to one or more embodiments of the present disclosure;

[0022] Fig. 6A and Figure 6Bis a plan view showing a connection relationship between a light emitting element and a pixel driving circuit and a connection relationship between a light receiving element and a sensor driving circuit according to one or more embodiments of the present disclosure;

[0023] Fig. 7A It is shown Figure 5C A cross-sectional view of the connection structure of the red light emitting element and the red pixel driving circuit shown in FIG.

[0024] Figure 7B It is shown Figure 5C A cross-sectional view of a connection structure of a second light receiving element and a second sensor driving circuit shown in FIG.

[0025] Figure 8 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0026] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J and Figure 9K is a plan view showing a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure;

[0027] Figure 9L It is along Figure 9K A cross-sectional view taken along line II' shown in FIG.

[0028] Fig. 10A and Fig. 10B is a plan view showing a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure;

[0029] Fig.11A and Fig. 11B is a plan view showing a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure;

[0030] Fig. 12A , Fig. 12B and Fig. 12C is a plan view showing a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure;

[0031] Fig.12D It is along Fig. 12C A cross-sectional view taken along line II-II' shown in FIG.

[0032] Fig.13Ais a plan view showing a portion of a display panel according to one or more embodiments of the present disclosure;

[0033] Fig. 13B It is shown Fig.13A an enlarged plan view of a portion of

[0034] Fig. 13C It is along Fig. 13B A cross-sectional view taken along line III-III' shown in FIG.

[0035] Fig.14A and Fig. 14B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another component, it means that it can be directly set on, connected to or coupled to the other component, or a third component can be set between the component and the other component.

[0037] The same reference numerals refer to the same elements. In addition, in the drawings, the thickness, ratio and size of the components are exaggerated for the effective description of the technical content. The term "and / or" includes one or more combinations that can define the relevant components.

[0038] It will be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. The terms are used only for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present disclosure. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0039] In addition, terms such as “below,” “beneath,” “above,” “over,” etc. are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions shown in the drawings.

[0040] It should be understood that terms such as “include” and “have” are intended to indicate the presence of the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an overly ideal or overly formal sense unless clearly defined herein.

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure, Figure 2A is an exploded perspective view of a display device according to one or more embodiments of the present disclosure, and Figure 2B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0044] Reference Figure 1 , Figure 2A and Figure 2B , the display device DD according to one or more embodiments of the present disclosure may have a rectangular shape having short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 crossing the first direction DR1. However, the present disclosure is not limited thereto, and the display device DD may have various shapes (such as a circular shape or a polygonal shape).

[0045] The display device DD may be a device activated according to an electrical signal. The display device DD may include various embodiments. For example, the display device DD may be applied to an electronic device (such as a smart watch, a tablet computer, a laptop computer, a computer, and / or a smart TV, etc.).

[0046] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the present specification, the meaning of "in a plan view" may mean a state viewed from the third direction DR3 (e.g., on the third direction DR3). In other words, a "plan view" may refer to a view from above and / or may refer to an imaginary view in which all elements are visible or shown as if they are located on the same plane.

[0047] An upper surface of the display device DD may be defined as (or may be referred to as) a display surface IS and may be parallel to a plane defined by the first and second directions DR1 and DR2. An image (or images) IM generated by the display device DD may be provided to a user through the display surface IS.

[0048] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which an image IM is displayed. A user views the image IM through the transmission area TA. In the present embodiment, the transmission area TA is shown in a rectangular shape with a rounded (rounded) vertex. However, this is shown as an example, and the transmission area TA may have various shapes and is not limited to any one embodiment.

[0049] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a suitable color (e.g., a predetermined color). The border area BZA may be around the transmission area TA (e.g., may surround the transmission area TA). Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is merely illustrative, and the border area BZA may be provided to be adjacent to only one side of the transmission area TA, or the border area BZA may be omitted.

[0050] The display device DD can sense external input applied from the outside. The external input may include various types of input provided from the outside of the display device DD. For example, the external input may include an external input (e.g., hovering) applied close to the display device DD or adjacent to the display device DD (e.g., spaced apart from the display device DD by a suitable distance (e.g., a predetermined distance)), as well as contact by a part of the user's body (such as the user's hand US_F) or contact by a separate device (e.g., an active pen or a digitizer). In addition, the external input may have various forms (such as force, pressure, temperature, and / or light, etc.).

[0051] The display device DD can sense the user's biometric information (e.g., fingerprint) applied from the outside. The biometric information sensing area capable of sensing the user's biometric information may be set on the display surface IS of the display device DD. The biometric information sensing area may be set in the entire area of ​​the transmission area TA, or may be set in a partial area of ​​the transmission area TA. As an example of the present disclosure, Figure 1 It is shown that the entire transmission area TA is used as the bio-information sensing area. However, the present disclosure is not limited thereto.

[0052] The display device DD may include a window WM, a display module DM, and a case EDC. In the present embodiment, the window WM and the case EDC are combined with each other to define the appearance of the display device DD.

[0053] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded with an adhesive, or may include a glass substrate and a plastic film bonded with an adhesive.

[0054] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image IM according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0055] The display panel DP according to one or more embodiments of the present disclosure may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods, etc. In the following, the display panel DP will be described as an organic light-emitting display panel. However, the present disclosure is not limited thereto.

[0056] Reference Figure 2B , the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to one or more embodiments of the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel or a rigid display panel folded relative to a folding axis.

[0057] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or any other suitable substrate known to those of ordinary skill in the art.

[0058] The circuit layer DP_CL is disposed on the base layer BL. The circuit layer DP_CL is disposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image and / or a sensor driving circuit included in each of a plurality of sensors for identifying external information, etc. The external information may be biological information. As an example of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, and / or an illumination sensor, etc. In addition, the sensor may be an optical sensor that optically recognizes biological information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0059] The element layer DP_ED may include a light emitting element included in each of the pixels and a light receiving element included in each of the sensors. As an example of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that senses light reflected by a user's fingerprint or reacts to light. FIG. 6A to FIG. 8 The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0060] The encapsulation layer TFE encapsulates the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer, but is not particularly limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0061] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to one or more embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a continuous process. That is, when the input sensing layer ISL is directly disposed on the display panel DP, the adhesive film is not disposed between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, the adhesive film may be disposed between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL may not be manufactured by a process continuous with the display panel DP, and may be manufactured by a process separate from the display panel DP, and then fixed to the upper surface of the display panel DP by the adhesive film.

[0062] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the external input into an input signal (e.g., a predetermined input signal), and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. For example, the sensing electrodes may sense the external input in a capacitive manner. The display panel DP may receive an input signal from the input sensing layer ISL and may generate an image corresponding to the input signal.

[0063] The display module DM may further include a color filter layer CFL. As an example, the color filter layer CFL may be disposed on the input sensing layer ISL. However, the present disclosure is not limited thereto. In other embodiments, the color filter layer CFL may be disposed between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include a plurality of color filters and a black matrix.

[0064] Details of the structures of the input sensing layer ISL and the color filter layer CFL according to one or more embodiments of the present disclosure will be described later.

[0065] The display device DD according to one or more embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the color filter layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, and / or a pressure sensitive adhesive (PSA).

[0066] For example, Figure 2A As shown in , the display module DM may further include a driving chip DIC and sensor chips SIC1 and SIC2. As an example, the driving chip DIC and the sensor chips SIC1 and SIC2 may be mounted on the display panel DP. The driving chip DIC and the sensor chips SIC1 and SIC2 may be disposed adjacent to an end portion (hereinafter, referred to as a first end portion) of the display panel DP. Figure 2A A structure is shown in which the driving chip DIC and the sensor chips SIC1 and SIC2 are disposed adjacent to the first end of the display panel DP, but the present disclosure is not limited thereto. For example, the driving chip DIC may be disposed adjacent to the first end of the display panel DP, and the sensor chips SIC1 and SIC2 may be disposed adjacent to the second end of the display panel DP opposite to the first end.

[0067] As an example, the sensor chips SIC1 and SIC2 may include a first sensor chip SIC1 disposed on one side (hereinafter, referred to as the first side) of the driver chip DIC and a second sensor chip SIC2 disposed on a second side of the driver chip DIC that is different from the first side. In other embodiments, both the sensor chips SIC1 and SIC2 may be disposed on the same side of the driver chip DIC. Alternatively, the first sensor chip SIC1 and the second sensor chip SIC2 may be integrated into one sensor chip, and the one sensor chip may be disposed adjacent to the driver chip DIC. In the present disclosure, the number of sensor chips SIC1 and SIC2 and the number of driver chips DIC are not particularly limited.

[0068] The housing EDC is coupled to the window WM. The housing EDC is coupled to the window WM to provide an internal space (e.g., a predetermined internal space). The display module DM may be accommodated in the internal space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates composed of a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. In one or more embodiments, a battery module or the like may be disposed between the display module DM and the housing EDC to supply the power necessary for the overall operation of the display device DD.

[0069] Figure 3 is a block diagram of a display device according to an example embodiment of the present disclosure.

[0070] Reference Figure 3 , the display device DD includes a display panel DP, a panel driver, and a driving controller 100. As an example, the panel driver includes a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400, and a readout circuit 500. Figure 3 , the scan driver 300 and the emission driver 350 are shown as being located in the display panel DP, while the data driver 200, the voltage generator 400 and the readout circuit 500 are shown as being located outside the display panel DP. However, the present disclosure is not limited thereto, and as will be understood by one of ordinary skill in the art, the various components of the panel driver may be located in the display panel DP or outside the display panel DP, respectively.

[0071] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA obtained by converting the data format of the image signal RGB into an interface specification suitable for the data driver 200. The driving controller 100 outputs the first control signal SCS, the second control signal ECS, the third control signal DCS and the fourth control signal RCS.

[0072] The data driver 200 receives the third control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal is an analog voltage corresponding to a gray value (e.g., a grayscale value) of the image data DATA. As an example of the present disclosure, the data driver 200 may be embedded in Figure 2A The driver chip shown in DIC.

[0073] The scan driver 300 receives a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS.

[0074] The voltage generator 400 generates voltages required for the operation of the display panel DP. In this embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, a bias voltage Vbias, and a reset voltage Vrst.

[0075] The display panel DP may include a plurality of areas TA (eg, Figure 1 ) and the display area DA corresponding to the frame area BZA (for example, Figure 1 ) corresponds to the non-display area NDA.

[0076] The display panel DP may include a plurality of pixels PX disposed in the display area DA and a plurality of sensors FX disposed in the display area DA. As an example of the present disclosure, each of the plurality of sensors FX may be disposed between two pixels PX adjacent to each other (e.g., two pixels PX adjacent to each other with only one sensor FX disposed therebetween). The plurality of pixels PX and the plurality of sensors FX may be alternately arranged in the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. That is, two or more pixels PX may be disposed between two sensors FX adjacent to each other in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be disposed between two sensors FX adjacent to each other in the second direction DR2 among the plurality of sensors FX.

[0077] The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn extend in the first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn are arranged to be spaced apart (e.g., spaced apart) from each other in the second direction DR2. The data lines DL1 to DLm and the readout lines RL1 to RLh extend in the second direction DR2 and are arranged to be spaced apart (eg, spaced apart) from each other in the first direction DR1. Here, n, m, and h are natural numbers of 1 or more.

[0078] The plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto, and may be different in one or more other embodiments.

[0079] The sensors FX are electrically connected to the write scan lines SWL1 to SWLn and the readout lines RL1 to RLh, respectively. Each of the plurality of sensors FX may be electrically connected to one scan line. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may vary. In one or more embodiments of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to 1 / 2, 1 / 4, or 1 / 8 of the number of data lines DL1 to DLm.

[0080] The scan driver 300 may be disposed in the non-display area NDA of the display panel DP. The scan driver 300 receives a first control signal SCS from the drive controller 100. The scan driver 300 outputs an initialization scan signal to the initialization scan lines SIL1 to SILn in response to the first control signal SCS, and outputs a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn and output a black scan signal to the black scan lines SBL1 to SBLn in response to the first control signal SCS. Optionally, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0081] The emission driver 350 may be disposed in the non-display area NDA of the display panel DP. The emission driver 350 receives the second control signal ECS from the drive controller 100. The emission driver 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, in one or more other embodiments, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may be omitted, and the scan driver 300 may output the emission control signal to the emission control lines EML1 to EMLn.

[0082] The readout circuit 500 receives the fourth control signal RCS from the driving controller 100. The readout circuit 500 may receive the sensing signals from the sensing lines RL1 to RLh in response to the fourth control signal RCS. The readout circuit 500 may process the sensing signals received from the sensing lines RL1 to RLh and may provide the processed sensing signals S_FS to the driving controller 100. The driving controller 100 may recognize the bio-information based on the processed sensing signals S_FS. As an example, the readout circuit 500 may be embedded in Figure 2A The sensor chips SIC1 and SIC2 are shown in FIG.

[0083] Figure 4A is a circuit diagram showing a pixel and a sensor according to one or more embodiments of the present disclosure, and Figure 4B Is used to describe Figure 4A The waveform diagram of the operation of the pixel and sensor is shown in FIG.

[0084] exist Figure 4A In the Figure 3The equivalent circuit diagram of one pixel PXij among the plurality of pixels PX shown in FIG is taken as an example. Since each of the plurality of pixels PX has the same circuit structure or substantially the same circuit structure, the description of the circuit structure of the pixel PXij can be applied to (or substantially applied to) the remaining pixels, and the detailed description of the remaining pixels will be omitted. Figure 4A It is shown in Figure 3 An equivalent circuit diagram of one sensor FXdj among the plurality of sensors FX shown in FIG. 1 is taken as an example. Since each of the plurality of sensors FX has the same circuit structure or substantially the same circuit structure, the description of the circuit structure of the sensor FXdj can be applied to (or substantially applied to) the remaining sensors, and a detailed description of the remaining sensors will be omitted.

[0085] Reference Figure 4A , the pixel PXij is connected to the i-th data line DLi of the data lines DL1 to DLm, the j-th initialization scan line SILj of the initialization scan line SIL1 to SILn, the j-th compensation scan line SCLj of the compensation scan line SCL1 to SCLn, the j-th write scan line SWLj of the write scan line SWL1 to SWLn, the j-th black scan line SBLj of the black scan line SBL1 to SBLn, and the j-th emission control line EMLj of the emission control line EML1 to EMLn.

[0086] The pixel PXij includes a light emitting element ED and a pixel driving circuit P_PD. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer.

[0087] The pixel driving circuit P_PD includes a first transistor to an eighth transistor T1, T2, T3, T4, T5, T6, T7 and T8 and a capacitor Cst. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the eighth transistor T8 may be P-type transistors, and the others may be N-type transistors. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2 and the fifth transistor T5 to the eighth transistor T8 may be LTPS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0088] The configuration of the pixel driving circuit P_PD according to the present disclosure is not limited to Figure 4A The embodiment shown in . Figure 4AThe pixel driving circuit P_PD shown in FIG. 1 is only an example, and the configuration of the pixel driving circuit P_PD may be modified and implemented. For example, all of the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be P-type transistors (e.g., Figure 4A as shown in ) or N-type transistor.

[0089] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a value similar to that input to the display device DD (e.g., see Figure 3 ) of the image signal RGB (for example, see Figure 3 ) corresponds to the voltage level.

[0090] As an example, the pixel PXij may be connected to a first driving voltage line VL1 and a second driving voltage line VL2, a first initialization voltage line VIL and a second initialization voltage line VAIL, and a bias voltage line VBL. The first driving voltage line VL1 may transmit a first driving voltage ELVDD to the pixel PXij, and the second driving voltage line VL2 may transmit a second driving voltage ELVSS to the pixel PXij. The first initialization voltage line VIL may transmit a first initialization voltage Vint to the pixel PXij, and the second initialization voltage line VAIL may transmit a second initialization voltage Vaint to the pixel PXij. The bias voltage line VBL may transmit a bias voltage Vbias to the pixel PXij.

[0091] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to the anode electrode of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (or one terminal) of the capacitor Cst (e.g., the first node N1). The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2 to supply the driving current Id to the light emitting element ED.

[0092] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on in response to the j-th write scan signal SWj received through the j-th write scan line SWLj to transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0093] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on in response to the j-th compensation scan signal SCj received through the j-th compensation scan line SCLj to diode-connect the first transistor T1 by connecting (e.g., electrically connecting) the third electrode and the second electrode of the first transistor T1 to each other.

[0094] The fourth transistor T4 is connected between the first initialization voltage line VIL to which the first initialization voltage Vint is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VIL through which the first initialization voltage Vint is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line SILj. The fourth transistor T4 is turned on in response to the jth initialization scan signal SIj received through the jth initialization scan line SILj. The turned-on fourth transistor T4 initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1) by transmitting the first initialization voltage Vint to the first node N1.

[0095] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0096] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode electrode of the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the jth emission control line EMLj.

[0097] The fifth transistor T5 and the sixth transistor T6 are simultaneously (e.g., concurrently) turned on in response to the jth emission control signal EMj received through the jth emission control line EMLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED.

[0098] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VAIL through which a second initialization voltage Vaint is transmitted, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to a j-th black scan line SBLj. The second initialization voltage Vaint may have a voltage level lower than or equal to a voltage level of the first initialization voltage Vint.

[0099] The eighth transistor T8 includes a first electrode connected to a bias voltage line VBL through which a bias voltage Vbias is transmitted, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to a j-th black scan line SBLj.

[0100] The seventh transistor T7 and the eighth transistor T8 are simultaneously (e.g., concurrently) turned on in response to the jth black scan signal SBj received through the jth black scan line SBLj. The second initialization voltage Vaint applied by the turned-on seventh transistor T7 may be transmitted to the anode electrode of the light emitting element ED. Therefore, the anode electrode of the light emitting element ED may be initialized to the second initialization voltage Vaint. The bias voltage Vbias applied by the turned-on eighth transistor T8 may be transmitted to the first electrode of the first transistor T1. Therefore, the bias voltage Vbias may be periodically applied to the first electrode of the first transistor T1, and therefore, it is possible to prevent or reduce the degradation of the display quality caused by the potential difference between the first electrode and the second electrode of the first transistor T1 increasing to a specific level or more due to the hysteresis phenomenon.

[0101] As described above, one end (e.g., one terminal) of the capacitor Cst is connected to the third electrode of the first transistor T1, and the opposite end (e.g., the opposite terminal) of the capacitor Cst is connected to the first driving voltage line VL1. The cathode electrode of the light emitting element ED may be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the voltage level of the first driving voltage ELVDD. As an example, the second driving voltage ELVSS may have a voltage level lower than the voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint.

[0102] Reference Figure 4A and Figure 4B, the j-th emission control signal EMj has a high level during the non-emission period NEP. In the non-emission period NEP, the j-th initialization scan signal SIj is activated. When the j-th initialization scan signal SIj of a high level is provided through the j-th initialization scan line SILj during the activation period AP1 (hereinafter, referred to as the first activation period) of the j-th initialization scan signal SIj, the fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj of a high level. The first initialization voltage Vint is transmitted to the third electrode of the first transistor T1 through the turned-on fourth transistor T4, and the first node N1 is initialized by the first initialization voltage Vint. Therefore, the first activation period AP1 can be defined as (or referred to as) the initialization period of the pixel PXij.

[0103] Next, the j-th compensation scan signal SCj is activated, and when the j-th compensation scan signal SCj having a high level is supplied through the j-th compensation scan line SCLj during an activation period AP2 (hereinafter, referred to as a second activation period) of the j-th compensation scan signal SCj, the third transistor T3 is turned on. The first transistor T1 is diode-connected through the turned-on third transistor T3 and is biased in the forward direction. The first activation period AP1 may not overlap with the second activation period AP2.

[0104] The jth write scan signal SWj is activated in the second activation period AP2 (for example, during a portion of the second activation period AP2). The jth write scan signal SWj has a low level during the activation period AP4 (hereinafter, referred to as the fourth activation period). During the fourth activation period AP4, the second transistor T2 is turned on by the low-level jth write scan signal SWj. Then, the compensation voltage "Di-Vth" of the i-th data signal Di supplied from the i-th data line DLi by reducing the threshold voltage (Vth) of the first transistor T1 is applied to the third electrode of the first transistor T1. That is, the potential of the third electrode of the first transistor T1 may be the compensation voltage "Di-Vth". The fourth activation period AP4 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the fourth activation period AP4.

[0105] The first driving voltage ELVDD and the compensation voltage "Di-Vth" may be applied to both ends (e.g., two opposite terminals) of the capacitor Cst, and charges corresponding to the voltage difference between the two ends (e.g., two opposite terminals) may be stored in the capacitor Cst. Here, the second activation period AP2 of the j-th compensation scan signal SCj may be referred to as a compensation period of the pixel PXij.

[0106] On the other hand, the jth black scan signal SBj is activated in the second activation period AP2 of the jth compensation scan signal SCj. The jth black scan signal SBj has a low level during the activation period AP3 (hereinafter, referred to as the third activation period). During the third activation period AP3, the seventh transistor T7 is turned on in response to the jth black scan signal SBj of the low level applied through the jth black scan line SBLj. A portion of the drive current Id may be discharged through the seventh transistor T7 as a bypass current Ibp. The third activation period AP3 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the third activation period AP3. The third activation period AP3 may be before the fourth activation period AP4 and may not overlap with the fourth activation period AP4.

[0107] When the pixel PXij displays a black image, if the light emitting element ED emits light even if the minimum driving current of the first transistor T1 flows as the driving current Id, the pixel PXij cannot display the black image normally. Therefore, the seventh transistor T7 in the pixel PXij according to one or more embodiments of the present disclosure can allocate a part of the minimum driving current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the light emitting element ED. Here, the minimum driving current of the first transistor T1 means (or refers to) the current flowing to the first transistor T1 under the condition that the gate-source voltage (Vgs) of the first transistor T1 is less than the threshold voltage (Vth) and the first transistor T1 is therefore turned off. Under the condition that the first transistor T1 is turned off, the minimum driving current (for example, a current of 10pA or less) flowing to the first transistor T1 is transmitted to the light emitting element ED to display a black image of black grayscale. When the pixel PXij displays a black image, the bypass current Ibp has a relatively large effect on the minimum driving current, while when an image such as a normal image or a white image is displayed, the bypass current Ibp has a relatively small effect on the driving current Id. Therefore, when a black image is displayed, a current (i.e., a light emitting current Ied) that is reduced by the amount of the bypass current Ibp escaping from the driving current Id through the seventh transistor T7 can be provided to the light emitting element ED to clearly display the black image. Therefore, the pixel PXij can implement an accurate black grayscale image (i.e., an accurate black grayscale image) using the seventh transistor T7, and therefore, the contrast can be improved.

[0108] Next, the j-th emission control signal EMj supplied from the j-th emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the low-level emission control signal EMj. Then, a driving current Id corresponding to the voltage difference between the voltage of the third electrode of the first transistor T1 and the first driving voltage ELVDD is generated, and the driving current Id is supplied to the light emitting element ED through the sixth transistor T6, so that the light emitting current Ied flows through the light emitting element ED.

[0109] Return to reference Figure 4A The sensor FXdj is connected to the dth readout line RLd, the jth write scan line SWLj, and the reset control line SRL among the readout lines RL1 to RLh.

[0110] The sensor FXdj includes a light receiving element OPD and a sensor driving circuit O_SD. As an example of the present disclosure, the light receiving element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. Figure 4A , a structure in which the sensor FXdj includes one light receiving element OPD is shown, but the present disclosure is not limited thereto. For example, the sensor FXdj may include a plurality of light receiving elements OPD connected in parallel to each other.

[0111] The anode electrode of the light receiving element OPD may be connected to the first sensing node SN1, and the cathode electrode of the light receiving element OPD may be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The cathode electrode of the light receiving element OPD may be electrically connected to the cathode electrode of the light emitting element ED. As an example of the present disclosure, the cathode electrode of the light receiving element OPD may be integrally formed with the cathode electrode of the light emitting element ED to form a common cathode electrode.

[0112] The sensor driving circuit O_SD includes three transistors ST1, ST2 and ST3. The three transistors ST1 to ST3 may be a reset transistor ST1, an amplifying transistor ST2 and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifying transistor ST2 and the output transistor ST3 may be an oxide semiconductor transistor. As an example, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, the present disclosure is not limited thereto, and at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS transistor.

[0113] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and some of them may be N-type transistors. As an example, the amplifying transistor ST2 and the output transistor ST3 may be PMOS transistors, and the reset transistor ST1 may be an NMOS transistor. However, the present disclosure is not limited thereto, for example, all of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be N-type transistors or may be P-type transistors.

[0114] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (e.g., the reset transistor ST1) may be transistors of the same type as the third transistor T3 and the fourth transistor T4 of the pixel PXij. The amplifying transistor ST2 and the output transistor ST3 may be transistors of the same type as the first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8 of the pixel PXij.

[0115] The circuit configuration of the sensor driving circuit O_SD according to the present disclosure is not limited to Figure 4A . Figure 4A The sensor driving circuit O_SD shown in FIG. 1 is merely an example, and the configuration of the sensor driving circuit O_SD may be modified and implemented.

[0116] The reset transistor ST1 includes a first electrode receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal SR. The reset transistor ST1 can reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal SR. The reset control signal SR may be a signal provided by a reset control line SRL. However, the present disclosure is not limited thereto. Alternatively, the reset control signal SR may be a jth compensation scan signal SCj supplied by a jth compensation scan line SCLj. That is, the reset transistor ST1 may receive a jth compensation scan signal SCj supplied from a jth compensation scan line SCLj as the reset control signal SR. As an example, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS at least during the activation period of the reset control signal SR. The reset voltage Vrst may be transmitted to the sensor FXdj through the reset voltage line VRL. The reset voltage Vrst may be a DC voltage maintained at a voltage level lower than the voltage level of the second drive voltage ELVSS. However, the present disclosure is not limited thereto.

[0117] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter, referred to as a first sub-reset transistor and a second sub-reset transistor). In this case, a third electrode of the first sub-reset transistor and a third electrode of the second sub-reset transistor are connected to a reset control line SRL. In addition, a second electrode of the first sub-reset transistor may be electrically connected to a first electrode of the second sub-reset transistor. In addition, a reset voltage Vrst may be applied to a first electrode of the first sub-reset transistor, and a second electrode of the second sub-reset transistor may be electrically connected to a first sensing node SN1. However, the number of sub-reset transistors is not limited thereto and may be modified differently.

[0118] The amplifier transistor ST2 includes a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 can be turned on in response to the potential of the first sensing node SN1 to apply the sensing drive voltage SLVD to the second sensing node SN2. As an example of the present disclosure, the sensing drive voltage SLVD can be one of the first drive voltage ELVDD, the first initialization voltage Vint, and the second initialization voltage Vaint. When the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of the amplifier transistor ST2 can be electrically connected to the first drive voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage Vint, the first electrode of the amplifier transistor ST2 can be electrically connected to the first initialization voltage line VIL, and when the sensing drive voltage SLVD is the second initialization voltage Vaint, the first electrode of the amplifier transistor ST2 can be electrically connected to the second initialization voltage line VAIL.

[0119] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. The output transistor ST3 can transmit the sensing signal FSd to the dth readout line RLd in response to the output control signal. The output control signal can be the jth write scan signal SWj supplied through the jth write scan line SWLj. That is, the output transistor ST3 can receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0120] The light receiving element OPD of the sensor FXdj may be exposed to light during the emission period of the light emitting element ED. The light may be light output from the light emitting element ED.

[0121] If the user's hand US_F (for example, see Figure 1 ) touch the display surface IS (see, for example, Figure 1), the light receiving element OPD generates a photocharge corresponding to the light reflected by the ridges of the fingerprint or the valleys between the ridges. The amount of current flowing through the light receiving element OPD varies by the generated photocharge. When the light receiving element OPD receives the light reflected by the ridges of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a first current, and when the light receiving element OPD receives the light reflected by the valleys of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a second current. Because the amount of light reflected by the ridges of the fingerprint is different from the amount of light reflected by the valleys of the fingerprint, this difference in the amount of light manifests itself as a difference between the first current and the second current. When the first current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a first potential, and when the second current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a second potential. As an example of the present disclosure, the first current may be greater than the second current, in which case the first potential may be lower than the second potential.

[0122] The amplifying transistor ST2 may be a source follower amplifier generating a source-drain current proportional to the potential of the first sensing node SN1 input to the third electrode.

[0123] During the fourth activation period AP4, the j-th write scan signal SWj having a low level is supplied to the output transistor ST3 through the j-th write scan line SWLj. When the output transistor ST3 is turned on in response to the j-th write scan signal SWj of the low level, the sensing signal FSd corresponding to the current flowing through the amplifying transistor ST2 can be output to the d-th readout line RLd.

[0124] Next, when a high-level reset control signal SR is supplied through the reset control line SRL during the reset period, the reset transistor ST1 is turned on. The reset period may be defined as (or referred to as) an activation period (i.e., a high-level period) of the reset control signal SR. Alternatively, when the reset transistor ST1 is formed by a P-type transistor, a low-level reset control signal SR may be supplied to the reset control line SRL during the reset period. During the reset period, the first sensing node SN1 may be reset to a potential corresponding to the reset voltage Vrst. As an example, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS. However, the present disclosure is not limited thereto.

[0125] Next, when the reset period ends, the light receiving element OPD may generate photo charges corresponding to the received light, and the generated photo charges may be accumulated in the first sensing node SN1.

[0126] Figure 5A is a schematic plan view showing the arrangement of a pixel driving circuit and a sensor driving circuit according to one or more embodiments of the present disclosure. Figure 5B is a plan view showing the arrangement of light emitting elements and light receiving elements according to one or more embodiments of the present disclosure. Figure 5C 1 is a plan view showing a connection relationship between a light emitting element and a pixel driving circuit and a connection relationship between a light receiving element and a sensor driving circuit according to one or more embodiments of the present disclosure.

[0127] Reference FIG. 5A to FIG. 5C , the display panel DP includes a plurality of pixels PXR, PXG1, PXG2, and PXB and a plurality of sensors FX1 and FX2.

[0128] A plurality of pixels PXR, PXG1, PXG2, and PXB may be grouped into a plurality of reference pixel units RPU. As an example of the present disclosure, each reference pixel unit RPU may include four pixels (i.e., a first pixel PXB (hereinafter referred to as a blue pixel), a second pixel PXR (hereinafter referred to as a red pixel), and two third pixels PXG1 and PXG2 (hereinafter referred to as a first green pixel and a second green pixel)). However, the number of pixels included in each reference pixel unit RPU is not limited thereto. Optionally, each reference pixel unit RPU may include three pixels (i.e., a blue pixel PXB, a red pixel PXR, and a green pixel (one of the first green pixel PXG1 and the second green pixel PXG2)).

[0129] The blue pixel PXB includes a first light-emitting element ED_B (hereinafter referred to as a blue light-emitting element) and a blue pixel driving circuit B_PD (or a first pixel driving circuit). The red pixel PXR includes a second light-emitting element ED_R (hereinafter referred to as a red light-emitting element) and a red pixel driving circuit R_PD (or a second pixel driving circuit). The first green pixel PXG1 includes a third light-emitting element ED_G1 (hereinafter referred to as a first green light-emitting element) and a first green pixel driving circuit G1_PD (hereinafter referred to as a third pixel driving circuit), and the second green pixel PXG2 includes a fourth light-emitting element ED_G2 (hereinafter referred to as a second green light-emitting element) and a second green pixel driving circuit G2_PD (hereinafter referred to as a fourth pixel driving circuit).

[0130] As an example of the present disclosure, the blue light emitting element ED_B outputs a first color light (e.g., blue light), and the red light emitting element ED_R outputs a second color light (e.g., red light) different from the first color light. Each of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 outputs a third color light (e.g., green light) different from the first color light and the second color light. The green light output from the first green light emitting element ED_G1 may have the same wavelength band as the green light output from the second green light emitting element ED_G2.

[0131] In the first direction DR1 and the second direction DR2, the red light emitting element ED_R and the blue light emitting element ED_B may be arranged alternately and repeatedly. The first green light emitting element ED_G1 and the second green light emitting element ED_G2 may be arranged alternately and repeatedly in the first direction DR1 and alternately and repeatedly in the second direction DR2. The light emitting elements ED_R, ED_G1, ED_G2, and ED_B may be arranged in a first row (e.g., odd-numbered row) parallel to the first direction DR1 in the order of the red light emitting element ED_R, the second green light emitting element ED_G2, the blue light emitting element ED_B, and the first green light emitting element ED_G1. The light emitting elements ED_R, ED_G1, ED_G2, and ED_B may be arranged in a second row (e.g., even-numbered row) parallel to the first direction DR1 in the order of the blue light emitting element ED_B, the first green light emitting element ED_G1, the red light emitting element ED_R, and the second green light emitting element ED_G2.

[0132] As an example of the present disclosure, the red light emitting element ED_R may have a size larger than the size of the first green light emitting element ED_G1 and the second green light emitting element ED_G2. In addition, the blue light emitting element ED_B may have a size greater than or equal to the size of the red light emitting element ED_R. The size of each of the light emitting elements ED_R, ED_G1, ED_G2, and ED_B is not limited thereto, and may be modified and applied differently. For example, in another embodiment of the present disclosure, the light emitting elements ED_R, ED_G1, ED_G2, and ED_B may have the same size (or substantially the same size).

[0133] The first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have the same shape (or substantially the same shape) as the red light emitting element ED_R and the blue light emitting element ED_B. As an example of the present disclosure, each of the red light emitting element ED_R and the blue light emitting element ED_B and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have a circular shape. Alternatively, each of the red light emitting element ED_R and the blue light emitting element ED_B and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have a polygonal shape (e.g., a shape of one of an octagonal shape, a square shape, and a rectangular shape). However, the present disclosure is not limited thereto, and the red light emitting element ED_R and the blue light emitting element ED_B and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 may have different suitable shapes as will be understood by those of ordinary skill in the art.

[0134] The blue light emitting element ED_B is electrically connected to the blue pixel driving circuit B_PD (or the first pixel driving circuit). Specifically, the blue light emitting element ED_B includes a blue anode electrode B_AE (or the first pixel anode electrode) and a blue light emitting layer B_EL, and the blue anode electrode B_AE is electrically connected to the blue pixel driving circuit B_PD through a blue pixel connecting electrode B_CNE (or the first pixel connecting electrode). The blue pixel connecting electrode B_CNE is respectively connected to the blue anode electrode B_AE and the blue pixel driving circuit B_PD through a blue contact hole B_CH.

[0135] The red light emitting element ED_R is electrically connected to the red pixel driving circuit R_PD (or the second pixel driving circuit). Specifically, the red light emitting element ED_R includes a red anode electrode R_AE (or the second pixel anode electrode) and a red light emitting layer R_EL, and the red anode electrode R_AE is electrically connected to the red pixel driving circuit R_PD through a red pixel connecting electrode R_CNE (or the second pixel connecting electrode). The red pixel connecting electrode R_CNE is respectively connected to the red anode electrode R_AE and the red pixel driving circuit R_PD through a red contact hole R_CH.

[0136] The first green light emitting element ED_G1 is electrically connected to the first green pixel driving circuit G1_PD (or the third pixel driving circuit). In detail, the first green light emitting element ED_G1 includes a first green anode electrode G1_AE (or the third pixel anode electrode) and a first green light emitting layer G1_EL, and the first green anode electrode G1_AE is electrically connected to the first green pixel driving circuit G1_PD through a first green pixel connecting electrode G1_CNE (or the third pixel connecting electrode). The first green pixel connecting electrode G1_CNE is respectively connected to the first green anode electrode G1_AE and the first green pixel driving circuit G1_PD through a first green contact hole G1_CH. The second green light emitting element ED_G2 is electrically connected to the second green pixel driving circuit G2_PD (or the fourth pixel driving circuit). For example, the second green light emitting element ED_G2 may include a second green anode electrode G2_AE (or the fourth pixel anode electrode) and a second green light emitting layer G2_EL, and the second green anode electrode G2_AE may be electrically connected to the second green pixel driving circuit G2_PD through a second green pixel connecting electrode G2_CNE (or the fourth pixel connecting electrode). The second green pixel connection electrode G2_CNE is connected to the second green anode electrode G2_AE and the second green pixel driving circuit G2_PD through the second green contact hole G2_CH, respectively.

[0137] The first green light emitting layer G1_EL and the second green light emitting layer G2_EL may have the same size and the same shape. However, the present disclosure is not limited thereto. For example, the first green light emitting layer G1_EL and the second green light emitting layer G2_EL may have the same size (or the same area) but different shapes. In addition, the first green anode electrode G1_AE and the second green anode electrode G2_AE may have different sizes (or different areas) and different shapes.

[0138] In the first row (e.g., odd-numbered row), the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD may be arranged in the order of a blue pixel driving circuit B_PD, a second green pixel driving circuit G2_PD, a red pixel driving circuit R_PD, and a first green pixel driving circuit G1_PD. In the second row (e.g., even-numbered row), the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD may be arranged in the order of a blue pixel driving circuit B_PD, a first green pixel driving circuit G1_PD, a red pixel driving circuit R_PD, and a second green pixel driving circuit G2_PD. The order of the pixel driving circuits R_PD, G1_PD, G2_PD, and B_PD in the first row and the second row may be repeated in the first direction DR1. The first row and the second row may be repeated along the second direction DR2.

[0139] As an example, a blue pixel driving circuit B_PD is arranged in a first column parallel to the second direction DR2, and a first green pixel driving circuit G1_PD and a second green pixel driving circuit G2_PD are alternately arranged in a second column. The blue pixel driving circuit B_PD may be arranged continuously in the second direction DR2. The red pixel driving circuit R_PD is arranged in a third column, and the second green pixel driving circuit G2_PD and the first green pixel driving circuit G1_PD are alternately arranged in a fourth column. The red pixel driving circuit R_PD may be arranged continuously in the second direction DR2.

[0140] As described above, when the pixel driving circuits of the same color are continuously arranged in each column, the data signal applied to each data line can also be fixed as a data signal for one color. Since the data signal applied to one data line is fixed as a data signal for one color, power consumption can be reduced compared to a structure in which data signals for two or more colors are repeatedly applied to one data line.

[0141] Each of the sensors FX1 and FX2 includes a light receiving element OPD1 or OPD2 and a sensor driving circuit O_SD1 or O_SD2. As an example of the present disclosure, one light receiving element OPD1 or OPD2 can be set to correspond to one reference pixel unit RPU. However, the number of light receiving elements set corresponding to each reference pixel unit RPU is not limited thereto. For example, two light receiving elements can be set correspondingly in each reference pixel unit RPU.

[0142] A plurality of light receiving elements OPD1 and OPD2 are arranged in a first direction DR1 and a second direction DR2 in the display panel DP. When the first direction DR1 is defined as (e.g., referred to as) a row direction and the second direction DR2 is defined as (e.g., referred to as) a column direction, light receiving elements disposed in a first row (e.g., an odd row) among the light receiving elements OPD1 and OPD2 are referred to as first light receiving elements OPD1, and light receiving elements disposed in a second row (e.g., an even row) among the light receiving elements OPD1 and OPD2 are referred to as second light receiving elements OPD2.

[0143] Each of the first light receiving element OPD1 and the second light receiving element OPD2 is disposed between the red light emitting element ED_R and the blue light emitting element ED_B in the first direction DR1. The first light receiving element OPD1 is disposed between the first green light emitting element ED_G1 and the second green light emitting element ED_G2 adjacent to each other in the second direction DR2, and the second light receiving element OPD2 is disposed between the first green light emitting element ED_G1 and the second green light emitting element ED_G2 adjacent to each other in the second direction DR2.

[0144] The sensor driving circuit O_SD1 or O_SD2 is arranged in the display panel DP in the first direction DR1 and the second direction DR2. Each of the sensor driving circuits O_SD1 and O_SD2 may have the same length as the red pixel driving circuit R_PD and the blue pixel driving circuit B_PD and the first green pixel driving circuit G1_PD and the second green pixel driving circuit G2_PD in the second direction DR2. The sensor driving circuit disposed in the first row (e.g., odd row) among the sensor driving circuits O_SD1 and O_SD2 is referred to as the first sensor driving circuit O_SD1, and the sensor driving circuit disposed in the second row (e.g., even row) among the sensor driving circuits O_SD1 and O_SD2 is referred to as the second sensor driving circuit O_SD2. The first sensor driving circuit O_SD1 and the second sensor driving circuit O_SD2 are alternately disposed in the second direction DR2 in the fifth column parallel to the second direction DR2. The fifth column may be adjacent to the fourth column, and the first to fifth columns may be repeated in the first direction DR1.

[0145] The first light receiving element OPD1 is connected to the first sensor driving circuit O_SD1, and the second light receiving element OPD2 is connected to the second sensor driving circuit O_SD2. As an example, the first light receiving element OPD1 may be disposed at a position overlapping with the first sensor driving circuit O_SD1 in a plan view, and the second light receiving element OPD2 may be disposed at a position not overlapping with the second sensor driving circuit O_SD2 in a plan view.

[0146] The first light receiving element OPD1 includes a first sensor anode electrode O_AE1 (or a first row anode electrode) and a first photoelectric conversion layer O_RL1, and the second light receiving element OPD2 includes a second sensor anode electrode O_AE2 (or a second row anode electrode) and a second photoelectric conversion layer O_RL2. The first sensor anode electrode O_AE1 is disposed at a position overlapping with the first sensor driving circuit O_SD1. The first sensor anode electrode O_AE1 is directly connected to the first sensor driving circuit O_SD1 through the first sensor contact hole O_CH1. The second sensor anode electrode O_AE2 is disposed at a position not overlapping with the second sensor driving circuit O_SD2. The second light receiving element OPD2 also includes a sensor connection electrode O_CNE2, which extends from the second sensor anode electrode O_AE2 in the first direction DR1 to overlap with the second sensor driving circuit O_SD2. That is, the sensor connection electrode O_CNE2 has a shape integral with the second sensor anode electrode O_AE2. The sensor connection electrode O_CNE2 is directly connected to the second sensor driving circuit O_SD2 through the second sensor contact hole O_CH2.

[0147] As an example of the present disclosure, the first light receiving element OPD1 further includes a dummy connection electrode D_CNE1 extending from the first sensor anode electrode O_AE1 in the first direction DR1. That is, the dummy connection electrode D_CNE1 has a shape integral with the first sensor anode electrode O_AE1. The sum of the area of ​​the first sensor anode electrode O_AE1 and the area of ​​the dummy connection electrode D_CNE1 may be the same as the sum of the area of ​​the second sensor anode electrode O_AE2 and the area of ​​the sensor connection electrode O_CNE2.

[0148] As an example, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have the same shape as each of the light emitting elements ED_G1, ED_G2, ED_R, and ED_B. For example, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a circular shape. However, the shape of each of the first light receiving element OPD1 and the second light receiving element OPD2 is not limited thereto. For example, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a polygonal shape (e.g., a shape such as an octagon, a square, a rectangle, etc.). Alternatively, each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a shape different from the shape of at least one of the light emitting elements ED_G1, ED_G2, ED_R, and ED_B.

[0149] Each of the first light receiving element OPD1 and the second light receiving element OPD2 may have a size smaller than or equal to that of each of the first green light emitting element ED_G1 and the second green light emitting element ED_G2. However, the size of each of the first light receiving element OPD1 and the second light receiving element OPD2 is not particularly limited and may be modified and applied differently.

[0150] The first sensor anode electrode O_AE1 and the second sensor anode electrode O_AE2, the sensor connection electrode O_CNE2, and the dummy connection electrode D_CNE1 may be disposed at the same layer (e.g., at the same layer) as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE. In this case, the first sensor anode electrode O_AE1 and the second sensor anode electrode O_AE2, the sensor connection electrode O_CNE2, and the dummy connection electrode D_CNE1 may include the same material as the anode electrodes R_AE, G1_AE, G2_AE, and B_AE, and may be disposed at the same layer (e.g., at the same layer) by the same process.

[0151] The first and second green pixel connection electrodes G1_CNE and G2_CNE, the red pixel connection electrode R_CNE and the blue pixel connection electrode B_CNE may be disposed at different layers (e.g., at different layers) than the anode electrodes R_AE, G1_AE, G2_AE and B_AE, the first and second sensor anode electrodes O_AE1 and O_AE2, the sensor connection electrode O_CNE2 and the dummy connection electrode D_CNE1.

[0152] Anode electrodes R_AE, G1_AE, G2_AE, and B_AE, first and second sensor anode electrodes O_AE1 and O_AE2, sensor connection electrodes O_CNE2, and dummy connection electrodes D_CNE1 may be included in an element layer DP_ED (eg, see Fig. 7A and Figure 7B ), and the first green pixel connection electrode G1_CNE and the second green pixel connection electrode G2_CNE, the red pixel connection electrode R_CNE and the blue pixel connection electrode B_CNE may be included in the circuit layer DP_CL (eg, see Fig. 7A and Figure 7B )middle.

[0153] The circuit layer DP_CL also includes a shielding electrode RSE overlapping (e.g., partially overlapping) the first sensor driving circuit O_PD1 and the second sensor driving circuit O_PD2. As an example, the first green pixel connection electrode G1_CNE and the second green pixel connection electrode G2_CNE, the red pixel connection electrode R_CNE, and the blue pixel connection electrode B_CNE may include the same material as the shielding electrode RSE and may be disposed at the same layer (e.g., at the same layer) by the same process.

[0154] The blue pixel driving circuit B_PD is disposed at a first side of the blue anode electrode B_AE, and the shielding electrode RSE is disposed at a second side of the blue anode electrode B_AE. In this case, a blue pixel connecting electrode B_CNE connecting the blue anode electrode B_AE and the blue pixel driving circuit B_PD is disposed between the blue pixel driving circuit B_PD and the shielding electrode RSE.

[0155] As an example, the blue anode electrode B_AE disposed in the first row may be connected to the blue pixel driving circuit B_PD disposed in the second row, and the blue pixel connecting electrode B_CNE may be connected to the blue pixel driving circuit B_PD disposed in the first column of the second row through a blue contact hole B_CH. The red anode electrode R_AE disposed in the first row may be connected to the red pixel driving circuit R_PD disposed in the second row, and the red pixel connecting electrode R_CNE may be connected to the red pixel driving circuit R_PD disposed in the third column of the second row through a red contact hole R_CH. The red pixel connecting electrode R_CNE may be disposed between the red anode electrode R_AE and the shielding electrode RSE.

[0156] The blue pixel connection electrode B_CNE and the red pixel connection electrode R_CNE may not overlap (or cross) the first sensor driving circuit O_SD1 and the second sensor driving circuit O_SD2 in a plan view.

[0157] As an example of the present disclosure, the blue pixel connection electrode B_CNE may overlap the sensor connection electrode O_CNE2 in a plan view. The blue pixel connection electrode B_CNE may not overlap the red light emitting element ED_R and the first and second green light emitting elements ED_G1 and ED_G2 in a plan view.

[0158] Fig. 6A and Figure 6B 1 is a plan view showing a connection relationship between a light emitting element and a pixel driving circuit and a connection relationship between a light receiving element and a sensor driving circuit according to an embodiment of the present disclosure.

[0159] Reference Fig. 6A The blue pixel connection electrode B_CNEa connecting the blue anode electrode B_AE and the blue pixel driving circuit B_PD is arranged between the blue pixel driving circuit B_PD and the shielding electrode RSE. The red pixel connection electrode R_CNE connecting the red pixel driving circuit R_PD and the red anode electrode R_AE can be arranged between the shielding electrode RSE and the red anode electrode R_AE.

[0160] The blue pixel connection electrode B_CNEa and the red pixel connection electrode R_CNE may not overlap (or cross) the first sensor driving circuit O_SD1 and the second sensor driving circuit O_SD2 in a plan view.

[0161] The blue anode electrode B_AE disposed in the first row may be connected to the blue pixel driving circuit B_PD disposed in the second row, and the blue pixel connecting electrode B_CNEa may be connected to the blue pixel driving circuit B_PD disposed in the first column of the second row through the blue contact hole B_CHa. As an example of the present disclosure, the blue pixel connecting electrode B_CNEa may overlap the red light emitting element ED_R and one of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 in a plan view.

[0162] although Fig. 6A A structure in which the blue pixel connection electrode B_CNEa overlaps the red light emitting element ED_R is shown, but the present disclosure is not limited thereto. The blue pixel connection electrode B_CNEa may pass through the center point of the red light emitting element ED_R. Alternatively, even when the blue pixel connection electrode B_CNEa overlaps the first green light emitting element ED_G1, the blue pixel connection electrode B_CNEa may pass through the center point of the first green light emitting element ED_G1. That is, when the blue pixel connection electrode B_CNEa overlaps the red light emitting element ED_R and one of the first green light emitting element ED_G1 and the second green light emitting element ED_G2, the blue pixel connection electrode B_CNEa passes through the center point of the overlapped light emitting elements, thereby preventing or reducing image quality distortion (such as reflection color bands) from occurring in the corresponding light emitting elements.

[0163] As an example of the present disclosure, the blue pixel connection electrode B_CNEa may overlap the dummy connection electrode D_CNE1 in a plan view, and may not overlap the sensor connection electrode O_CNE2 in a plan view.

[0164] Reference Figure 6B , the red anode electrode R_AE disposed in the first row may be connected to the red pixel driving circuit R_PD disposed in the first row, and the red pixel connecting electrode R_CNEb may be connected to the red pixel driving circuit R_PD disposed in the third column of the first row through a red contact hole R_CHb. The red pixel connecting electrode R_CNEb may be disposed between the red anode electrode R_AE and the shielding electrode RSE. The blue anode electrode B_AE disposed in the first row may be connected to the blue pixel driving circuit B_PD disposed in the second row, and the blue pixel connecting electrode B_CNEb may be connected to the blue pixel driving circuit B_PD disposed in the first column of the second row through a blue contact hole B_CHb. As an example of the present disclosure, the blue pixel connecting electrode B_CNEb may overlap with the red light emitting element ED_R and one of the first green light emitting element ED_G1 and the second green light emitting element ED_G2 in a plan view.

[0165] although Figure 6B A structure in which the blue pixel connection electrode B_CNEb overlaps the first green light emitting element ED_G1 is shown, but the present disclosure is not limited thereto. For example, the blue pixel connection electrode B_CNEb may not overlap the red light emitting element ED_R and the first green light emitting element ED_G1 and the second green light emitting element ED_G2 in a plan view. In addition, the blue pixel connection electrode B_CNEb may not overlap the dummy connection electrode D_CNE1 and the sensor connection electrode O_CNE2 in a plan view.

[0166] When the blue pixel connection electrode B_CNEb does not overlap with the dummy connection electrode D_CNE1 and the sensor connection electrode O_CNE2 in a plan view, the coupling capacitance generated between the blue pixel connection electrode B_CNEb and the first light receiving element OPD1 and the second light receiving element OPD2 can be reduced. Therefore, it is possible to prevent or substantially prevent the sensing performance of the first light receiving element OPD1 and the second light receiving element OPD2 from being degraded due to the coupling capacitance.

[0167] Fig. 7A It is shown Figure 5C A cross-sectional view of the connection structure of the red light emitting element and the red pixel driving circuit shown in FIG. Figure 7B It is shown Figure 5C A cross-sectional view of a connection structure of a second light receiving element and a second sensor driving circuit shown in FIG.

[0168] Reference Fig. 7A and Figure 7B , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0169] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate and / or an organic / inorganic composite material substrate, etc.

[0170] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in a plurality of layers.

[0171] The circuit layer DP_CL is disposed on the base layer BL. Fig. 7A Shows Figure 5C The first transistor T1, the fourth transistor T4 and the sixth transistor T6 of the red pixel driving circuit R_PD shown in FIG. Fig. 7A , the blocking layer BML may be disposed on the base layer BL. The blocking layer BML may overlap the first transistor T1 in the thickness direction of the base layer BL. The blocking layer BML may include a metal and may receive a constant voltage. When the constant voltage is applied to the blocking layer BML, the value of the threshold voltage (Vth) of the first transistor T1 disposed on the blocking layer BML may be maintained without changing.

[0172] In addition, the blocking layer BML may block incident light from the outside that propagates from below the blocking layer BML toward the first transistor T1. For example, the blocking layer BML may include a reflective metal. In one or more embodiments of the present disclosure, the blocking layer BML may be omitted.

[0173] The buffer layer BFL may be disposed on the base layer BL and the barrier layer BML, and the buffer layer BFL may include an inorganic layer. The buffer layer BFL may cover the barrier layer BML. The semiconductor layer SCP1 (or semiconductor pattern region, hereinafter referred to as the first semiconductor layer) of the first transistor T1 and the semiconductor layer SCP6 (or semiconductor pattern region, hereinafter referred to as the sixth semiconductor layer) of the sixth transistor T6 may be disposed on the buffer layer BFL. Hereinafter, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include polycrystalline silicon. However, the present disclosure is not limited thereto, and in one or more embodiments, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include amorphous silicon.

[0174] The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be formed by the same process, and a partial region of each of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be doped with an N-type dopant or a P-type dopant. The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may have a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than the conductivity of the low-doping region. The high-doping region may substantially correspond to the source and drain of the first transistor T1 and the sixth transistor T6. The low-doping region may substantially correspond to the active region (or channel) of the first transistor T1 and the sixth transistor T6.

[0175] The high doping region of the first semiconductor layer SCP1 may include a first source region S1 and a first drain region D1. The low doping region of the first semiconductor layer SCP1 is defined as (or referred to as) a first channel region C1, and is disposed between the first source region S1 and the first drain region D1. The sixth semiconductor layer SCP6 may include a sixth source region S6, a sixth channel region C6, and a sixth drain region D6. The first source region S1 is defined as (e.g., may be referred to as) a first electrode of the first transistor T1, and the first drain region D1 is defined as (e.g., may be referred to as) a second electrode of the first transistor T1. The sixth source region S6 is defined as (e.g., may be referred to as) a first electrode of the sixth transistor T6, and the sixth drain region D6 is defined as (e.g., may be referred to as) a second electrode of the sixth transistor T6.

[0176] Although the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 Fig. 7A , the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may have an integral shape in a plan view. In other words, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be different parts or different regions of one semiconductor pattern (e.g., a continuous semiconductor pattern).

[0177] A first insulating layer INS1 covering the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be disposed on the buffer layer BFL. The third electrodes (or gate electrodes) of the first transistor T1 and the sixth transistor T6 are disposed on the first insulating layer INS1. The gate electrodes of the first transistor T1 and the sixth transistor T6 may be formed by the same process. Hereinafter, the gate electrode of the first transistor T1 is referred to as the first gate electrode G1, and the gate electrode of the sixth transistor T6 is referred to as the sixth gate electrode G6.

[0178] The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. The upper gate electrode UGE may be disposed on the second insulating layer INS2. The upper gate electrode UGE may be disposed on the first gate electrode G1 and may overlap the first gate electrode G1 in a plan view (ie, in a thickness direction of the base layer BL). The upper gate electrode UGE may be formed together with the first gate electrode G1. Figure 4A In other words, the first gate electrode G1 corresponds to one electrode (or one terminal) of the capacitor Cst, and the upper gate electrode UGE corresponds to an opposite electrode (or opposite terminal) of the capacitor Cst.

[0179] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the upper gate electrode UGE. The semiconductor layer SCP4 (or semiconductor pattern region, hereinafter, referred to as the fourth semiconductor layer) of the fourth transistor T4 may be disposed on the third insulating layer INS3. The fourth semiconductor layer SCP4 may include an oxide semiconductor including a metal oxide. The oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor.

[0180] The fourth semiconductor layer SCP4 may include a plurality of regions divided according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduction region) has a greater conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region may substantially correspond to the source and drain of the fourth transistor T4. The non-reduction region may substantially correspond to the active region (or channel) of the fourth transistor T4.

[0181] The reduction region of the fourth semiconductor layer SCP4 may include a fourth source region S4 and a fourth drain region D4. A fourth channel region C4 may be disposed between the fourth source region S4 and the fourth drain region D4. The fourth source region S4 is defined as (or may be referred to as) a first electrode of a fourth transistor T4, and the fourth drain region D4 is defined as (or may be referred to as) a second electrode of the fourth transistor T4.

[0182] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the fourth semiconductor layer SCP4. A third electrode (eg, a fourth gate electrode G4) of the fourth transistor T4 may be disposed on the fourth insulating layer INS4.

[0183] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4 . The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include an inorganic layer.

[0184] The circuit connection electrodes CNE1, CNE2, and CNE3 and the red pixel connection electrode R_CNE may be disposed between the sixth transistor T6 and the red light emitting element ED_R. The circuit connection electrodes CNE1, CNE2, and CNE3 and the red pixel connection electrode R_CNE may electrically connect the sixth transistor T6 and the red light emitting element ED_R. As an example, the circuit connection electrodes CNE1, CNE2, and CNE3 may include a first circuit connection electrode CNE1, a second circuit connection electrode CNE2 disposed on the first circuit connection electrode CNE1, and a third circuit connection electrode CNE3 disposed on the second circuit connection electrode CNE2.

[0185] The first circuit connection electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first circuit connection electrode CNE1. The second circuit connection electrode CNE2 may be disposed on the sixth insulating layer INS6. The second circuit connection electrode CNE2 may be connected to the first circuit connection electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6. The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to cover the second circuit connection electrode CNE2.

[0186] The third circuit connection electrode CNE3 may be disposed on the seventh insulating layer INS7. The third circuit connection electrode CNE3 may be connected to the second circuit connection electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7.

[0187] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 to cover the third circuit connection electrode CNE3. The red pixel connection electrode R_CNE may be disposed on the eighth insulating layer INS8. The red pixel connection electrode R_CNE may overlap the circuit connection electrodes CNE1, CNE2, and CNE3 and the red anode electrode R_AE in a plan view (i.e., in the thickness direction of the base layer BL).

[0188] The red pixel connection electrode R_CNE is connected to the third circuit connection electrode CNE3 through the first red contact hole R_CH1 defined in the eighth insulating layer INS8. The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8 and the red pixel connection electrode R_CNE. The sixth insulating layer INS6 to the ninth insulating layer INS9 may include an inorganic layer and / or an organic layer. In the present embodiment, each of the sixth insulating layer INS6 to the ninth insulating layer INS9 may include an organic layer.

[0189] The red light emitting element ED_R is disposed on the ninth insulating layer INS9. The red light emitting element ED_R may include a red anode electrode R_AE, a red cathode electrode R_CE, and a red light emitting layer R_EL. The red cathode electrode R_CE is disposed on the red anode electrode R_AE, and the red light emitting layer R_EL is disposed between the red anode electrode R_AE and the red cathode electrode R_CE. As an example of the present disclosure, a hole control layer HCL may be further disposed between the red anode electrode R_AE and the red light emitting layer R_EL, and an electron control layer ECL may be further disposed between the red cathode electrode R_CE and the red light emitting layer R_EL.

[0190] The red anode electrode R_AE may be disposed on the ninth insulating layer INS9 and may be connected to the red pixel connection electrode R_CNE through a second red contact hole R_CH2 defined in the ninth insulating layer INS9 .

[0191] The pixel defining layer PDL may be disposed on the ninth insulating layer INS9 to expose a portion (eg, a predetermined portion) of the red anode electrode R_AE. A pixel opening PDL-OP1 for exposing a portion (eg, a predetermined portion) of the red anode electrode R_AE may be defined in the pixel defining layer PDL.

[0192] The red light emitting layer R_EL may include an organic material and / or an inorganic material. The red light emitting layer R_EL may generate red light.

[0193] The hole control layer HCL and the electron control layer ECL may be commonly provided in the pixel PX (eg, see Figure 3 ). In addition, the red cathode electrode R_CE may be formed integrally with the cathode electrode of an adjacent light emitting element to form a common cathode electrode.

[0194] The layers from the buffer layer BFL to the ninth insulating layer INS9 may be defined as (or referred to as) a circuit layer DP_CL. The layer in which the red light emitting element ED_R is disposed may be defined as (or referred to as) an element layer DP_ED.

[0195] The encapsulation layer TFE may be disposed on the element layer DP_ED. The encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. The inorganic layer may include an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer may include an organic material and may protect the pixel PX from foreign matter such as dust particles.

[0196] Reference Figure 7B The semiconductor layer SCP1' (hereinafter, referred to as the first sensing semiconductor layer) of the amplifying transistor ST2 can be connected to Fig. 7AThe first semiconductor layer SCP1 of the reset transistor ST1 is formed by the same process, and the semiconductor layer SCP2' (hereinafter, referred to as the second sensing semiconductor layer) of the reset transistor ST1 may be formed with the first semiconductor layer SCP1 of the reset transistor ST1. Fig. 7A The fourth semiconductor layer SCP4 is formed by the same process. The first sensing semiconductor layer SCP1' may include a first source region S1', a first drain region D1', and a first channel region C1'. The second sensing semiconductor layer SCP2' may include a second source region S2', a second drain region D2', and a second channel region C2'. The first source region S1' is defined as (or may be referred to as) a first electrode of the amplifying transistor ST2, and the first drain region D1' is defined as (or may be referred to as) a second electrode of the amplifying transistor ST2. The second source region S2' is defined as (or may be referred to as) a first electrode of the reset transistor ST1, and the second drain region D2' is defined as (or may be referred to as) a second electrode of the reset transistor ST1.

[0197] The stacked structure of the amplifier transistor ST2 can be Fig. 7A The stack structure of the first transistor T1 shown in FIG. 1 is substantially the same as that of the reset transistor ST1. Fig. 7A The stack structure of the fourth transistor T4 shown in FIG. 1 is substantially the same. In one or more embodiments, the stack structure of the output transistor ST3 may be substantially the same as the stack structure of the amplifying transistor ST2.

[0198] The circuit connection electrodes CNE1', CNE2' and CNE3' may include a fourth circuit connection electrode CNE1', a fifth circuit connection electrode CNE2' and a sixth circuit connection electrode CNE3'. The fourth circuit connection electrode CNE1' may be connected to Fig. 7A The first circuit connection electrode CNE1 shown in FIG. 1 is disposed in the same layer (e.g., at the same layer) and may be connected to the third electrode (i.e., the first gate electrode G1') of the amplifying transistor ST2 through the fourth contact hole CH1'. Hereinafter, the first gate electrode G1' is defined as (or may be referred to as) a first sensor gate electrode G1' to be distinguished from the above-mentioned first gate electrode G1.

[0199] The fifth circuit connection electrode CNE2' can be connected to Fig. 7A The second circuit connection electrode CNE2 shown in FIG. 1 is disposed in the same layer (eg, at the same layer) and may be connected to the fourth circuit connection electrode CNE1′ through a fifth contact hole CH2′ defined in the sixth insulating layer INS6. The sixth circuit connection electrode CNE3′ may be connected to the fourth circuit connection electrode CNE1′. Fig. 7A The third circuit connection electrode CNE3 shown in FIG. 1 is disposed in the same layer (eg, at the same layer) and may be connected to the fifth circuit connection electrode CNE2 ′ through a sixth contact hole CH3 ′.

[0200] The second sensor anode electrode O_AE2 and the sensor connection electrode O_CNE2 are disposed on the ninth insulating layer INS9. The sensor connection electrode O_CNE2 may extend from the second sensor anode electrode O_AE2 and may overlap with the fourth to sixth circuit connection electrodes CNE1', CNE2', and CNE3' in a plan view (i.e., in the thickness direction of the base layer BL). The sensor connection electrode O_CNE2 may be connected to the sixth circuit connection electrode CNE3' through a second sensor contact hole O_CH2 defined in the eighth insulating layer INS8 and the ninth insulating layer INS9.

[0201] The second light receiving element OPD2 may include a second sensor anode electrode O_AE2, a second sensor cathode electrode O_CE2, and a second photoelectric conversion layer O_RL2. Fig. 7A The red anode electrode R_AE shown in FIG. 1 is formed by the same process. The second sensor cathode electrode O_CE2 can be Fig. 7A The red cathode electrode R_CE shown in FIG. has an integral shape. That is, Figure 7B The second sensor cathode electrode O_CE2 and Fig. 7A The red cathode electrode R_CE may be a different region of the common cathode electrode. The common cathode electrode may be deposited through an open mask to have an integral shape.

[0202] The hole control layer HCL' may be disposed between the second sensor anode electrode O_AE2 and the second photoelectric conversion layer O_RL2, and the electron control layer ECL' may be disposed between the second sensor cathode electrode O_CE2 and the second photoelectric conversion layer O_RL2. The hole control layer HCL' and the electron control layer ECL' may be respectively Fig. 7A The hole control layer HCL and the electron control layer ECL extend.

[0203] Figure 8 is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0204] Reference Figure 8 The display panel DP includes a display area DA and a non-display area NDA. Figure 3 ) and multiple sensors FX (see, for example, Figure 3 ) is disposed in the display area DA. The driving chip DIC and the sensor chips SIC1 and SIC2 are mounted in the non-display area NDA.

[0205] Data lines DL1 to DLm (for example, see Figure 3 ) are connected to a plurality of pixels PX in the display area DA, and are connected to a driving chip DIC in the non-display area NDA. Figure 3 ) is connected to a plurality of sensors FX in the display area DA, and is connected to sensor chips SIC1 and SIC2 in the non-display area NDA.

[0206] The data lines DL1 to DLm may be divided into a first group and a second group. The first group includes a plurality of first data lines DL_G1, and the second group includes a plurality of second data lines DL_G2. The first data lines DL_G1 are arranged in a first direction DR1, and the second data lines DL_G2 are arranged in the first direction DR1. The first data lines DL_G1 are separated (e.g., spaced apart) from the second data lines DL_G2 in the first direction DR1.

[0207] The first data line DL_G1 is connected to the pixel driving circuit P_PD of the first group of pixels among the pixels PX, and the second data line DL_G2 is connected to the pixel driving circuit P_PD of the second group of pixels among the pixels PX. The first group of pixels and the first data line DL_G1 are arranged in the first area A1, and the second group of pixels and the second data line DL_G2 are arranged in the second area A2. The first area A1 includes a first-first area A1-1 defined at (or located at) a first side of a center line parallel to the second direction DR2 of the display panel DP and a first-second area A1-2 defined at (or located at) a second side relative to the center line. The second area A2 includes a second-first area A2-1 arranged between the first-first area A1-1 and the non-display area NDA and a second-second area A2-2 arranged between the first-second area A1-2 and the non-display area NDA.

[0208] The plurality of first data lines DL_G1 include a first-first data line DL1-1 disposed in the first-first area A1-1 and a first-second data line DL1-2 disposed in the first-second area A1-2. The plurality of second data lines DL_G2 include a second-first data line DL2-1 disposed in the second-first area A2-1 and a second-second data line DL2-2 disposed in the second-second area A2-2.

[0209] The first-first data line DL1-1 and the first-second data line DL1-2 may be connected to the driving chip DIC. Figure 8 By way of example, it is shown that the first-first data line DL1-1 and the first-second data line DL1-2 are connected to the same driving chip DIC, but the present disclosure is not limited thereto. For example, the first-first data line DL1-1 and the first-second data line DL1-2 may be connected to different driving chips, respectively.

[0210] The display panel DP further includes data connection lines connecting the second data lines DL_G2 to the driving chip DIC. The data connection lines include a plurality of vertical data connection lines V_DCL extending along the first data lines DL_G1 and a plurality of horizontal data connection lines H_DCL extending along the first direction DR1.

[0211] The horizontal data connection lines H_DCL include first horizontal data connection lines H_DCL1 (i.e., H_DCL11 to H_DCL13) and second horizontal data connection lines H_DCL2 (i.e., H_DCL21 to H_DCL23). The first horizontal data connection lines H_DCL11 to H_DCL13 are connected to the second-first data lines DL2-1, and the second horizontal data connection lines H_DCL21 to H_DCL23 are connected to the second-second data lines DL2-2. The plurality of vertical data connection lines V_DCL may include first vertical data connection lines V_DCL1 and second vertical data connection lines V_DCL2. The first vertical data connection lines V_DCL1 are connected to the first horizontal data connection lines H_DCL11 to H_DCL13, and the second vertical data connection lines V_DCL2 are connected to the second horizontal data connection lines H_DCL21 to H_DCL23.

[0212] Therefore, the first vertical data link line V_DCL1 is electrically connected to the second-first data line DL2-1 through the first horizontal data link lines H_DCL11 to H_DCL13. The second vertical data link line V_DCL2 is electrically connected to the second-second data line DL2-2 through the second horizontal data link lines H_DCL21 to H_DCL23.

[0213] The first vertical data link line V_DCL1 and the first-first data line DL1-1 are alternately and repeatedly arranged in the first-first area A1-1. The second vertical data link line V_DCL2 and the first-second data line DL1-2 are alternately and repeatedly arranged in the first-second area A1-2.

[0214] A portion of the vertical data connection line V_DCL and a plurality of horizontal data connection lines H_DCL may be disposed in the display area DA. That is, a portion of the data connection line for connecting the second data line DL_G2 and the driving chip DIC is disposed in the display area DA. Therefore, the area of ​​the area occupied by the data connection line in the non-display area NDA may be reduced, and thus, the area of ​​the dead zone of the display panel DP may be reduced.

[0215] The readout lines RL1 to RLh may be divided into a first group and a second group. The first group includes a plurality of first readout lines RL_G1, and the second group includes a plurality of second readout lines RL_G2. The plurality of first readout lines RL_G1 are arranged in a first direction DR1, and the plurality of second readout lines RL_G2 are arranged in the first direction DR1. The first readout lines RL_G1 are separated (e.g., spaced apart) from the second readout lines RL_G2 in the first direction DR1.

[0216] A plurality of first readout lines RL_G1 are connected to sensor drive circuits O_SD of sensors belonging to a first group among the plurality of sensors FX, and a plurality of second readout lines RL_G2 are connected to sensor drive circuits O_SD of sensors belonging to a second group among the plurality of sensors FX. The first group of sensors and the first readout lines RL_G1 are disposed in the second area A2, and the second group of sensors and the second readout lines RL_G2 are disposed in the first area A1.

[0217] The plurality of first readout lines RL_G1 include first-first readout lines RL1-11 to RL1-13 and first-second readout lines RL1-21 to RL1-23. The first-first readout lines RL1-11 to RL1-13 may be disposed in the second-first area A2-1 and may be connected to the first sensor chip SIC1. The first-second readout lines RL1-21 to RL1-23 may be disposed in the second-second area A2-2 and may be connected to the second sensor chip SIC2.

[0218] The plurality of second readout lines RL_G2 may include second-first readout lines RL2-11 to RL2-13 and second-second readout lines RL2-21 to RL2-23. The second-first readout lines RL2-11 to RL2-13 may be disposed in the first-first area A1-1 and may be electrically connected to the first sensor chip SIC1. The second-second readout lines RL2-21 to RL2-23 may be disposed in the first-second area A1-2 and may be electrically connected to the second sensor chip SIC2. The plurality of second readout lines RL_G2 may be disposed between the first-first readout lines RL1-11 to RL1-13 and the first-second readout lines RL1-21 to RL1-23.

[0219] The display panel DP also includes connection lines electrically connected to the second readout lines RL_G2. The connection lines include a plurality of vertical connection lines V_RL extending along the first readout lines RL_G1 and a plurality of horizontal connection lines H_RL extending in the first direction DR1. The vertical connection lines V_RL may include first vertical connection lines V_RL1 (i.e., V_RL11 to V_RL13) electrically connected to the first sensor chip SIC1 and second vertical connection lines V_RL2 (i.e., V_RL21 to V_RL23) electrically connected to the second sensor chip SIC2.

[0220] The first vertical connection line V_RL1 and the first-first readout lines RL1-11 to RL1-13 may be alternately and repeatedly arranged one by one in the first direction DR1. The second vertical connection line V_RL2 and the first-second readout lines RL1-21 to RL1-23 may be alternately and repeatedly arranged one by one in the first direction DR1.

[0221] The horizontal connection line H_RL may electrically connect the vertical connection line V_RL to the second readout line RL_G2. The horizontal connection line H_RL includes first horizontal connection lines H_RL1 (i.e., H_RL11 to H_RL13) that connect the first vertical connection line V_RL1 to the second-first readout lines RL2-11 to RL2-13, respectively, and second horizontal connection lines H_RL2 (i.e., H_RL21 to H_RL23) that connect the second vertical connection line V_RL2 to the second-second readout lines RL2-21 to RL2-23, respectively.

[0222] A portion of the vertical connection line V_RL and a plurality of horizontal connection lines H_RL may be disposed in the display area DA. That is, a portion of the connection lines for connecting the second readout line RL_G2 with the first sensor chip SIC1 and the second sensor chip SIC2 is disposed in the display area DA. Therefore, the area occupied by the connection lines in the non-display area NDA may be reduced, and thus, the area of ​​the dead zone of the display panel DP may be reduced.

[0223] Even if the first sensor chip SIC1 or the second sensor chip SIC2 is disposed adjacent to the driving chip DIC, when the second readout line RL_G2 is connected to the first sensor chip SIC1 or the second sensor chip SIC2 through the connection line and the second data line DL_G2 is connected to the driving chip DIC through the data connection line, the readout line and the data line may not cross each other in the non-display area NDA. Therefore, the coupling capacitance between the readout line and the data line may be reduced, and thus, the sensing accuracy of the sensor FX may be improved.

[0224] FIG. 9A to FIG. 9K is a plan view illustrating a stacked structure of a circuit layer and an element layer according to example embodiments. Figure 9L It is along Figure 9K A cross-sectional view taken along line II' shown in FIG.

[0225] Reference FIG. 9A to FIG. 9K , each of the conductive pattern and the semiconductor pattern may have a structure in which the conductive pattern and the semiconductor pattern are repeatedly arranged according to a rule (eg, according to a predetermined rule) in a plan view. FIG. 9A to FIG. 9K , a pixel driving circuit P_PD (eg, see Figure 4A ) and the sensor drive circuit O_SD (see, for example, Figure 4A ) and some of the pixel driving circuits P_PD and some of the sensor driving circuits O_SD arranged in the second row EVEN_R. The first row ODD_R and the second row EVEN_R are adjacent to each other in the second direction DR2. In the first row ODD_R, eight first circuit areas P_PA (or pixel circuit areas) corresponding to the eight pixel driving circuits P_PD adjacent to each other in the first direction DR1 and a second circuit area O_SA (or sensor circuit area) corresponding to one sensor driving circuit O_SD are defined. In the second row EVEN_R, eight first circuit areas P_PA corresponding to the eight pixel driving circuits P_PD adjacent to each other in the first direction DR1 and a second circuit area O_SA corresponding to one sensor driving circuit O_SD are defined. FIG. 9A to FIG. 9K In FIG. 1 , a boundary between the first circuit area P_PA and the second circuit area O_SA is shown by a dotted line.

[0226] Reference Fig.9A The blocking layer BML may be formed on the buffer layer BFL. The blocking layer BML may be a conductive pattern having a light blocking function. The blocking layer BML may be disposed on the transistors T1 to T8 (eg, see Figure 4A ) below at least one of the transistors T1 to T8 to block light incident on the transistors T1 to T8 from the outside.

[0227] Reference Fig.9A and Fig. 9B , the first semiconductor pattern layer ACT1 may be disposed on the barrier layer BML and the buffer layer BFL. The first semiconductor pattern layer ACT1 may overlap the barrier layer BML on the buffer layer BFL. The first semiconductor pattern layer ACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon, etc. For example, the first semiconductor pattern layer ACT1 may include low temperature polycrystalline silicon (LTPS).

[0228] The first semiconductor pattern layer ACT1 includes a first semiconductor pattern P_ACT1 disposed in each of the first circuit areas P_PA and a second semiconductor pattern S_ACT1 disposed in each of the second circuit areas O_SA.

[0229] Reference Fig. 9C , the first gate pattern layer GAT1 may be disposed on the first insulating layer INS1. The first gate pattern layer GAT1 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material, etc. For example, the first gate pattern layer GAT1 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), and / or indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0230] The first gate pattern layer GAT1 may include a first gate wiring SBL, a second gate wiring EML, a third gate wiring SWL, a first gate electrode G1, and a first sensor gate electrode G1'.

[0231] Each of the first to third gate wirings SBL, EML, and SWL may extend in the first direction DR1. Figure 4A For example, the jth black scan signal SBj (eg, see Figure 4A ) may be provided to the first gate wiring SBL. The first gate wiring SBL may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The seventh transistor T7.

[0232] The second gate wiring EML Figure 4A For example, the j-th emission control signal EMj (for example, refer to Figure 4A ) may be provided to the second gate wiring EML. The second gate wiring EML may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The fifth transistor T5 and the sixth transistor T6.

[0233] The third gate wiring SWL is Figure 4A For example, the j-th write scan signal SWj (for example, see Figure 4A ) may be provided to the third gate wiring SWL. The third gate wiring SWL may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The second transistor T2 and the second semiconductor pattern S_ACT1 may constitute Figure 4A The output transistor ST3.

[0234] The first gate electrode G1 and the first sensor gate electrode G1' may be provided in an island shape. The first gate electrode G1 may constitute a first semiconductor pattern P_ACT1 together with the first semiconductor pattern P_ACT1. Figure 4A The first gate electrode G1 can be connected to the first transistor T1. Fig. 7A The first sensor gate electrode G1 ′ may be formed together with the second semiconductor pattern S_ACT1 . Figure 4A Amplifying transistor ST2.

[0235] Reference Fig. 9C and Fig.9D The second insulating layer INS2 may cover the first gate pattern layer GAT1 and may be disposed on the first insulating layer INS1. The second gate pattern layer GAT2 may be disposed on the second insulating layer INS2. The second gate pattern layer GAT2 may include metal, alloy, conductive metal oxide and / or transparent conductive material, etc.

[0236] The second gate pattern layer GAT2 may include a fourth gate wiring G2_SRL, a fifth gate wiring G2_SCL, a sixth gate wiring G2_SIL, and an upper gate electrode UGE.

[0237] The fourth to sixth gate wirings G2_SRL, G2_SCL, and G2_SIL may extend in the first direction DR1. The fourth gate wiring G2_SRL corresponds to (or includes) a reset control line SRL (eg, see Figure 4A ). The fifth gate wiring G2_SCL may correspond to (or may include) the jth compensation scan line SCLj (eg, see Figure 4A ). The sixth gate wiring G2_SIL may correspond to (or may include) the jth initialization scan line SILj (eg, see Figure 4A ).

[0238] The upper gate electrode UGE may overlap the first gate electrode G1 and may be provided in an island shape. For example, the upper gate electrode UGE may constitute a capacitor Cst together with the first gate electrode G1 (eg, see Figure 4A ). The upper gate electrode UGE can be connected to Fig. 7A An opening UGE_OP penetrating the upper gate electrode UGE may be formed in the upper gate electrode UGE, and the first gate electrode G1 may be partially exposed through the opening UGE_OP.

[0239] Reference Fig.9D and Fig.9E, the third insulating layer INS3 may cover the second gate pattern layer GAT2 and may be disposed on the second insulating layer INS2. The second semiconductor pattern layer ACT2 may be disposed on the third insulating layer INS3. The second semiconductor pattern layer ACT2 may include an oxide semiconductor. The second semiconductor pattern layer ACT2 may be disposed at a different layer (e.g., may be located at a different layer) from the first semiconductor pattern layer ACT1 and may not overlap with the first semiconductor pattern layer ACT1.

[0240] The second semiconductor pattern layer ACT2 includes a third semiconductor pattern P_ACT2 disposed in each of the first circuit areas P_PA and a fourth semiconductor pattern S_ACT2 disposed in each of the second circuit areas O_SA.

[0241] Reference FIG. 9E to FIG. 9G The fourth insulating layer INS4 may cover the second semiconductor pattern layer ACT2 and may be disposed on the third insulating layer INS3. The third gate pattern layer GAT3 may be disposed on the fourth insulating layer INS4. The third gate pattern layer GAT3 may include metal, alloy, conductive metal oxide and / or transparent conductive material, etc.

[0242] The third gate pattern layer GAT3 may include a seventh gate wiring G3_SRL, an eighth gate wiring G3_SCL, a ninth gate wiring G3_SIL, a second-first horizontal initialization voltage line H_VAIL1, a second-second horizontal initialization voltage line H_VAIL2, and a first horizontal reset voltage line G3_VRL. The second-first horizontal initialization voltage line H_VAIL1 and the second-second horizontal initialization voltage line H_VAIL2 may be referred to as a second horizontal initialization voltage line.

[0243] The seventh to ninth gate wirings G3_SRL, G3_SCL, and G3_SIL may extend in the first direction DR1. The seventh gate wiring G3_SRL may overlap the fourth semiconductor pattern S_ACT2. The seventh gate wiring G3_SRL may form a semiconductor pattern S_ACT2 together with the fourth semiconductor pattern S_ACT2. Figure 4A The seventh gate wiring G3_SRL may be electrically connected to the reset transistor ST1. Fig.9D The fourth gate wiring G2_SRL shown in .

[0244] The eighth gate wiring G3_SCL may overlap the fifth gate wiring G2_SCL and the third semiconductor pattern P_ACT2. In some embodiments, the eighth gate wiring G3_SCL may contact the fifth gate wiring G2_SCL through a contact portion. Therefore, the j-th compensation scan signal SCj applied to the fifth gate wiring G2_SCL may be provided to the eighth gate wiring G3_SCL. The fifth gate wiring G2_SCL, the third semiconductor pattern P_ACT2, and the eighth gate wiring G3_SCL may constitute Figure 4A The third transistor T3.

[0245] The ninth gate wiring G3_SIL may overlap the sixth gate wiring G2_SIL and the third semiconductor pattern P_ACT2. The ninth gate wiring G3_SIL may be electrically connected to the sixth gate wiring G2_SIL. The j-th initialization scan signal SIj may be provided to the ninth gate wiring G3_SIL through the sixth gate wiring G2_SIL. The sixth gate wiring G2_SIL, the third semiconductor pattern P_ACT2, and the ninth gate wiring G3_SIL may constitute Figure 4A The fourth transistor T4.

[0246] The second-first horizontal initialization voltage line H_VAIL1 and the second-second horizontal initialization voltage line H_VAIL2 may be included in the second initialization voltage line VAIL (eg, see Figure 4A ). The second-first horizontal initialization voltage line H_VAIL1 is connected to Figure 3 The first color pixel (eg, red pixel) among the plurality of pixels PX shown in the figure, and the second-second horizontal initialization voltage line H_VAIL2 is connected to a second color pixel or a third color pixel (blue pixel or green pixel) different from the first color pixel among the plurality of pixels PX.

[0247] The second-first horizontal initialization voltage line H_VAIL1 uses the second-first horizontal initialization voltage as the second initialization voltage Vaint (eg, see Figure 4A ) is applied to the first color pixel, and the second-second horizontal initialization voltage line H_VAIL2 applies the second-second initialization voltage as the second initialization voltage Vaint to the second color pixel or the third color pixel. The second-second initialization voltage may have a voltage level different from that of the second-first initialization voltage.

[0248] The first horizontal reset voltage line G3_VRL may include Figure 4A The reset voltage line VRL is in the reset voltage line VRL. The reset voltage Vrst (for example, see Figure 4A) may be provided to the first horizontal reset voltage line G3_VRL. The first horizontal reset voltage line G3_VRL may be electrically connected to the reset transistor ST1. The reset transistor ST1 may receive the reset voltage Vrst through the first horizontal reset voltage line G3_VRL.

[0249] Reference Fig.9F and Figure 9G , the fifth insulating layer INS5 may cover at least a portion of the third gate pattern layer GAT3 and may be disposed on the fourth insulating layer INS4. The first data pattern layer SD1 may be disposed on the fifth insulating layer INS5. The first data pattern layer SD1 may include, for example, a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material. In the following, for ease of description, Figure 9G Only some of the components included in the first data pattern layer SD1 are shown in FIG.

[0250] The first data pattern layer SD1 may include a second horizontal reset voltage line D1_VRL, a bias voltage line D1_VBL, a first horizontal initialization voltage line H_VIL, and a plurality of first connection electrode patterns C_CNE1.

[0251] The second horizontal reset voltage line D1_VRL, the bias voltage line D1_VBL, and the first horizontal initialization voltage line H_VIL may extend in the first direction DR1 and may be spaced apart (eg, spaced apart) from each other in the second direction DR2.

[0252] The second horizontal reset voltage line D1_VRL may include Figure 4A The reset voltage line VRL is in the reset voltage line VRL. The reset voltage Vrst (for example, see Figure 4A ) may be provided to the second horizontal reset voltage line D1_VRL. The second horizontal reset voltage line D1_VRL may be electrically connected to the first horizontal reset voltage line G3_VRL. The bias voltage line D1_VBL may be connected to Figure 4A The bias voltage Vbias (for example, refer to Figure 4A ) may be provided to the bias voltage line D1_VBL. The bias voltage line D1_VBL may be connected to the eighth transistor T8 through a contact. The eighth transistor T8 may receive the bias voltage Vbias through the bias voltage line D1_VBL.

[0253] The first horizontal initialization voltage line H_VIL may include Figure 4A The first initialization voltage Vint (for example, refer to Figure 4A) may be provided to the first horizontal initialization voltage line H_VIL. The first horizontal initialization voltage line H_VIL may be connected to the fourth transistor T4 through a contact. The fourth transistor T4 may receive the first initialization voltage Vint through the first horizontal initialization voltage line H_VIL.

[0254] The plurality of first connection electrode patterns C_CNE1 may contact one of the first to fourth semiconductor patterns P_ACT1, S_ACT1, P_ACT2, and S_ACT2. The plurality of first connection electrode patterns C_CNE1 may perform a function of electrically connecting one of the first to fourth semiconductor patterns P_ACT1, S_ACT1, P_ACT2, and S_ACT2 to other wirings or other lines. The plurality of first connection electrode patterns C_CNE1 may be connected to one of the first to fourth semiconductor patterns P_ACT1, S_ACT1, P_ACT2, and S_ACT2 through a contact portion. The plurality of first connection electrode patterns C_CNE1 may include Fig. 7A and Figure 7B The first circuit connection electrode CNE1 and the fourth circuit connection electrode CNE1 ′ are shown in FIG.

[0255] The first data pattern layer SD1 may further include a horizontal connection wiring D1_HCL. The horizontal connection wiring D1_HCL may extend in the first direction DR1. The horizontal connection wiring D1_HCL may be used as Figure 8 The horizontal data connection line H_DCL shown in Figure 8 The horizontal connecting line H_RL shown in FIG.

[0256] Reference Figure 9G and Figure 9H The sixth insulating layer INS6 may cover at least a portion of the first data pattern layer SD1 and may be disposed on the fifth insulating layer INS5. The second data pattern layer SD2 may be disposed on the sixth insulating layer INS6. The second data pattern layer SD2 may include, for example, metal, alloy, conductive metal oxide and / or transparent conductive material.

[0257] The second data pattern layer SD2 includes a first readout line portion RL_P1 , a first vertical reset voltage line D2_VRL, a first driving voltage line VL1 , and a plurality of voltage connection patterns C_VP.

[0258] The first readout line portion RL_P1 extends in the second direction DR2 in each of the second circuit regions O_SA. That is, the first readout line portion RL_P1 may overlap a corresponding one of the second circuit regions O_SA. The first readout line portion RL_P1 may be Figure 3The first readout line portion RL_P1 may be connected to a portion of each of the readout lines RL1 to RLh shown in FIG. Figure 4A The sensor drive circuit O_SD (specifically, the output transistor ST3) shown in FIG.

[0259] The first vertical reset voltage lines D2_VRL extend in the second direction DR2 and are disposed to be spaced apart (eg, spaced apart) from each other in the first direction DR1. The first vertical reset voltage lines D2_VRL may include Figure 4A The first vertical reset voltage line D2_VRL may be connected to the first horizontal reset voltage line G3_VRL and the second horizontal reset voltage line D1_VRL. By combining the first vertical reset voltage line D2_VRL and the first horizontal reset voltage line G3_VRL and the second horizontal reset voltage line D1_VRL, the reset voltage line VRL may have a mesh shape.

[0260] The first driving voltage line VL1 may overlap the first circuit region P_PA. Figure 4A The first driving voltage ELVDD (for example, refer to Figure 4A ) may be provided to the first driving voltage line VL1. The first driving voltage line VL1 may be arranged in a grid form in the display area DA of the display panel DP (eg, see Figure 3 ). The first driving voltage line VL1 can be connected to Figure 4A The fifth transistor T5 and the capacitor Cst are shown in FIG.

[0261] The plurality of voltage connection patterns C_VP may be connected to a vertical voltage line V_VL which will be described later.

[0262] The second data pattern layer SD2 may further include a plurality of second connection electrode patterns C_CNE2. The plurality of second connection electrode patterns C_CNE2 may include Fig. 7A and Figure 7B The second circuit connection electrode CNE2 and the fifth circuit connection electrode CNE2' are shown in FIG.

[0263] Reference Figure 9H and Fig.9I The seventh insulating layer INS7 may cover at least a portion of the second data pattern layer SD2 and may be disposed on the sixth insulating layer INS6. The third data pattern layer SD3 may be disposed on the seventh insulating layer INS7. The third data pattern layer SD3 may include, for example, metal, alloy, conductive metal oxide and / or transparent conductive material.

[0264] The third data pattern layer SD3 may include the data wiring DL, the second readout line portion RL_P2 , the vertical connection wiring D3_VCL, the vertical voltage line V_VL, the second vertical reset voltage line D3_VRL, and a plurality of third connection electrode patterns C_CNE3 .

[0265] The data wiring DL, the vertical connection wiring D3_VCL, and the vertical voltage line V_VL may extend in the second direction DR2. The data wiring DL, the vertical connection wiring D3_VCL, and the vertical voltage line V_VL may be spaced apart (eg, spaced apart) from each other in the first direction DR1.

[0266] Data wiring DL can be used with Figure 3 The data wiring DL may be connected to the data lines DL1 to DLm shown in FIG. Figure 4A The pixel driving circuit P_PD (specifically, the second transistor T2) shown in FIG. 1 is a vertical connection wiring D3_VCL, which can be used as Figure 8 The vertical data connection line V_DCL or Figure 8 The vertical connection wiring D3_VCL can be electrically connected to Figure 9G The horizontal connection wiring D1_HCL shown in FIG.

[0267] The second readout line portion RL_P2 may overlap two second circuit regions O_SA adjacent to each other. The second readout line portion RL_P2 may be connected to two adjacent first readout line portions RL_P1, respectively. Therefore, one readout wiring RL may include a plurality of first readout line portions RL_P1 and a plurality of second readout line portions RL_P2. The readout wiring RL may overlap two second circuit regions O_SA adjacent to each other. Figure 3 corresponds to one of the readout lines RL1 to RLh shown in FIG.

[0268] One of the vertical voltage lines V_VL may be connected via a corresponding voltage connection pattern C_VP (eg, see Figure 9H ) is electrically connected to Fig.9F The second-first horizontal initialization voltage line H_VAIL1 shown in FIG. 1 and the other of the vertical voltage lines V_VL may be electrically connected to the first voltage connection pattern C_VP through the corresponding voltage connection pattern C_VP. Fig.9F That is, some of the vertical voltage lines V_VL may be used as the second initialization voltage line VAIL (eg, see Figure 4A ). In addition, another one of the vertical voltage lines V_VL may be connected via a corresponding voltage connection pattern C_VP (eg, see Figure 9H ) is electrically connected to Figure 9G , to serve as the first horizontal initialization voltage line VIL (eg, see Figure 4A ).

[0269] The other of the vertical voltage lines V_VL can be used as Figure 4A As described above, the vertical voltage line V_VL can be used as a second driving voltage line VL2 connected to the pixel PX (eg, see Figure 3 ) and sensor FX (see, for example, Figure 3 ), and thus, a voltage drop phenomenon of a voltage applied to each voltage line can be alleviated. The second vertical reset voltage lines D3_VRL can extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The second vertical reset voltage lines D3_VRL can be included in Figure 4A The second vertical reset voltage line D3_VRL may be connected to the first horizontal reset voltage line G3_VRL and the second horizontal reset voltage line D1_VRL (see, for example Fig.9F and Figure 9G ) and the first vertical reset voltage line D2_VRL.

[0270] The plurality of third connection electrode patterns C_CNE3 may include Fig. 7A and Figure 7B The third circuit connection electrode CNE3 and the sixth circuit connection electrode CNE3 ′ are shown in FIG.

[0271] Reference Fig.9I and Figure 9J The eighth insulating layer INS8 may cover at least a portion of the third data pattern layer SD3 and may be disposed on the seventh insulating layer INS7. The conductive pattern TCO may be disposed on the eighth insulating layer INS8. The conductive pattern TCO may include a transparent conductive oxide. Alternatively, the conductive pattern TCO may include a metal, an alloy, a conductive metal oxide and / or a transparent conductive material, etc.

[0272] The conductive pattern TCO may include a shielding electrode RSE and a plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE. As an example of the present disclosure, the shielding electrode RSE may extend in the second direction DR2 and may overlap with the readout wiring RL in a plan view. The shielding electrode RSE may be connected to the first vertical reset voltage line D2_VRL (e.g., see Figure 9H ) contact. Therefore, the reset voltage Vrst (eg, see Figure 4A ) can be applied to the shielding electrode RSE.

[0273] The shielding electrode RSE may be disposed to partially cover the sensor driving circuit O_SD in each of the second circuit regions O_SA. Specifically, the shielding electrode RSE may be disposed to cover the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 (eg, see Figure 4A ) in whole or in part. The opening RSE_OP may be provided in the shielding electrode RSE to partially expose the sensor driving circuit O_SD.

[0274] The shielding electrode RSE may perform a function of shielding the sensing signal output from the readout wiring RL from being coupled to the data signal applied to the data wiring DL. To prevent or substantially prevent shielding performance degradation, the opening RSE_OP may be provided at a position not overlapping the readout wiring RL in a plan view.

[0275] The plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE include first and second green pixel connection electrodes G1_CNE and G2_CNE, a red pixel connection electrode R_CNE, and a blue pixel connection electrode B_CNE.

[0276] The first green pixel connection electrode G1_CNE is connected to the first green pixel driving circuit G1_PD (eg, see FIG. 1 ) through a first-first green contact hole G1_CH1 defined in the eighth insulating layer INS8. Figure 5C The second green pixel connection electrode G2_CNE is connected to the second green pixel driving circuit G2_PD through the second-first green contact hole G2_CH1 defined in the eighth insulating layer INS8 (see, for example, Figure 5C The red pixel connection electrode R_CNE is connected to the red pixel driving circuit R_PD through a first red contact hole R_CH1 defined in the eighth insulating layer INS8 (see, for example, Figure 5C ), and the blue pixel connection electrode B_CNE is connected to the blue pixel driving circuit B_PD (eg, see Figure 5C ). The blue pixel connection electrode B_CNE may be disposed below the red pixel connection electrode R_CNE in a plan view.

[0277] A plurality of shielding electrodes RSE and pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE may be disposed on the same layer (e.g., at the same layer) (i.e., disposed on the eighth insulating layer INS8), and may be spaced apart from each other (e.g., spaced apart) in a plan view to be electrically separated from each other. As an example, each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE may not overlap with the second circuit area O_SA in a plan view.

[0278] Reference Figure 9J and Figure 9K The ninth insulating layer INS9 may cover at least a portion of the conductive pattern TCO and may be disposed on the eighth insulating layer INS8. The anode pattern AEP may be disposed on the ninth insulating layer INS9. The anode pattern AEP may include metal, alloy, conductive metal oxide and / or transparent conductive material, etc.

[0279] The anode pattern AEP may include a plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE and a plurality of sensor anode electrodes O_AE1 and O_AE2. The plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE include first and second green anode electrodes G1_AE and G2_AE, a red anode electrode R_AE, and a blue anode electrode B_AE. The plurality of sensor anode electrodes O_AE1 and O_AE2 include a first sensor anode electrode O_AE1 disposed in a first row ODD_R and a second sensor anode electrode O_AE2 disposed in a second row EVEN_R.

[0280] The first green anode electrode G1_AE is connected to the first green pixel connection electrode G1_CNE through the first-second green contact hole G1_CH2 defined in the ninth insulating layer INS9. The second green anode electrode G2_AE is connected to the second green pixel connection electrode G2_CNE through the second-second green contact hole G2_CH2 defined in the ninth insulating layer INS9. The red anode electrode R_AE is connected to the red pixel connection electrode R_CNE through the second red contact hole R_CH2 defined in the ninth insulating layer INS9, and the blue anode electrode B_AE is connected to the blue pixel connection electrode B_CNE through the second blue contact hole B_CH2 defined in the ninth insulating layer INS9.

[0281] As such, the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE may be disposed on a layer different from the layer on which the pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE are disposed (e.g., disposed on the eighth insulating layer INS8), and the pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE may be connected to the corresponding pixel driving circuits. Figure 3 ) can also improve the resolution of the pixel anode electrodes G1_AE, G2_AE, R_AE and B_AE.

[0282] Each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE is disposed at a first side (e.g., left side) or a second side (e.g., right side) of a readout wiring RL (or a first readout line). That is, each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE does not cross (or overlap) the readout wiring RL. Each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNE is separated (e.g., spaced apart) from the readout wiring RL in a first direction DR1.

[0283] Reference Figure 9K and Figure 9L , the readout wiring RL includes a first readout line portion RL_P1 and a second readout line portion RL_P2. The readout wiring RL is covered by the shielding electrode RSE. The blue pixel connection electrode B_CNE is disposed on the eighth insulating layer INS8 together with the shielding electrode RSE, and is separated (e.g., spaced apart) from the shielding electrode RSE in the first direction DR1. The blue pixel connection electrode B_CNE does not cross the readout wiring RL. Therefore, the formation of a coupling capacitance between the blue pixel connection electrode B_CNE and the readout wiring RL can be blocked and prevented (or substantially prevented) by the shielding electrode RSE.

[0284] As an example of the present disclosure, the blue pixel connection electrode B_CNE may not overlap the red anode electrode R_AE and the first and second green anode electrodes G1_AE and G2_AE in a plan view.

[0285] The first sensor anode electrode O_AE1 may be disposed to overlap the sensor circuit area O_SA, and the second sensor anode electrode O_AE2 may be disposed not to overlap the sensor circuit area O_SA. The second sensor anode electrode O_AE2 may overlap the pixel circuit area P_PA. The first sensor anode electrode O_AE1 may be connected to the corresponding sensor driving circuit through the first sensor contact hole O_CH1.

[0286] As an example of the present disclosure, the anode pattern AEP may further include a sensor connection electrode O_CNE2 and a dummy connection electrode D_CNE1. The sensor connection electrode O_CNE2 may extend from the second sensor anode electrode O_AE2 to partially overlap with the sensor circuit area O_SA. The sensor connection electrode O_CNE2 may be formed integrally with the second sensor anode electrode O_AE2. The sensor connection electrode O_CNE2 may be connected to the corresponding sensor drive circuit through the second sensor contact hole O_CH2. The second sensor anode electrode O_AE2 may be electrically connected to the corresponding sensor drive circuit through the sensor connection electrode O_CNE2.

[0287] As an example of the present disclosure, the blue pixel connection electrode B_CNE may partially overlap the sensor connection electrode O_CNE2 in a plan view.

[0288] The dummy connection electrode D_CNE1 may extend from the first sensor anode electrode O_AE1 to overlap the pixel circuit area P_PA. As an example of the present disclosure, the dummy connection electrode D_CNE1 may have a shape similar to that of the sensor connection electrode O_CNE2. The sum of the area of ​​the first sensor anode electrode O_AE1 and the area of ​​the dummy connection electrode D_CNE1 may be substantially equal to the sum of the area of ​​the second sensor anode electrode O_AE2 and the area of ​​the sensor connection electrode O_CNE2.

[0289] As for the first light receiving element OPD1 and the second light receiving element OPD2 (for example, see Figure 5C ) are different from each other, the coupling capacitances acting on the first light receiving element OPD1 and the second light receiving element OPD2 (for example, see Figure 5C ) may be different in size from each other. In this case, a deviation may occur between the sensing signals of each row. However, when the dummy connection electrode D_CNE1 is designed so that the sum of the area of ​​the first sensor anode electrode O_AE1 and the area of ​​the dummy connection electrode D_CNE1 is substantially equal to the sum of the area of ​​the second sensor anode electrode O_AE2 and the area of ​​the sensor connection electrode O_CNE2, the deviation between the sensing signals generated for each row can be reduced, and therefore, the sensing uniformity and the sensing accuracy can be improved.

[0290] In addition, the number of data wirings DL and vertical connection wirings D3_VCL crossing the sensor connection electrode O_CNE2 may be substantially the same as the number of data wirings DL and vertical connection wirings D3_VCL crossing the dummy connection electrode D_CNE1. Therefore, the size of the coupling capacitance acting on the sensor connection electrode O_CNE2 through the data wirings DL and the vertical connection wirings D3_VCL may be the same as the size of the coupling capacitance acting on the dummy connection electrode D_CNE1 through the data wirings DL and the vertical connection wirings D3_VCL. Therefore, the difference between the coupling capacitance acting on the first light receiving element OPD1 disposed in the first row ODD_R and the coupling capacitance acting on the second light receiving element OPD2 disposed in the second row EVEN_R may be reduced.

[0291] Fig. 10A and Fig. 10B is a plan view illustrating a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure.

[0292] Reference Fig. 10A, the conductive pattern TCOa may include a shielding electrode RSE and a plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa.

[0293] The plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNE and B_CNEa include first and second green pixel connection electrodes G1_CNE and G2_CNE, red pixel connection electrodes R_CNE and blue pixel connection electrodes B_CNEa. In a plan view, the blue pixel connection electrode B_CNEa may be disposed above the red pixel connection electrode R_CNE.

[0294] Reference Fig. 10A and Fig. 10B The ninth insulating layer INS9 may cover at least a portion of the conductive pattern TCOa and may be disposed on the eighth insulating layer INS8. The anode pattern AEP may be disposed on the ninth insulating layer INS9.

[0295] The anode pattern AEP may include a plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE and a plurality of sensor anode electrodes O_AE1 and O_AE2.

[0296] As such, the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa may be disposed on a layer different from the pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE (e.g., disposed on the eighth insulating layer INS8), and the pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE may be connected to the corresponding pixel driving circuits. Figure 3 ) can also improve the resolution of the pixel anode electrodes G1_AE, G2_AE, R_AE and B_AE.

[0297] Each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa is disposed at a first side (e.g., left side) or a second side (e.g., right side) of a readout wiring RL (or a first readout wiring). That is, each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa does not cross (or overlap) the readout wiring RL. Each of the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa is separated (e.g., spaced apart) from the readout wiring RL in a first direction DR1. The formation of coupling capacitance between the pixel connection electrodes G1_CNE, G2_CNE, R_CNE, and B_CNEa and the readout wiring RL may be blocked and prevented (or substantially prevented) by the shielding electrode RSE.

[0298] As an example of the present disclosure, the blue pixel connection electrode B_CNEa may overlap the red anode electrode R_AE and one of the first and second green anode electrodes G1_AE and G2_AE (eg, the red anode electrode R_AE) in a plan view. The blue pixel connection electrode B_CNEa may pass through a center point of the red anode electrode R_AE.

[0299] As an example of the present disclosure, the blue pixel connection electrode B_CNEa may not overlap the sensor connection electrode O_CNE2 in a plan view, and may partially overlap the dummy connection electrode D_CNE1 .

[0300] Fig.11A and Fig. 11B is a plan view illustrating a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure.

[0301] Reference Fig.11A , the conductive pattern TCOb may include a shielding electrode RSE and a plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNEb, and B_CNEb.

[0302] The plurality of pixel connection electrodes G1_CNE, G2_CNE, R_CNEb and B_CNEb include first and second green pixel connection electrodes G1_CNE and G2_CNE, red pixel connection electrode R_CNEb and blue pixel connection electrode B_CNEb. The blue pixel connection electrode B_CNEb may be disposed under the red pixel connection electrode R_CNEb in a plan view.

[0303] Reference Fig.11A and Fig. 11B The ninth insulating layer INS9 may cover at least a portion of the conductive pattern TCOb and may be disposed on the eighth insulating layer INS8. The anode pattern AEP may be disposed on the ninth insulating layer INS9.

[0304] The anode pattern AEP may include a plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE and a plurality of sensor anode electrodes O_AE1 and O_AE2.

[0305] As an example of the present disclosure, the blue pixel connection electrode B_CNEb may overlap the red anode electrode R_AE and one (eg, the first green anode electrode G1_AE) of the first and second green anode electrodes G2_AE in a plan view.

[0306] As an example of the present disclosure, the blue pixel connection electrode B_CNEb may not overlap the sensor connection electrode O_CNE2 and the dummy connection electrode D_CNE1 in a plan view. The red pixel connection electrode R_CNEb may not overlap the sensor connection electrode O_CNE2 and the dummy connection electrode D_CNE1 in a plan view.

[0307] When the blue pixel connection electrode B_CNEb and the red pixel connection electrode R_CNEb do not overlap with the dummy connection electrode D_CNE1 and the sensor connection electrode O_CNE1 in a plan view, the coupling capacitance generated between the blue pixel connection electrode B_CNEb and the red pixel connection electrode R_CNEb and the first light receiving element OPD1 and the second light receiving element OPD2 can be reduced. Therefore, it is possible to prevent or substantially prevent the sensing performance of the first light receiving element OPD1 and the second light receiving element OPD2 from being degraded due to the coupling capacitance.

[0308] FIG. 12A to FIG. 12C is a plan view illustrating a process of stacking circuit layers and element layers according to one or more embodiments of the present disclosure. Fig.12D It is along Fig. 12C A cross-sectional view taken along line II-II' shown in FIG.

[0309] Reference FIG. 12A to FIG. 12D , the shielding electrode RSE may be disposed on the eighth insulating layer INS8 (or the first intermediate insulating layer). The ninth insulating layer INS9 may cover at least a portion of the shielding electrode RSE and may be disposed on the eighth insulating layer INS8. A plurality of pixel connection electrodes G1_CNEc, G2_CNEc, R_CNEc, and B_CNEc may be disposed on the ninth insulating layer INS9 (or the second intermediate insulating layer).

[0310] As an example, the plurality of pixel connection electrodes G1_CNEc, G2_CNEc, R_CNEc, and B_CNEc may be disposed on a layer (e.g., disposed on a ninth insulating layer INS9) different from a layer (e.g., an eighth insulating layer INS8) on which the shielding electrode RSE is formed. The blue pixel connection electrode B_CNEc is connected to a blue pixel driving circuit B_PD (e.g., see FIG. 1 ) through a first blue contact hole B_CH1 defined in the ninth insulating layer INS9. Figure 5C ).

[0311] Alternatively, a plurality of pixel connection electrodes G1_CNEc, G2_CNEc, R_CNEc and B_CNEc may be disposed on the eighth insulating layer INS8, and the shielding electrode RSE may be disposed on the ninth insulating layer INS9. In this case, the blue pixel connection electrode B_CNEc is connected to the blue pixel driving circuit B_PD (for example, see FIG. 1 ) through the first blue contact hole B_CH1 defined in the eighth insulating layer INS8. Figure 5C ).

[0312] The tenth insulating layer INS10 (or the third intermediate insulating layer) may cover at least a portion of the plurality of pixel connection electrodes G1_CNEc, G2_CNEc, R_CNEc, and B_CNEc and may be disposed on the ninth insulating layer INS9. The anode pattern AEP may be disposed on the tenth insulating layer INS10.

[0313] The anode pattern AEP may include a plurality of pixel anode electrodes G1_AE, G2_AE, R_AE, and B_AE and a plurality of sensor anode electrodes O_AE1 and O_AE2.

[0314] The blue anode electrode B_AE is connected to the blue pixel connection electrode B_CNEc through the second blue contact hole B_CH2 defined in the tenth insulating layer INS10. Alternatively, when the plurality of pixel connection electrodes G1_CNEc, G2_CNEc, R_CNEc and B_CNEc are disposed on the eighth insulating layer INS8, the blue anode electrode B_AE may be connected to the blue pixel connection electrode B_CNEc through the second blue contact hole B_CH2 defined in the ninth insulating layer INS9 and the tenth insulating layer INS10.

[0315] Fig.13A is a plan view showing a portion of a display panel according to one or more embodiments. Fig. 13B It is shown Fig.13A An enlarged plan view of a portion of the. Fig. 13C It is along Fig. 13B A cross-sectional view taken along line III-III' shown in FIG.

[0316] Reference Fig.13A , the display panel DP includes a plurality of pixels PXR, PXG1, PXG2, and PXB and a plurality of sensors FX1 and FX2.

[0317] The blue light emitting element ED_B is electrically connected to the blue pixel driving circuit B_PD (or the first pixel driving circuit). Specifically, the blue light emitting element ED_B includes a blue anode electrode B_AEa (or the first pixel anode electrode) and a blue light emitting layer B_EL, and the blue anode electrode B_AEa is electrically connected to the blue pixel driving circuit B_PD. The blue anode electrode B_AEa is connected to the blue pixel driving circuit B_PD through a blue contact hole B_CHa.

[0318] The red light emitting element ED_R is electrically connected to the red pixel driving circuit R_PD (or the second pixel driving circuit). Specifically, the red light emitting element ED_R includes a red anode electrode R_AEa (or the second pixel anode electrode) and a red light emitting layer R_EL, and is electrically connected to the red pixel driving circuit R_PD. The red anode electrode R_AEa is connected to the red pixel driving circuit R_PD through a red contact hole R_CHa.

[0319] The first green light emitting element ED_G1 is electrically connected to the first green pixel driving circuit G1_PD (or the third pixel driving circuit). For example, the first green light emitting element ED_G1 includes a first green anode electrode G1_AEa (or the third pixel anode electrode) and a first green light emitting layer G1_EL, and the first green anode electrode G1_AEa is electrically connected to the first green pixel driving circuit G1_PD. The first green anode electrode G1_AEa is connected to the first green pixel driving circuit G1_PD through a first green contact hole G1_CHa. The second green light emitting element ED_G2 is electrically connected to the second green pixel driving circuit G2_PD (or the fourth pixel driving circuit). Specifically, the second green light emitting element ED_G2 includes a second green anode electrode G2_AEa (or the fourth pixel anode electrode) and a second green light emitting layer G2_EL, and the second green anode electrode G2_AEa is electrically connected to the second green pixel driving circuit G2_PD. The second green anode electrode G2_AEa is connected to the second green pixel driving circuit G2_PD through a second green contact hole G2_CHa.

[0320] Reference Fig. 13B and Fig. 13C The eighth insulating layer INS8 may cover the third data pattern layer SD3 (eg, see Fig.9I ) and may be disposed on a seventh insulating layer INS7 (eg, see Fig.9I The anode pattern AEPa may be disposed on the eighth insulating layer INS8.

[0321] The anode pattern AEPa may include a plurality of pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa and a plurality of sensor anode electrodes O_AE1 and O_AE2. Figure 3) is not high, it is possible to ensure a sufficient distance between the pixel anode electrodes G1_AEa, G2_AEa, R_AEa and B_AEa. In this case, the display device DD may not include Figure 5C The pixel connection electrodes shown in FIG.

[0322] Each of the pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa is disposed at a first side (e.g., left side) or a second side (e.g., right side) of a readout wiring RL (or a first readout wiring). That is, each of the pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa does not cross (or overlap) the readout wiring RL. The pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa are separated (e.g., spaced apart) from the readout wiring RL in a first direction DR1.

[0323] The readout wiring RL includes a first readout line portion RL_P1 and a second readout line portion RL_P2 As an example of the present disclosure, the blue anode electrode B_AEa is disposed between the blue pixel driving circuit B_PD and the readout wiring RL in a plan view.

[0324] The pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa and the first and second sensor anode electrodes O_AE1 and O_AE2 are disposed in the same layer (e.g., at the same layer) (i.e., disposed on the eighth insulating layer INS8). The pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa may be disposed to be separated (e.g., spaced apart) from the first and second sensor anode electrodes O_AE1 and O_AE2, the sensor connection electrode O_CNE2, and the dummy connection electrode D_CNE1 in a plan view.

[0325] exist Fig. 13B and Fig. 13C In the embodiment, the shield electrode RSE is omitted (for example, referring to Figure 9K ), but the present disclosure is not limited thereto. The shielding electrode RSE can also be used for Fig. 13B and Fig. 13C In this case, the pixel anode electrodes G1_AEa, G2_AEa, R_AEa, and B_AEa may be disposed on the ninth insulating layer INS9 covering the shielding electrode RSE.

[0326] Fig.14A and Fig. 14B is a cross-sectional view illustrating a light emitting element and a light receiving element of a display panel according to one or more embodiments of the present disclosure.

[0327] Reference Fig.14A and Fig. 14B, the first electrode layer is arranged on the circuit layer DP_CL. The pixel defining layer PDL is formed on the first electrode layer. The first electrode layer may include a red anode electrode R_AE, a green anode electrode G_AE and a blue anode electrode B_AE. The first light emitting opening to the third light emitting opening OP1_1, OP1_2 and OP1_3 of the pixel defining layer PDL expose at least part of the red anode electrode R_AE, the green anode electrode G_AE and the blue anode electrode B_AE respectively. In one or more embodiments of the present disclosure, the pixel defining layer PDL may also include a black material. The pixel defining layer PDL may also include a black organic dye / pigment (such as carbon black or aniline black). The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may also include a liquid-repellent organic material.

[0328] like Fig.14A As shown in , the display panel DP may include first to third light emitting areas PXA-R, PXA-G, and PXA-B and first to third non-light emitting areas NPXA-R, NPXA-G, and NPXA-B adjacent to the first to third light emitting areas PXA-R, PXA-G, and PXA-B. Each of the non-light emitting areas NPXA-R, NPXA-G, and NPXA-B may surround the corresponding light emitting areas PXA-R, PXA-G, and PXA-B. In this embodiment, the first light emitting area PXA-R is defined as a portion corresponding to the red anode electrode R_AE exposed through the first light emitting opening OP1_1 (e.g., corresponding to the portion of the red anode electrode R_AE exposed through the first light emitting opening OP1_1). The second light emitting area PXA-G is defined as a portion corresponding to the green anode electrode G_AE exposed through the second light emitting opening OP1_2 (e.g., corresponding to the portion of the green anode electrode G_AE exposed through the second light emitting opening OP1_2). The third light emitting region PXA-B is defined to correspond to a portion of the blue anode electrode B_AE exposed by the third light emitting opening OP1_3 (e.g., corresponds to a portion of the blue anode electrode B_AE exposed by the third light emitting opening OP1_3). The non-pixel region NPA may be defined (e.g., may be located) between the first to third non-light emitting regions NPXA-R, NPXA-G, and NPXA-B.

[0329] The light-emitting layer may be disposed on the first electrode layer. The light-emitting layer may include a red light-emitting layer R_EL, a green light-emitting layer G_EL, and a blue light-emitting layer B_EL. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may be disposed in regions corresponding to the first to third light-emitting openings OP1_1, OP1_2, and OP1_3, respectively. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may be formed separately. Each of the red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may include an organic material and / or an inorganic material. The red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL may generate light of a corresponding color (e.g., light of a predetermined color). For example, the red light-emitting layer R_EL may generate red light, the green light-emitting layer G_EL may generate green light, and the blue light-emitting layer B_EL may generate blue light.

[0330] Although the patterned red light emitting layer R_EL, green light emitting layer G_EL, and blue light emitting layer B_EL are shown as examples in this embodiment, one light emitting layer may be commonly provided in the first to third light emitting regions PXA-R, PXA-G, and PXA-B. In this case, the light emitting layer may generate white light or blue light. In addition, the light emitting layer may have a multilayer structure called a series connection.

[0331] Each of the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL may include a low molecular organic material or a high molecular organic material as a light emitting material. Optionally, each of the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL may include a quantum dot material as a light emitting material. The core of the quantum dot may be selected from II-VI group compounds, III-V group compounds, IV-VI group compounds, IV group elements, IV group compounds and combinations thereof.

[0332] The second electrode layer is arranged on the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL. The second electrode layer may include a red cathode electrode R_CE, a green cathode electrode G_CE and a blue cathode electrode B_CE. The red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may be electrically connected to each other. As an example, the red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may have an integral shape. In this case, the red cathode electrode R_CE, the green cathode electrode G_CE and the blue cathode electrode B_CE may be commonly arranged in the first to third light emitting regions PXA-R, PXA-G and PXA-B, the first to third non-light emitting regions NPXA-R, NPXA-G and NPXA-B and the non-pixel region NPA.

[0333] The element layer DP_ED may further include a light receiving element OPD. The light receiving element OPD may be a photodiode. The pixel defining layer PDL may further include a light receiving opening OP2 provided corresponding to the light receiving element OPD.

[0334] The light receiving element OPD may include a sensing anode electrode O_AE, a photoelectric conversion layer O_RL, and a sensing cathode electrode O_CE. The sensing anode electrode O_AE may be disposed on the same layer (e.g., at the same layer) as the first electrode layer. That is, the sensing anode electrode O_AE may be disposed on the circuit layer DP_CL and may be formed simultaneously with the red anode electrode R_AE, the green anode electrode G_AE, and the blue anode electrode B_AE through the same process.

[0335] The light receiving opening OP2 of the pixel defining layer PDL exposes at least a portion of the sensing anode electrode O_AE. The photoelectric conversion layer O_RL is disposed on the sensing anode electrode O_AE exposed by the light receiving opening OP2. The photoelectric conversion layer O_RL may include an organic photosensitive material. The sensing cathode electrode O_CE may be disposed on the photoelectric conversion layer O_RL. The sensing cathode electrode O_CE and the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE may be formed simultaneously by the same process. As an example of the present disclosure, the sensing cathode electrode O_CE may have an integral shape with the red cathode electrode R_CE, the green cathode electrode G_CE, and the blue cathode electrode B_CE to form a common cathode electrode.

[0336] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one or more embodiments of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. In one or more embodiments of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers stacked alternately.

[0337] The inorganic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B, and the light receiving element OPD from moisture / oxygen, and the organic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B, and the light receiving element OPD from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an acrylic organic layer, but is not particularly limited thereto.

[0338] The display device DD includes an input sensing layer ISL disposed on the display panel DP and a color filter layer CFL disposed on the input sensing layer ISL.

[0339] The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. The input sensing layer ISL includes a first conductive layer ICL1, an insulating layer IL, a second conductive layer ICL2 and a protection layer PL. The first conductive layer ICL1 may be disposed on the encapsulation layer TFE. Fig.14A and Fig. 14B A structure in which the first conductive layer ICL1 is directly disposed on the encapsulation layer TFE is shown, but the present disclosure is not limited thereto. The input sensing layer ISL may further include a base insulating layer disposed between the first conductive layer ICL1 and the encapsulation layer TFE. In this case, the encapsulation layer TFE may be covered by the base insulating layer, and the first conductive layer ICL1 may be disposed on the base insulating layer. As an example of the present disclosure, the base insulating layer may include an inorganic insulating material.

[0340] The insulating layer IL may cover the first conductive layer ICL1. The second conductive layer ICL2 is disposed on the insulating layer IL. Although a structure in which the input sensing layer ISL includes the first conductive layer ICL1 and the second conductive layer ICL2 is shown, the present disclosure is not limited thereto. For example, the input sensing layer ISL may include only one of the first conductive layer ICL1 and the second conductive layer ICL2.

[0341] The protection layer PL may be disposed on the second conductive layer ICL2. The protection layer PL may include an organic insulating material. The protection layer PL may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from moisture / oxygen and from foreign matter.

[0342] The color filter layer CFL may be disposed on the input sensing layer ISL. The color filter layer CFL may be disposed directly on the protection layer PL. The color filter layer CFL may include a first color filter CF_R, a second color filter CF_G, and a third color filter CF_B. The first color filter CF_R has a first color, the second color filter CF_G has a second color, and the third color filter CF_B has a third color. As an example, the first color may be red, the second color may be green, and the third color may be blue.

[0343] The color filter layer CFL may further include a dummy color filter DCF. As an example of the present disclosure, when the area in which the photoelectric conversion layer O_RL is disposed is defined as (or may be referred to as) a sensing area SA, and the periphery of the sensing area SA is defined as (or may be referred to as) a non-sensing area NSA, the dummy color filter DCF may be disposed to correspond to the sensing area SA. The dummy color filter DCF may overlap the sensing area SA and the non-sensing area NSA. As an example, the dummy color filter DCF may have the same color as one of the first to third color filters CF_R, CF_G, and CF_B. As an example, the dummy color filter DCF may have a green color in the same manner as the second color filter CF_G.

[0344] The color filter layer CFL may further include a black matrix BM. The black matrix BM may be disposed to correspond to the non-pixel area NPA. The black matrix BM may be disposed to overlap with the first conductive layer ICL1 and the second conductive layer ICL2 in the non-pixel area NPA. As an example, the black matrix BM may overlap with the non-pixel area NPA and the first to third non-luminous areas NPXA-G, NPXA-B, and NPXA-R. The black matrix BM may not overlap with the first to third luminous areas PXA-R, PXR-G, and PXA-B.

[0345] The color filter layer CFL may further include an outer coating layer OCL. The outer coating layer OCL may include an organic insulating material. The outer coating layer OCL may be set to have a thickness sufficient to remove the steps between the first to third color filters CF_R, CF_G, and CF_B. The outer coating layer OCL may include any material having a suitable thickness (e.g., a predetermined thickness) and that can flatten the upper surface of the color filter layer CFL without particular limitation, and may include, for example, an acrylate organic material.

[0346] Reference Fig. 14B , when operating the display device DD (see, for example Figure 1 ), each of the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B can output light. The red light emitting element ED_R outputs red light in the red band, the green light emitting element ED_G outputs green light in the green band, and the blue light emitting element ED_B outputs blue light in the blue band.

[0347] As an example of the present disclosure, the light receiving element OPD can receive light from a specific light emitting element (e.g., green light emitting element ED_G) among the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B. That is, the light receiving element OPD can receive the second reflected light Lg2 generated by the second light Lg1 output from the green light emitting element ED_G being reflected by the fingerprint of the user. The second light Lg1 and the second reflected light Lg2 can be green light with a green wavelength. The dummy color filter DCF is disposed on the light receiving element OPD. The dummy color filter DCF can have a green color. Therefore, the second reflected light Lg2 can pass through the dummy color filter DCF and can be incident on the light receiving element OPD.

[0348] On the other hand, the red light and blue light output from the red light emitting element ED_R and the blue light emitting element ED_B may also be reflected by the user's hand US_F. For example, when the light generated by the red light Lr1 output from the red light emitting element ED_R being reflected by the user's hand US_F is defined as (or may be referred to as) the first reflected light Lr2, the first reflected light Lr2 may not pass through the dummy color filter DCF and may be absorbed. Therefore, the first reflected light Lr2 cannot pass through the dummy color filter DCF and cannot be incident on the light receiving element OPD. Similarly, even if the blue light is reflected by the user's hand US_F, it may be absorbed by the dummy color filter DCF. Therefore, only the second reflected light Lg2 may be provided to the light receiving element OPD.

[0349] According to the above description, the pixel connection electrode can be arranged at the same layer (for example, at the same layer) as the shielding electrode, and the pixel anode electrode can be connected to the corresponding pixel driving circuit. Therefore, even if the resolution of the display device is increased, the arrangement freedom of the pixel anode electrode can be improved.

[0350] In addition, since the pixel connection electrode is arranged not to cross the readout wiring, the coupling capacitance acting on the readout wiring can be reduced, and thus the sensing accuracy of the sensor can be improved.

[0351] Although some exemplary embodiments of the present disclosure have been described above with reference to the described embodiments, it will be understood by those skilled in the art that the present disclosure may be modified and altered in various ways without departing from the spirit and technical field of the present disclosure described in the described claims. Therefore, the technical scope of the present disclosure should not be limited to the contents described in the specific embodiments of the specification, but should be determined by the attached claims and their equivalents.

Claims

1. A display device, comprising: Base layer; A circuit layer, located on the substrate layer; as well as an element layer, located on the circuit layer and including a light emitting element and a light receiving element, The circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; and a readout wiring connected to the sensor driving circuit. wherein a first pixel driving circuit among the pixel driving circuits is continuously arranged in a direction parallel to the readout wiring and is connected to a first light emitting element among the light emitting elements, and The circuit layer further includes a first pixel connection electrode connecting the first pixel driving circuit to the first light-emitting element, and the first pixel connection electrode does not cross the readout wiring in a plan view.

2. The display device according to claim 1, wherein: The first pixel driving circuit is located at a first side of a first pixel anode electrode of the first light emitting element, and a first readout wiring adjacent to the first pixel anode electrode among the readout wirings is located at a second side of the first pixel anode electrode, and The first pixel connecting electrode is located between the first pixel driving circuit and the first readout wiring.

3. The display device according to claim 2, wherein: The circuit layer comprises: a data line connected to the pixel driving circuit; and a shielding electrode located on the data line and overlapping the readout wiring and the sensor driving circuit in a plan view, and Wherein, the shielding electrode and the first pixel connecting electrode are located at the same layer.

4. The display device according to claim 2, wherein: The first light emitting element comprises: The first pixel anode electrode, Wherein, the first pixel anode electrode is connected to the first pixel driving circuit through the first pixel connecting electrode, and The first pixel anode electrode and the first pixel connecting electrode are located at different layers.

5. The display device according to claim 4, wherein: The light receiving element comprises: first light receiving elements located in a first row; and a second light receiving element, located in the second row, wherein each of the first light receiving elements overlaps with a corresponding first sensor driving circuit among the sensor driving circuits in a plan view, and wherein each of the second light receiving elements does not overlap with a corresponding second sensor driving circuit among the sensor driving circuits in a plan view.

6. The display device according to claim 5, wherein: Each of the second light receiving elements includes: a second sensor anode electrode; and a sensor connection electrode extending from the second sensor anode electrode to overlap with the second sensor driving circuit, and Wherein, the second sensor anode electrode and the sensor connecting electrode are located at the same layer.

7. The display device according to claim 6, wherein: The sensor connection electrode overlaps the first pixel connection electrode in a plan view.

8. The display device according to claim 7, wherein: The circuit layer also includes: a second pixel connection electrode, connecting a second light emitting element among the light emitting elements and a second pixel driving circuit among the pixel driving circuits, and Wherein, each of the first pixel connection electrode and the second pixel connection electrode does not overlap with other light emitting elements in a plan view.

9. The display device according to claim 6, wherein: Each of the first light receiving elements includes: a first sensor anode electrode; and a dummy connecting electrode extending from the first sensor anode electrode, and Wherein, the first sensor anode electrode overlaps with the first sensor driving circuit and is connected to the first sensor driving circuit.

10. The display device according to claim 9, wherein: The sum of the area of ​​the dummy connection electrode and the area of ​​the first sensor anode electrode is equal to the sum of the area of ​​the sensor connection electrode and the area of ​​the second sensor anode electrode.

11. The display device according to claim 10, wherein: The dummy connection electrode overlaps the first pixel connection electrode in a plan view.

12. The display device according to claim 11, wherein: The first pixel connecting electrode overlaps a second light emitting element among the light emitting elements in a plan view.

13. The display device according to claim 12, wherein: The first pixel connecting electrode passes through a center point of the second light emitting element.

14. The display device according to claim 2, wherein: The circuit layer also includes: A second pixel connection electrode is connected to a second light emitting element among the light emitting elements and a second pixel driving circuit among the pixel driving circuits. wherein the second pixel connecting electrode does not overlap with the first light emitting element in a plan view, and The first pixel connecting electrode overlaps with a third light emitting element among the light emitting elements in a plan view.

15. The display device according to claim 14, wherein: The first pixel connecting electrode and the second pixel connecting electrode do not overlap the light receiving element in a plan view.

16. The display device according to claim 2, wherein: The circuit layer comprises: a data line connected to the pixel driving circuit; and a shielding electrode overlapping the readout wiring and the sensor driving circuit in a plan view and located on a first intermediate insulating layer covering the data line, and Wherein, the first pixel connecting electrode is located on the second intermediate insulating layer covering the shielding electrode.

17. The display device according to claim 16, wherein: The first light emitting element comprises: The first pixel anode electrode, Wherein, the first pixel anode electrode is connected to the first pixel driving circuit through the first pixel connecting electrode, and Wherein, the first pixel anode electrode is located on the third intermediate insulating layer covering the first pixel connecting electrode.

18. A display device, comprising: Base layer; A circuit layer, located on the substrate layer; as well as an element layer, located on the circuit layer and including a light emitting element and a light receiving element, The circuit layer includes: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a readout wiring connected to the sensor driving circuit; and a shielding electrode overlapping the readout wiring and the sensor driving circuit in a plan view. wherein a first pixel driving circuit among the pixel driving circuits is continuously arranged in a direction parallel to the readout wiring and is connected to a first light emitting element among the light emitting elements, and The circuit layer further includes a first pixel connection electrode connecting the first pixel driving circuit to the first light emitting element, and the first pixel connection electrode is located at a layer different from a layer on which the shielding electrode is located.

19. The display device according to claim 18, wherein: The first pixel driving circuit is located at a first side of a first pixel anode electrode of the first light emitting element, and a first readout wiring adjacent to the first pixel anode electrode among the readout wirings is located at a second side of the first pixel anode electrode, and The first pixel connection electrode is located between the first pixel driving circuit and the first readout wiring, and does not cross the first readout wiring.

20. The display device according to claim 19, wherein: The circuit layer also includes: A data line connected to the pixel driving circuit, Wherein, the shielding electrode is located on the first intermediate insulating layer covering the data line, and Wherein, the first pixel connecting electrode is located on the second intermediate insulating layer covering the shielding electrode.

21. The display device according to claim 20, wherein: The first light emitting element comprises: The first pixel anode electrode is electrically connected to the first pixel driving circuit, and Wherein, the first pixel anode electrode is located on the third intermediate insulating layer covering the first pixel connecting electrode.

22. The display device according to claim 21, wherein: The light receiving element comprises: first light receiving elements located in a first row; and a second light receiving element, located in the second row, wherein each of the first light receiving elements overlaps with a corresponding first sensor driving circuit among the sensor driving circuits in a plan view, and wherein each of the second light receiving elements does not overlap with a corresponding second sensor driving circuit among the sensor driving circuits in a plan view.

23. The display device according to claim 22, wherein: Each of the second light receiving elements includes: a second sensor anode electrode; and a sensor connection electrode extending from the second sensor anode electrode to overlap with the second sensor driving circuit, and Wherein, the sensor connecting electrode is located on the third intermediate insulating layer.

24. The display device according to claim 23, wherein: Each of the first light receiving elements includes: a first sensor anode electrode; and a dummy connecting electrode extending from the first sensor anode electrode, wherein the first sensor anode electrode overlaps with the first sensor drive circuit and is connected to the first sensor drive circuit, and Wherein, the dummy connecting electrode is located on the third intermediate insulating layer.

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