Display substrate, preparation method thereof and display device
By designing an independent voltage divider power line and sub-pixel structure on the display substrate, the problem of high power consumption of the display substrate of large-size display devices is solved, and the power consumption and voltage drop loss are reduced.
Patent Information
- Application Number
- CN202510059142.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-04-11
AI Technical Summary
The display substrates of large-size display devices consume high power, making it difficult to meet the needs of efficient display.
A display substrate is designed, which includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, and uses a plurality of independent voltage divider power lines to correspond to the sub-pixels one by one, and is electrically connected to the voltage divider power line through a driving transistor to achieve accurate signal transmission.
By transmitting signals to different sub-pixels using voltage divider power lines, the voltage drop loss is reduced, and the power consumption of the display substrate is reduced.
Smart Images
Figure CN119816139A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of display technology, and more specifically, to a display substrate and a method for preparing the same, and a display device. Background Art
[0002] In the field of display applications, electronic products with displays, such as televisions, are gradually developing towards larger sizes and higher PPI (Pixels Per Inch, pixel density unit). Display devices such as liquid crystal displays (LCD) and organic light emitting diodes (OLED) are commonly used in electronic products.
[0003] At present, the display substrate of the large-size display device in the related art has the problem of high power consumption. Summary of the invention
[0004] The embodiments of the present application provide a display substrate and a method for manufacturing the same, and a display device, aiming to reduce the power consumption of the display substrate.
[0005] A first aspect of an embodiment of the present application provides a display substrate, comprising: A plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixels; The pixel unit includes a pixel circuit, and the pixel circuit includes a plurality of voltage-dividing power supply lines that are independent of each other, and the voltage-dividing power supply lines correspond to the sub-pixels one by one; The sub-pixel includes a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer includes a driving transistor, and a first electrode of the driving transistor is electrically connected to the corresponding divided voltage power line.
[0006] Optionally, the driving circuit layer includes a first metal layer, a buffer layer, a semiconductor layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer which are sequentially arranged on the substrate; A plurality of divided voltage power lines are located on the first metal layer.
[0007] Optionally, the driving circuit layer of the sub-pixel also includes a switching transistor and a sensing transistor, the active layers of the driving transistor, the switching transistor and the sensing transistor are located in the semiconductor layer, the gates of the driving transistor, the switching transistor and the sensing transistor are located in the second metal layer, and the first and second electrodes of the driving transistor, the switching transistor and the sensing transistor are located in the third metal layer.
[0008] Optionally, the first electrode of the driving transistor of the sub-pixel is electrically connected to the corresponding voltage-dividing power line through a via hole penetrating the second insulating layer, the first insulating layer and the buffer layer.
[0009] Optionally, the orthographic projections of the plurality of divided voltage power lines on the substrate are located between the orthographic projections of the gate of the switching transistor on the substrate and the orthographic projections of the gate of the sensing transistor on the substrate.
[0010] Optionally, the driving circuit layer further includes a shielding layer, the shielding layer is located on the first metal layer, and the orthographic projection of the active layer of the driving transistor on the substrate is located within the orthographic projection range of the shielding layer on the substrate.
[0011] Optionally, the pixel unit includes a first sub-pixel, a second sub-pixel, a third pixel and a fourth sub-pixel arranged along a first direction; the shielding layer is reused as a first plate of a capacitor, and the semiconductor layer includes a second plate formed on each sub-pixel; The orthographic projection of the second electrode plate on the substrate is within the orthographic projection range of the first electrode plate on the substrate; An area of the second electrode plate in the first sub-pixel is greater than an area of the second electrode plate in the second sub-pixel, the third sub-pixel, and the fourth sub-pixel.
[0012] Optionally, the voltage-dividing power line extends along a first direction; The voltage-dividing power lines of the plurality of pixel units arranged along the first direction are connected to each other.
[0013] Optionally, the display substrate further comprises a plurality of mains voltage power lines, and the mains voltage power lines extend along the second direction; The total voltage power line is connected to each corresponding divided voltage power line in the second direction; The first direction is perpendicular to the second direction.
[0014] Optionally, the pixel unit includes a first sub-pixel, a second sub-pixel, a third pixel and a fourth sub-pixel arranged along a first direction; The pixel circuit comprises a first voltage division line, a second voltage division line, a third voltage division line and a fourth voltage division line extending along the first direction; The first electrode of the driving transistor of the first sub-pixel is connected to the first voltage dividing line, the first electrode of the driving transistor of the second sub-pixel is connected to the second voltage dividing line, the first electrode of the driving transistor of the third sub-pixel is connected to the third voltage dividing line, and the first electrode of the driving transistor of the fourth sub-pixel is connected to the fourth voltage dividing line.
[0015] Optionally, the sub-pixel further includes a light emitting structure layer located on a side of the driving circuit layer away from the substrate; The second electrode of the driving transistor is electrically connected to the anode in the light emitting structure layer.
[0016] A second aspect of the embodiments of the present application provides a display device, comprising a display substrate provided in the first aspect of the embodiments of the present application.
[0017] A third aspect of an embodiment of the present application provides a method for preparing a display substrate, wherein the display substrate includes a plurality of pixel units arranged in an array, each of the pixel units includes a plurality of sub-pixels, and the preparation method includes: providing a substrate; forming a first metal layer on one side of the substrate, the first metal layer comprising a plurality of voltage-dividing power lines extending along a first direction; forming a buffer layer on a side of the first metal layer facing away from the substrate; Forming a semiconductor layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer of a driving circuit layer on a side of the buffer layer away from the substrate; Wherein, the first electrode of the driving transistor in the driving circuit layer of the sub-pixel is electrically connected to the corresponding voltage-dividing power line.
[0018] Beneficial effects: The present application provides a display substrate and a preparation method thereof, and a display device. The display substrate includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, the pixel unit includes a pixel circuit, the pixel circuit includes a plurality of independent voltage-dividing power lines, the voltage-dividing power lines correspond to the sub-pixels one-to-one, the sub-pixels include a substrate and a driving circuit layer, wherein the first electrode of the driving transistor in the driving circuit layer is connected to the corresponding voltage-dividing power line; in this way, different voltage-dividing power lines can be used to transmit signals to different sub-pixels, thereby reducing voltage drop losses, and reducing power consumption of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0020] Figure 1 is a schematic diagram of a planar structure of a display substrate proposed in one embodiment of the present application; Figure 2 is a schematic cross-sectional structure diagram of a display substrate proposed in one embodiment of the present application; Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit proposed in an embodiment of the present application; Figure 4 is a schematic diagram of a planar structure of another display substrate proposed in an embodiment of the present application; Figure 5 is a flowchart of a method for preparing a display substrate according to an embodiment of the present application; Figure 6 It is a structural schematic diagram of forming a first metal layer pattern in a method for preparing a display substrate proposed in one embodiment of the present application; Figure 7 It is a structural schematic diagram of forming a semiconductor layer pattern in a method for preparing a display substrate proposed in one embodiment of the present application; Figure 8 It is a structural schematic diagram of forming a second metal layer pattern in a method for preparing a display substrate proposed in one embodiment of the present application; Fig. 9 It is a structural schematic diagram of forming a third metal layer pattern in a method for preparing a display substrate proposed in an embodiment of the present application. DETAILED DESCRIPTION
[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0022] In the embodiment of the present application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and a source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where the current mainly flows.
[0023] In the application embodiment, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" may sometimes be interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.
[0024] In the embodiments of the present application, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" can be, for example, an electrode or wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor or capacitor.
[0025] Figure 1 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 1 As shown, the display substrate may include a plurality of pixel units 10 arranged in a matrix, at least one of the plurality of pixel units 10 includes a first sub-pixel 11 emitting a first color light, a second sub-pixel 12 emitting a second color light, a third sub-pixel 13 emitting a third color light, and a fourth sub-pixel 14 emitting a fourth color light, and the four sub-pixels may each include a circuit unit and a light-emitting device, the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line and the data signal line, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
[0026] In an exemplary embodiment, the first sub-pixel 11 may be a red sub-pixel (R) that emits red light, the second sub-pixel 12 may be a white sub-pixel (W) that emits white light, the third sub-pixel 13 may be a blue sub-pixel (B) that emits blue light, and the fourth sub-pixel 14 may be a green sub-pixel (G) that emits green light.
[0027] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon. In an exemplary embodiment, four sub-pixels may be arranged in parallel horizontally to form a RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a square, a diamond, or in parallel vertically, which is not limited in the present disclosure.
[0028] like Figure 2 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display substrate may include a driving circuit layer 30 disposed on the substrate 20 and a light emitting structure layer 40 disposed on a side of the driving circuit layer 30 away from the substrate 20 .
[0029] Specifically, the substrate 20 may be a flexible substrate or a rigid substrate. The driving circuit layer 30 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 40 of each sub-pixel may include a light-emitting device composed of a plurality of film layers, and the plurality of film layers may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
[0030] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer and the electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of all sub-pixels may be a common layer connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap. In some possible implementations, the display substrate may include other film layers, which are not limited in the embodiments of the present application.
[0031] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 3 As shown, the pixel driving circuit is a 3T1C structure, which may include three transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C and six signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a compensation signal line S, a first power line VDD and a second power line VSS).
[0032] The first electrode of the storage capacitor C is coupled to the control electrode of the second transistor T2, the second electrode of the storage capacitor C is coupled to the second electrode of the second transistor T2, and the storage capacitor C is used to store the potential of the control electrode of the second transistor T2. The control electrode of the first transistor T1 is coupled to the first scan signal line S1, the first electrode of the first transistor T1 is coupled to the data signal line D, the second electrode of the first transistor T1 is coupled to the control electrode of the second transistor T2, and the first transistor T1 is used to receive the data signal transmitted by the data signal line D under the control of the first scan signal line S1, so that the control electrode of the second transistor T2 receives the data signal. The control electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, the second electrode of the second transistor T2 is coupled to the first electrode of the light-emitting device, and the second transistor T2 is used to generate a corresponding current at the second electrode under the control of the data signal received by its control electrode. The control electrode of the third transistor T3 is coupled to the second scanning signal line S2, the first electrode of the third transistor T3 is coupled to the compensation signal line S, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.
[0033] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode), the first electrode of the OLED is coupled to the second electrode of the second transistor T2, the second electrode of the OLED is coupled to the second power line VSS, and the OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.
[0034] In an exemplary embodiment, the signal of the first power line VDD continuously provides a high level signal, and the signal of the second power line VSS is a low level signal. The first transistor T1 to the third transistor T3 can be a P-type transistor, or can be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.
[0035] In the related art, for a plurality of sub-pixels of a pixel unit 10, the VDD signal line of each sub-pixel uses the same data line, so the DC signal provided is the same, resulting in high power consumption for displaying different pictures.
[0036] For this purpose, refer to Figure 4 and Fig. 9As shown, an embodiment of the present application provides a display substrate, which includes a plurality of pixel units 10 arranged in an array, each pixel unit 10 includes a plurality of sub-pixels, and the pixel unit 10 includes a pixel circuit, the pixel circuit includes a plurality of independent voltage-dividing power lines 50, and the voltage-dividing power lines 50 correspond to the sub-pixels one by one; the sub-pixels include a substrate and a driving circuit layer 30 arranged on the substrate, the driving circuit layer 30 includes a driving transistor T2, and the first electrode of the driving transistor T2 is electrically connected to the corresponding voltage-dividing power line 50.
[0037] Specifically, in the embodiment of the present application, a pixel unit 10 includes a first sub-pixel 11, a second sub-pixel 12, a third sub-pixel 13, and a fourth sub-pixel 14 arranged along a first direction X. At the same time, the pixel circuit includes a first voltage dividing line 51, a second voltage dividing line 52, a third voltage dividing line 53, and a fourth voltage dividing line 54 extending along the first direction X. Among them, the first voltage dividing line 51 corresponds to the first sub-pixel 11, the second voltage dividing line 52 corresponds to the second sub-pixel 12, the third voltage dividing line 53 corresponds to the third sub-pixel 13, and the fourth voltage dividing line 54 corresponds to the fourth sub-pixel 14, that is, the first electrode of the driving transistor T2 of the first sub-pixel 11 is connected to the first voltage dividing line 51, the first electrode of the driving transistor T2 of the second sub-pixel 12 is connected to the second voltage dividing line 52, the first electrode of the driving transistor T2 of the third sub-pixel 13 is connected to the third voltage dividing line 53, and the first electrode of the driving transistor T2 of the fourth sub-pixel 14 is connected to the fourth voltage dividing line 54. It should be noted that the correspondence between the sub-pixels and the voltage-dividing power lines 50 refers to the correspondence in connection relationship, not the correspondence in position.
[0038] In this way, the first electrode of the driving transistor T2 of each sub-pixel is electrically connected to the corresponding voltage-dividing power line 50, so that an electrical signal can be input to the driving transistor T2 of the sub-pixel through the corresponding voltage-dividing power line 50, so that different voltage-dividing signals can be derived to match the display requirements of different sub-pixels, thereby reducing the voltage drop loss and achieving a reduction in the power consumption of the display substrate.
[0039] Reference Figure 2 As shown, in the embodiment of the present application, the driving circuit layer 30 of the sub-pixel includes a first metal layer 31, a buffer layer 32, a semiconductor layer 33, a first insulating layer 34, a second metal layer 35, a second insulating layer 36 and a third metal layer 37 which are sequentially arranged on the substrate. Among them, a plurality of voltage-dividing power lines 50 are located in the first metal layer 31. That is to say, in the embodiment of the present application, the voltage-dividing power lines 50 are directly arranged on the substrate 20, so that the influence on the subsequent driving circuit layer 30 pattern is small, and the production of the mask process is reduced.
[0040] Reference Fig. 9As shown, in the embodiment of the present application, the driving circuit layer 30 of the sub-pixel further includes a switch transistor T1, a sensing transistor T3 and a storage capacitor C. Among them, the active layers of the driving transistor T2, the switch transistor T1 and the sensing transistor T3 are located in the semiconductor layer 33, the gates G of the driving transistor T2, the switch transistor T1 and the sensing transistor T3 are located in the second metal layer 35, and the first and second electrodes of the driving transistor T2, the switch transistor T1 and the sensing transistor T3 are located in the third metal layer 37. Therefore, the first electrode of the driving transistor T2 of the sub-pixel needs to be electrically connected to the corresponding voltage-dividing power line 50 through a via hole penetrating the second insulating layer 35, the first insulating layer 34 and the buffer layer 32.
[0041] At the same time, refer to Fig. 9 As shown, in the embodiment of the present application, the orthographic projections of the plurality of voltage-dividing power lines 50 on the substrate 10 are located between the orthographic projections of the gate G1 of the switching transistor T1 on the substrate 10 and the orthographic projections of the gate G2 of the sensing transistor T3 on the substrate 10. In this way, the layout of the voltage-dividing power lines 50 can be made more reasonable.
[0042] In the embodiment of the present application, the driving circuit layer 30 further includes a shielding layer, which is located on the first metal layer, and the orthographic projection of the active layer of the driving transistor T2 on the substrate 10 is located within the orthographic projection range of the shielding layer on the substrate.
[0043] Reference Fig. 9 As shown, in an embodiment of the present application, the pixel unit 10 includes a first sub-pixel 11, a second sub-pixel 12, a third sub-pixel 13 and a fourth sub-pixel 14 arranged along a first direction; the shielding layer is reused as the first electrode plate of the storage capacitor C, and the semiconductor layer 33 includes a second electrode plate formed in each sub-pixel; the orthographic projection of the second electrode plate on the substrate 10 is located within the orthographic projection range of the first electrode plate on the substrate 10; the area of the second electrode plate in the first sub-pixel 11 is greater than the area of the second electrode plate in the second sub-pixel 12, the third sub-pixel 13 and the fourth sub-pixel 14.
[0044] The first sub-pixel 11 may be a green sub-pixel (G) emitting green light, the second sub-pixel 12 may be a blue sub-pixel (B) emitting blue light, the third sub-pixel 13 may be a red sub-pixel (R) emitting red light, and the fourth sub-pixel 14 may be a white sub-pixel (W) emitting white light. Furthermore, the area of the second electrode plate in the first sub-pixel 11 is larger than the areas of the second electrode plates in the second sub-pixel 12, the third sub-pixel 13, and the fourth sub-pixel 14, so that the larger driving current required to drive the light-emitting diode corresponding to the green sub-pixel (i.e., the first sub-pixel 11) can be satisfied.
[0045] Reference Figure 4As shown, in the embodiment of the present application, the voltage-dividing power line 50 extends along the first direction X. And in the multiple pixel units 10 arranged along the first direction X, the voltage-dividing power lines 50 of each pixel unit 10 are connected to each other. That is, in the multiple pixel units 10 along the first direction X, the voltage-dividing power line 50 is a complete and continuous signal line, which can better ensure the transmission of the signal on the voltage-dividing power line 50.
[0046] In addition, refer to Fig. 9 As shown, the display substrate further includes a plurality of total voltage power lines 60, which extend along the second direction Y, and the types of the total voltage power lines 60 correspond one to one with the types of the voltage-dividing power lines 50. For example, when the voltage-dividing power lines 50 include the first voltage-dividing line 51, the second voltage-dividing line 52, the third voltage-dividing line 53 and the fourth voltage-dividing line 54, the total voltage power lines 60 also include the first total voltage line 61, the second total voltage line 62, the third total voltage line 63 and the fourth total voltage line 64; the first total voltage line 61 is connected to all the first voltage-dividing lines 51, the second total voltage line 62 is connected to all the second voltage-dividing lines 52, the third total voltage line 63 is connected to all the third voltage-dividing lines 53, and the fourth total voltage line 64 is connected to all the fourth voltage-dividing lines 54; thus, the total voltage power lines 60 can be used to transmit signals to the corresponding voltage-dividing power lines 50, and then transmit the signals to the corresponding sub-pixels.
[0047] In the embodiment of the present application, the sub-pixel further includes a light emitting structure layer 40 located on the side of the driving circuit layer 30 away from the substrate; the second electrode of the driving transistor T2 is electrically connected to the anode in the light emitting structure layer 40 .
[0048] Figure 5 A flow chart showing a method for preparing a display substrate is shown. Figure 5 As shown, the embodiment of the present application discloses a method for preparing a display substrate, the preparation method comprising: Step 101: Provide a substrate 20.
[0049] Specifically, the substrate 20 may be a rigid substrate or a flexible substrate.
[0050] Step 102: Form a first metal layer 31 on one side of the substrate.
[0051] Specifically, forming the first metal layer 31 may include: depositing a first metal film on the substrate 20, and patterning the first metal film through a patterning process to form a pattern of the first metal layer 31 disposed on the substrate, such as Figure 6 , which is a schematic plan view of the first metal layer 31 .
[0052] Among them, patterning the first metal film through a patterning process may include: coating a layer of photoresist on the first metal film, forming a photoresist pattern through masking, exposure and development, forming an unexposed area in the pattern area of the first metal layer 31, retaining the photoresist, forming an exposed area in the area outside the first metal layer pattern 31, without photoresist, etching the first metal film in the exposed area using an etching process, and finally stripping off the remaining photoresist to form a pattern of the first metal layer 31.
[0053] In the embodiment of the present application, the pattern of the first metal layer 31 at least includes a plurality of voltage-dividing power lines 50 extending along the first direction X and a first electrode plate formed in the storage capacitor C of each sub-pixel. The first electrode plate can also be reused as a shielding layer.
[0054] The first metal layer 31 thin film can be formed by a sputtering process. In an exemplary embodiment, the material of the first metal layer 31 can be molybdenum oxide MoO x Molybdenum oxide is black in color, has stable properties, and is easily available. The material of the shading film can also be replaced by other materials as long as the shading film is opaque.
[0055] Step 103 : forming a buffer layer 32 on a side of the first metal layer 31 facing away from the substrate 10 .
[0056] Specifically, the material of the buffer layer 32 may be silicon nitride or silicon oxide.
[0057] Step 104 : forming a semiconductor layer 33 , a first insulating layer 34 , a second metal layer 35 , a second insulating layer 36 , and a third metal layer 37 of a driving circuit layer 30 on a side of the buffer layer 32 facing away from the substrate 10 .
[0058] Specifically, the step of forming the semiconductor layer 33 may include: forming a semiconductor film on the buffer layer 32, patterning the semiconductor film through a patterning process to form a semiconductor layer 33 pattern, the semiconductor layer 33 pattern at least includes an active layer of a driving transistor T2, a switching transistor T1 and a sensing transistor T3 formed in each sub-pixel and a second plate of a storage capacitor, such as Figure 7 shown.
[0059] The semiconductor layer 33 may be made of metal oxides, such as oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, etc. The semiconductor layer 33 may be a single layer, a double layer, or a multilayer.
[0060] The step of forming the second metal layer 35 may include: depositing the first insulating layer 34 and the second metal film on the semiconductor layer 33 in sequence, patterning the second metal film by a patterning process to form a second metal layer 35 pattern, wherein the second metal layer 35 pattern includes at least a gate electrode of the driving transistor T2, the switching transistor T1 and the sensing transistor T3 formed in each sub-pixel, such as Figure 8 shown.
[0061] The step of forming the third metal layer 37 may include: depositing a second insulating layer 36 and a third metal film on the second metal layer 35 in sequence, patterning the third metal film by a patterning process to form a pattern of the third metal layer 37, wherein the pattern of the third metal layer 37 includes at least a first electrode and a second electrode of a driving transistor T2, a switching transistor T1, and a sensing transistor T3 formed in each sub-pixel, such as Fig. 9 shown.
[0062] A via hole is provided on the second insulating layer 36 at a position corresponding to each voltage-dividing power line 50, and the via hole exposes part of the voltage-dividing power line 50. The first electrode of the driving transistor T2 of each sub-pixel is electrically connected to the corresponding voltage-dividing power line 50 through the via hole. The orthographic projection of the plurality of voltage-dividing power lines 50 on the substrate 10 is located between the orthographic projection of the gate G1 of the switching transistor T1 on the substrate 10 and the orthographic projection of the gate G2 of the sensing transistor T3 on the substrate 10.
[0063] In addition, the third metal layer 37 may further include a total voltage power line 60 , which is electrically connected to the corresponding divided voltage power line 50 through a via hole penetrating the second insulating layer 36 , the first insulating layer 34 and the buffer layer 32 .
[0064] In the display substrate prepared by the preparation method provided in the embodiment of the present application, the first electrode of the driving transistor T2 of each sub-pixel is electrically connected to the corresponding voltage-dividing power line 50, so that an electrical signal can be input to the driving transistor T2 of the sub-pixel through the corresponding voltage-dividing power line 50, so that different voltage-dividing signals can be induced to match the display requirements of different sub-pixels, thereby reducing the voltage drop loss and achieving a reduction in the power consumption of the display substrate.
[0065] Based on the same inventive concept, an embodiment of the present application discloses a display device, comprising any display substrate as described above in the embodiment of the present application.
[0066] Specifically, the display device may include a computer monitor, a television, a billboard, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a laptop computer, a digital camera, a camcorder, a viewfinder, a vehicle, a large-area wall, a theater screen, or a stadium sign, etc.
[0067] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0068] It should also be noted that, in this article, the orientation or position relationship indicated by the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. Without more restrictions, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or terminal device comprising the element.
[0069] The technical solution provided by the present application is described in detail above. The principle and implementation method of the present application are described in this article using specific examples. The description of the above embodiments is only used to help understand the present application, and the content of this specification should not be understood as limiting the present application. At the same time, for those of ordinary skill in the art, according to the present application, there will be different forms of changes in the specific implementation methods and application scopes. It is not necessary and impossible to list all the implementation methods here, and the obvious changes or modifications derived therefrom are still within the scope of protection of the present application.
Claims
1. A display substrate, characterized in that: include: A plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixels; The pixel unit includes a pixel circuit, and the pixel circuit includes a plurality of voltage-dividing power supply lines that are independent of each other, and the voltage-dividing power supply lines correspond to the sub-pixels one by one; The sub-pixel includes a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer includes a driving transistor, and a first electrode of the driving transistor is electrically connected to the corresponding divided voltage power line.
2. The display substrate according to claim 1, characterized in that: The driving circuit layer includes a first metal layer, a buffer layer, a semiconductor layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer which are sequentially arranged on the substrate; A plurality of divided voltage power lines are located on the first metal layer.
3. The display substrate according to claim 2, characterized in that: The driving circuit layer of the sub-pixel includes a switching transistor and a sensing transistor, the active layers of the driving transistor, the switching transistor and the sensing transistor are located in the semiconductor layer, the gates of the driving transistor, the switching transistor and the sensing transistor are located in the second metal layer, and the first and second electrodes of the driving transistor, the switching transistor and the sensing transistor are located in the third metal layer.
4. The display substrate according to claim 3, characterized in that: The first electrode of the driving transistor of the sub-pixel is electrically connected to the corresponding voltage-dividing power line through a via hole penetrating the second insulating layer, the first insulating layer and the buffer layer.
5. The display substrate according to claim 3, characterized in that: The orthographic projections of the plurality of divided voltage power lines on the substrate are located between the orthographic projections of the gate of the switch transistor on the substrate and the orthographic projections of the gate of the sensing transistor on the substrate.
6. The display substrate according to claim 3, characterized in that: The driving circuit layer further includes a shielding layer, which is located on the first metal layer. The orthographic projection of the active layer of the driving transistor on the substrate is located within the orthographic projection range of the shielding layer on the substrate.
7. The display substrate according to claim 6, characterized in that: The pixel unit includes a first sub-pixel, a second sub-pixel, a third pixel and a fourth sub-pixel arranged along a first direction; the shielding layer is reused as a first plate of a capacitor, and the semiconductor layer includes a second plate formed on each sub-pixel; The orthographic projection of the second electrode plate on the substrate is within the orthographic projection range of the first electrode plate on the substrate; An area of the second electrode plate in the first sub-pixel is greater than an area of the second electrode plate in the second sub-pixel, the third sub-pixel, and the fourth sub-pixel.
8. The display substrate according to claim 1, characterized in that: The voltage-dividing power line extends along a first direction; The voltage-dividing power lines of the plurality of pixel units arranged along the first direction are connected to each other.
9. The display substrate according to claim 8, characterized in that: The display substrate further comprises a plurality of main voltage power lines, and the main voltage power lines extend along the second direction; The total voltage power line is connected to each corresponding divided voltage power line in the second direction; The first direction is perpendicular to the second direction.
10. The display substrate according to claim 1, characterized in that: The pixel unit includes a first sub-pixel, a second sub-pixel, a third pixel and a fourth sub-pixel arranged along a first direction; The pixel circuit comprises a first voltage division line, a second voltage division line, a third voltage division line and a fourth voltage division line extending along the first direction; The first electrode of the driving transistor of the first sub-pixel is connected to the first voltage dividing line, the first electrode of the driving transistor of the second sub-pixel is connected to the second voltage dividing line, the first electrode of the driving transistor of the third sub-pixel is connected to the third voltage dividing line, and the first electrode of the driving transistor of the fourth sub-pixel is connected to the fourth voltage dividing line.
11. The display substrate according to any one of claims 1 to 10, characterized in that: The sub-pixel further includes a light emitting structure layer located on a side of the driving circuit layer away from the substrate; The second electrode of the driving transistor is electrically connected to the anode in the light emitting structure layer.
12. A display device, characterized in that: Comprising the display substrate as described in any one of claims 1-11.
13. A method for preparing a display substrate, wherein the display substrate comprises a plurality of pixel units arranged in an array, each of the pixel units comprises a plurality of sub-pixels, characterized in that: The preparation method comprises: providing a substrate; forming a first metal layer on one side of the substrate, the first metal layer comprising a plurality of voltage-dividing power lines extending along a first direction; forming a buffer layer on a side of the first metal layer facing away from the substrate; Forming a semiconductor layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer of a driving circuit layer in sequence on a side of the buffer layer away from the substrate; Wherein, the first electrode of the driving transistor in the driving circuit layer of the sub-pixel is electrically connected to the corresponding voltage-dividing power line.