Light-emitting display device

Abstract

One aspect of the present disclosure relates to providing a light-emitting display device in which some pixels that output light can transmit external light, and includes a substrate configured to be divided into a transmission region that transmits light and a non-transmission region that blocks light, a first color pixel, a second color pixel, and a third color pixel. A first color pixel configured to be disposed in the non-transmissive area and including a first pixel driving circuit and a first light emitting device, a second color pixel configured to be disposed in the non-transmissive area and including a second pixel driving circuit and a second light emitting device, and a transparent pixel configured to be disposed in the non-transmissive area and including a second pixel driving circuit and a second light emitting device, the transparent pixel is configured to be disposed in the transmissive region and includes only a transparent light emitting device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0132530, filed on October 5, 2023, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light-emitting display device. Background Art

[0004] The light-emitting display device is installed on or set in an electronic product to display an image, and the electronic product is such as a television, a monitor, a notebook computer, a smart phone, a tablet computer, an electronic tablet, a wearable device, a watch phone, a portable information device, a navigation device, or a vehicle control display device.

[0005] In order to provide various functions, a transparent light emitting display device has recently been used.

[0006] In order to display images, pixels should be arranged in a transparent light-emitting display device.

[0007] In this case, it is difficult for light to pass through the pixel. Therefore, the improvement of the transparency of the light-emitting display device is limited due to the area of ​​the pixel.

[0008] The above background is a part of the present disclosure used for designing the present disclosure, or is technical information acquired through the process of designing the present disclosure, but may not be considered as known technology disclosed to the general public before the disclosure of the present disclosure. Summary of the invention

[0009] Accordingly, the present disclosure is directed to a light emitting display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0010] An aspect of the present disclosure is directed to providing a light emitting display device in which some pixels that output light can transmit external light through the pixels.

[0011] Additional advantages and features of the present disclosure will be set forth in part in the following description, and in part will become apparent to those of ordinary skill in the art upon studying the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and obtained by the structures particularly pointed out in the written description and its claims and the accompanying drawings.

[0012] To achieve these and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, there is provided a light-emitting display device comprising a substrate configured to be divided into a transmissive region for transmitting light and a non-transmissive region for blocking light, a first color pixel configured to be disposed in the non-transmissive region and comprising a first pixel driving circuit and a first light-emitting device, a second color pixel configured to be disposed in the non-transmissive region and comprising a second pixel driving circuit and a second light-emitting device, and a transparent pixel configured to be disposed in the transmissive region and comprising only a transparent light-emitting device.

[0013] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0015] Figure 1 is an exemplary view showing a configuration of a light emitting display device according to an embodiment of the present disclosure;

[0016] Figure 2 is an exemplary view showing a structure of a pixel applied to a light-emitting display device according to an embodiment of the present disclosure;

[0017] Figure 3 is an exemplary view showing the structure of a control driver applied to a light emitting display device according to an embodiment of the present disclosure;

[0018] Figure 4 is an exemplary view showing a structure of a gate driver applied to a light emitting display device according to an embodiment of the present disclosure;

[0019] Figure 5 is an exemplary view showing a structure of a data driver applied to a light emitting display device according to an embodiment of the present disclosure;

[0020] Figure 6 It is shown that the arrangement Figure 1 A plan view of pixels in an area A;

[0021] Figure 7 It is shown Figure 6 A plan view of area B shown in FIG.

[0022] Figure 8is an exemplary view showing a light-emitting display panel applied to a light-emitting display device according to an embodiment of the present disclosure;

[0023] Fig. 9 is an exemplary view schematically showing a cross section of a pixel applied to a light-emitting display device according to an embodiment of the present disclosure;

[0024] Fig.10 is an exemplary view schematically showing a cross section of a transparent pixel applied to a light-emitting display device according to an embodiment of the present disclosure;

[0025] Fig.11 is shown along Figure 7 An exemplary view of a cross section taken along line CC';

[0026] Fig.12 is shown along Figure 7 An exemplary view of a cross section taken along line D-D' of FIG.

[0027] Fig.13 is shown along Figure 7 An exemplary view of a cross section taken along line EE'. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0029] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0030] The shapes, sizes, ratios, angles and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. The same reference numerals always represent the same elements. In the following description, when it is determined that the detailed description of the relevant known functions or configurations makes it unnecessary to understand the key points of the present disclosure, the detailed description will be omitted. When "comprising", "having" and "including" described in this specification are used, another part may be added unless "only" is used. Unless otherwise specified, terms in the singular may include plural forms.

[0031] When explaining an element, the element is interpreted as including an error or tolerance range although such error or tolerance range is not explicitly described.

[0032] When describing a positional relationship, for example, when the positional relationship between two parts is described as, for example, "on," "above," "below," and "beside," one or more other parts may be set between the two parts, unless more restrictive terms such as "just" or "directly" are used.

[0033] When describing a temporal relationship, for example, when a temporal order is described as, for example, "after," "subsequently," "next," and "before," discontinuities may be included unless more restrictive terms such as "just," "immediately," or "directly" are used.

[0034] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0035] When describing the elements of the present disclosure, the terms "first", "second", "A", "B", "(a)", "(b)", etc. may be used. These terms are intended to identify the corresponding elements with other elements, and the basis, order or number of the corresponding elements should not be limited by these terms. An element "connected", "coupled" or "adhered" to another element or layer expresses that the element or layer can be not only directly connected or adhered to the other element or layer, but also indirectly connected or adhered to the other element or layer, with one or more intermediate elements or layers "disposed" or "interposed" between the elements or layers, unless otherwise specified.

[0036] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" means a combination of all items proposed from two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0037] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be driven technically differently from each other, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1is an exemplary view showing a configuration of a light emitting display device according to an embodiment of the present disclosure, Figure 2 is an exemplary view showing a structure of a pixel applied to a light-emitting display device according to an embodiment of the present disclosure, Figure 3 is an exemplary view showing the structure of a control driver applied to a light emitting display device according to an embodiment of the present disclosure, Figure 4 is an exemplary view showing a structure of a gate driver applied to a light emitting display device according to an embodiment of the present disclosure, and Figure 5 is an exemplary view showing a structure of a data driver applied to a light emitting display device according to an embodiment of the present disclosure.

[0040] The light-emitting display device according to the embodiment of the present disclosure can be used as various electronic devices, such as televisions, monitors, etc.

[0041] like Figure 1 As shown, the light-emitting display device according to an embodiment of the present disclosure may include: a light-emitting display panel 100, which includes a display area DA for displaying an image and a non-display area NDA arranged outside the display area DA; a gate driver 200, which provides a gate signal GS to a plurality of gate lines GL1 to GLg arranged in the display area DA of the display panel 100; a data driver 300, which provides a data voltage Vdata to a plurality of data lines DL1 to DLd arranged in the display area DA of the display panel 100; an anode driver 800, which provides an anode voltage to a plurality of anode lines AL1 to ALv; a cathode driver 700, which provides a cathode voltage to a plurality of cathode lines CL1 to CLw; a control driver 400, which controls the driving of the gate driver 200, the data driver 300, the anode driver 800 and the cathode driver 700; and a power supply unit 500, which supplies power to the control driver 400, the gate driver 200, the data driver 300, the anode driver 800, the cathode driver 700 and the light-emitting display panel 100.

[0042] First, the light-emitting display panel 100 may include a display area DA and a non-display area NDA. Gate lines GL1 to GLg, data lines DL1 to DLd, anode lines AL1 to ALv, cathode lines CL1 to CLw, transparent pixels TP, and pixels P may be disposed in the display area DA. Therefore, an image may be displayed in the display area DA. Here, g, d, v, and w are natural numbers. The non-display area NDA may surround the outer periphery of the display area DA.

[0043] like Figure 2As shown, a pixel P included in the light-emitting display panel 100 may include a pixel driving circuit PDC including a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2, and a light-emitting device ED connected to the pixel driving circuit PDC.

[0044] A first terminal of the driving transistor Tdr may be connected to a first voltage supply line through which a first voltage EVDD is supplied, and a second terminal of the driving transistor Tdr may be connected to the light emitting device ED.

[0045] A first terminal of the switching transistor Tsw1 may be connected to the data line DL, a second terminal of the switching transistor Tsw1 may be connected to the gate of the driving transistor Tdr, and a gate of the switching transistor Tsw1 may be connected to the gate line GL.

[0046] The data voltage Vdata may be provided through the data line DL from the data driver 300. The gate signal GS may be provided through the gate line GL from the gate driver 200. The gate signal GS may include a gate pulse GP for turning on the switching transistor Tsw1 and a gate-off signal for turning off the switching transistor Tsw1.

[0047] The sensing transistor Tsw2 may be provided for measuring a threshold voltage or mobility of the driving transistor Tdr, or for providing a reference voltage Vref to the pixel driving circuit PDC. A first terminal of the sensing transistor Tsw2 may be connected to a second terminal of the driving transistor Tdr and the light emitting device ED, a second terminal of the sensing transistor Tsw2 may be connected to a sensing line SL through which the reference voltage Vref is provided, and a gate of the sensing transistor Tsw2 may be connected to a sensing control line SCL through which a sensing control signal SCS is provided.

[0048] The sensing line SL may be connected to the data driver 300, and may be connected to the power supply unit 500 through the data driver 300. For example, a reference voltage Vref provided from the power supply unit 500 may be provided to the pixel through the sensing line SL, a sensing signal transmitted from the pixel P may be converted into a digital sensing signal in the data driver 300, and the digital sensing signal may be transmitted to the control driver 400.

[0049] The sensing control line may be provided independently of the gate line GL, but the gate line GL may also be used as the sensing control line.

[0050] In the following, the following will describe Figure 2The illustrated gate line GL is connected to a pixel driving circuit of a gate of a switching transistor Tsw1 and a gate of a sensing transistor Tsw2 as an example of a pixel driving circuit PDC applied to a light emitting display device according to the present disclosure.

[0051] The light emitting device ED may include a first electrode supplied with a first voltage EVDD through a driving transistor Tdr, a second electrode connected to a second voltage supply line PLB through which a second voltage is supplied, and a light emitting layer disposed between the first electrode and the second electrode.

[0052] The structure of the pixel P applied to the present disclosure is not limited to Figure 2 Therefore, the structure of the pixel P can be changed into various shapes.

[0053] A unit pixel UP including at least two pixels P and one transparent pixel TP may be provided in the display area DA. White light may be emitted by the unit pixel UP. Hereinafter, for ease of description, a unit pixel UP including two pixels P and one transparent pixel TP will be used as an example to describe the light-emitting display device according to an embodiment of the present disclosure.

[0054] For example, two pixels P constituting a unit pixel UP may be a red pixel and a blue pixel, and a transparent pixel TP constituting a unit pixel UP may be a green pixel. The red pixel may output red light, the blue pixel may output blue light, and the green pixel may output green light.

[0055] Hereinafter, for convenience of description, a red pixel (or a blue pixel) is referred to as a first color pixel, a blue pixel (or a red pixel) is referred to as a second color pixel, and a green pixel is referred to as a transparent pixel TP.

[0056] In this case, each of the first color pixel and the second color pixel may be referred to by a reference numeral P. That is, each of the first color pixel P and the second color pixel P may be a pixel having a reference numeral P. Figure 2 Describe the structure of a pixel P.

[0057] The first color pixel P and the second color pixel P are opaque pixels that do not transmit light, and the transparent pixel TP may transmit light.

[0058] As described above, the transparent pixel TP may be a green pixel, but the light emitting display device according to the present disclosure is not limited thereto. Therefore, the transparent pixel TP may be any one of pixels outputting light of various colors except the green pixel.

[0059] For example, as the transparent pixel TP, a pixel that outputs light of a color that does not significantly affect the generation of white light can be used.

[0060] Transparent pixels TP only include Figure 2 The light emitting device ED in the element shown. Therefore, the transparent pixel TP does not include Figure 2 The pixel driving circuit PDC is shown.

[0061] The light emitting device ED provided in the transparent pixel TP may include a transparent anode formed of a transparent metal and a transparent cathode formed of a transparent metal.

[0062] The transparent anode may be connected to the anode line AL, and the transparent cathode may be connected to the cathode line CL.

[0063] The control driver 400 may realign the input image data Ri, Gi, and Bi transmitted from the external system 600 by using the timing synchronization signal TSS transmitted from the external system, and may generate a data control signal DCS to be provided to the data driver 300 and a gate control signal GCS to be provided to the gate driver 200 .

[0064] For this reason, Figure 3 As shown, the control driver 400 may include a data aligner 430, which realigns the input image data Ri, Gi and Bi to generate image data Dada corresponding to the first color pixel P and the second color pixel and anode data corresponding to the transparent pixel TP; a control signal generator 420, which generates a gate control signal GCS and a data control signal DCS by using a timing synchronization signal TSS; an input unit 410, which transmits the timing synchronization signal TSS transmitted from the external system 600 to the control signal generator 420, and transmits the input image data Ri, Gi and Bi transmitted from the external system 600 to the data aligner 430; and an output unit 440, which provides the image data Dada generated by the data aligner 430 and the data control signal DCS generated by the control signal generator 420 to the data driver 300, provides the gate control signal GCS generated by the control signal generator 420 to the gate driver 200, and provides the anode data ADada generated by the data aligner 430 and the anode control signal ACS generated by the control signal generator 420 to the anode driver 800.

[0065] The control signal generator 420 may generate a power control signal provided to the power supply unit 500 .

[0066] The control signal generator 420 may generate a cathode control signal CCS capable of controlling the cathode driver 700 to transmit it to the output unit 440 , and the output unit 440 may transmit the cathode control signal CCS to the cathode driver 700 .

[0067] The control signal generator 420 may generate an anode control signal ACS capable of controlling the anode driver 800 to transmit the anode control signal ACS to the output unit 440 , and the output unit 440 may transmit the anode control signal ACS to the anode driver 800 .

[0068] The control driver 400 may further include a storage unit for storing various information. The storage unit 450 may be included in Figure 3 The control driver 400 is shown in the figure, but can be separated from the control driver 400 and independently provided.

[0069] The external system 600 may perform a function of driving and controlling the driver 400 and the electronic device.

[0070] For example, when the electronic device is a television (TV), the external system 600 may receive various sound information, image information, and letter information through a communication network, and may transmit the received image information to the control driver 400. For example, the external system 600 may convert the image information into input image data Ri, Gi, and Bi, and transmit the input image data Ri, Gi, and Bi to the control driver 400.

[0071] The power supply unit 500 may generate various powers and supply the generated powers to the control driver 400 , the gate driver 200 , the data driver 300 , the cathode driver 700 , the anode driver 800 , and the light-emitting display panel 100 .

[0072] The gate driver 200 may be directly embedded in the non-display area NDA by using a gate in panel (GIP) type, or the gate driver 200 may be disposed in the display area DA where the light emitting device ED is disposed, or the gate driver 200 may be disposed on a chip on film installed in the non-display area NDA.

[0073] The gate driver 200 may provide gate pulses GP1 to GPg to the gate lines GL1 to GLg.

[0074] The switching transistor Tsw1 included in the pixel P may be turned on when a gate pulse GP generated by the gate driver 200 is supplied to the gate of the switching transistor Tsw1. When the switching transistor Tsw1 is turned on, the pixel P may be supplied with a data voltage Vdata supplied through the data line DL.

[0075] When the gate-off signal generated by the gate driver 200 is supplied to the switching transistor Tsw1, the switching transistor Tsw1 may be turned off. When the switching transistor Tsw1 is turned off, the data voltage may no longer be supplied to the pixel P.

[0076] The gate signal GS supplied to the gate line GL may include a gate pulse GP and a gate-off signal.

[0077] In order to provide gate pulses GP1 to GPg to the gate lines GL1 to GLg, as shown in FIG. Figure 4 As shown, the gate driver 200 may include stages ST1 to STg connected to the gate lines GL1 to GLg.

[0078] Each of the stages ST1 to STg may be connected to one gate line GL, but may also be connected to at least two gate lines GL.

[0079] In order to generate the gate pulses GP1 to GPg, the gate start signal VST and at least one gate clock GCLK generated by the control signal generator 420 may be transmitted to the gate driver 200. For example, the gate start signal VST and at least one gate clock GCLK may be included in the gate control signal GCS.

[0080] One of the stages ST1 to STg may be driven by the gate start signal VST to output a gate pulse GP to the gate line GL. The gate pulse GP may be generated by the gate clock GCLK.

[0081] At least one of the signals output from the stage ST outputting the gate pulse may be provided to another stage ST to drive the other stage ST. Therefore, the gate pulse may be output in the other stage ST.

[0082] For example, the stages ST may be driven sequentially to sequentially supply the gate pulses GP to the gate lines GL.

[0083] The data driver 300 may provide a data voltage Vdata to the data lines DL1 to DLd.

[0084] For this reason, Figure 5 As shown, the data driver 300 may include a shift register 310 that outputs a sampling signal; a latch 320 that latches image data Dada received from the control driver 400; a digital-to-analog converter 330 that converts the image data Dada transmitted from the latch 320 into a data voltage Vdata and outputs the data voltage Vdata; and an output buffer 340 that outputs the data voltage transmitted from the digital-to-analog converter 330 to the data line DL based on a source output enable signal SOE.

[0085] The shift register 310 may output a sampling signal by using the data control signal DCS received from the control signal generator 420. For example, the data control signal DCS transmitted to the shift register 310 may include a source start pulse SSP and a source shift clock signal SSC.

[0086] The latch 320 may latch the image data Dada sequentially received from the control driver 400 and then simultaneously output the image data Dada to the digital-to-analog converter 330 based on the sampling signal.

[0087] The digital-to-analog converter 330 may convert the image data Dada transferred from the latch 320 into a data voltage Vdata and output the data voltage Vdata.

[0088] The output buffer 340 may simultaneously output the data voltage Vdata transmitted from the digital-to-analog converter 330 to the data lines DL1 to DLd of the light-emitting display panel 100 based on the source output enable signal SOE transmitted from the control signal generator 420 .

[0089] To this end, the output buffer 340 may include a buffer 341 storing the data voltage Vdata transmitted from the digital-to-analog converter 330 and a switch 342 outputting the data voltage Vdata stored in the buffer 341 to the data line DL based on a source output enable signal SOE.

[0090] For example, when the switch 342 is turned on based on the source output enable signal SOE simultaneously supplied to the switch 342 , the data voltage Vdata stored in the buffer 341 may be supplied to the data lines DL1 to DLd through the switch 342 .

[0091] The data voltage Vdata supplied to the data lines DL1 to DLd may be supplied to the pixels P connected to the gate line GL to which the gate pulse GP is supplied.

[0092] The cathode driver 700 may be configured in a similar structure to the gate driver 200 .

[0093] For example, the cathode driver 700 may be directly embedded in the non-display area NDA, or may be disposed in the display area DA where the light emitting device ED is disposed, or may be disposed on a chip on film installed in the non-display area NDA.

[0094] When the cathode driver 700 is directly embedded in the non-display area NDA, the cathode driver 700 may be disposed in the non-display area NDA facing the non-display area NDA where the gate driver 200 is disposed, or may be disposed in the non-display area NDA where the gate driver 200 is disposed.

[0095] The cathode driver 700 may provide cathode voltages to the cathode lines CL1 to CLw.

[0096] When a cathode voltage generated in the cathode driver 700 is supplied to a transparent cathode disposed in the transparent pixel TP and an anode voltage generated in the anode driver 800 is supplied to a transparent anode disposed in the transparent pixel TP, light may be output from the transparent pixel TP.

[0097] In order to provide cathode voltages to the cathode lines CL1 to CLw, Figure 4 The cathode driver 700 is configured with a similar structure to the gate driver 200 shown.

[0098] For example, the cathode driver 700 may include cathode stages capable of sequentially outputting cathode voltages.

[0099] Each of the cathode stages may be connected to one cathode line CL, but may also be connected to at least two cathode lines CL.

[0100] In order to generate the cathode voltage, the cathode start signal VST and at least one cathode clock generated by the control signal generator 420 may be transmitted to the cathode driver 700. That is, the cathode start signal VST and the at least one cathode clock may be included in the cathode control signal CCS.

[0101] Any one of the cathode stages may be driven by a cathode start signal to output a cathode voltage to the cathode line CL. The cathode voltage may be generated by a cathode clock.

[0102] At least one of the signals output from the cathode stage outputting the cathode voltage may be provided to another cathode stage to drive the other cathode stage. Therefore, the cathode voltage may be output from the other cathode stage.

[0103] That is, the cathode stages may be sequentially driven to sequentially supply cathode voltages to the cathode lines CL.

[0104] However, the cathode driver 700 may include the power supply unit 500 and a power control unit that may generate a power control signal capable of controlling the power supply unit 500 .

[0105] For example, when a cathode voltage generator provided in the power supply unit 500 and generating a cathode voltage is connected to the cathode line CL through a cathode switch, the power control unit may sequentially turn on the cathode switches and may provide the cathode voltage to the cathode line CL connected to the turned-on cathode switch.

[0106] In this case, the power control unit may have Figure 4 The gate driver 200 shown in the figure may have a structure similar to that of the gate driver 200, or may have one of various structures capable of outputting a power control signal that can sequentially turn on the cathode switches.

[0107] Finally, the anode driver 800 may output anode voltages to the anode lines AL1 to ALv simultaneously.

[0108] In this case, the anode voltages simultaneously supplied to the anode lines AL1 to ALv may have different levels or the same level.

[0109] When the anode voltages simultaneously supplied to the anode lines AL1 to ALv have different levels, the anode driver 800 has a voltage level different from the reference voltage. Figure 5 The structure of the data driver 300 described above is the same as or similar to that of the data driver 300 .

[0110] For example, when the first anode voltage supplied to the first anode line AL1 is supplied to one transparent pixel TP, the control driver 400 may generate the first anode data ADada by using the input image data corresponding to the transparent pixel TP supplied with the first anode voltage. The anode driver 800 may generate the first anode voltage by using the first anode data ADada and then supply the first anode voltage to the first anode line AL1.

[0111] This operation may be similarly performed on the second to vth anode lines ALv.

[0112] Therefore, anode voltages simultaneously supplied to the anode lines AL1 to ALv may have different levels. Therefore, light having different brightness may be output from the transparent pixels TP that simultaneously emit light.

[0113] As another example, when the first anode voltage supplied to the first anode line AL1 is supplied to at least two transparent pixels TP, the control driver 400 may generate the first anode data ADada by using input image data corresponding to the transparent pixels TP supplied with the first anode voltage.

[0114] For example, the control driver 400 may generate the first anode data ADada by using an average value of input image data corresponding to the transparent pixels TP to which the first anode voltage is to be supplied.

[0115] The anode driver 800 may generate an anode voltage by using the first anode data ADada and then supply the first anode voltage to the first anode line AL1.

[0116] This operation may be similarly performed on the second to vth anode lines ALv.

[0117] Therefore, anode voltages simultaneously supplied to the anode lines AL1 to ALv may have different levels.

[0118] In this case, light having the same brightness may be output from the transparent pixels TP supplied with the first anode voltage through the first anode line AL1, and the brightness of light output from the transparent pixels TP connected to the first anode line AL1 may be different from the brightness of light output from the transparent pixels TP connected to the vth anode line ALv.

[0119] When the anode voltages simultaneously supplied to the anode lines AL1 to ALv have the same level, the anode driver 800 may simultaneously supply the same anode voltage to the anode lines AL1 to ALv according to the anode control signal ACS transmitted from the control driver 400 .

[0120] In this case, after the first anode voltage is simultaneously supplied to the anode lines AL1 to ALv, when the second anode voltage is simultaneously supplied to the anode lines AL1 to ALv, the second anode voltage may have the same level as the first anode voltage or have a different level from the first anode voltage.

[0121] For example, the control driver 400 may transmit only the anode control signal ACS related to the timing at which the anode voltage is to be output to the anode driver 800. The anode driver 800 may provide a predetermined first anode voltage to the anode lines AL1 to ALv according to the anode control signal ACS.

[0122] In this case, the anode driver 800 may include an anode switch. The anode switch may be provided in the power supply unit 500, and in particular, may be provided between an anode voltage generator generating the first anode voltage and the anode lines AL1 to ALv.

[0123] The anode switches may be simultaneously turned on according to the anode control signal ACS so that the first anode voltage transmitted from the anode voltage generator may be provided to the anode lines AL1 to ALv.

[0124] Therefore, light having brightness corresponding to the first anode voltage may be output from the transparent pixels TP that simultaneously emit light.

[0125] After the first anode voltage is simultaneously supplied, when the second anode voltage is simultaneously supplied to the anode lines AL1 to ALv, the second anode voltage may have the same level as the first anode voltage.

[0126] Therefore, light having brightness corresponding to the first anode voltage may be output from the transparent pixels TP that simultaneously emit light by the second anode voltage.

[0127] In this case, the first anode voltage may be set through various tests and simulations in the manufacturing process of the light-emitting display device. For example, in the light-emitting display device, only the first anode voltage set in the manufacturing process of the light-emitting display device may be used.

[0128] However, for each frame period, the first anode voltage may be set in the control driver 400. The frame period may represent a period for displaying one image. Therefore, in the following description, the first frame period may represent a period for displaying the first image, and the second frame period may represent a period for displaying the second image.

[0129] In addition, in the following description, one frame period represents the actual length of each frame period. For example, one frame period may be 1 ms (milliseconds), 1 us (microseconds), 1 ns (nanoseconds), etc.

[0130] To provide additional description, the control driver 400 may analyze the input image data corresponding to the first frame period to set the first anode voltage to be supplied to the anode lines AL1 to ALv in the first frame period. In addition, the control driver 400 may analyze the input image data corresponding to the second frame period to set the second anode voltage to be supplied to the anode lines AL1 to ALv in the second frame period. In addition, the control driver 400 may analyze the input image data corresponding to the k-th frame period (k is a natural number) to set the k-th anode voltage to be supplied to the anode lines AL1 to ALv in the k-th frame period.

[0131] For example, the control driver 400 may transmit first anode data ADada corresponding to a first anode voltage set in the first frame period to the anode driver 800. The anode driver 800 may generate the first anode voltage by using the first anode data ADada and continuously supply the first anode voltage to the anode lines AL1 to ALv during the first frame period.

[0132] In this case, the first anode voltage may be supplied to the anode lines AL1 to ALv at least twice during the first frame period.

[0133] The control driver 400 may transmit second anode data ADada corresponding to the second anode voltage set in the second frame period to the anode driver 800. The anode driver 800 may generate the second anode voltage by using the second anode data ADada and continuously supply the second anode voltage to the anode lines AL1 to ALv during the second frame period.

[0134] In this case, the second anode voltage may be supplied to the anode lines AL1 to ALv at least twice during the second frame period.

[0135] In this case, the anode driver 800 may have the same Figure 5However, since the same anode voltage is supplied to all anode lines AL1 to ALv, the anode driver 800 may include only one buffer 341 and one switch 342.

[0136] After the first anode voltage is simultaneously supplied, when the second anode voltage is simultaneously supplied to the anode lines AL1 to ALv, the second anode voltage may have a different level from the first anode voltage.

[0137] In this case, for example, the control driver 400 can set the first anode voltage by using the average value of the input image data corresponding to the transparent pixels TP to which the first anode voltage is to be provided, and can set the second anode voltage by using the average value of the input image data corresponding to the transparent pixels TP to which the second anode voltage is to be provided.

[0138] For example, the control driver 400 may set a first anode voltage and a second anode voltage having different levels output to the anode lines AL1 to ALv during the first frame period. The control driver 400 may generate first anode data ADada corresponding to the first anode voltage and second anode data ADada corresponding to the second anode voltage to transmit them to the anode driver 800.

[0139] The anode driver 800 may generate a first anode voltage by using the first anode data ADada, and supply the first anode voltage to the anode lines AL1 to ALv during a portion of the first frame period. In addition, after supplying the first anode voltage, the anode driver 800 may generate a second anode voltage by using the second anode data ADada, and supply the second anode voltage to the anode lines AL1 to ALv during another portion of the first frame period.

[0140] In this case, the anode driver 800 may have the same Figure 5 However, since the same anode voltage is supplied to all anode lines AL1 to ALv, the anode driver 800 may include only one buffer 341 and one switch 342.

[0141] As described above, the anode driver 800 may generate an anode voltage and simultaneously supply the anode voltage to the anode lines AL1 to ALv. In this case, the anode voltages supplied to the anode lines AL1 to ALv may be the same or different. In addition, when the second anode voltage is supplied after the first anode voltage is supplied to the anode lines AL1 to ALv, the second anode voltage may be the same or different from the first anode voltage.

[0142] In the following, reference will be made to Figures 6 to 8The specific structure of the light-emitting display panel 100 is described below.

[0143] Figure 6 It is shown that the arrangement Figure 1 In the following description, the pixel in the region A is omitted or briefly described. Figures 1 to 5 The details described are the same or similar details.

[0144] The light emitting display panel applied to the light emitting display device according to the embodiment of the present disclosure may include a transmission area TA through which light is transmitted and a non-transmission area NTA that blocks the light from passing therethrough.

[0145] For example, the display area DA of the light-emitting display panel 100 may include a transmission area TA (or referred to as a transparent area) and a non-transmission area NTA.

[0146] The transmission area TA may be an area that allows most of light incident from the outside to pass through the transmission area TA. In one embodiment, the non-transmission area NTA has lower transmittance to external light than the transmission area TA.

[0147] In particular, in the light-emitting display device according to the present disclosure, the transmission area TA may include a light-emitting area EA in which transparent pixels TP are disposed and a non-light-emitting area NEA in which no light-emitting device is disposed, such as Figure 6 shown.

[0148] For example, the transparent pixel TP may be provided with a light emitting device ED including a transparent anode and a transparent cathode. Therefore, light may be output from the transparent pixel TP, and thus, the transparent pixel TP may become the light emitting area EA. In addition, since light may be transmitted through the transparent anode and the transparent cathode in the transparent pixel TP, the transparent pixel TP may become the transmission area TA.

[0149] To provide additional description, since the transparent pixel TP is not provided with the pixel driving circuit PDC formed of a material that may block light but is provided with a transparent anode and a transparent cathode, light may be transmitted in the transparent pixel TP.

[0150] In addition, since the non-emission area NEA is not provided with the light emitting device ED, the non-emission area NEA is not provided with a metal that can block light. Therefore, since light can be transmitted in the non-emission area NEA, the non-emission area NEA can become a transmission area TA.

[0151] The non-transmission area NTA may be an area that does not transmit most of the light incident from the outside. In addition, the non-transmission area NTA may refer to an area where the first color pixel P1 and the second color pixel P2 are disposed. As described above, Figure 6The illustrated first color pixel P1 , second color pixel P2 , and transparent pixel TP may constitute a unit pixel UP.

[0152] That is, the first color pixel P1 and the second color pixel P2 may be the emission area EA which is capable of outputting light, and may be the non-transmission area NTA which does not transmit light.

[0153] To provide additional description, the pixel P may be provided with a light emitting device ED and a pixel driving circuit PDC, as shown in FIG. Figure 2 In this case, the pixel driving circuit PDC may overlap with the light emitting device ED, and the transistor constituting the pixel driving circuit PDC may include an opaque electrode. Therefore, the pixel P may become a non-transmitting area NTA.

[0154] For example, Figure 6 Each of the first color pixel P1 and the second color pixel P2 shown may be an anode constituting a pixel P, and Figure 6 The transparent pixel shown may be a transparent anode constituting the transparent pixel TP. In this case, the non-luminous area NEA is not provided with an anode and a transparent anode.

[0155] Therefore, light cannot be transmitted through the anode electrode of the first color pixel P1 and the anode electrode of the second color pixel P2 , but light may be transmitted through the transparent anode electrode of the transparent pixel TP, and light may be transmitted through the non-emission area NEA.

[0156] Therefore, the first color pixel P1 and the second color pixel P2 may become the non-transmission area NTA, and the transparent pixel TP and the non-emission area NEA may become the transmission area TA.

[0157] Figure 7 It is shown Figure 6 A plan view of area B is shown in FIG.

[0158] First, as described above, in the light emitting display device according to the present disclosure, the unit pixel UP may include two pixels P and one transparent pixel TP.

[0159] In this case, the two pixels P may be a first color pixel P1 and a second color pixel P2.

[0160] The first color pixel P1 may include a first pixel driving circuit PDC1 and a first light-emitting device ED1 electrically connected to the first pixel driving circuit PDC1, and the second color pixel P2 may include a second pixel driving circuit PDC2 and a second light-emitting device ED2 electrically connected to the second pixel driving circuit PDC2. In the following description, when there is no need to distinguish between the first color pixel P1 and the second color pixel P2, each of the first color pixel P1 and the second color pixel P2 may be referred to as a pixel P. In addition, when there is no need to distinguish between the first light-emitting device ED1 and the second light-emitting device ED2, each of the first light-emitting device ED1 and the second light-emitting device ED2 may be referred to as a light-emitting device ED.

[0161] For example, each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 may have Figure 2 The pixel driving circuit PDC shown has the same structure.

[0162] For example, each of the first light emitting device ED1 and the second light emitting device ED2 may have a Figure 2 The light emitting device ED described has the same structure.

[0163] The first light emitting device ED1 may include a first anode AN1, a common cathode CA, and a first light emitting layer disposed between the first anode AN1 and the common cathode CA.

[0164] The second light emitting device ED2 may include a second anode AN2, a common cathode CA, and a second light emitting layer disposed between the second anode AN2 and the common cathode CA.

[0165] The common cathode CA may be commonly disposed in the first color pixel P1 and the second color pixel P2. For example, the common cathode CA may constitute the first light emitting device ED1 and may also constitute the second light emitting device ED2.

[0166] In the following description, when there is no need to distinguish the first anode AN1 from the second anode AN2 , each of the first anode AN1 and the second anode AN2 may be referred to as an anode AN.

[0167] As reference Figure 6 As described above, each of the first color pixel P1 and the second color pixel P2 may be the non-transmission area NTA.

[0168] The transparent pixel TP may include a transparent light emitting device TED without being electrically connected to a pixel driving circuit, and may be a transparent area TA.

[0169] The transparent light emitting device TED may have the same structure as the first light emitting device ED1 and the second light emitting device ED2.

[0170] In this case, each of the first light emitting device ED1 and the second light emitting device ED2 includes an anode and a cathode, one of the anode and the cathode may be an opaque metal, and the other may be a transparent metal.

[0171] For example, in the light-emitting display device according to the embodiment of the present disclosure, when light is output toward the upper end of the cathode, the first anode AN1 constituting the first light-emitting device ED1 may be an opaque metal, and the cathode CA constituting the first light-emitting device ED1 may be a transparent metal. In addition, the second anode AN2 constituting the second light-emitting device ED2 may be an opaque metal, and the cathode CA constituting the second light-emitting device ED2 may be a transparent metal. That is, the cathode CA included in the first light-emitting device ED1 and the second light-emitting device ED2 may be a transparent metal.

[0172] In this case, since light is output toward the upper end of the cathode, the pixel driving circuit PDC provided at the lower ends of the cathode and the anode may be provided to overlap with the anode.

[0173] For example, Figure 7 As shown, the first pixel driving circuit PDC1 may be disposed to overlap the first anode AN1, and the second pixel driving circuit PDC2 may be disposed to overlap the second anode AN2.

[0174] However, the transparent light emitting device TED may include a transparent anode TAN, a transparent cathode TCA and a light emitting layer. The transparent anode TAN and the transparent cathode TCA may be transparent metals. Therefore, light may be transmitted through the transparent light emitting device TED.

[0175] In this case, if Figure 7 As shown, the common cathode CA and the transparent cathode TCA are physically separated from each other and are not electrically connected. Therefore, the first light emitting device ED1 and the second light emitting device ED2 may be adjacent to each other, and the transparent light emitting device TED may be spaced apart from the first light emitting device ED1 and the second light emitting device ED2.

[0176] The size of the first anode AN1 and the size of the second anode AN2 may be the same, and the size of the transparent anode TAN may be the same as the size of the first anode AN1 or the size of the second anode AN2.

[0177] However, the size of the transparent anode TAN may be larger than each of the size of the first anode AN1 and the size of the second anode AN2, and smaller than the combined size of the first anode AN1 and the second anode AN2. Figure 7As shown, the size of the transparent anode TAN may be greater than or equal to the combined size of the first anode AN1 and the second anode AN2. To provide additional description, the size of the transparent anode TAN may be set to various sizes in consideration of the emission efficiency of the transparent pixel TP, the transmittance of the transparent pixel TP, and the transmittance of the light-emitting display panel 100.

[0178] The transparent anode TAN may be connected to an anode line AL disposed in parallel with a data line DL disposed on a substrate constituting the light-emitting display panel 100, and the transparent cathode TCA may be connected to a cathode line CL disposed on the substrate.

[0179] Since the transparent pixel TP only includes a transparent light emitting device ED, the transparent light emitting device TED is not connected to the pixel driving circuit PDC.

[0180] However, since the transparent anode TAN is connected to the anode line AL and the transparent cathode TCA is connected to the cathode line CL, the transparent anode TNA may be supplied with the anode voltage AVdata through the anode line AL and the transparent cathode TCA may be supplied with the cathode voltage CV through the cathode line CL.

[0181] Thus, light may be output from the transparent light emitting device TED.

[0182] The cathode voltage CV may be the second voltage EVSS supplied to the cathode of the light emitting device ED, but may be a voltage different from the second voltage EVSS. Hereinafter, the light emitting display apparatus according to the present disclosure will be described using an example in which the cathode voltage CV is the second voltage EVSS.

[0183] In this case, the substrate may be provided with a common cathode line connected to the common cathode CA. The common cathode line may be a reference Figure 2 Therefore, in the following description, reference numeral PLB may be assigned to the common cathode line.

[0184] The common cathode line PLB may be connected to a common cathode CA disposed along the common cathode line PLB. The common cathode line PLB may extend in a direction parallel to the anode line AL, for example, along the Y-axis direction. Figure 7 shown.

[0185] In this case, the cathode lines CL may extend in a direction different from the common cathode lines PLB and the anode lines AL, and in particular, extend in a direction perpendicular to the common cathode lines PLB and the anode lines AL.

[0186] For example, the cathode line CL may extend along the X-axis direction. Figure 1 and Figure 7 shown.

[0187] In the following description, the first direction may be the X-axis direction, and the second direction may be the Y-axis direction. To provide additional description, the common cathode lines PLB and the anode lines AL may extend in the second direction (e.g., the Y-axis direction), and the cathode lines CL may extend in a first direction (e.g., the X-axis direction) different from the directions of the common cathode lines PLB and the anode lines AL.

[0188] The substrate constituting the light emitting display panel 100 may be provided with data lines DL for supplying data voltages to the first pixel driving circuit PDC1 , and the substrate may be provided with gate lines GL for supplying gate signals GS to the first pixel driving circuit PDC1 .

[0189] For example, as referenced Figure 2 As described above, the data line DL and the gate line GL may be connected to the pixel driving circuit PDC. Figure 2 The pixel driving circuit PDC1 has the same structure as shown, so the light-emitting display panel 100 may be provided with data lines DL and gate lines GL connected to the first pixel driving circuit PDC1.

[0190] The common cathode lines PLB may be disposed in parallel with the data lines DL, and the cathode lines CL may be disposed in parallel with the gate lines GL.

[0191] For example, cathode lines CL and gate lines GL may be disposed in a first direction (eg, X-axis direction), and common cathode lines PLB and data lines DL may be disposed in a second direction (eg, Y-axis direction) different from the first direction.

[0192] In this case, the first color pixels P1, the second color pixels P2, and the transparent pixels TP may be arranged in a row along the data line DL.

[0193] Because the anode line AL connected to the transparent anode TAN may be disposed in parallel with the data line DL along the second direction, the first color pixel P1 , the second color pixel P2 , and the transparent pixel TP may be disposed in a row along the anode line AL.

[0194] Furthermore, since the common cathode line PLB may also be disposed in parallel with the data line DL along the second direction, the first color pixels P1 , the second color pixels P2 , and the transparent pixels TP may be disposed in a row along the common cathode line PLB.

[0195] The arrangement structure of the first color pixels P1 , the second color pixels P2 , and the transparent pixels TP may be repeated along the data lines DL (or anode lines AL).

[0196] For example, Figure 7As shown, along the data line DL, the second color pixel P2 may be disposed below the first color pixel P1, the transparent pixel TP may be disposed below the second color pixel P2, and another first color pixel P1, another second color pixel P2, and another transparent pixel TP may be disposed below the transparent pixel TP.

[0197] The light emitting display panel 100 may be further provided with another data line DL for supplying a data voltage to the second pixel driving circuit PDC2 .

[0198] In the following description, when the data line DL connected to the first pixel driving circuit PDC1 and the data line DL connected to the second pixel driving circuit PDC2 are different, for the convenience of description, the data line DL connected to the first pixel driving circuit PDC1 is referred to as the first color data line RDL, and the data line DL connected to the second pixel driving circuit PDC2 is referred to as the second color data line BDL.

[0199] For example, in the above example, a data line connected to the first pixel driving circuit PDC1 may be a first color data line RDL, and another data line connected to the second pixel driving circuit PDC2 may be a second color data line BDL.

[0200] To provide additional description, such as Figure 7 As shown, when the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are arranged in a row along the anode line AL (or the common cathode line PLB), the first color data line RDL and the second color data line BDL may also be arranged in parallel with the anode line AL. In this case, the first color data line RDL may be connected to the first pixel driving circuit PDC1, and the second color data line BDL may be connected to the second pixel driving circuit PDC2.

[0201] Therefore, the data voltages may be simultaneously provided to the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, and the first color data voltage RVdata provided to the first pixel driving circuit PDC1 may be different from the second color data voltage BVdata provided to the second pixel driving circuit PDC2.

[0202] In this case, the gate line GL connected to the first pixel driving circuit PDC1 may be connected to the second pixel driving circuit PDC2. Figure 7 shown.

[0203] Therefore, the switching transistor Tsw1 of the first pixel driving circuit PDC1 and the switching transistor Tsw1 of the second pixel driving circuit PDC2 may be turned on at the same time.

[0204] Furthermore, an operation of supplying the first color data voltage RVdata to the first pixel driving circuit PDC1 through the first color data line RDL and an operation of supplying the second color data voltage BVdata to the second pixel driving circuit PDC2 through the second color data line BDL may be simultaneously performed.

[0205] Therefore, light may be output from the first color pixel P1 and the second color pixel P2 at the same time.

[0206] To provide additional description, a first color pixel P1 and a second color pixel P2 adjacent to each other between two transparent pixels TP disposed along the anode line AL may emit light at the same time.

[0207] Finally, in the above example, the first color pixel P1 and the second color pixel P2 adjacent to each other between two transparent pixels TP disposed along the anode line AL may emit light at the same time.

[0208] However, the first color pixel P1 and the second color pixel P2 adjacent to each other between two transparent pixels TP disposed along the anode line AL may emit light at different timings.

[0209] In this case, the light-emitting display panel 100 may be provided with a data line DL for providing a data voltage to the first pixel driving circuit PDC1, may be provided with a gate line GL for providing a gate signal GS to the first pixel driving circuit PDC1, and may be provided with another gate line GL for providing a gate signal GS to the second pixel driving circuit PDC2, and the data line DL connected to the first pixel driving circuit PDC1 may be connected to the second pixel driving circuit PDC2.

[0210] To provide additional explanation, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 may be connected to one data line DL, and the gate line GL connected to the first pixel driving circuit PDC1 and the gate line GL connected to the second pixel driving circuit PDC2 may be different.

[0211] In this case, as referenced Figure 3 As described above, the gate pulse GP may be sequentially provided to different gate lines GL.

[0212] In addition, a data voltage Vdata corresponding to the first pixel driving circuit PDC1 and a data voltage Vdata corresponding to the second pixel driving circuit PDC2 may be sequentially provided through the data lines DL.

[0213] Therefore, when the gate pulse GP is supplied to the gate line GL connected to the first pixel driving circuit PDC1 and the data voltage Vdata corresponding to the first pixel driving circuit PDC1 is supplied to the data line DL, light may be output from the first light emitting device ED1 connected to the first pixel driving circuit PDC1.

[0214] Subsequently, when the gate pulse GP is supplied to the gate line GL connected to the second pixel driving circuit PDC2 and the data voltage Vdata corresponding to the second pixel driving circuit PDC2 is applied to the data line DL, light may be output from the second light emitting device ED2 connected to the second pixel driving circuit PDC2.

[0215] To provide additional description, in a light-emitting display device according to the present disclosure, as Figure 7 As shown, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be connected to one gate line, the first color data line RDL can be connected to the first pixel driving circuit PDC1, and the second color data line BDL can be connected to the second pixel driving circuit PDC2. In this case, for the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, two data lines RDL and BDL and one gate line GL can be set in the light-emitting display panel.

[0216] However, in the light-emitting display device according to the present disclosure, as described above, a gate line may be connected to the first pixel driving circuit PDC1, another gate line may be connected to the second pixel driving circuit PDC2, and one data line DL may be connected to the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2. In this case, one data line DL and two gate lines GL may be provided for the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 in the light-emitting display panel.

[0217] Therefore, based on the transmittance in the case where two data lines RDL and BDL are set in the second direction (Y-axis direction) and one gate line GL is set in the first direction (X-axis direction), and the transmittance in the case where one data line DL is set in the second direction (Y-axis direction) and two gate lines GL are set in the first direction (X-axis direction), any one of the above two examples can be applied to the light-emitting display device according to the contents of the present disclosure.

[0218] Furthermore, based on the difficulty of the design and manufacturing processes of the above two examples, any one of the two examples may be applied to the light-emitting display device according to the present disclosure.

[0219] However, in addition to the above-described connection structure of the data line DL and the gate line GL, any of various connection structures that can drive the first color pixel P1 and the second color pixel P2 may be applied to the light emitting display device according to the present disclosure.

[0220] In the following, for the convenience of description, Figure 7 The light-emitting display device of the illustrated structure serves as an example of the light-emitting display device according to the present disclosure.

[0221] Figure 8 is an exemplary view showing a light-emitting display panel applied to a light-emitting display device according to an embodiment of the present disclosure. Figure 8 It is shown that Figure 7 However, for the convenience of description, the light emitting display panel 100 is shown in FIG. Figure 8 Omitted Figure 7 The common cathode line PLB, the sensing line SL and the first voltage supply line PLA are shown. Figure 8 The first color pixel P1 and the second color pixel P2 shown in FIG. 1 may be connected to a common cathode line PLB. In the following description, the description related to the reference numerals 1 and 2 may be omitted or briefly described. Figures 1 to 7 The details described are the same or similar details.

[0222] First, a data line (e.g., a first color data line RDL) of a first pixel driving circuit PDC1 for providing a data voltage Vdata to a first color pixel P1 may be provided in the light-emitting display panel 100. In addition, the first color pixel P1, the second color pixel P2, and the transparent pixel TP may be provided along the first color data line RDL. In the following description, when it is not necessary to distinguish between the first color data line RDL and the second color data line BDL, each of the first color data line RDL and the second color data line BDL may be referred to as a data line DL.

[0223] In this case, the second color data line BDL may be connected to the second pixel driving circuit PDC2 of the second color pixel P2, and the gate line GL connected to the first pixel driving circuit PDC1 may also be connected to the second pixel driving circuit PDC2.

[0224] The transparent light emitting device TED constituting the transparent pixel TP may include a transparent anode TAN and a transparent cathode TCA.

[0225] The transparent pixels TP may be divided into a first group 1GR and a second group 2GR along the data line DL. For example, the first group 1GR and the second group 2GR may be disposed along the data line DL. However, the transparent pixels TP may be divided into at least three groups.

[0226] For example, the number of groups may be set in various ways based on the size of the light-emitting display panel 100 , the number of cathode lines CL, a frequency for driving the light-emitting display panel 100 , and the like.

[0227] In the following, Figure 8 As shown, a light-emitting display device including transparent pixels TP divided into three groups of 1GR, 2GR, and 3GR is described as an example of the light-emitting display device according to an embodiment of the present disclosure.

[0228] In this case, the transparent pixels TP included in the first group 1GR may simultaneously output light, the transparent pixels TP included in the second group 2GR may simultaneously output light, and the transparent pixels TP included in the third group 3GR may simultaneously output light.

[0229] In addition, the first group 1GR to the third group 3GR may output light in sequence.

[0230] In this case, by referring to Figure 5 According to the described anode driver 800 , the first group 1GR to the third group 3GR may output light of the same brightness or may output light of different brightness.

[0231] For example, the transparent pixel TP may be a green pixel and thus may output light of the same color (green).

[0232] However, according to the structure and function of the anode driver 800, the first to third groups 1GR to 3GR may output light having the same brightness in the first frame period or may output light having different brightness.

[0233] In addition, the first to third groups 1GR to 3GR may output light having the same brightness during the first frame period, and may output light having brightness different from that in the first frame period during the second frame period.

[0234] In addition, the brightness of the light output from the first group 1GR to the third group 3GR in the first frame period may be different from each other, and the brightness of the light output from the first group 1GR to the third group 3GR in the second frame period may be different from each other. In this case, the brightness of the light output from the first group 1GR to the third group 3GR in the first frame period may be different from the brightness of the light output from the first group 1GR to the third group 3GR in the second frame period.

[0235] For example, the brightness of light output from each of the first to third groups 1GR to 3GR may vary according to an image output from the light-emitting display panel 100. Therefore, the quality of an image output from the light-emitting display device according to the present disclosure may be the same as or similar to the quality of an image output from a related art light-emitting display device.

[0236] As described above, when the transparent pixels TP are divided into the first group 1GR to the third group 3GR, the light-emitting display panel 100 may be provided with a first group of anode lines 1GAL connected to the transparent anodes TAN included in the first group 1GR, a second group of anode lines 2GAL connected to the transparent anodes TAN included in the second group 2GR, and a third group of anode lines 3GAL connected to the transparent anodes TAN included in the third group 3GR, as shown in FIG. Figure 8 shown.

[0237] In this case, the first group of anode lines 1GAL, the second group of anode lines 2GAL, and the third group of anode lines 3GAL may be disposed along the data line DL and may be adjacent to each other.

[0238] For example, the transparent pixels TP arranged along one data line DL may be divided into first to third groups 1GR to 3GR. Figure 8 shown.

[0239] Among the transparent pixels TP disposed along one data line DL, the transparent pixels TP included in the first group 1GR may be connected to the first group anode lines 1GAL. In particular, the transparent anodes TAN of the transparent pixels TP included in the first group 1GR may be connected to the first group anode lines 1GAL.

[0240] Among the transparent pixels TP disposed along one data line DL, the transparent pixels TP included in the second group 2GR may be connected to the second group anode line 2GAL. In particular, the transparent anodes TAN of the transparent pixels TP included in the second group 2GR may be connected to the second group anode line 2GAL.

[0241] Among the transparent pixels TP disposed along one data line DL, the transparent pixels TP included in the third group 3GR may be connected to the third group anode line 3GAL. In particular, the transparent anodes TAN of the transparent pixels TP included in the third group 3GR may be connected to the third group anode line 3GAL.

[0242] The first group of anode lines 1GAL, the second group of anode lines 2GAL, and the third group of anode lines 3GAL may be disposed along the data lines DL and may be adjacent to each other.

[0243] In this case, as referenced Figure 7 As described above, the first color pixels P1 and the second color pixels P2 arranged in a row along the Y-axis direction may be connected to different data lines DL. For example, the first color data line RDL may be connected to the first color pixel P1, and the second color data line BDL may be connected to the second color pixel P2.

[0244] In this case, the first group of anode lines 1GAL, the second group of anode lines 2GAL, and the third group of anode lines 3GAL may be disposed along the first color data lines RDL and the second color data lines BDL, and may be adjacent to each other.

[0245] The structure described above may be similarly applied to other data lines DL (or other first color data lines RDL or other second color data lines BDL).

[0246] The light emitting display panel 100 may be divided into a display area DA where the first color pixels P1 , the second color pixels P2 , and the transparent pixels TP are disposed, and a non-display area NDA surrounding the display area DA.

[0247] The display area DA may be provided with cathode lines CL disposed in a direction (eg, first direction or X-axis direction) different from a direction (eg, second direction or Y-axis direction) in which the data lines DL are disposed and connected to the transparent cathodes TCA.

[0248] For example, transparent cathodes TCA arranged in a row along the first direction (X-axis direction) may be connected to the cathode lines CL.

[0249] Therefore, the light emitting display panel 100 may be provided with cathode lines CL, the number of which is equal to the number of transparent cathodes TCA disposed along one data line DL.

[0250] A first group of cathode lines 1GCL connected to the cathode lines CL of the transparent pixels TP included in the first group 1GR, a second group of cathode lines 2GCL connected to the cathode lines CL of the transparent pixels TP included in the second group 2GR, and a third group of cathode lines 3GCL connected to the cathode lines CL of the transparent pixels TP included in the third group 3GR may be disposed in the non-display area NDA.

[0251] To provide additional description, the cathode lines CL included in the same group may be connected to each other.

[0252] In this case, the cathode voltage can be changed from the reference Figure 4 The cathode driver 700 is described to be sequentially provided to the first group of cathode lines 1GCL, the second group of cathode lines 2GCL, and the third group of cathode lines 3GCL.

[0253] When the cathode voltage CV is supplied to the first group of cathode lines 1GCL, light may be output from the transparent pixels TP connected to the first group of cathode lines 1GCL. When the cathode voltage CV is supplied to the second group of cathode lines 2GCL, light may be output from the transparent pixels TP connected to the second group of cathode lines 2GCL. When the cathode voltage CV is supplied to the third group of cathode lines 3GCL, light may be output from the transparent pixels TP connected to the third group of cathode lines 3GCL.

[0254] Therefore, light may be output sequentially from the first group 1GR to the third group 3GR.

[0255] To this end, when the cathode voltage CV is supplied to the first group of cathode lines 1GCL, the anode voltage AVdata can be supplied to the first group of anode lines 1GAL, when the cathode voltage CV is supplied to the second group of cathode lines 2GCL, the anode voltage AVdata can be supplied to the second group of anode lines 2GAL, and when the cathode voltage CV is supplied to the third group of cathode lines 3GCL, the anode voltage AVdata can be supplied to the third group of anode lines 3GAL.

[0256] For example, the cathode voltage CV supplied to the first group cathode line 1GCL may be supplied to the transparent cathode TCA included in the first group 1GR, and the anode voltage AVdata supplied to the first group anode line 1GAL may be supplied to the transparent anode TAN included in the first group 1GR. Therefore, light may be output from the transparent light emitting device TED included in the first group 1GR.

[0257] The cathode voltage CV supplied to the second group cathode line 2GCL may be supplied to the transparent cathode TCA included in the second group 2GR, and the anode voltage AVdata supplied to the second group anode line 2GAL may be supplied to the transparent anode TAN included in the second group 2GR. Therefore, light may be output from the transparent light emitting device TED included in the second group 2GR.

[0258] The cathode voltage CV supplied to the third group cathode line 3GCL may be supplied to the transparent cathode TCA included in the third group 3GR, and the anode voltage AVdata supplied to the third group anode line 3GAL may be supplied to the transparent anode TAN included in the third group 3GR. Therefore, light may be output from the transparent light emitting device TED included in the third group 3GR.

[0259] In this case, as described above, if the cathode voltage CV is sequentially supplied from the cathode driver 700 to the first group of cathode lines 1GCL, the second group of cathode lines 2GCL, and the third group of cathode lines 3GCL, and the anode voltage AVdata is sequentially supplied from the anode driver 800 to the first group of anode lines 1GAL, the second group of anode lines 2GAL, and the third group of anode lines 3GAL, light can be output sequentially from the first group 1GR to the third group 3GR.

[0260] When the cathode lines CL are divided into first to n-th groups of cathode lines 1GCL (n is a natural number less than or equal to the number of cathode lines CL), the cathode voltage CV may be supplied to each of the first to n-th groups of cathode lines 1GCL within a 1 / n period of a frame period.

[0261] For example, Figure 8 As shown, when the cathode lines CL are divided into first to third groups of cathode lines 1GCL to 3GCL, the cathode voltage CV may be supplied to each of the first to third groups of cathode lines 1GCL to 3GCL within 1 / 3 of one frame period.

[0262] For example, when the light-emitting display device according to the present disclosure displays 120 images within one second, one frame period may be 1 / 120 seconds.

[0263] When one frame period is 1 / 120 seconds, the cathode voltage CV may be supplied to each of the first to third groups of cathode lines 1GCL to 3GCL within a period of 1 / 360 seconds.

[0264] To provide additional description, if the cathode voltage CV is sequentially supplied to each cathode line CL, the period for which the cathode voltage CV is supplied to the cathode line CL may be shorter than 1 / 360 seconds. If the period for supplying the cathode voltage CV is shortened, the period for which the light emitting device connected to the cathode line CL supplied with the cathode voltage CV emits light is shortened.

[0265] If the cathode voltage CV is not supplied to the cathode line CL, the light emitting device connected to the cathode line CL no longer outputs light.

[0266] In this case, the image afterimage of the light output from the light emitting device connected to the cathode lines CL should be maintained until the light is output from the light emitting device connected to the last cathode line CL in order to normally display an image.

[0267] However, as described above, if the period during which the cathode voltage CV is supplied to the cathode line CL is shortened, the period during which the light emitting device ED connected to the first cathode line CL1 emits light may be shortened.

[0268] Therefore, image afterimage of light output from the light emitting device ED connected to the first cathode line CL1 cannot be maintained until light is output from the light emitting device ED connected to the g-th cathode line CLg. Therefore, an image cannot be normally displayed during one frame period.

[0269] However, as in the light emitting display device according to the present disclosure, if the cathode lines CL are divided into groups, the period during which the cathode voltage CV is supplied to the cathode lines CL can be extended, and thus the period during which light is output from the light emitting device ED connected to the first cathode line CL1 can be extended.

[0270] Therefore, image afterimage of light output from the light emitting device ED connected to the first cathode line CL1 may remain until light is output from the light emitting device ED connected to the g-th cathode line CLg. Therefore, an image may be normally displayed during one frame period.

[0271] Finally, the gate driver 200 may be provided to provide gate signals to the first and second pixel driving circuits PDC1 and PDC2 , and the cathode driver 700 may be provided in the light emitting display panel 100 to sequentially provide cathode voltages CV to the cathode lines CL.

[0272] For example, the gate driver 200 may sequentially supply the gate pulses GP to the gate lines GL. In addition, the cathode driver 700 may sequentially supply the cathode voltages CV to the cathode lines CL, or sequentially supply the cathode voltages CV to the group cathode lines GCL.

[0273] As described above, the gate driver 200 may be directly embedded in the non-display area NDA by using a gate-in-panel (GIP) type, or may be disposed in the display area DA where the light-emitting device ED is disposed, or may be disposed on a chip-on-film mounted in the non-display area NDA.

[0274] In addition, as described above, the cathode driver 700 may be directly embedded in the non-display area NDA, or may be disposed in the display area DA where the light-emitting device ED is disposed, or may be disposed on a chip-on-film installed in the non-display area NDA.

[0275] In this case, when the gate driver 200 is disposed in the non-display area NDA disposed on the left side of the light-emitting display panel 100, as shown in FIG. Figure 1 and Figure 8 As shown, the cathode driver 700 may be disposed on the right side of the light-emitting display panel 100 .

[0276] However, as described above, when the cathode driver 700 includes a power supply unit 500 and a power control unit that can generate a power control signal capable of controlling the power supply unit 500, and a cathode voltage generator set in the power supply unit 500 is connected to the cathode line CL or the group cathode line GCL through a cathode switch, the power control unit can turn on the cathode switch in sequence.

[0277] In this case, the power control unit may be disposed in the non-display area NDA of the light-emitting display panel 100, may be disposed in the control driver 400, may be disposed in the power supply unit 500, and may be disposed on a printed circuit board on which the power supply unit 500 and the control driver 400 are mounted.

[0278] Fig. 9 is an exemplary view schematically showing a cross section of a pixel applied to a light-emitting display device according to an embodiment of the present disclosure, and Fig.10is an exemplary view schematically showing a cross section of a transparent pixel applied to a light-emitting display device according to an embodiment of the present disclosure. In particular, Fig. 9 , a cross section of a region where a driving transistor Tdr and a light emitting device ED are provided in the light emitting display panel 100 is shown. Fig. 9 A cross section of a pixel P is shown. In the following description, the pixel P may be a first color pixel P1 or a second color pixel P2.

[0279] As described above, the pixel driving circuit PDC may overlap with the light emitting device ED and Fig. 9 , a cross section where the driving transistor Tdr of the pixel driving circuit PDC overlaps with the light emitting device ED is shown.

[0280] like Fig. 9 As shown, the light-emitting display panel 100 applied to the light-emitting display device according to an embodiment of the present disclosure may include a substrate 101, a pixel driving circuit layer PDL arranged on the substrate 101, a planarization layer 106 arranged on the pixel driving circuit layer PDL to cover the pixel driving circuit layer PDL, an anode AN arranged on the planarization layer 106, a light-emitting layer EL arranged on the anode AN, a cathode CA arranged on the light-emitting layer EL, and an encapsulation layer 107 covering the cathode CA.

[0281] First, refer to Fig. 9 The cross-sectional structure of the pixel P is described. The substrate 101 may be a glass substrate or a plastic substrate, but is not limited thereto, and may be formed of one of various films.

[0282] A pixel driving circuit layer PDL including a driving transistor Tdr may be disposed on the substrate.

[0283] A pixel driving circuit PDC including a driving transistor Tdr may be provided in the pixel driving circuit layer PDL. Figure 2 As described above, the pixel driving circuit PDC may include a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2. For example, at least two transistors may be provided in the pixel driving circuit layer PDL.

[0284] Each transistor may include an active layer AC including a semiconductor, a gate insulating layer 103 disposed on the active layer AC, and a gate G disposed on the gate insulating layer 103 .

[0285] The gate G may be covered by a gate insulating layer 104 , and various electrodes or wires may be provided on the gate insulating layer 104 .

[0286] The electrodes or wires disposed on the insulating layer 104 may be covered by the passivation layer 105 , and the passivation layer 105 may be covered by the planarization layer 106 .

[0287] For example, Fig. 9 The driving transistor Tdr shown may include an active layer AC disposed on a buffer layer 102, a gate insulating layer 103 disposed on the active layer AC, a gate G disposed on the insulating layer 103, an insulating layer 104 covering an upper end of the gate G, a first voltage supply line PLA connected to a first terminal of the driving transistor Tdr, and a passivation layer 105 covering the first voltage supply line PLA. In this case, other transistors disposed in the pixel driving circuit PDC may also be connected in the same manner as Fig. 9 The driving transistor Tdr shown is formed in a similar shape.

[0288] However, the structures of the driving transistor Tdr and other transistors are not limited to Fig. 9 Therefore, the structures of the driving transistor Tdr and other transistors can be changed into various shapes.

[0289] In this case, if Fig. 9 As shown, a light shielding electrode LS may be provided at a lower end of the driving transistor Tdr in order to block external light incident on the active layer AC during a manufacturing process of the light emitting display device or when the light emitting display device is used.

[0290] The light-shielding electrode LS may be connected to any one of the gate electrode, the first gate electrode, and the second gate electrode of the driving transistor Tdr.

[0291] Another light shielding electrode disposed on the same layer as the light shielding electrode LS may be used as various lines, such as a data line DL or a gate line GL.

[0292] Therefore, each of the light shielding electrode LS and the other light shielding electrode may be provided in a floating state, or may be connected to a signal line to which a voltage is supplied.

[0293] The light-shielding electrode LS may or may not be provided at the lower end of other transistors provided in the pixel driving circuit layer PDL. That is, the light-shielding electrode LS may be provided not only at the lower end of the driving transistor Tdr, but also at the lower end of another transistor that needs light shielding, and may be provided in an area that needs light shielding in an area where no transistor is provided.

[0294] The light-shielding electrode LS may be disposed on the substrate 101 , the light-shielding electrode LS may be covered by the buffer layer 102 , and the active layer AC may be disposed on the buffer layer 102 .

[0295] In addition, the data lines DL, the gate lines GL, the sensing control lines SCL, the sensing lines SL, and the first voltage supply lines PLA connected to the pixel driving circuit PDC may be disposed in the pixel driving circuit layer PDL.

[0296] Hereinafter, a common name of the data line DL, the gate line GL, the sensing line SL, and the first voltage supply line PLA may be a signal line. That is, at least one signal line may be provided in the pixel driving circuit layer PDL.

[0297] Each of the buffer layer 102, the gate insulating layer 103, the insulating layer 104, and the passivation layer 105 may be formed of at least one inorganic layer, or at least one organic layer, or at least one inorganic layer and at least one organic layer. The buffer layer 102, the gate insulating layer 103, the insulating layer 104, and the passivation layer 105 may perform an insulating function. Therefore, each of the buffer layer 102, the gate insulating layer 103, the insulating layer 104, and the passivation layer 105 may be referred to as an insulating functional layer.

[0298] The gate electrode of the driving transistor Tdr, the light shielding electrode LS, and the signal line are metal. Therefore, a layer provided with at least one of the gate electrode, the light shielding electrode LS, and the signal line can be referred to as a metal layer.

[0299] That is, the pixel driving circuit layer PDL may include at least two metal layers and at least two insulating functional layers.

[0300] The planarization layer 103 may be disposed on the pixel driving circuit layer 102 .

[0301] The planarization layer 106 may perform a function of planarizing an uneven upper surface of the pixel driving circuit layer PDL. To this end, the planarization layer 106 may be formed to have a thickness greater than that of the pixel driving circuit layer PDL, and thus, the upper surface of the planarization layer 106 may be planarized.

[0302] The planarization layer 106 may be formed of at least one organic layer, or at least one inorganic layer, or at least one inorganic layer and at least one organic layer.

[0303] The anode AN may be disposed on the planarization layer 106. The anode may constitute the light emitting device ED.

[0304] like Figure 2 and Fig. 9 As shown, the anode AN is electrically connected to the driving transistor Tdr provided in the pixel driving circuit layer PDL, and is patterned for each pixel P. Therefore, the anodes AN provided in the pixels P are physically and electrically separated from each other.

[0305] The anode AN may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO), and may be formed of an opaque metal such as silver (Ag), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr), and tungsten (W). In particular, when the light-emitting display panel 100 according to the present disclosure uses a top emission type, light generated in the light-emitting device ED may be output toward the cathode CA. In this case, the anode AN may be formed of an opaque metal to reflect light transmitted from the light-emitting device ED toward the cathode CA.

[0306] The bank BK may be provided in the planarization layer 106 , and may include an opening portion through which the anode AN is exposed.

[0307] For example, the bank BK covers the outer edge of the anode AN to form an opening portion through which light is output from the pixel P. That is, Fig. 9 The region of the anode AN shown in FIG. 1 that is not covered by the bank BK is an opening portion. The opening portion may be the light emitting area EA.

[0308] To provide additional description, the bank BK covers the outer edge of the anode AN and may be disposed in the display area DA of the substrate 101 such that the anode AN is exposed.

[0309] The bank BK may prevent light from overlapping between adjacent pixels.

[0310] The bank BK may be formed of at least one inorganic layer, or at least one organic layer, or at least one inorganic layer and at least one organic layer.

[0311] The light emitting layer EL may be disposed on the substrate 101 to cover the anode AN and the bank BK.

[0312] For example, the light emitting layer EL may be continuously disposed in the first color pixel P1 and the second color pixel P2, and may not be disposed in the transmission area TA. However, the light emitting layer EL may be disposed in each of the first color pixel P1 and the second color pixel P2, and the light emitting layer EL disposed in the first color pixel P1 and the light emitting layer EL disposed in the second color pixel P2 may be separated from each other.

[0313] In addition, the light emitting layer EL provided in the first color pixel P1 and the second color pixel P2 may extend to the transparent pixel TP or may be separated from the light emitting layer provided in the transparent pixel TP.

[0314] The light emitting layer EL may include one of an organic light emitting layer, an inorganic light emitting layer and a quantum dot light emitting layer. Alternatively, the light emitting device EL may include a stack or combination structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

[0315] The light emitting layer EL may include a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron injection layer (EIL), an electron transport layer (ETL), an electron blocking layer (EBL), and a charge generation layer (CGL).

[0316] In the case where the light-emitting layer EL emits white light, the light-emitting layer EL may include a hole injection layer (HIL) / hole transport layer (HTL), a blue organic layer, an electron injection layer (EIL) / charge generation layer (CGL) / electron transport layer (ETL), a red organic layer, a yellow-green organic layer, an electron injection layer (EIL) / charge generation layer (CGL) / electron transport layer (ETL), a blue organic layer, an electron injection layer (EIL) / electron transport layer (ETL), and an organic buffer layer sequentially stacked on the anode AN.

[0317] In addition to the layers having the stacking order as described above, the light emitting layer EL may include a plurality of layers having various stacking orders.

[0318] The cathode CA may be provided on the light emitting layer EL.

[0319] The cathode electrode CA may be continuously disposed in the first color pixel P1 and the second color pixel P2 and may not be disposed in the transmission area TA.

[0320] In addition, the cathodes CA disposed in the first and second color pixels P1 and P2 are separated from the transparent cathodes TCA disposed in the transparent pixels TP.

[0321] In the case where the light emitting device ED emits white light, a color filter may be provided under the anode AN or on the cathode.

[0322] For example, when the light-emitting display panel 100 uses a top emission type, a color filter may be disposed at an upper end of the cathode electrode CA.

[0323] The cathode CA may be covered by an encapsulation layer 107 .

[0324] The encapsulation layer 107 may be formed of at least one organic layer, or at least one inorganic layer, or at least one inorganic layer and at least one organic layer.

[0325] Moisture and oxygen flowing in from the outside may be blocked by the encapsulation layer 106 and thus cannot penetrate into the light emitting layer EL.

[0326] The cross-sectional structure of the pixel P as described above can be commonly applied to Figure 8 A first color pixel P1 and a second color pixel P2 are shown.

[0327] Secondly, refer to Fig.10The cross-sectional structure of the transparent pixel TP is described. In the following description, the cross-sectional structure of the transparent pixel TP is omitted or briefly described. Fig. 9 The details described are the same or similar details.

[0328] The substrate 101 may be a glass substrate or a plastic substrate, but is not limited thereto, and may be formed of one of various films.

[0329] Since the transparent pixel TP is not provided with the pixel driving circuit PDC, the cross section of the transparent pixel TP is not provided with the pixel driving circuit layer PDL. That is, the transparent pixel TP lacks the pixel driving circuit layer PDL.

[0330] The anode line AL may be disposed on the substrate 101. For example, the anode line AL may be disposed on the upper surface of the substrate 101. However, the anode line AL may be disposed on the upper surface of any one of the buffer layer 102, the gate insulating layer 103, the insulating layer 104, and the passivation layer 105.

[0331] also, Fig.10 The anode line AL shown may be Figure 7 and Figure 8 The anode line AL shown, or Figure 7 and Figure 8 The anode connection line shown connects the anode line AL and the transparent anode TAN.

[0332] To provide additional description, Figure 7 and Figure 8 The anode line AL shown may be the anode line AL itself, or may be an anode connection line connected to the anode line AL.

[0333] When the anode line AL is disposed on the upper surface of the substrate 101 , the anode line AL may be any one of the light shielding electrodes disposed on the substrate 101 .

[0334] When the anode line AL is disposed on the upper surface of the substrate 101 , at least one of the buffer layer 102 , the gate insulating layer 103 , the insulating layer 104 , and the passivation layer may be disposed on an upper end of the anode line AL.

[0335] The planarization layer 106 may be disposed on the pixel driving circuit layer PDL. The transparent anode TAN may be disposed on the planarization layer 106.

[0336] The transparent anode TAN can constitute a transparent light-emitting device TED. Fig.10 As shown, a transparent anode TAN is patterned on each transparent pixel TP. The transparent anode TAN can be directly connected to an anode like AL, thereby eliminating the need for a pixel driving circuit in the transparent pixel TP.

[0337] Therefore, the transparent anodes TAN disposed in the transparent pixels TP are physically and electrically separated from each other. In addition, the transparent anode TAN is separated from the anode AN.

[0338] The transparent anode TAN may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0339] The bank BK may be disposed on the planarization layer 106 , and may include an opening portion through which the transparent anode TAN is exposed.

[0340] For example, the bank BK may cover the outer edge of the transparent anode TAN to form an opening portion through which light is output from the transparent pixel TP. Fig.10 The area of ​​the transparent anode TAN shown in FIG. 1 that is not covered by the bank BK is an opening portion. The opening portion may be the emission area EA.

[0341] To provide additional description, the bank BK covers the outer edge of the transparent anode TAN and may be disposed in the display area DA of the substrate 101 such that the anode AN is exposed.

[0342] However, the bank BK may not be provided outside the transparent anode TAN.

[0343] A transparent light emitting layer TEL may be disposed on the substrate 101 to cover the transparent anode TAN and the bank BK.

[0344] The transparent light emitting layer TEL may not be disposed in the transmission area TA.

[0345] In addition, the transparent light emitting layer TEL may be connected to the light emitting layer EL provided in the first color pixel P1 and the second color pixel P2 , but may also be separated from the light emitting layer EL.

[0346] The transparent light emitting layer TEL may be formed with the same or similar structure as the above-described light emitting layer EL. Since the transparent light emitting layer TEL may be formed thin enough to allow light to pass therethrough, light may be transmitted through the transparent light emitting layer TEL. In addition, since each material constituting the transparent light emitting layer TEL may be formed of a material that may transmit light, light may be transmitted through the transparent light emitting layer TEL.

[0347] The transparent cathode TCA may be disposed on the transparent light emitting layer TEL.

[0348] The transparent cathode TCA may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO). Therefore, light generated in the transparent light emitting layer TEL may be output to the outside of the light emitting display panel 100 through the transparent cathode TCA.

[0349] Furthermore, since the transparent anode TAN and the transparent cathode TCA are formed of a transparent metal and the transparent light emitting layer TEL may also be transparently formed, light may be transmitted in the transparent light emitting device TED.

[0350] The transparent cathode TCA may be disposed only in the transparent pixel TP, and may not be disposed in the transmission area TA.

[0351] In addition, the transparent cathode TCA is separated from the cathodes CA disposed in the first color pixel P1 and the second color pixel P2.

[0352] In case the transparent light emitting device TED emits white light, a color filter may be provided under the transparent anode TAN or on the transparent cathode TCA.

[0353] For example, when the light-emitting display panel 100 uses a top emission type, a color filter may be disposed at an upper end of the transparent cathode TCA.

[0354] The transparent cathode TCA may be covered by an encapsulation layer 107 .

[0355] Fig.11 is shown along Figure 7 An exemplary view of a cross section taken along line CC' of Fig.12 is shown along Figure 7 An exemplary view of a cross section taken along line D-D' of Fig.13 is shown along Figure 7 In the following description, the description related to the reference numerals will be omitted or briefly described. Figures 1 to 10 The details described are the same or similar details.

[0356] first, Fig.11 A cross section of a region where the common cathode line PLB, the gate line GL, and the cathode line CL intersect is shown.

[0357] For example, as described above, the cathode lines CL and the gate lines GL may be disposed along the first direction (X-axis direction) of the light-emitting display panel 100 , and the common cathode lines PLB may be disposed along the second direction (Y-axis direction).

[0358] The cathode lines CL may be connected to the cathode driver 700 , the gate lines GL may be connected to the gate driver 200 , and the common cathode lines PLB may be connected to the power supply unit 500 .

[0359] Therefore, the cathode lines CL and the gate lines GL may intersect the common cathode lines PLB.

[0360] The common cathode line PLB may be connected to the cathodes CA constituting the first light emitting device ED1 disposed in the first color pixel P1 and the second light emitting device ED2 disposed in the second color pixel P2. For example, the cathodes CA constituting the first light emitting device ED1 and the cathodes CA constituting the second light emitting device ED2 may be formed as one plate, and the cathodes CA may be connected to the common cathode line PLB.

[0361] The cathode lines CL and the gate lines GL may be arranged in parallel on the same layer, or may be arranged on different layers, such as Fig.11 shown.

[0362] For example, Fig.11 As shown, the gate line GL may be disposed on the upper surface of the substrate 101 , the gate line GL may be covered by the buffer layer 102 , and the cathode line CL may be disposed on the upper surface of the buffer layer 102 .

[0363] The cathode line CL may be covered by the gate insulating layer 103 or the insulating layer 104 or the passivation layer 105 , or may be covered by at least two of the gate insulating layer 103 , the insulating layer 104 , and the passivation layer 105 .

[0364] In this case, the gate lines GL and the cathode lines CL may be disposed to overlap.

[0365] The common cathode line PLB may be disposed on the upper surface of the substrate 101. However, in a region where the common cathode line PLB intersects the gate line GL and the cathode line CL, the common cathode line PLB may be disposed on an upper end of at least one of the gate insulating layer 103, the insulating layer 104, and the passivation layer 105.

[0366] Each of the gate line GL, the cathode line CL, and the common cathode line PLB may be formed of an opaque metal such as silver (Ag), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr), and tungsten (W), but may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) to improve transmittance.

[0367] For example, a region where the gate lines GL, the cathode lines CL, and the common cathode lines PLB are disposed may be the transmission region TA.

[0368] The cathode CA disposed on the bank BK may be connected to the gate line GL, the cathode line CL, and the common cathode line PLB through a first contact hole 1CH penetrating at least one of the buffer layer 102, the gate insulating layer 103, the insulating layer 104, the passivation layer 105, the planarization layer 106, and the bank BK. Fig.11 As shown, the cathode CA may be connected to the common cathode line PLB through a first contact hole 1CH provided in the bank BK.

[0369] For example, when the gate line GL, the cathode line CL and the common cathode line PLB are formed of a transparent metal, in order to improve the transmittance in the common cathode line PLB, the common cathode line PLB can be covered only by the embankment BK and thus can be connected to the cathode CA through a first contact hole 1CH set in the embankment BK.

[0370] Next, Fig.12 A cross section of a region where the cathode line CL is connected to the transparent cathode TCA is shown.

[0371] For example, as described above, the cathode lines CL and the gate lines GL may be disposed along the first direction (X-axis direction) of the light-emitting display panel 100 , and the cathode lines CL may be connected to the transparent cathodes TCA.

[0372] The cathode lines CL and the gate lines GL may be arranged in parallel on the same layer, or may be arranged on different layers, such as Fig.11 and Fig.12 shown.

[0373] For example, Fig.11 and Fig.12 As shown, the gate line GL may be disposed on the upper surface of the substrate 101, the gate line GL may be covered by the buffer layer 102, the cathode line CL may be disposed on the upper surface of the buffer layer 102, the cathode line CL may be covered by any one of the gate insulating layer 103, the insulating layer 104, the passivation layer 105, and the planarization layer 106, any one of the gate insulating layer 103, the insulating layer 104, the passivation layer 105, and the planarization layer 106 may be covered by the bank BK, and the transparent cathode TCA may be disposed on the bank BK. However, the cathode line CL may be covered by at least two of the gate insulating layer 103, the insulating layer 104, the passivation layer 105, and the planarization layer 106.

[0374] In this case, the gate lines GL and the cathode lines CL may be disposed to overlap.

[0375] The transparent cathode TCA disposed on the bank BK may be connected to the cathode line CL through a second contact hole 2CH penetrating at least one of the gate insulating layer 103, the insulating layer 104, the passivation layer 105, the planarization layer 106, and the bank BK. Fig.12 As shown, the transparent cathode TCA may be connected to the cathode line CL through a second contact hole 2CH provided in at least one of the gate insulating layer 103, the insulating layer 104, and the passivation layer 105, and the bank.

[0376] In this case, a transparent anode TAN constituting a transparent light emitting device TED together with a transparent cathode TCA and a transparent light emitting layer TEL may be disposed on the upper surface of the substrate 101, as shown in FIG. Fig.12 shown.

[0377] For example, the transparent anode TAN may be disposed on the upper surface of the planarization layer 106, such as Fig.10 However, in order to improve the transmittance in the transparent light emitting device TED, the transparent anode TAN may be disposed on the upper surface of the substrate 101, as shown in FIG. Fig.12 shown.

[0378] To provide additional description, the buffer layer 102, the gate insulating layer 103, the insulating layer 104, the passivation layer 105, and the planarization layer 106 may not be disposed in a region where the transparent anode TAN is disposed. Therefore, the transmittance of the transparent light emitting device TED may be improved.

[0379] However, the region in which the transparent anode TAN is disposed may be provided with at least one of the buffer layer 102 , the gate insulating layer 103 , the insulating layer 104 , the passivation layer 105 , and the planarization layer 106 .

[0380] The transparent light emitting layer TEL may be disposed between the transparent anode TAN and the transparent cathode TCA.

[0381] at last, Fig.13 The cross section of the region where the first color data line RDL, the second color data line BDL and the group anode line GAL are arranged is shown. The first color data line RDL, the second color data line BDL and the at least two groups of anode lines GAL may be arranged in parallel on the same layer. In the at least two groups of anode lines GAL, Fig.13 The cross section shown in FIG. 1 shows a first group of anode lines 1GAL and a second group of anode lines 2GAL adjacent to the transparent anode TAN. Fig.13 A cross section is shown where the first group of anode lines 1GAL closest to the transparent anode TAN is connected to the transparent anode TAN.

[0382] For example, as described above, the first color data line RDL, the second color data line BDL, and the anode line AL may be disposed along the second direction (Y-axis direction) of the light-emitting display panel 100 .

[0383] The first and second color data lines RDL and BDL may be connected to the data driver 300 , and at least two groups of anode lines GAL may be connected to the anode driver 800 .

[0384] A set of anode lines GAL may be connected to a transparent anode TAN via an anode connection line ACL.

[0385] For example, as described above and Fig.13As shown, the transparent anode TAN may be disposed on the upper surface of the substrate 101. In this case, an anode connection line ACL connected to the transparent anode TAN may be disposed on the upper surface of the substrate 101.

[0386] The anode connection line ACL may be covered by at least one of the buffer layer 102 , the gate insulating layer 103 , the insulating layer 104 , the passivation layer 105 , and the planarization layer 106 .

[0387] The first color data lines RDL, the second color data lines BDL, and at least two groups of anode lines GAL may be disposed on at least one of the buffer layer 102 , the gate insulating layer 103 , the insulating layer 104 , the passivation layer 105 , and the planarization layer 106 .

[0388] In particular, the first color data lines RDL, the second color data lines BDL, and at least two groups of anode lines GAL may be disposed in a layer where the gate lines GL and the cathode lines CL are not disposed.

[0389] For example, when the gate line GL is set on the upper surface of the substrate 101 and the cathode line CL is set on the upper surface of the buffer layer 102, the first color data line RDL, the second color data line BDL and at least two groups of anode lines GAL can be set on any one of the gate insulation layer 103, the insulation layer 104 and the passivation layer 105.

[0390] Any one of the at least two groups of anode lines GAL may be connected to the anode connection line ACL through a third contact hole 3CH passing through at least one of the gate insulating layer 103, the insulating layer 104, and the passivation layer 105, and may be connected to the transparent anode TAN through the anode connection line ACL.

[0391] In this case, a transparent anode TAN constituting the transparent light emitting device TED together with a transparent cathode CA and a transparent light emitting layer TEL may be disposed on the upper surface of the substrate 101, as shown in FIG. Fig.12 described.

[0392] The transparent light emitting layer TEL may be disposed on the transparent anode TAN, and the transparent cathode CA may be disposed on an upper surface of the transparent light emitting layer TEL and an upper surface of the bank BK.

[0393] However, the arrangement structure of the gate lines GL, the cathode lines CL, the common cathode lines PLB, the first color data lines RDL, the second color data lines BDL, and the at least two groups of anode lines GAL is not limited to the above structure.

[0394] Therefore, the arrangement structure of the gate lines GL, the cathode lines CL, the common cathode lines PLB, the first color data lines RDL, the second color data lines BDL, and the at least two groups of anode lines GAL may be changed in various forms.

[0395] In addition, each of the first color data line RDL, the second color data line BDL and the at least two groups of anode lines GAL can be formed of an opaque metal such as silver (Ag), aluminum (Al), copper (Cu) and molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr) and tungsten (W), but can also be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) to improve transmittance.

[0396] For example, the first color data line RDL, the second color data line BDL, and at least two groups of anode lines GAL may be the transmission area TA.

[0397] In this case, the first color data line RDL, the second color data line BDL, and at least two groups of anode lines GAL may not be covered by the bank BK.

[0398] Furthermore, the first and second color data lines RDL and BDL may be formed of an opaque metal, but in order to improve transmittance, at least two groups of anode lines GAL may be formed of a transparent metal such as indium tin oxide (ITO) or indium zinc oxide (ZO).

[0399] For example, at least two groups of anode lines GAL may be the transmission areas TA.

[0400] In this case, if Fig.13 As shown, the first color data lines RDL and the second color data lines BDL may be covered by the bank BK, and at least two groups of anode lines GAL may not be covered by the bank BK.

[0401] According to the present disclosure as described above, the area of ​​the transmission region TA may be increased compared to the related art, and thus, the transmittance of the light emitting display panel may be increased compared to the related art.

[0402] Features of the light emitting display device according to the embodiment of the present disclosure are briefly summarized as follows.

[0403] According to an embodiment of the present disclosure, a light-emitting display device includes a substrate, which is configured to be divided into a transmission area that transmits light and a non-transmission area that blocks light, a first color pixel, which is configured to be arranged in the non-transmission area and includes a first pixel driving circuit and a first light-emitting device, a second color pixel, which is configured to be arranged in the non-transmission area and includes a second pixel driving circuit and a second light-emitting device, and a transparent pixel, which is configured to be arranged in the transmission area and includes only a transparent light-emitting device.

[0404] The transmission area includes a light emitting area in which transparent pixels are disposed and a non-light emitting area in which no light emitting device is disposed.

[0405] The transparent light emitting device includes a transparent anode and a transparent cathode.

[0406] The transparent anode is connected to an anode line disposed in parallel with the data line disposed on the substrate, and the transparent cathode is connected to a cathode line disposed on the substrate.

[0407] The first light emitting device includes a first anode and a common cathode, the second light emitting device includes a second anode and a common cathode, the transparent light emitting device includes a transparent anode and a transparent cathode, and the common cathode and the transparent cathode are separated from each other.

[0408] The substrate is provided with common cathode lines connected to the common cathode and cathode lines connected to the transparent cathode.

[0409] The substrate is provided with data lines for providing data voltages to the first pixel driving circuit, the substrate is provided with gate lines for providing gate signals to the first pixel driving circuit, the common cathode lines are provided in parallel with the data lines, and the cathode lines are provided in parallel with the gate lines.

[0410] The substrate is provided with data lines for providing data voltages to the first pixel driving circuit, the substrate is provided with gate lines for providing gate signals to the first pixel driving circuit, and the first color pixels, the second color pixels and the transparent pixels are arranged in rows along the data lines.

[0411] The substrate is provided with anode lines connected to transparent anodes provided in transparent pixels, and the anode lines are provided on the substrate in parallel with the data lines.

[0412] The substrate is also provided with another data line for supplying a data voltage to the second pixel driving circuit, and the gate line connected to the first pixel driving circuit is connected to the second pixel driving circuit.

[0413] The substrate is also provided with another gate line connected to a second pixel driving circuit, and the data line is connected to the second pixel driving circuit.

[0414] The transparent pixels are not provided with a pixel driving circuit.

[0415] The substrate is provided with a data line for providing a data voltage to a first pixel driving circuit, first color pixels, second color pixels and transparent pixels are arranged along the data line, a transparent light-emitting device constituting the transparent pixel includes a transparent anode and a transparent cathode, and the transparent pixels are divided into a first group and a second group along the data line.

[0416] The substrate is provided with a first group of anode lines connected to the transparent anodes included in the first group and a second group of anode lines connected to the transparent anodes included in the second group, and the first group of anode lines and the second group of anode lines are disposed along the data lines and adjacent to each other.

[0417] The substrate is divided into a display area and a non-display area, the display area is provided with first color pixels, second color pixels and transparent pixels, the non-display area surrounds the display area, the display area is provided with cathode lines connected to the transparent cathode in a direction different from a direction in which the data lines are provided, and the non-display area is provided with a first group of cathode lines connected to the cathode lines included in the first group and a second group of cathode lines connected to the cathode lines included in the second group.

[0418] The cathode voltage is sequentially supplied to the first group of cathode lines and the second group of cathode lines.

[0419] When the cathode voltage is supplied to the first group of cathode lines, the anode voltage is supplied to the first group of anode lines, and when the cathode voltage is supplied to the second group of cathode lines, the anode voltage is supplied to the second group of anode lines.

[0420] When the cathode lines are divided into first to n-th groups of cathode lines (n is a natural number less than the number of cathode lines), a cathode voltage is supplied to each of the first to n-th groups of cathode lines during a 1 / n period of one frame period.

[0421] The light emitting display device further includes a gate driver and a cathode driver, wherein the gate driver is configured to provide a gate signal to the first pixel driving circuit, and the cathode driver is configured to provide a cathode voltage to the cathode lines in sequence.

[0422] The transparent pixels included in the first group simultaneously output light, and the transparent pixels included in the second group simultaneously output light.

[0423] The light-emitting display device according to the present disclosure can be applied to all electronic devices including light-emitting display panels. For example, the light-emitting display device according to the present disclosure can be applied to virtual reality (VR) devices, augmented reality (AR) devices, mobile devices, video phones, smart watches, watch phones or wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic notebooks, electronic books, PMP (portable multimedia player), PDA (personal digital assistant), MP3 player, mobile medical equipment, desktop PC, laptop PC, netbook computer, workstation, navigation, car navigation, vehicle display device, TV, wallpaper display device, signage device, gaming device, laptop computer, monitor, camera, video camera and household appliances.

[0424] According to the light-emitting display device of the embodiment of the present disclosure, since some pixels that output light can transmit light flowing in from the outside, the transmittance of the light-emitting display device can be improved.

[0425] According to the light-emitting display device of the embodiment of the present disclosure, the pixels capable of transmitting light can be divided into groups, and the output of light can be controlled for each group. Therefore, the period of light output from the pixels capable of transmitting light can be increased, thereby preventing the quality of the image output from the light-emitting display device from deteriorating.

[0426] The above-mentioned features, structures and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. In addition, the features, structures and effects described in at least one embodiment of the present disclosure can be realized by those skilled in the art through the combination or modification of other embodiments. Therefore, the contents associated with the combination and modification should be interpreted as being within the scope of the present disclosure.

[0427] It will be apparent to those skilled in the art that various modifications and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: a substrate configured to be divided into a transmission area that transmits light and a non-transmission area that blocks light; a first color pixel configured to be disposed in the non-transmitting region and comprising a first pixel driving circuit and a first light emitting device; a second color pixel configured to be disposed in the non-transmissive region and including a second pixel driving circuit and a second light emitting device; as well as A transparent pixel is configured to be disposed in the transmission area and includes only a transparent light emitting device.

2. The light-emitting display device according to claim 1, wherein: The transmission area includes a light emitting area in which the transparent pixels are disposed and a non-light emitting area in which no light emitting device is disposed.

3. The light-emitting display device according to claim 1, wherein: The transparent light emitting device includes a transparent anode and a transparent cathode.

4. The light-emitting display device according to claim 3, wherein: The transparent anode is connected to an anode line arranged in parallel with a data line arranged on the substrate, and The transparent cathode is connected to a cathode line disposed on the substrate.

5. The light-emitting display device according to claim 1, wherein: The first light emitting device comprises a first anode and a common cathode, The second light emitting device comprises a second anode and the common cathode, The transparent light emitting device comprises a transparent anode and a transparent cathode, and The common cathode and the transparent cathode are separated from each other.

6. The light-emitting display device according to claim 5, wherein: The substrate is provided with a common cathode line connected to the common cathode and a cathode line connected to the transparent cathode.

7. The light-emitting display device according to claim 6, wherein: The substrate is provided with a data line for providing a data voltage to the first pixel driving circuit, The substrate is provided with a gate line for providing a gate signal to the first pixel driving circuit. The common cathode line is arranged parallel to the data line, and The cathode lines are arranged parallel to the gate lines.

8. The light-emitting display device according to claim 1, wherein: The substrate is provided with a data line for providing a data voltage to the first pixel driving circuit, The substrate is provided with a gate line for providing a gate signal to the first pixel driving circuit, and The first color pixels, the second color pixels and the transparent pixels are arranged in a row along the data lines.

9. The light-emitting display device according to claim 8, wherein: The substrate is provided with an anode line connected to a transparent anode provided in the transparent pixel, and The anode lines are arranged on the substrate in parallel with the data lines.

10. The light emitting display device according to claim 8, wherein: The substrate is further provided with another data line for supplying a data voltage to the second pixel driving circuit, and The gate line connected to the first pixel driving circuit is connected to the second pixel driving circuit.

11. The light emitting display device according to claim 8, wherein: The substrate is also provided with another gate line connected to the second pixel driving circuit, and The data line is connected to the second pixel driving circuit.

12. The light-emitting display device according to claim 1, wherein: The transparent pixel is not provided with a pixel driving circuit.

13. The light-emitting display device according to claim 1, wherein: The substrate is provided with a data line for providing a data voltage to the first pixel driving circuit, A first color pixel, a second color pixel and a transparent pixel are arranged along the data line, The transparent light emitting device constituting the transparent pixel includes a transparent anode and a transparent cathode, and The transparent pixels are divided into a first group and a second group along the data line.

14. The light emitting display device according to claim 13, wherein: The substrate is provided with a first group of anode lines connected to transparent anodes included in the first group of transparent pixels and a second group of anode lines connected to transparent anodes included in the second group of transparent pixels, and The first group of anode lines and the second group of anode lines are disposed along the data lines and are adjacent to each other.

15. The light emitting display device according to claim 14, wherein: The substrate is divided into a display area and a non-display area, the display area is provided with the first color pixel, the second color pixel and the transparent pixel, and the non-display area surrounds the display area. The display area is provided with cathode lines, the cathode lines are connected to the transparent cathode in a direction different from the direction in which the data lines are provided, and The non-display area is provided with a first group of cathode lines connected to cathode lines included in the first group of transparent pixels and a second group of cathode lines connected to cathode lines included in the second group of transparent pixels.

16. The light-emitting display device according to claim 15, wherein: A cathode voltage is sequentially supplied to the first group of cathode lines and the second group of cathode lines.

17. The light emitting display device according to claim 16, wherein: while supplying a cathode voltage to the first group of cathode lines, supplying an anode voltage to the first group of anode lines, and While the cathode voltage is supplied to the second group of cathode lines, the anode voltage is supplied to the second group of anode lines.

18. The light emitting display device according to claim 16, wherein: When the cathode lines are divided into the first to n-th groups of cathode lines, a cathode voltage is supplied to each of the first to n-th groups of cathode lines during a 1 / n period of a frame period, wherein n is a natural number less than the number of cathode lines.

19. The light-emitting display device according to claim 16, further comprising: a gate driver configured to provide a gate signal to the first pixel driving circuit; as well as A cathode driver is configured to sequentially provide cathode voltages to the cathode lines.

20. The light emitting display device according to claim 13, wherein: The transparent pixels included in the first group of transparent pixels simultaneously output light, and the transparent pixels included in the second group of transparent pixels simultaneously output light.

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