Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a display panel; a cover panel disposed under the display panel and including a heat dissipation layer; the first release film is arranged below the covering panel, and a step difference exists between the first release film and the edge of the covering panel; and a second release film disposed under the first release film and having a step difference with an edge of the first release film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0135399 filed on October 11, 2023 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] The display device visually displays data. The display device may provide an image by using a light emitting diode. The use of the display device has been diversified, and various designs have been tried to improve the quality of the display device. Summary of the invention

[0005] Embodiments include a display device and a method of manufacturing the display device.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the disclosure.

[0007] According to an embodiment, a display device may include: a display panel; a cover panel, arranged under the display panel and including a heat dissipation layer; a first release film, arranged under the cover panel and having a step difference with an edge of the cover panel; and a second release film, arranged under the first release film and having a step difference with an edge of the first release film.

[0008] According to an embodiment, in a thickness direction of the display panel, the thickness of the first release film may be in a range of about 10 μm to about 20 μm.

[0009] According to an embodiment, at least a portion of the cover panel may be exposed due to the step difference from the edge of the first release film.

[0010] According to an embodiment, a step difference may be formed between the first release film and an edge of the heat dissipation layer of the cover panel.

[0011] According to an embodiment, the heat dissipation layer may include copper (Cu).

[0012] According to an embodiment, the cover panel may further include a cushion layer disposed on the heat dissipation layer.

[0013] According to an embodiment, a step difference may be formed between edges of the cover panel and the display panel.

[0014] According to an embodiment, the display device may further include a cover glass disposed on the display panel.

[0015] According to an embodiment, a step difference may be formed between the cover glass and the edge of the display panel.

[0016] According to an embodiment, at least a portion of the cover glass may be exposed due to the step difference from the edge of the display panel.

[0017] According to an embodiment, the display device may further include a coating layer disposed on a portion of the heat dissipation layer of the cover panel exposed by the first release film.

[0018] According to an embodiment, the coating may include propane (C 3 H 8 ) and butane (C 4 H 10 ) at least one of.

[0019] According to an embodiment, the coating layer may be disposed in at least a portion of one side of the first release film.

[0020] According to an embodiment, a thickness of the coating layer may be less than or equal to about 20 μm in a thickness direction of the display panel.

[0021] According to an embodiment, the coating layer may be disposed at one side of the cover panel and at least a portion of a lower surface of the display panel and one side of the display panel.

[0022] According to an embodiment, a method for manufacturing a display device may include: arranging a cover panel including a heat dissipation layer on a display panel; arranging a first release film on the cover panel so as to form a step difference with an edge of the cover panel; arranging a second release film on the first release film so as to form a step difference with an edge of the first release film; and forming a coating by applying a coating-forming material on the heat dissipation layer of the cover panel at a distance of approximately 0.1 mm from the edge of the first release film.

[0023] According to an embodiment, in a thickness direction of the display panel, the thickness of the first release film may be in a range of about 10 μm to about 20 μm.

[0024] According to an embodiment, the coating may include propane (C 3 H 8 ) and butane (C 4 H 10 ) at least one of.

[0025] According to an embodiment, the coating layer may be provided on a portion of the heat dissipation layer of the cover panel.

[0026] According to an embodiment, the method may further include forming a cover glass under the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic plan view of the rear side of the display device;

[0029] Figure 2 is a schematic cross-sectional view of at least a portion of one side of a display device in which a coating is disposed;

[0030] Figures 3 to 7 is a schematic cross-sectional view illustrating a method of manufacturing a display device;

[0031] Figure 8 is a photograph schematically showing the thickness of a coating layer applied on the upper portion of the heat dissipation layer;

[0032] Fig. 9 is a schematic diagram of an equivalent circuit of a pixel; and

[0033] Fig.10 is a schematic cross-sectional view of a display device. DETAILED DESCRIPTION

[0034] Now will refer to embodiment in detail, its example is shown in the accompanying drawings, wherein the same reference numerals always indicate the same element.In this regard, embodiment can have different forms and should not be construed as being limited to the description set forth herein.Therefore, the embodiment is described below only by reference to the accompanying drawings to explain the various aspects of the specification.As used herein, the term "and / or" includes any combination and all combinations of one or more associated listed items.In the entire disclosure, the statement "at least one (person / kind) of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or their variants.

[0035] Since the present disclosure allows various variations and many embodiments, specific embodiments will be shown in the drawings and described in the detailed description. The effects and features of the present disclosure, and methods for achieving these effects and features, will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and may be embodied in various forms.

[0036] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are denoted by the same reference numerals throughout and their repeated description is omitted.

[0037] In the specification, the terms “first” and “second” are not used in a limiting sense but are used to distinguish one component from another.

[0038] As used herein, the singular expressions “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0039] It will also be understood that the terms “comprises” and / or “comprising” as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0040] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, when an element is referred to as being "in contact with" or "contacted to" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element, or "indirectly in contact with" or "directly in contact with" the other element.

[0041] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. For example, because the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the present disclosure is not limited thereto.

[0042] When a specific embodiment can be implemented differently, the order of a specific process can be performed differently from the order described. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the order described.

[0043] In the present specification, the expression "A and / or B" may mean A, B, or A and B. In addition, the expression "at least one of A and B" may mean A, B, or A and B.

[0044] In the embodiments hereinafter, it will be understood that when an element, region or layer is referred to as being connected to another element, region or layer, the element, region or layer may be directly and / or indirectly connected to the other element, region or layer. For example, it will be understood in this specification that when an element, region or layer is referred to as being in contact with or electrically connected to another element, region or layer, the element, region or layer may be directly and / or indirectly in contact with or electrically connected to the other element, region or layer.

[0045] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broad sense. For example, the x-axis direction, the y-axis direction, and the z-axis direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0046] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0047] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined in this specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technical field, and should not be interpreted in an idealized or overly formal sense.

[0048] Figure 1 is a schematic plan view of the rear side of the display device 1 .

[0049] Reference Figure 1 The release film 500 may be disposed on the display panel 10 ( Figure 2 ). The release film 500 may not be arranged in at least a portion of one side of the display device 1. The coating layer 800 may be arranged in at least a portion of one side of the display device 1 where the release film 500 is not provided. The coating layer 800 may have antistatic properties.

[0050] The sound key or the power key may be arranged in at least a portion of one side of the display device 1. In the case where a person touches the sound key or the power key by hand, an antistatic effect may occur in at least a portion of one side of the display device 1, thereby causing a defect in the display device 1. In an embodiment, in the case where a coating 800 having an antistatic property is provided in at least a portion of the display device 1, even without contact by hand, the occurrence of antistatic can be prevented, and the reliability and quality of the display device 1 can be improved.

[0051] Figure 2 is a display device 1 ( Figure 1 ) is a schematic cross-sectional view of at least a portion of one side of a device in which a coating 800 is disposed. Specifically, Figure 2 It is along Figure 1 Schematic cross-sectional view of one side of the display device 1 taken along line II'.

[0052] Reference Figure 2 , the cover glass 700 may be disposed on the display panel 10 (e.g., in the z direction). The cover panel 600 including the heat dissipation layer 601 may be disposed under the display panel 10. The heat dissipation layer 601 may include copper (Cu). The edges of the cover glass 700 and the display panel 10 may have a step difference. Due to the step difference with the edge of the display panel 10, at least a portion of the lower surface of the cover glass 700 may be exposed.

[0053] The cover panel 600 may include a pad layer 602 disposed on the heat dissipation layer 601 (e.g., in the z direction). The cover panel 600 including the pad layer 602 and the heat dissipation layer 601 may be arranged under the display panel 10 (e.g., in the −z direction) to protect the display panel 10 from the display device 1 ( Figure 1 ) external pressure and prevent the temperature of the rear side of the display device 1 from increasing due to the heat generated in the display device 1, thereby improving the quality and reliability of the display device 1.

[0054] The release film 500 may be disposed below the cover panel 600 (e.g., in the -z direction). The release film 500 may include a first release film 501 and a second release film 502. The first release film 501 may contact the lower surface of the heat dissipation layer 601 of the cover panel 600. The first release film 501 and the edge of the cover panel 600 may have a step difference. For example, the first release film 501 may form a step difference with the edge of the heat dissipation layer 601 of the cover panel 600. Due to the step difference between the edge of the cover panel 600 and the first release film 501, at least a portion of the lower surface of the cover panel 600 may be exposed. For example, due to the step difference between the edge of the cover panel 600 and the first release film 501, at least a portion of the lower surface of the heat dissipation layer 601 of the cover panel 600 may be exposed.

[0055] The second release film 502 may be disposed (e.g., in the -z direction) below the first release film 501. The edges of the first release film 501 and the second release film 502 may have a step difference. That is, due to the step difference with the edge of the second release film 502, at least a portion of the lower surface of the first release film 501 may be exposed.

[0056] In an embodiment, the thickness t1 of the first release film 501 may be in the range of about 10 μm to about 20 μm. In the case where the thickness t1 of the first release film 501 is less than about 10 μm, it may not be easy to manufacture the release film, resulting in defects. Since the step difference between the first release film 501 and the lower surface of the heat dissipation layer 601 of the cover panel 600 is relatively small, when the coating forming material 800s ( Figure 6 ) is applied onto the heat dissipation layer 601, the coating forming material 800s may be squeezed onto the first release film 501 to form the coating layer 800 on an unnecessary portion (e.g., on the first release film 501). In the case where the thickness t1 of the first release film 501 is greater than 20 μm, the coating forming material 800s may be gathered together at one side of the first release film 501, and thus, the thickness t2 of the coating layer 800 may be greater than 20 μm. In the case where the thickness t2 of the coating layer 800 is greater than 20 μm, when the set including the cover panel 600, the cover glass 700, the coating layer 800 and the display panel 10 is attached to the display device 1 ( Figure 1 ), pressure may be inappropriately applied to the display device 1 ( Figure 1 ) of the rest of the display device 1, thereby reducing the connection force between the kit and the rest of the display device 1. However, the present disclosure is not limited thereto.

[0057] The coating layer 800 may be disposed on the heat dissipation layer 601 of the cover panel 600 exposed due to the step difference with the edge of the first release film 501. The coating layer 800 may have antistatic properties. The coating layer 800 may include propane (C 3 H 8 ) and butane (C 4 H 10 ). The coating layer 800 may be disposed on at least a portion of one side of the first release film 501. The coating layer 800 may also be disposed on at least a portion of one side of the cover panel 600, at least a portion of the lower surface of the display panel 10, one side of the display panel 10, and at least a portion of the lower surface of the cover glass 700.

[0058] The thickness t2 of the coating layer 800 may be less than or equal to about 20 μm. In the case where the thickness t2 of the coating layer 800 is greater than 20 μm, when the kit is attached to the display device 1 ( Figure 1), pressure may be inappropriately applied to the display device 1 ( Figure 1 ) of the rest of the display device 1, thereby reducing the connection force between the kit and the rest of the display device 1.

[0059] In the case where the release film of the display device 1 includes a single release film, the thickness of the single release film may be about 85 μm. In the case where the coating-forming material 800s is applied on the heat dissipation layer 601, the coating-forming material 800s may be gathered at one side of the single release film, and therefore, the thickness of the coating layer 800 may be greater than 20 μm.

[0060] In an embodiment, the edges of the first release film 501 and the second release film 502 may have a step difference, and the thickness t1 of the first release film 501 may be in the range of about 10 μm to about 20 μm. In the case where the thickness t1 of the first release film 501 is in the range of about 10 μm to about 20 μm, when the coating forming material 800s ( Figure 6 ) when forming the coating layer 800, even if the coating layer forming material 800s is gathered at one side of the first release film 501 or is squeezed onto the first release film 501, the thickness t2 of the coating layer 800 may be less than or equal to about 20 μm.

[0061] Figures 3 to 7 is a diagram showing the manufacturing process of the display device 1 ( Figure 1 ) is a schematic cross-sectional view of the method. Figure 8 is a schematic diagram showing the heat dissipation layer 601 ( Figure 7 ) of the upper coating 800( Figure 7 ) of the thickness of the photo. Figures 3 to 7 is a schematic cross-sectional view showing a method of manufacturing the display device 1 and a stacked structure of the display device 1, and the directions of the upper and lower parts may be different from Figure 2 direction of the display device 1.

[0062] Reference Figures 3 to 7 , a cover panel 600 including a heat dissipation layer 601 may be disposed on the display panel 10. The cover panel 600 may include a heat dissipation layer 601 and a pad layer 602. The cover glass 700 may be disposed below the display panel 10 (e.g., in the z direction). The first release film 501 may be disposed on the cover panel 600 to have a step difference with the cover panel 600. For example, the first release film 501 may be disposed on the heat dissipation layer 601 of the cover panel 600 to have a step difference with the heat dissipation layer 601 of the cover panel 600.

[0063] The second release film 502 may be disposed on the first release film 501 to have a step difference with an edge of the first release film 501. Due to the step difference with the second release film 502, at least a portion of an upper surface of the first release film 501 may be exposed.

[0064] The coating layer 800 may be formed by applying a coating forming material 800s from a coater on the heat dissipation layer 601 of the cover panel 600, the coater being spaced approximately 0.1 mm from the edge of the first release film 501. The shortest distance t3 between the edge of the first release film 501 and the coater may be approximately 0.1 mm. The coating forming material 800s may be coated at a position spaced approximately 0.1 mm from the edge of the first release film 501, and thus, the coated coating forming material 800s may be prevented from being squeezed onto the first release film 501 and coated on the upper portion of the first release film 501.

[0065] The thickness t1 of the first release film 501 may be in the range of about 10 μm to about 20 μm. In the case where the thickness t1 of the first release film 501 is less than about 10 μm, it may not be easy to manufacture the release film, resulting in defects. Since the step difference occurring between the first release film 501 and the upper surface of the heat dissipation layer 601 of the cover panel 600 is relatively small, during the process of applying the coating forming material 800s to the heat dissipation layer 601, the coating forming material 800s may be squeezed onto the first release film 501 to form the coating 800 on an unnecessary portion (e.g., on the first release film 501). In the case where the thickness t1 of the first release film 501 is greater than 20 μm, the coating forming material 800s may gather together at one side of the first release film 501, and therefore, the thickness t2 of the coating 800 may be greater than 20 μm. In the case where the thickness t2 of the coating 800 is greater than 20 μm, when the kit is attached to the display device 1 ( Figure 1 ), pressure may be inappropriately applied to the display device 1 ( Figure 1 ) of the rest of the display device 1, thereby reducing the connection force between the kit and the rest of the display device 1. However, the present disclosure is not limited thereto.

[0066] Reference Figure 8 Combined with Figure 6 and Figure 7 , even in the case where a portion of the applied coating-forming material 800s is gathered at one side of the first release film 501, the thickness t2 of the coating 800 at one side of the first release film 501 may be about 14 μm or about 16 μm. For example, the thickness t2 of the coating 800 at one side of the first release film 501 may be less than or equal to about 20 μm.

[0067] Fig. 9is a schematic diagram of the equivalent circuit of a pixel.

[0068] Reference Fig. 9 , the pixel P may include an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit light such as red light, green light, or blue light via the organic light emitting diode OLED, or emit red light, green light, blue light, or white light.

[0069] The second thin film transistor T2 may be a switching thin film transistor, may be connected to the scan line SL and the data line DL, and may be configured to transfer a data voltage supplied from the data line DL to the first thin film transistor T1 based on a switching voltage supplied from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and a first power supply voltage ELVDD supplied from the driving voltage line PL.

[0070] The first thin film transistor T1 may be a driving thin film transistor, may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the value of the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a brightness according to the driving current. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED may receive a second power supply voltage ELVSS.

[0071] Fig. 9 The pixel circuit PC is shown to include two thin film transistors and one storage capacitor. However, the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously modified according to the design of the pixel circuit PC. For example, the pixel circuit PC may include two thin film transistors as described above, or four, five or more thin film transistors.

[0072] Fig.10 is a display device 1 ( Figure 1 ). Specifically, Fig.10 It is along Figure 1 Schematic cross-sectional view of the display device 1 taken along line II-II′.

[0073] Reference Fig.10The substrate 100 may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c and a second barrier layer 100d. In an embodiment, the first base layer 100a, the first barrier layer 100b, the second base layer 100c and the second barrier layer 100d may be stacked in sequence in the thickness direction of the substrate 100.

[0074] At least one of the first base layer 100a and the second base layer 100c may include a polymer resin including polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or the like.

[0075] The first barrier layer 100b and the second barrier layer 100d as barrier layers for preventing penetration of external foreign matter may include a material including silicon nitride (SiN x ), silicon oxide (SiO 2 ) and / or multilayer or single layer of inorganic materials of silicon oxynitride (SiON).

[0076] The buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may include a SiN x , SiON and SiO 2 of an inorganic insulating material, and may have a single-layer or multi-layer structure including the inorganic insulating material.

[0077] The inorganic insulating layer IIL may be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0078] The pixel circuit PC may be arranged in the display area DA. The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0079] The semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may include polycrystalline silicon. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The semiconductor layer Act may include a channel region and a drain region and a source region respectively disposed on both sides of the channel region.

[0080] The gate electrode GE may be disposed on the semiconductor layer Act. The gate electrode GE may overlap with the channel region in a plan view. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including Mo, Al, Cu, Ti, etc., and may include a multilayer or a single layer including a conductive material.

[0081] The first gate insulating layer 112 may be disposed between the semiconductor layer Act and the gate electrode GE. The first gate insulating layer 112 may include a layer such as SiO 2 、SiN x , SiON, Alumina (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO) inorganic insulating material.

[0082] The second gate insulating layer 113 may be disposed on the gate electrode GE. The second gate insulating layer 113 may cover the gate electrode GE. The second gate insulating layer 113 may include a layer such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 Or inorganic insulating materials of ZnO.

[0083] The second capacitor plate CE2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113. The second capacitor plate CE2 may overlap the gate electrode GE in a plan view. The gate electrode GE and the second capacitor plate CE2 overlapping each other and the second gate insulating layer 113 between the gate electrode GE and the second capacitor plate CE2 may form a storage capacitor Cst. For example, the gate electrode GE may serve as the first capacitor plate CE1 of the storage capacitor Cst.

[0084] As described above, the storage capacitor Cst may overlap with the thin film transistor TFT in a plan view. However, the present disclosure is not limited thereto. For example, the storage capacitor Cst may not overlap with the thin film transistor TFT in a plan view. For example, the first capacitor plate CE1 of the storage capacitor Cst may be an element separated from the gate electrode GE of the thin film transistor TFT and may be spaced apart from the gate electrode GE of the thin film transistor TFT in a plan view.

[0085] The second capacitor plate CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (ND), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may have a single-layer or multi-layer structure including the above materials.

[0086] The interlayer insulating layer 114 may be disposed on the second capacitor plate CE2. The interlayer insulating layer 114 may cover the second capacitor plate CE2. The interlayer insulating layer 114 may include a material such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 or an inorganic insulating material such as ZnO. The interlayer insulating layer 114 may have a single layer or a multilayer structure including an inorganic insulating material.

[0087] The drain electrode DE and the source electrode SE may each be disposed on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may each be connected to the semiconductor layer Act through a contact hole included in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may include a material having high conductivity. The drain electrode DE and the source electrode SE may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multilayer or a single layer including a conductive material. For example, the drain electrode DE and the source electrode SE may have a multilayer structure of Ti / Al / Ti.

[0088] The organic insulating layer OIL may be disposed on the inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. Fig.10 It is shown that the display panel 10 includes two organic insulating layers, but the present disclosure is not limited thereto. In another embodiment, the display panel may include three or four organic insulating layers.

[0089] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include an organic insulating material such as a general polymer such as polystyrene (PS), polymethyl methacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a mixture thereof.

[0090] The connection electrode CM may be disposed on the first organic insulating layer 115, and the connection electrode CM may be connected to the drain electrode DE or the source electrode SE through the contact hole of the first organic insulating layer 115. The connection electrode CM may include a material having high conductivity. The connection electrode CM may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a multilayer or single layer including a conductive material. For example, the connection electrode CM may have a multilayer structure of Ti / Al / Ti.

[0091] The second organic insulating layer 116 may be disposed on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 and the first organic insulating layer 115 may include the same material or different materials.

[0092] The light emitting diode may be disposed on the second organic insulating layer 116. In an embodiment, an organic light emitting diode OLED may be disposed on the second organic insulating layer 116. In another embodiment, although not shown, an inorganic light emitting diode may be disposed on the second organic insulating layer 116.

[0093] The organic light emitting diode OLED may emit red light, green light, or blue light, or emit red light, green light, blue light, or white light. The organic light emitting diode OLED may include a first electrode 211, an emission layer 212b, a functional layer 212f, a second electrode 213, and a capping layer 215. The first electrode 211 may be a pixel electrode (e.g., an anode) of the organic light emitting diode OLED, and the second electrode 213 may be an opposite electrode (e.g., a cathode) of the organic light emitting diode OLED.

[0094] The first electrode 211 may be disposed on the second organic insulating layer 116. The first electrode 211 may be electrically connected to the connection electrode CM through a contact hole defined in the second organic insulating layer 116. The first electrode 211 may include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or zinc aluminum oxide (AZO). In an embodiment, the first electrode 211 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof. In an embodiment, the first electrode 211 may also include a conductive oxide including ITO, IZO, ZnO or In above / below the above reflective layer. 2 O 3 For example, the first electrode 211 may have a multi-layer structure of ITO / Ag / ITO.

[0095] A pixel defining layer 118 including an opening exposing at least a portion of the first electrode 211 may be disposed on the first electrode 211. An emission region of light emitted from the organic light emitting diode OLED may be defined by the opening of the pixel defining layer 118. For example, a width of the opening may correspond to a width of the emission region.

[0096] The pixel defining layer 118 may include an organic insulating material. In another embodiment, the pixel defining layer 118 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide. In another embodiment, the pixel defining layer 118 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining layer 118 may include a light blocking material. The light blocking material may include a resin or paste containing carbon black, carbon nanotubes, black pigments, metal particles such as Ni, Al, Mo, and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). In the case where the pixel defining layer 118 includes a light blocking material, external light reflection caused by a metal structure disposed below the pixel defining layer 118 may be reduced.

[0097] The spacer 119 may be disposed on the pixel defining layer 118. The spacer 119 may include an organic insulating material such as polyimide. In another embodiment, the spacer 119 may include an organic insulating material such as SiN x or SiO 2 of inorganic insulating materials, or may include organic insulating materials and inorganic insulating materials.

[0098] In an embodiment, the spacer 119 and the pixel defining layer 118 may include the same material and may be formed together through a mask process using a half-tone mask. In another embodiment, the spacer 119 and the pixel defining layer 118 may include different materials.

[0099] The emission layer 212b may be disposed in the opening of the pixel defining layer 118. The emission layer 212b may include a high molecular weight or low molecular weight organic material that emits colored light.

[0100] The functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be arranged between the first electrode 211 and the emission layer 212b, and the second functional layer 212c may be arranged between the emission layer 212b and the second electrode 213. However, the present disclosure is not limited thereto, and in another embodiment, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. Hereinafter, an embodiment in which the first functional layer 212a and the second functional layer 212c are each arranged will be described in detail.

[0101] The first functional layer 212a may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Similar to the second electrode 213 to be described below, the first functional layer 212a and / or the second functional layer 212c may be a common layer that completely covers the substrate 100.

[0102] The second electrode 213 may be disposed on the functional layer 212f. The second electrode 213 may include a conductive material having a low work function. For example, the second electrode 213 may include a transparent (or semi-transmissive and semi-reflective) layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. In another embodiment, the second electrode 213 may also include a conductive material including ITO, IZO, ZnO, or In on the transparent (or semi-transmissive and semi-reflective) layer. 2 O 3 layer.

[0103] In an embodiment, a capping layer 215 may be disposed on the second electrode 213. The capping layer 215 may include LiF, an inorganic material, and / or an organic material.

[0104] The encapsulation layer 300 may be disposed on the organic light emitting diode OLED. The encapsulation layer 300 may cover the organic light emitting diode OLED. The encapsulation layer 300 may be disposed on the second electrode 213 and / or the capping layer 215. In an embodiment, the encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Fig.10 An encapsulation layer 300 including a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 stacked in sequence is shown.

[0105] The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may each include Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZrO 2 、SiO 2 、SiN x At least one of and SiON. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each be a single layer or a multilayer including the above materials. The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may be an acrylic-based resin, an epoxy-based resin, polyimide, polyethylene, etc. In an embodiment, the organic encapsulation layer 320 may include an acrylic-based resin.

[0106] The input sensing layer 400 may be disposed on the encapsulation layer 300. The input sensing layer 400 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460.

[0107] In an embodiment, the first touch insulating layer 410 may be disposed on the second inorganic encapsulation layer 330, and the second touch insulating layer 420 may be disposed on the first touch insulating layer 410. In an embodiment, the first touch insulating layer 410 and the second touch insulating layer 420 may each include an inorganic insulating material and / or an organic insulating material. For example, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material such as SiO 2 、SiN x and / or SiON inorganic insulating material.

[0108] In an embodiment, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, the first touch insulating layer 410 may be omitted, and the second touch insulating layer 420 may be disposed on the second inorganic encapsulation layer 330, and the first conductive layer 430 may be disposed on the second touch insulating layer 420.

[0109] The first conductive layer 430 may be disposed on the second touch insulating layer 420, and the third touch insulating layer 440 may be disposed on the first conductive layer 430. In an embodiment, the third touch insulating layer 440 may include an inorganic insulating material and / or an organic insulating material. For example, the third touch insulating layer 440 may include an inorganic insulating material such as SiO 2 、SiN x and / or SiON inorganic insulating material.

[0110] The second conductive layer 450 may be disposed on the third touch insulating layer 440. The touch electrode TE of the input detection layer 400 may have a structure in which the first conductive layer 430 is connected to the second conductive layer 450. In another embodiment, the touch electrode TE may be formed in one of the first conductive layer 430 and the second conductive layer 450, and may include a metal wire in the corresponding conductive layer. The first conductive layer 430 and the second conductive layer 450 may each include at least one of Al, Cu, Ti, MO, and ITO, and may include a multilayer or a single layer including the above materials. For example, the first conductive layer 430 and the second conductive layer 450 may each have a three-layer structure of Ti / Al / Ti.

[0111] In an embodiment, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0112] In the embodiment, the first release film 501 ( Figure 2 ) and the second release film 502 ( Figure 2 ) may have a step difference, and the thickness t1 ( Figure 2) may be in the range of about 10 μm to about 20 μm. In the case where the thickness t1 of the first release film 501 is in the range of about 10 μm to about 20 μm, when the heat dissipation layer 601 ( Figure 2 ) is coated with a coating forming material for 800s ( Figure 6 ) forms a coating 800( Figure 2 ), even in the case where the coating-forming material 800s is gathered at one side of the first release film 501 or is pressed onto the first release film 501, the thickness t2 ( Figure 2 ) can also be less than or equal to about 20 μm.

[0113] The thickness t2 of the coating layer 800 may be less than or equal to about 20 μm to allow appropriate application of pressure to attach the kit to the rest of the display device 1 and maintain the connection force between the kit and the rest of the display device 1 , thereby improving the quality and reliability of the display device 1 .

[0114] According to the embodiment, a display device having improved reliability and quality and a method of manufacturing the display device may be realized. However, the scope of the present disclosure is not limited by these effects.

[0115] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the above disclosed embodiments can be implemented separately or in combination with each other.

[0116] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and should be interpreted as all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: Display panel; A cover panel, disposed below the display panel and comprising a heat dissipation layer; A first release film, disposed under the cover panel and having a step difference with an edge of the cover panel; and The second release film is disposed below the first release film and has a step difference with an edge of the first release film.

2. The display device according to claim 1, wherein: In the thickness direction of the display panel, the thickness of the first release film is in the range of 10 μm to 20 μm.

3. The display device according to claim 1, wherein: At least a portion of the cover panel is exposed due to the step difference from the edge of the first release film.

4. The display device according to claim 1, wherein: A step difference is formed between the first release film and an edge of the heat dissipation layer of the cover panel.

5. The display device according to claim 1, wherein: The heat dissipation layer includes copper.

6. The display device according to claim 1, wherein: The cover panel further includes a cushion layer disposed on the heat dissipation layer.

7. The display device according to claim 1, wherein: A step difference is formed between edges of the cover panel and the display panel.

8. The display device according to claim 1, wherein: The display device further includes: The cover glass is arranged on the display panel.

9. The display device according to claim 8, wherein: A step difference is formed between the cover glass and an edge of the display panel.

10. The display device according to claim 9, wherein: At least a portion of the cover glass is exposed due to the step difference from the edge of the display panel.

11. The display device according to claim 1, wherein: The display device further includes: A coating layer is disposed on a portion of the heat dissipation layer of the cover panel exposed by the first release film.

12. The display device according to claim 11, wherein: The coating includes at least one of propane and butane.

13. The display device according to claim 11, wherein: The coating layer is disposed in at least a portion of one side of the first release film.

14. The display device according to claim 11, wherein: In the thickness direction of the display panel, the thickness of the coating layer is less than or equal to 20 μm.

15. The display device according to claim 11, wherein: The coating layer is disposed at one side of the cover panel and at least a portion of a lower surface of the display panel and one side of the display panel.

16. A method for manufacturing a display device, wherein: The method comprises: arranging a cover panel including a heat dissipation layer on the display panel; Arranging a first release film on the cover panel so as to form a step difference with an edge of the cover panel; placing a second release film on the first release film so as to form a step difference with an edge of the first release film; and A coating layer is formed by applying a coating-forming material on the heat dissipation layer of the cover panel at a distance of 0.1 mm from the edge of the first release film.

17. The method according to claim 16, wherein: In the thickness direction of the display panel, the thickness of the first release film is in the range of 10 μm to 20 μm.

18. The method according to claim 16, wherein: The coating includes at least one of propane and butane.

19. The method according to claim 16, wherein: The coating layer is disposed on a portion of the heat dissipation layer of the cover panel.

20. The method according to claim 19, wherein: The method further comprises: A cover glass is formed under the display panel.

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