Group III-V compound semiconductor light-emitting element and method for manufacturing group III-V compound semiconductor light-emitting element

Abstract

Provided is a group III-V compound semiconductor light-emitting element which has better light-emitting power per injection power than conventional light-emitting elements. This group III-V compound semiconductor light-emitting element has an n-type cladding layer, a light-emitting layer, and a p-type cladding layer in this order, and has an undoped electron blocking layer between the light-emitting layer and the p-type cladding layer, the light-emitting layer having a laminated structure in which a barrier layer and a well layer are repeatedly laminated, and in the conduction band, the p-type cladding layer has an n-type cladding layer, and the p-type cladding layer has a p-type cladding layer. The band gap of the electron blocking layer is larger than the band gap of the barrier layer and the band gap of the p-type cladding layer, the band gap of the p-type cladding layer is larger than the band gap of the barrier layer, and in the valence band, the band gap of the electron blocking layer is located between the band gap of the barrier layer and the band gap of the cladding layer.

Description

Technical Field

[0001] The present invention relates to a III-V compound semiconductor light-emitting element and a method for manufacturing the III-V compound semiconductor light-emitting element. Background Art

[0002] As the semiconductor material of the semiconductor layer in the semiconductor light-emitting element, III-V compound semiconductors such as InGaAsP, InGaAlAs, and InAsSbP are used. By adjusting the composition ratio of the light-emitting layer formed by the III-V compound semiconductor material, the light-emitting wavelength of the semiconductor light-emitting element can be widely adjusted in the range of green to infrared. For example, if the infrared light-emitting semiconductor light-emitting element uses the infrared region with a wavelength of more than 750nm as the light-emitting wavelength, it can be widely used in sensors, gas analysis, monitoring cameras, communications, etc.

[0003] Patent document 1 describes a light-emitting element, in which, in a semiconductor stack obtained by stacking multiple layers of InGaAsP-based III-V compound semiconductor layers containing at least In and P, the semiconductor stack sequentially includes an n-type cladding layer, an active layer and a p-type cladding layer, and the thickness of the p-type cladding layer is set to 2400 to 9000 nm.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-186539 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] In recent years, it has been sought to further improve the luminous efficiency of light-emitting elements. The present inventors have conducted research to further improve the luminous power per unit injected power compared to the structure of Patent Document 1. Therefore, the purpose of the present invention is to obtain a III-V compound semiconductor light-emitting element with better luminous power per unit injected power than conventional light-emitting elements.

[0009] Solutions for solving problems

[0010] The present inventors have conducted intensive studies to achieve the above-mentioned object, and as a result, have completed the present invention described below. That is, the gist of the present invention is as follows.

[0011] (1) A III-V compound semiconductor light-emitting element, characterized in that it has an n-type cladding layer, a light-emitting layer, and a p-type cladding layer in this order,

[0012] An undoped electron blocking layer is provided between the light emitting layer and the p-type cladding layer.

[0013] The light emitting layer has a stacked structure in which barrier layers and well layers are repeatedly stacked, wherein:

[0014] (i) in the conduction band, the band gap (Ec) of the electron blocking layer is larger than the band gap (Ecb) of the potential barrier layer and the band gap (Ecs) of the p-type cladding layer, and the band gap (Ecs) of the p-type cladding layer is larger than the band gap (Ecb) of the potential barrier layer,

[0015] (ii) In the valence band, the band gap (Ev) of the electron blocking layer is located between the band gap (Evb) of the barrier layer and the band gap (Evs) of the p-type cladding layer.

[0016] (2) The III-V compound semiconductor light-emitting device according to (1) above, wherein the electron blocking layer and the p-type cladding layer have main group V elements different from each other.

[0017] (3) A III-V compound semiconductor light-emitting element according to (1) or (2), wherein an undoped spacer layer is provided between the electron blocking layer and the p-type cladding layer, and the main Group V elements of the p-type cladding layer and the spacer layer are the same.

[0018] (4) The III-V compound semiconductor light-emitting device according to any one of (1) to (3) above, wherein the thickness of the spacer layer is 300 nm or less.

[0019] (5) The Group III-V compound semiconductor light-emitting device according to any one of (1) to (4), wherein the electron blocking layer is adjacent to the p-type cladding layer.

[0020] (6) A method for manufacturing a Group III-V compound semiconductor light-emitting device according to any one of (1) to (5), comprising:

[0021] A step of forming the aforementioned n-type cladding layer;

[0022] forming the light-emitting layer on the n-type cladding layer;

[0023] forming the electron blocking layer on the light-emitting layer; and

[0024] A step of forming the p-type cladding layer on the electron blocking layer.

[0025] Effects of the Invention

[0026] According to the present invention, it is possible to provide a Group III-V compound semiconductor light-emitting element having a better light-emitting power per unit injected power than a conventional light-emitting element, and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a diagram showing an example of the energy band structure in the light-emitting layer and the semiconductor layers before and after it in the present embodiment calculated using simulation software.

[0028] Figure 2 This is a schematic cross-sectional view showing one mode of the main part of a III-V compound semiconductor light-emitting element based on the present invention.

[0029] Figure 3 This is a schematic cross-sectional view showing a III-V compound semiconductor light-emitting element according to an embodiment of the present invention.

[0030] Figure 4 This is a schematic cross-sectional view showing a manufacturing method of a III-V compound semiconductor light-emitting element according to an embodiment of the present invention using the bonding method.

[0031] Figure 5 This is a diagram showing the energy band structure in the light-emitting layer and the semiconductor layers before and after it in Example 1, Comparative Example 1, and Comparative Example 6 calculated using simulation software.

[0032] Figure 6 This is a diagram showing the diffusion of the dopant in the p-type cladding layer of Example 3 in the light-emitting layer. Detailed Embodiments

[0033] Before describing the embodiments of the present invention, each definition in this specification will be described.

[0034] <III-V Compound Semiconductor Layer>

[0035] First, when simply referred to as "III-V compound semiconductor" in this specification, its composition is represented by the general formula: (In a Ga b Al c )(P x As y Sb z ). Here, regarding the composition ratio of each element, the following relationship holds.

[0036] Regarding group III elements, c = 1 - a - b, 0 ≤ a ≤ 1, 0 ≤ b ≤ 1, 0 ≤ c ≤ 1.

[0037] Regarding group V elements, z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1.

[0038] The III-V compound semiconductor layer of the present invention is composed of one or more group III elements selected from the group consisting of Al, Ga, and In and one or more group V elements selected from the group consisting of As, Sb, and P.

[0039] In addition, when the III-V compound semiconductor layer is composed of one or more III-group elements selected from the group consisting of Al, Ga, and In and one V-group element selected from the group consisting of As, Sb, and P, the composition ratios of the elements show the following relationship.

[0040] Regarding the Group III elements, c=1-ab, 0≤a≤1, 0≤b≤1, 0≤c≤1.

[0041] For Group V elements, any one of x, y, and z is 1, and the other two are 0.

[0042] Furthermore, when there is one type of group V element in the III-V compound semiconductor layer in the light-emitting layer, the group III element is preferably composed of two or more elements, and more preferably composed of three elements. Furthermore, the III-V compound semiconductor layer in the electron blocking layer of the present invention is preferably composed of three or more elements. This is because if the total of the group III element and the group V element in the electron blocking layer is set to less than two elements, the composition options that can form the positional relationship between the electron blocking layer and the light-emitting layer and the electron blocking layer and the band gap of the p-type cladding layer of the present invention are limited.

[0043] Here, the electron blocking layer and the p-type cladding layer preferably have different main V group elements. The main V group elements are different from each other means that: in one layer, when one of the V group elements selected from x, y, and z exceeds 0.5, in another layer, one of the V group elements x, y, and z different from the x, y, and z selected in one layer exceeds 0.5. In order to suppress the diffusion of dopants in the p-type cladding described later, the composition ratio of the different V group elements is preferably 0.6 or more, and more preferably 0.8 or more. For example, when the main V group element of the p-type cladding is P, the main V group element of the electron blocking layer can be As.

[0044] <Lattice constants based on composition>

[0045] The calculation of the lattice constant of the mixed crystal in this specification is explained. When the lattice constant exists in two directions, vertical (growth direction) and horizontal (in-plane direction) relative to the substrate plane, the value in the vertical direction is used in this specification. First, the simple lattice constant of the mixed crystal is calculated according to Feger's law. If the InGaAsP system (i.e., the general formula: (In a Ga b )(P x As y )) is used as an example. When the composition ratio (solid ratio) is known, the physical property constant A abxy(Lattice constant based on Feger's law) Based on the physical property constants B of the four binary mixed crystals that form the basis of the pseudo-quaternary mixed crystal ax , B bx , B ay , B by (the lattice constant of the literature value in Table 1 below) and using the following formula <1> to calculate.

[0046] A abxy =a×x×B ax +b×x×B bx +a×y×B ay +b×y×B by ··· <1>

[0047] [Table 1]

[0048]

[0049] Next, for the elastic constant C 11 , C 12 , and the above formula <1> The same operation is performed to calculate (In a Ga b )(P x As y ) of the elastic constant C 11abxy , C 12abxy .

[0050] Furthermore, if the lattice constant of the growth substrate is set to a s , then the following formula is applied considering the lattice deformation based on the elastic properties of semiconductor crystals <2> , the lattice constant a (in the vertical direction) can be calculated taking into account the lattice deformation abxy .

[0051] a abxy =A abxy -2×(a s -A abxy )×C 12abxy / C 11abxy ··· <2>

[0052] Here, in this embodiment, since InP is used as the growth substrate, the lattice constant a of the growth substrate is s It is sufficient to use the lattice constant of InP.

[0053] In the case of a pseudo-ternary mixed crystal, if the general formula: (In a Ga b Al c )(As)) as an example, according to the following formula <3> , <4> The band gap Eg can be calculated abcy and the lattice constant A based on Feger's law abcy .

[0054]

[0055] A abcy =a×B ay +b×B by +c×B cy … <4>

[0056] It should be noted that even when the III-V compound semiconductor is a ternary system, a quinary system or a hexavalent system, the composition wavelength and the lattice constant can be obtained by transforming the formula according to the same idea as above. In addition, for a binary system, the values ​​described in the above literature can be used.

[0057] <Band gap calculation based on the conduction band side and valence band side of each layer>

[0058] The band structure was calculated using simulation software (SiLENSe_Version 6.4) manufactured by STR Japan by inputting the value of the composition ratio of each layer in an initial setting state. Figure 1 The energy band structures of the light-emitting layer, electron blocking layer, spacer layer and cladding layer of this embodiment calculated using the simulation software are shown in the figure. If the simulation software is used, the band gap (Ec, Ev) of the electron blocking layer, the band gap (Ecb, Evb) of the light-emitting layer barrier layer, and the band gap (Ecs, Evs) of the spacer layer and cladding layer are calculated while showing the energy band structure. It should be noted that Figure 1 The example in the figure shows the case where the band gap of the spacer layer and the cladding layer is set to be the same, so the band gap of the spacer layer and the cladding layer are made consistent. The unit of the band gap energy in the figure is eV, the symbols starting from "Ec" are the values ​​of each band gap energy in the conduction band, and the symbols starting from "Ev" are the values ​​of the band gap energy in the valence band. In addition, if the simulation software is used, while showing the energy band structure, the energy band gap Eg (eV) of each layer, the band gap difference between the barrier layer and the well layer on the conduction band side, that is, the well depth, and the band gap difference between the barrier layer and the well layer on the valence band side, that is, the well depth, are calculated. And, based on the energy band gap Eg, the following formula is calculated. <5> The wavelength λ to be converted indicates the component wavelength of each layer.

[0059] Eg=1239.8 / λ··· <5>

[0060] <Thickness and composition of each layer>

[0061] In addition, the thickness of each formed layer as a whole can be measured using an optical interference film thickness measuring instrument. Furthermore, the thickness of each layer can be calculated separately based on the cross-sectional observation of the growth layer by an optical interference film thickness measuring instrument and a transmission electron microscope. In addition, when the thickness of each layer is about several nm and is as small as the extent similar to the superlattice structure, TEM-EDS can be used to measure the thickness. Regarding the composition ratio (solid phase ratio) of each layer in this specification, the value obtained by SIMS analysis is used. Regarding the composition ratio (solid phase ratio) of each layer of the light-emitting layer, the composition ratio of the electron blocking layer, and the composition ratio of the spacer layer in this specification, the following values are used: After the uppermost layer near the light-emitting layer is exposed by etching (starting from the n-layer side), the value obtained by performing SIMS analysis (quadrupole type) along the thickness direction of the light-emitting layer. It should be noted that for the SIMS analysis result, the average element concentration value in the half-thickness range of the central part of each layer in the thickness direction of each layer is used. During manufacturing, for the layer grown in the form of a single film, the solid phase ratio is calculated by using the value obtained by converting the lattice constant measured by XRD and the emission center wavelength measured by PL into Eg, thereby determining the growth conditions presenting the target composition ratio, and the layers with the target composition ratio can be stacked using these growth conditions.

[0062] <p-type, n-type, and i-type, and doping concentration>

[0063] In this specification, the layer that functions as a p-type electrically is referred to as a p-type layer, and the layer that functions as an n-type electrically is referred to as an n-type layer. On the other hand, when specific impurities such as Si, Zn, S, Sn, and Mg are not actively added and it does not function as a p-type or n-type electrically, it is called "i-type" or "undoped". Impurities that are inevitable during the manufacturing process may be mixed in the undoped III-V compound semiconductor layer. Specifically, when the doping concentration is low (for example, less than 7.6×10 15 atoms / cm 3 ), it is regarded as "undoped" in this specification. The values of the impurity concentrations of Si, Zn, S, Sn, Mg, etc. are obtained based on SIMS analysis. Similarly, the values of the impurity concentrations ("dopant concentrations") of the n-type dopants (such as Si, S, Te, Sn, Ge, O, etc.) in the light-emitting layer are also obtained based on SIMS analysis. It should be noted that near the boundary of each semiconductor layer, the value of the doping concentration changes significantly. Therefore, the value of the doping concentration at the center in the thickness direction is set as the doping concentration value of this layer.

[0064] Hereinafter, embodiments of the present invention will be illustrated in detail with reference to the accompanying drawings. It should be noted that for the same component, the same reference numerals are basically used in principle, and repeated descriptions are omitted. In each figure, for the sake of easy explanation, the aspect ratio of the substrate and each layer is exaggeratedly shown compared with the actual ratio.

[0065] (III-V compound semiconductor light-emitting device)

[0066] Figure 2 1 shows the main parts of the III-V compound semiconductor light-emitting element 100 of the present invention. The III-V compound semiconductor light-emitting element 100 has an n-type cladding layer 31, a light-emitting layer 40, and a p-type cladding layer 71 in this order, and has an undoped electron blocking layer 43 between the light-emitting layer 40 and the p-type cladding layer 71. In addition, the light-emitting layer 40 has a stacked structure in which a barrier layer 41 and a well layer 42 are repeatedly stacked. The composition ratios of the barrier layer 41 and the well layer 42 are different from each other.

[0067] Furthermore, in the III-V compound semiconductor light-emitting element 100, (i) in the conduction band, the band gap (Ec) of the electron blocking layer 43 is larger than the band gap (Ecb) of the barrier layer 41 and the band gap (Ecs) of the p-type cladding layer 71, and the band gap (Ecs) of the p-type cladding layer 71 is larger than the band gap (Ecb) of the barrier layer 41. Furthermore, in the III-V compound semiconductor light-emitting element 100, (ii) in the valence band, the band gap (Ev) of the electron blocking layer 43 is located between the band gap (Evb) of the barrier layer 41 and the band gap (Evs) of the p-type cladding layer 71. The inventors of the present invention have discovered through experimental verification that by designing in a manner that satisfies these conditions (i) and (ii), the luminous power per unit of injected power of the III-V compound semiconductor light-emitting element 100 can be improved compared to conventional semiconductor light-emitting elements, and when comparing III-V compound semiconductor light-emitting elements having luminous wavelengths in at least the same wavelength region, a higher luminous power per unit of injected power can be achieved.

[0068] In the conduction band and the valence band, regarding the relationship between the band gaps of the electron blocking layer 43, the barrier layer 41, and the p-type cladding layer 71, if an inequality sign is used to represent the design conditions of the band gaps of the present invention, the conduction band is Ec>Ecb and Ec>Ecs, and the valence band is Evb>Ev and Ev>Evs. The difference in the values ​​of the band gaps in the inequality sign of this design condition can be set to be greater than 0.030eV. Moreover, in the band gap relationship of the conduction band, the value of Ec-Ecb is preferably greater than 0.120eV, and more preferably greater than 0.150eV. The value of Ec-Ecs is preferably greater than 0.060eV, and more preferably greater than 0.120eV. In addition, the value of Ec-Ecb is preferably greater than the value of Ec-Ecs by 0.030eV or more (the value of Ecs-Ecb is greater than 0.030eV). Furthermore, in the band gap relationship of the valence band, the value of Evb-Ev is preferably 0.060 eV or more. In addition, the value of Ev-Evs is preferably 0.060 eV or more.

[0069] In order to design the electron blocking layer 43 in such a way that the band gap (Ev) of the valence band when the undoped electron blocking layer 43 is provided is located between the band gap (Evb) of the barrier layer and the band gap (Evs) of the p-type cladding layer, it is preferred that the main V group elements of the electron blocking layer and the p-type cladding layer are different from each other. When the main V group elements of the electron blocking layer and the p-type cladding layer are the same, in the conduction band, if the band gap (Ec) of the electron blocking layer 43 is made larger than the band gap (Ecs) of the p-type cladding layer 71, the band gap (Ev) of the valence band is usually smaller than the band gap (Evs) of the p-type cladding layer, and therefore, it is difficult to make the band gap (Ev) of the valence band located between the band gap (Evb) of the barrier layer and the band gap (Evs) of the p-type cladding layer.

[0070] The main V group element in the barrier layer 41 and the well layer 42 is preferably different from that in the p-type cladding layer 71, and the main V group element is more preferably As or Sb. It is further preferred that the diffusion of the V group element at the boundary between the well layer 42 and the barrier layer 41 can be eliminated by limiting the V group element to one type. In addition, by making the main V group element different from that in the p-type cladding layer 71, although the effect is weaker than that brought about by the sandwiched electron blocking layer, the diffusion of p-type impurities in the light-emitting layer can be suppressed.

[0071] Various changes can be made as long as they are within the scope of the effect of the present invention. For example, not only is it the case that the stack formed by the barrier layer 41 and the well layer 42 is distributed throughout the entire quantum well structure as in the present embodiment, but it is also possible that the stack formed by the barrier layer 41 and the well layer 42 is a part of the quantum well structure, and peaks and valleys are set in the energy band structure by combining it with other stacks.

[0072] <Luminous Layer>

[0073] Hereinafter, each structure of the light emitting layer 40 in the embodiment of the present invention will be described in further detail.

[0074] -Film thickness-

[0075] The overall film thickness of the light-emitting layer 40 is not limited, and can be set to 0.1 μm to 8 μm, for example. In addition, the film thickness of each layer of the barrier layer 41 and the well layer 42 in the stack of the light-emitting layer 40 is also not limited, and can be set to about 1 nm or more and 15 nm or less, for example. The film thickness of each layer can be the same or different. In addition, the film thickness of each barrier layer 41 can be the same or different in the stack. The same is true for the film thickness of each well layer 42. Among them, setting the film thickness of each barrier layer 41 and the film thickness of each well layer 42 to be the same and making the light-emitting layer 40 into a superlattice structure is one of the preferred embodiments of the present invention.

[0076] -Number of stacked groups-

[0077] Reference Figure 2The number of groups of the barrier layer 41 and the well layer 42 is not limited, and can be set to 3 or more and 50 or less, for example. One end of the stack can be set as the barrier layer 41, and the other end can be set as the well layer 42. In this case, the number of groups of the barrier layer 41 and the well layer 42 is expressed as n groups (n is a natural number).

[0078] Alternatively, one end of the stack may be provided as the barrier layer 41, a well layer 42 and the barrier layer 41 may be provided as a repeated structure, and the other end may be provided as the barrier layer 41. Alternatively, both ends may be provided as the well layer 42. In this case, the number of sets of the barrier layer 41 and the well layer 42 is expressed as n (n is a natural number), and is referred to as n.5 sets. Figure 2 In the figure, both ends of the stacked body are shown as barrier layers 41.

[0079] - Composition ratio -

[0080] As long as the conditions of the difference in composition wavelength and lattice constant are met, the general formula of each layer of the barrier layer 41 and the well layer 42 is: a Ga b Al c )(P x As y Sb z) There is no limitation on the composition ratios a, b, c, x, y, and z of the III-V compound semiconductor shown. Among them, in order to suppress the deterioration of the crystallinity of the light-emitting layer 40, regarding the selection range of the composition ratios, it is preferable that the ratio of the lattice constant difference between the growth substrate and each of the barrier layer 41 and the well layer 42 in the light-emitting layer 40 is set to 1% or less. That is, the value obtained by dividing the absolute value of the lattice constant difference between the growth substrate and the barrier layer 41 by the average value of the growth substrate and the barrier layer 41, and the value obtained by dividing the absolute value of the lattice constant difference between the growth substrate and the well layer 42 by the average value of the growth substrate and the well layer 42 are both preferably 1% or less. For example, when the light-emitting center wavelength is set to 1000 nm or more and 1900 nm or less, if the growth substrate is an InP substrate, the composition ratio a of In in each layer can be set to 0.0 or more and 1.0 or less, the composition ratio b of Ga can be set to 0.0 or more and 1.0 or less, the composition ratio c of Al can be set to 0.0 or more and 0.35 or less, the composition ratio x of P can be set to 0.0 or more and 0.95 or less, the composition ratio y of As can be set to 0.15 or more and 1.0 or less, and the composition ratio z of Sb can be set to 0.0 or more and 0.7 or less. As long as it is appropriately set within these ranges to satisfy the conditions of the composition wavelength difference and the ratio of the lattice constant difference. The above light-emitting center wavelength is just an example. For example, in the case of an InGaAsP-based semiconductor or an InGaAlAs-based semiconductor, the light-emitting center wavelength can be set within the range of 1000 nm or more and 2200 nm or less, preferably the light-emitting center wavelength is set to 1300 nm or more, and more preferably 1400 nm or more. In the case of containing Sb, it can be further set to infrared rays with a long wavelength (11 μm or less).

[0081] - Dopant -

[0082] The dopant in each layer of the light-emitting layer 40 is not limited. In order to reliably obtain the effects of the present invention, it is preferable that both the barrier layer 41 and the well layer 42 are set to be i-type. Among them, for each layer, an n-type or p-type dopant can be doped.

[0083] <n-type cladding>

[0084] An n-type cladding 31 is provided on one side of the light-emitting layer 40. The composition of the III-V compound semiconductor of the n-type cladding 31 can be appropriately set according to the composition of the III-V compound semiconductor of the light-emitting layer 40. When the light-emitting layer 40 is composed of an InGaAsP-based semiconductor or an InGaAlAs-based semiconductor, for example, an n-type InP layer can be used. The n-type cladding 31 can be a single-layer structure or a composite layer stacked with multiple layers. As the thickness of the n-type cladding, 1 μm or more and 5 μm or less can be exemplified.

[0085] <p-type cladding>

[0086] A p-type cladding layer 71 is provided on the other side of the light emitting layer 40. The composition of the III-V compound semiconductor constituting the p-type cladding layer 71 may be appropriately set according to the composition of the III-V compound semiconductor of the light emitting layer 40, and p-type AlInP may be exemplified. The p-type cladding layer 71 may be a single-layer structure or a composite layer having a plurality of layers stacked. The film thickness of the p-type cladding layer 71 is not particularly limited and may be set to be greater than 1 μm and less than 5 μm.

[0087] <Electron blocking layer>

[0088] exist Figure 2 In the embodiment, the electron blocking layer 43 is disposed adjacently just above the light-emitting layer 40. The electron blocking layer 43 is usually disposed between a quantum well structure (MQW) functioning as the light-emitting layer 40 and a p-type cladding layer 71 to serve as a layer for blocking electrons and injecting electrons into the light-emitting layer 40 (injected into the well layer in the case of MQW) to improve the electron injection efficiency. In the past, when such an electron blocking layer 43 was designed in a manner to increase the band gap Ec of the conduction band in order to improve the luminous power, the band gap (potential) Ev of the valence band was usually reduced. However, the inventors found that: in the present invention, contrary to this technical common sense, the electron blocking layer 43 was designed in a manner that the band gap (potential) Ev of the valence band when an undoped electron blocking layer 43 was provided was increased, thereby being able to improve the luminous power per unit injected power. It should be noted that the thickness of the electron blocking layer 43 is preferably set to be greater than 6nm and less than 60nm, more preferably set to be greater than 10nm and less than 50nm, and further preferably set to be greater than 10nm and less than 50nm.

[0089] As described above, in order to set the electron blocking layer 43 in such a manner that the band gap (Ev) of the valence band when the undoped electron blocking layer 43 is provided is located between the band gap (Evb) of the barrier layer and the band gap (Evs) of the p-type cladding layer, the main V group elements in the electron blocking layer and the p-type cladding layer are preferably different from each other. However, even if the layers have different main V group elements, if epitaxial growth cannot be performed in a state where the lattice constant difference is small, the luminous efficiency is reduced due to the occurrence of defects caused by the lattice constant difference. Therefore, it is preferred to adjust the composition range in such a manner that the lattice constant difference between the light-emitting layer and the electron blocking layer and the lattice constant difference between the electron blocking layer and the p-type cladding layer are less than 0.54%. For example, if the light-emitting layer 40 is set to an InGaAlAs system with a light emission center wavelength of more than 1300nm, the p-type cladding 71 is set to InP, and the lattice constant of InP is used as a reference for element design, the electron blocking layer 43 can be set to In with As as the main V group element. a Ga b Al cAs, the composition ratio a of In is set to be greater than or equal to 0.51 and less than or equal to 0.57, the composition ratio b of Ga is set to be greater than or equal to 0.0 and less than or equal to 0.13, and the composition ratio c of Al is set to be greater than or equal to 0.46 and less than or equal to 0.49. The design conditions also vary depending on the light-emitting layer and the p-cladding layer, and can be appropriately set so as to satisfy the conditions of the present invention.

[0090] <Spacer Layer>

[0091] In addition, between the electron blocking layer 43 and the p-type cladding layer 71, that is, on the p-side of the semiconductor stacked structure, an undoped spacer layer 52 having the same main V group element as the p-type cladding layer 71 may be formed. In this case, the main V group elements in the electron blocking layer 43 and the spacer layer 52 are preferably different from each other. The thickness of the spacer layer 52 is preferably 320 nm or less, more preferably 200 nm or less, and further preferably 100 nm or less. The composition of the spacer layer 52 and the p-type cladding layer 71 may be the same.

[0092] By providing the spacer layer 52, it is possible to suppress the diffusion of dopants in the p-type cladding layer 71 into the light-emitting layer 40, and as a result, the light-emitting power can be improved. In addition, in the present invention, by providing the electron blocking layer 43, even if the spacer layer 52 is thinned, the effect of preventing the diffusion of dopants can be fully maintained, and therefore, compared with the conventional type of III-V compound semiconductor light-emitting element having a thick spacer layer, the light-emitting power can be further improved.

[0093] For example, for a p-type InP cladding, even if the spacer layer 52 has the same main V group element as the i-type InP spacer layer, it has the effect of preventing dopants from diffusing from the p-type InP cladding by not containing impurities. In addition, when the electron blocking layer 43 of the present invention is formed with a different main V group element, the electron blocking layer has a strong effect of preventing dopants from diffusing, and therefore, a thinner spacer layer 52 can be made than before. In this way, when the spacer layer 52 separated by the electron blocking layer 43 of the present invention is thin, the luminous power can be improved, and therefore, the thickness of the spacer layer 52 is preferably less than 320nm, more preferably less than 200nm, and further preferably less than 100nm. In addition, it is also preferred to set a spacer layer 32 on the n-side of the light-emitting layer 40. The spacer layer 32 on the n-side can be set as an undoped III-V compound semiconductor layer, for example, an i-type InP spacer layer is preferably used. The thickness of the spacer layer 32 on the n-side is not limited, for example, it can be set to be greater than 5nm and less than 500nm.

[0094] It should be noted that the electron blocking layer 43 and the p-type cladding layer 71 may be adjacent. In this case, the main V group elements in the electron blocking layer 43 and the p-type cladding layer 71 are preferably different from each other. With the effect of suppressing the diffusion of dopants achieved by the above-mentioned electron blocking layer 43, it is expected that the thickness of the spacer layer 52 can be thinner than before.

[0095] The following further describes specific aspects that the III-V compound semiconductor light-emitting device of the present invention may further include, but is not intended to limit the specific configuration of the III-V compound semiconductor light-emitting device of the present invention. Figure 3 , a III-V compound semiconductor light-emitting element 100 according to an embodiment of the present invention is described.

[0096] The III-V compound semiconductor light-emitting device 100 of one embodiment of the present invention preferably includes at least the light-emitting layer 40 having the above-mentioned stacked body, and further includes a desired structure in order from the support substrate 10, the intercalation layer 20, the n-type cladding layer 31, the n-side spacer layer 32 and the p-side spacer layer 52, and the p-type semiconductor layer 70. In addition, the p-type electrode 80 may be further provided on the p-type semiconductor layer 70 of the III-V compound semiconductor light-emitting device 100, and the n-type electrode 90 may be further provided on the back surface of the support substrate 10. By sandwiching the light-emitting layer 40 between the n-type cladding layer 31 and the p-type semiconductor layer 70, electrons and holes are combined in the light-emitting layer 40 by energizing the light-emitting layer 40 to emit light.

[0097] <Growth Substrate>

[0098] The growth substrate can be appropriately selected from compound semiconductor substrates such as InP substrates, InAs substrates, GaAs substrates, GaSb substrates, and InSb substrates according to the composition of the light emitting layer 40. The conductivity type of each substrate is preferably made to correspond to the conductivity type of the semiconductor layer on the growth substrate, and examples of compound semiconductor substrates applicable to this embodiment include n-type InP substrates and n-type GaAs substrates.

[0099] <Support substrate>

[0100] As the support substrate 10, a growth substrate on which the light emitting layer 40 can be grown can be used. When the bonding method described later is used, various substrates different from the growth substrate can be used as the support substrate 110 (see Figure 4 ).

[0101] <Inclusion layer>

[0102] An inclusion layer 20 can be provided on the support substrate 10. When using a growth substrate as the support substrate 10, the inclusion layer 20 can be made into a group III-V compound semiconductor layer. It can be used as an initial growth layer for epitaxially growing a semiconductor layer on the support substrate 10 as a growth substrate. In addition, for example, it can also be used as a buffer layer for buffering the lattice strain between the support substrate 10 as a growth substrate and the n-type cladding layer 31. In addition, by making the growth substrate lattice-matched with the inclusion layer 20 and changing the semiconductor composition, it can also be used as an etch stop layer. For example, when the support substrate is an n-type InP substrate, it is preferable to set the inclusion layer 20 as an n-type InGaAs layer. At this time, in order to make the inclusion layer 20 lattice-matched with the InP growth substrate, it is preferable to set the In composition ratio in group III elements to 0.3 or more and 0.7 or less, and more preferably 0.5 or more and 0.6 or less. In addition, if the composition ratio is set to be similar to that of the above InGaAs in terms of lattice constant and close to the InP substrate, it can be set to AlInAs, AlInGaAs, or InGaAsP. The inclusion layer 20 can be a single layer, or can be a composite layer (such as a superlattice layer) with other layers.

[0103] <p-type semiconductor layer>

[0104] A p-type semiconductor layer 70 can be provided on the light-emitting layer 40 and, if necessary, the p-side spacer layer 52. The p-type semiconductor layer 70 can sequentially include the above-mentioned p-type cladding layer 71 and p-type contact layer 73 from the light-emitting layer 40 side. It is also preferable to provide an intermediate layer 72 between the p-type cladding layer 71 and the p-type contact layer 73. By providing the intermediate layer 72, the lattice mismatch between the p-type cladding layer 71 and the p-type contact layer 73 can be alleviated. The composition of the group III-V compound semiconductor of the p-type semiconductor layer 70 can be appropriately determined according to the composition of the group III-V compound semiconductor of the light-emitting layer 40. When the light-emitting layer 40 is composed of an InGaAlAs-based semiconductor, p-type InP can be exemplified as the p-type cladding layer, p-type InGaAsP can be exemplified as the intermediate layer 72, and p-type InGaAs without P can be exemplified as the p-type contact layer 73. The film thickness of each layer of the p-type semiconductor layer 70 is not particularly limited. As the film thickness of the p-type cladding layer 71, 1 μm or more and 5 μm or less can be exemplified. As the film thickness of the intermediate layer 72, 10 nm or more and 200 nm or less can be exemplified. As the film thickness of the p-type contact layer 73, 50 nm or more and 200 nm or less can be exemplified.

[0105] <Electrode>

[0106] A p-type electrode 80 and an n-type electrode 90 may be provided on the p-type semiconductor layer 70 and on the back of the support substrate 10, respectively. The metal material used to form each electrode may be a metal such as Ti, Pt, Au, or a general metal material such as a metal that forms a eutectic alloy with gold (Sn, etc.). Furthermore, the electrode pattern of each electrode is arbitrary and not limited in any way.

[0107] Up to this point, an embodiment of using a compound semiconductor substrate as a growth substrate and directly using it as a supporting substrate 10 has been described, but the present invention is not limited to this. As a supporting substrate for the III-V compound semiconductor light-emitting element of the present invention, after each semiconductor layer is formed on the growth substrate, the growth substrate can be removed by a bonding method, and a semiconductor substrate such as a Si substrate, a metal substrate such as Mo, W, Kovar, or various submount substrates using AlN or the like can be pasted at the same time and used as a supporting substrate (hereinafter referred to as a "bonding method", refer to Japanese Patent Gazette No. 2018-006495 and Japanese Patent Gazette No. 2019-114650). For the case of using the bonding method, refer to the following. Figure 4 It should be noted that the last two digits of the symbols in the figure are the same as the above-mentioned structures, and repeated description is omitted.

[0108] When the bonding method is used, for example, it is sufficient to form each semiconductor layer on the growth substrate 10. And, after forming each semiconductor layer, the two are bonded using the metal reflective layer 122 and the metal bonding layer 121 provided on the support substrate 110, and then the growth substrate 10 is removed. The implementation of the manufacturing method is described in detail later. The structure of the III-V compound semiconductor light-emitting element 200 after the growth substrate 10 is removed is described in more detail. In the III-V compound semiconductor light-emitting element 200, in addition to providing each electrode, a layer other than the III-V compound semiconductor can also be provided. For example, when the bonding method is used, it can be formed in a manner that includes a metal bonding layer 121 for bonding to a support substrate instead of the above-mentioned initial growth layer on the support substrate 110 formed by a Si substrate, and a p-type semiconductor layer 170, a light-emitting layer 140, and an n-type cladding layer 131 are sequentially arranged thereon. It should be noted that a metal reflective layer 122 can be provided on the metal bonding layer 121. Furthermore, in addition to the III-V compound semiconductor layer, an ohmic electrode portion 181 and a dielectric layer 160 surrounding the ohmic electrode portion 181 dispersed in an island shape may be provided on the metal reflective layer 122 as needed. Examples of the dielectric material include SiO2, SiN, and ITO.

[0109] It should be noted that, of course, it can be understood that the conductivity type of each layer, n-type / p-type, may be opposite to that in the above-mentioned embodiment.

[0110] (Method for manufacturing III-V compound semiconductor light-emitting device)

[0111] The manufacturing method of the aforementioned III-V compound semiconductor light-emitting element of the present invention includes: a process of forming an n-type cladding layer 31; a process of forming a light-emitting layer 40 on the n-type cladding layer 31; a process of forming an electron blocking layer 43 on the light-emitting layer 40; and a process of forming a p-type cladding layer 71 on the electron blocking layer 43.

[0112] In addition, as needed, references can be included Figure 3 The process of each layer of the III-V compound semiconductor light-emitting element 100 is described. The III-V compound semiconductor materials that can be used as the barrier layer 41 and the well layer 42, the conditions of their composition wavelength difference and lattice constant difference, and further the film thickness, the number of stacking groups, etc. are as described above, and repeated description is omitted.

[0113] Each layer of the III-V compound semiconductor layer can be formed by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, etc. If it is an InGaAsP semiconductor, for example, trimethyl indium (TMIn) as an In source, trimethyl gallium (TMGa) as a Ga source, arsine (AsH3) as an As source, phosphine (PH3) as a P source, etc. can be used in a predetermined mixing ratio, and these raw material gases can be vapor-phase grown while using a carrier gas, thereby making the InGaAsP semiconductor layer epitaxially grow with a desired thickness according to the growth time. In addition, when Al is used as a III group element, as an Al source, for example, trimethyl aluminum (TMA) can be used, and when Sb is used as a V group element, as an Sb source, TMSb (trimethyl antimony) can be used. Furthermore, when each semiconductor layer is doped to become p-type or n-type, a dopant source gas containing Si, Zn, or the like as constituent elements may be used as desired.

[0114] In addition, the formation of metal layers such as n-type electrodes and p-type electrodes can use a known method, such as sputtering, electron beam evaporation, or resistance heating. When the bonding method is used, as long as the dielectric layer 160 is formed, a known film forming method such as plasma CVD or sputtering can be applied, and a known etching method can also be used to form concave and convex as needed.

[0115] The bonding method (see Japanese Patent Application Laid-Open No. 2018-006495 and Japanese Patent Application Laid-Open No. 2019-114650) is used to form Figure 4When the element shown is used, for example, the III-V compound semiconductor light-emitting element can be produced as follows.

[0116] First, the layers of the III-V compound semiconductor layer including the etching stop layer 120, the n-type cladding layer 131, the light emitting layer 140, the p-type cladding layer 171, the intermediate layer 172, and the p-type contact layer 173 are sequentially formed on the growth substrate 10 (it should be noted that Figure 4 It is a state after bonding, so it is upside down.) Next, a p-type ohmic electrode portion 181 dispersed in an island shape is formed on the p-type contact layer 173. Thereafter, an etching mask is formed on the p-type ohmic electrode portion 181 and its surroundings, and the p-type contact layer 173 except for the portion where the ohmic electrode portion 181 is formed is removed by wet etching or the like to expose the intermediate layer 172. Then, a dielectric layer 160 is formed on the intermediate layer 172. Furthermore, the upper part of the p-type ohmic electrode portion 181 and the intermediate layer 172 of the surrounding portion of the p-type ohmic electrode portion 181 are exposed by partially etching the dielectric layer 160. The metal reflective layer 122 is formed on the entire surface including the p-type ohmic electrode portion 181, the intermediate layer 172 exposed in the surrounding portion of the p-type ohmic electrode portion 181, and the dielectric layer 160 in the area that is not removed.

[0117] On the other hand, a conductive Si substrate or the like is used as a support substrate 110, and a metal bonding layer 121 is formed on the support substrate. The metal reflective layer 122 and the metal bonding layer 121 are arranged opposite to each other and bonded by heating and compression. Then, the growth substrate is etched away to expose the etching stop layer 120. An n-type electrode 190 is formed on the etching stop layer 120, and the etching stop layer 120 other than the n-type electrode formation portion is etched away, or after etching away portions other than a portion of the etching stop layer 120, an n-type electrode 190 is formed on a portion of the etching stop layer 120, thereby obtaining a junction-type III-V compound semiconductor light-emitting element 200. As described above, the conductivity type of each layer, n-type / p-type, may be opposite to the above example.

[0118] The above is an explanation of the present embodiment, but the embodiment is not limited thereto, and various modifications can be made within the scope of the present invention using known techniques. For example, each layer of the initial growth layer and the etch stop layer 120, the n-type cladding layer 131, the n-side spacer layer 132, the p-side spacer layer 152, the p-type cladding layer 171, the intermediate layer 172, and the p-type contact layer 173 can be a single layer, or a composite layer with other layers (such as a superlattice layer), and can also include a composition gradient. In addition, a structure in which a tunnel junction is stacked can also be inserted in a portion. Below, the present invention is further described in detail using embodiments, but the present invention is not limited to the following embodiments at all.

[0119] Example

[0120] The target emission center wavelength was set to 1480 nm, and the III-V compound semiconductor light-emitting devices of Examples 1 to 5 and Comparative Examples 1, 2, 34, and 6 were prepared by the bonding method. Similarly, the target emission center wavelength was set to 1330 nm, and Examples 6 and 7 and Comparative Examples 5 and 7 were prepared.

[0121] (Example 1)

[0122] For the configurations of the III-V compound semiconductor layer of the III-V compound semiconductor light emitting device 200 of Example 1, refer to Figure 4 The thickness and doping concentration of the substrate before being bonded to the support substrate described later are shown in Table 2. An S-doped n-type InP substrate was used as the growth substrate 10. 18 atoms / cm 3 ) on the (100) surface of the substrate, an n-type InP layer with a thickness of 100 nm and an n-type In layer with a thickness of 20 nm were sequentially formed by MOCVD. 0.57 Ga 0.43 As layer (initial growth layer and etching stop layer 120 respectively), n-type InP layer with a thickness of 3500nm (n-type cladding layer 131), i-type InP layer with a thickness of 100nm (n-side spacer layer 132), light-emitting layer 140 described later, i-type InAlAs layer with a thickness of 20nm (electron blocking layer 143), i-type InP layer with a thickness of 300nm (p-side spacer layer 152), p-type InP layer with a thickness of 2400nm (p-type cladding layer 171), p-type InAlAs layer with a thickness of 50nm (electron blocking layer 143), p-type InAlAs layer with a thickness of 200nm (electron blocking layer 143), p-type InAlAs layer with a thickness of 200nm (p-side spacer layer 152), p-type InAlAs layer with a thickness of 200nm (p-side spacer layer 152), p-type InAlAs layer with a thickness of 200nm (p-type cladding layer 171), p-type InAlAs layer with a thickness of 50nm (electron blocking layer 143), p-type InAlAs layer with a thickness of 20 ... 0.8 Ga 0.2 As 0.5 P 0.5 layer (intermediate layer 172), p-type In 0.57 Ga 0.43 As layer (p-type contact layer 173). The n-type InP layer and n-type InGaAs layer (initial growth layer and etching stop layer 120, respectively), and the n-type InP layer (n-type cladding layer 131) are doped with Si, and the doping concentration is set to 5.0×10 17 atoms / cm 3 The p-type InP layer (p-type cladding layer 171) is doped with Zn, and the doping concentration is set to 7.0×10 17 atoms / cm 3 The p-type InGaAsP layer (intermediate layer 172) and the p-type InGaAs layer (p-type contact layer 173) are doped with Zn, and the doping concentration is set to 1.5×10 19 atoms / cm3 .

[0123] When forming the light emitting layer 140, first, an i-type In a1 Ga b1 Al c1 As layer (barrier layer 141), then, the i-type In a2 Ga b2 Al c2 As layer (well layer 142) and i-type In a1 Ga b1 Al c1 As layers (barrier layers 141) were alternately stacked in 10 layers each, and 10.5 stacked layers were formed. That is, both ends of the light emitting layer 140 were barrier layers 141. The barrier layer 141 was an In layer with a thickness of 8 nm. 0.5264 Ga 0.3166 Al 0.1570 That is, the In composition ratio (a1) is 0.5264, the Ga composition ratio (b1) is 0.3166, and the Al composition ratio (c1) is 0.1570. In addition, the well layer 142 is an In layer with a thickness of 10 nm. 0.5435 Ga 0.3976 Al 0.0589 As. That is, the In composition ratio (a2) is 0.5435, the Ga composition ratio (b2) is 0.3976, and the Al composition ratio (c2) is 0.0589. In addition, the lattice constants are calculated as described above, and the band structure is calculated using the simulation software (SiLENSe) manufactured by STRJapan. The thickness, composition ratio, composition wavelength and lattice constant values ​​of the barrier layer 141 and the well layer 142, the carrier concentration of the p-type InP layer (p-type cladding 171), and the composition of the electron blocking layer (EBL layer) are recorded in Table 3. In the band gap based on the cladding Ec of Example 1, the value obtained by subtracting the smaller band gap from the larger band gap is, on the conduction band side, Ec-Ecb is 0.371eV, Ec-Ecs is 0.169eV, and Ecs-Ecb is 0.371eV-0.169eV=0.202eV. In addition, on the valence band side, Evb-Ev is 0.130eV, Ev-Evs is 0.077eV, and Evb-Evs is 0.130eV+0.077eV=0.208eV. These values ​​are recorded in Table 4. It should be noted that the composition of each layer in the above-mentioned Example 1 is a value measured by SIMS analysis. Regarding each layer of the light-emitting layer, after the light-emitting layer is exposed, SIMS analysis is performed to confirm the solid phase of each layer. In addition, the band structure in the light-emitting layer of Example 1 and the semiconductor layers before and after it calculated using simulation software is shown together with the calculation results of Comparative Example 1. Figure 5 .

[0124] [Table 2]

[0125]

[0126] A p-type ohmic electrode portion 181 (Au / AuZn / Au, total thickness: 530nm) dispersed in an island shape is formed on the p-type contact layer. It should be noted that when forming the island pattern, a resist pattern is formed, and then the ohmic electrode portion 181 is vapor deposited and formed by peeling off the resist pattern. The ratio of the area of ​​the p-type ohmic electrode portion 181 to the chip area (contact area ratio) is 0.95%, and the chip size is 280μm square.

[0127] Next, an etching mask is formed on the p-type ohmic electrode portion 181 and its surroundings, and the p-type contact layer 173 except for the portion where the ohmic electrode portion 181 is formed is removed by wet etching using a tartaric acid-hydrogen peroxide system, thereby exposing the intermediate layer 172. Thereafter, a dielectric layer 160 (thickness: 700 nm) composed of SiO2 is formed on the entire surface of the intermediate layer 172 by a plasma CVD method. Furthermore, in the upper region of the p-type ohmic electrode portion 181, a window pattern having a shape with a width of 3 μm in the width direction and the length direction is formed by using an etchant, and the p-type ohmic electrode portion 181 and the dielectric layer 160 surrounding the p-type ohmic electrode portion 181 are removed by wet etching using BHF, thereby exposing the upper portion of the p-type ohmic electrode portion 181 and the intermediate layer 172 surrounding the p-type ohmic electrode portion 181.

[0128] Next, a metal reflective layer 122 is formed on the entire surface of the intermediate layer 172 (the upper part of the p-type ohmic electrode portion 181, the upper part of the dielectric layer 160, and the exposed intermediate layer 172 around the p-type ohmic electrode portion 181) by evaporation. The thickness of each metal layer of the metal reflective layer (Ti / Au / Pt / Au) is 2nm, 650nm, 100nm, and 900nm, respectively. On the other hand, a metal bonding layer 121 is formed on a conductive Si substrate (thickness: 200μm) serving as a supporting substrate. The thickness of each metal layer of the metal bonding layer (Ti / Pt / Au) is 650nm, 10nm, and 900nm, respectively.

[0129] The metal reflective layer 122 and the metal bonding layer 121 are arranged to face each other and are heat-compressed and bonded at 315° C. Then, the n-type InP substrate 110 is wet-etched with a hydrochloric acid dilute solution to be removed.

[0130] On the etching stop layer 120, an n-type electrode 190 (Au (thickness: 10nm) / Ge (thickness: 33nm) / Au (thickness: 57nm) / Ni (thickness: 34nm) / Au (thickness: 800nm) / Ti (thickness: 100nm) / Au (thickness: 1000nm)) is formed as a wiring portion of the top surface electrode by forming an anti-etching pattern, evaporating an n-type electrode, and peeling off the anti-etching pattern. Furthermore, a pad portion (Ti (thickness: 150nm) / Pt (thickness: 100nm) / Au (thickness: 2500nm)) is formed on the n-type electrode to form a pattern of the top surface electrode. Then, the etching stop layer 120 except for the area directly below and in the vicinity of the n-type electrode 190 is removed by wet etching, and a roughening treatment is performed. Thereafter, a dielectric protective film (not shown) is formed on the top surface and side surfaces of the III-V compound semiconductor light-emitting element 200 except for the top surface of the pad portion.

[0131] (Example 2, Example 3, Example 4)

[0132] Group III-V compound semiconductor light-emitting devices of Examples 2, 3 and 4 were obtained in the same manner as in Example 1 except that the thickness of the spacer layer 152 was changed to 200 nm, 100 nm and no spacer layer.

[0133] (Example 5)

[0134] The composition of the barrier layer 141 is changed from In 0.5264 Ga 0.3166 Al 0.1570 As changed to In 0.5264 Ga 0.1626 Al 0.3110 The same operation as in Example 1 was carried out except for As to obtain the III-V compound semiconductor light-emitting device of Example 5.

[0135] (Example 6)

[0136] The composition of the barrier layer 141 is changed from In 0.5264 Ga 0.3166 Al 0.1570 As changed to In 0.5453 Ga 0.2440 Al 0.2107 As, the composition of the well layer 142 is changed from In 0.5435 Ga 0.3976 Al 0.0589 As changed to In 0.5601 Ga 0.3088 Al 0.1311 The same operation as in Example 1 was carried out except for As to obtain the III-V compound semiconductor light-emitting device of Example 6.

[0137] (Example 7)

[0138] The III-V compound semiconductor light-emitting device of Example 7 was obtained in the same manner as in Example 6 except that the thickness of the spacer layer 152 was changed to 100 nm.

[0139] (Comparative Example 1)

[0140] A III-V compound semiconductor light-emitting device of Comparative Example 1 was obtained in the same manner as in Example 1 except that the thickness of the spacer layer 152 was changed to 320 nm and the electron blocking layer 143 was not provided.

[0141] (Comparative Example 2, Comparative Example 3)

[0142] Group III-V compound semiconductor light-emitting devices of Comparative Examples 2 and 3 were obtained in the same manner as in Comparative Example 1 except that the thickness of the spacer layer 152 was changed to 100 nm and no spacer layer was provided.

[0143] (Comparative Example 4)

[0144] A III-V compound semiconductor light-emitting device of Comparative Example 4 was obtained in the same manner as in Example 5 except that the spacer layer 152 and the electron blocking layer 143 were not provided.

[0145] (Comparative Example 5)

[0146] A III-V compound semiconductor light-emitting device of Comparative Example 4 was obtained in the same manner as in Example 5 except that the thickness of the spacer layer 152 was changed to 320 nm and the electron blocking layer 143 was not provided.

[0147] (Comparative Example 6)

[0148] The composition of the electron blocking layer 143 is changed to In 0.95 Al 0.05 P. Except for this, the same operations as in Example 1 were carried out to obtain a III-V compound semiconductor light-emitting device of Comparative Example 6.

[0149] (Comparative Example 7)

[0150] The composition of the electron blocking layer 143 is changed to In 0.95 Al 0.05 P. Except for this, the same operations as in Example 6 were carried out to obtain a III-V compound semiconductor light-emitting device of Comparative Example 7.

[0151] For the embodiment and the comparative example, the respective composition wavelengths and lattice constants calculated from the composition of the barrier layer 141 and the composition of the well layer 142 are recorded in Table 3. In addition, the band gaps of Ec-Ecb, Ec-Ecs, and Ecs-Ecb on the conduction band side and the band gaps of Evb-Ev, Ev-Evs, and Evb-Evs on the valence band side are recorded in Table 4, respectively.

[0152] [Table 3]

[0153]

[0154] [Table 4]

[0155]

[0156] (Evaluation of light emitting characteristics)

[0157] The forward voltage Vf (V) and the luminous power Po (mW) based on the integrating sphere were measured when the forward current If (mA) of 30 mA and 36 mA was respectively passed through the III-V compound semiconductor light-emitting elements of Examples 1 to 7 and Comparative Examples 1 to 7 using a constant current voltage power supply. In addition, the luminous center wavelength λp (nm) and the half-value width (FWHM, unit: nm) based on the spectrum analyzer (AQ6374 manufactured by Yokogawa Instruments Co., Ltd.) were also measured. It should be noted that the average value of the measurement results of the three samples was calculated during the measurement. Next, Po / (Vf·If) was calculated by dividing the luminous power by the injected power at that time, and this value was used as an indicator of the luminous power per unit injected power. The respective measurement results and calculation results are shown in Table 4.

[0158] (Dopant Diffusion Evaluation)

[0159] As a representative example, the dopant diffusion state in the light-emitting element of Example 3 was measured by SIMS. The measurement results are shown in FIG. Figure 6 .

[0160] According to the results in Table 4, it can be seen that in the embodiments that satisfy the bandgap relationship of the present invention, the luminous power per unit of injected power is large. In addition, if we focus on embodiments 1 to 3 in which an electron blocking layer is provided and only the thickness of the spacer layer is different, the thinner the spacer layer is, the greater the luminous power per unit of injected power becomes. On the other hand, in comparative examples 1 to 3 in which no electron blocking layer is provided, the luminous power per unit of injected power is small or no light is emitted at all. In this regard, the relationship between embodiment 5 and comparative example 4 also presents the same result. Furthermore, in embodiments 6 and 7 and comparative example 5 in which the luminous wavelength is about 1330nm, in embodiments 5 and 6 in which an electron blocking layer is provided, when the spacer layer is thin, the luminous power per unit of injected power is large, and in comparative example 5 in which no electron blocking layer is provided, the luminous power per unit of injected power is smaller than that of the embodiments.

[0161] In addition, if you refer to Figure 6 In Example 3, regarding Zn as a dopant in the p-type cladding layer (InP), the Zn concentration in the electron blocking layer decreases sharply, and the Zn concentration in the adjacent light-emitting layer is also kept extremely low (1×10 16 atoms / cm 3 Below, the quantitative value of InP is 7×10 15 atoms / cm 3 Although not shown in the figure, in Comparative Examples 2 and 3, which do not have the electron blocking layer of the present invention and have a thin spacer layer, more than 1×10 16 atoms / cm 3 In addition, in Comparative Example 6 in which the electron blocking layer is formed of InAlP, the diffusion of Zn is also increased compared with Example 1. It can be understood that since the electron blocking layer whose V group element is As exists in the example, the diffusion of Zn is suppressed.

[0162] Industrial Applicability

[0163] According to the present invention, a III-V compound semiconductor light-emitting element having a better light-emitting power per unit injected power than conventional light-emitting elements and a method for manufacturing the same are useful.

[0164] Description of Reference Numerals

[0165] 10Support base plate

[0166] 20 Inclusion layer

[0167] 31n type cladding

[0168] 32n side spacer

[0169] 40 luminous layers

[0170] 41 Barrier layer

[0171] 42-well layer

[0172] 43Electron blocking layer

[0173] 52p side spacer

[0174] 60 dielectric layer

[0175] 70p type semiconductor layer

[0176] 71p type cladding

[0177] 72 Middle Layer

[0178] 73p type contact layer

[0179] 80p type electrode

[0180] 90n electrode

[0181] 100III-V compound semiconductor light-emitting device

Claims

1. A III-V compound semiconductor light-emitting element, characterized in that: It has an n-type cladding layer, a light-emitting layer, and a p-type cladding layer in sequence. An undoped electron blocking layer is provided between the light emitting layer and the p-type cladding layer. The light emitting layer has a stacked structure in which barrier layers and well layers are repeatedly stacked, wherein: (i) in the conduction band, the band gap (Ec) of the electron blocking layer is larger than the band gap (Ecb) of the barrier layer and the band gap (Ecs) of the p-type cladding layer, and the band gap (Ecs) of the p-type cladding layer is larger than the band gap (Ecb) of the barrier layer, (ii) In the valence band, the band gap (Ev) of the electron blocking layer is located between the band gap (Evb) of the barrier layer and the band gap (Evs) of the p-type cladding layer.

2. The III-V compound semiconductor light-emitting device according to claim 1, wherein: The electron blocking layer and the p-type cladding layer have main group V elements different from each other.

3. The III-V compound semiconductor light-emitting device according to claim 1, wherein: An undoped spacer layer is provided between the electron blocking layer and the p-type cladding layer, and main group V elements of the p-type cladding layer and the spacer layer are the same.

4. The III-V compound semiconductor light-emitting device according to claim 3, wherein: The thickness of the spacer layer is less than 300 nm.

5. The III-V compound semiconductor light-emitting device according to claim 1, wherein: The electron blocking layer is adjacent to the p-type cladding layer.

6. A method for manufacturing a III-V compound semiconductor light-emitting element according to any one of claims 1 to 5, comprising: A step of forming the n-type cladding layer; forming the light-emitting layer on the n-type cladding layer; forming the electron blocking layer on the light-emitting layer; as well as The step of forming the p-type cladding layer on the electron blocking layer.

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