A timing method, device and storage medium based on FLASH chip

Abstract

The present invention provides a timing method based on a FLASH chip. The method utilizes the principle that the logic level of the storage unit in the FLASH chip is irreversible, that is, the logic "0" in the chip can only be converted to a logic "1" by erasing. The storage unit of the FLASH chip is erased once when the power is turned on. Subsequently, each bit in the FLASH storage unit is used as a counting scale for the minimum time interval during timing, and logic "0" is written in sequence. By counting the number of logic "0"s in the storage chip, the total timing time can be obtained, and the erasing operation is avoided, effectively extending the service life of the chip. The timing method is simple and effective, does not require the configuration of a dedicated display, and effectively reduces project costs. The present invention also provides a timing device based on a FLASH chip and a computer-readable storage medium.

Description

Technical Field

[0001] The present invention relates to a timing method, a device and a storage medium based on a FLASH chip, and belongs to the field of embedded system timing applications. Background Art

[0002] A timer is a tool or device used to measure time intervals and is widely used in daily life, scientific research, industrial production, sporting events, and other fields. Timers can be categorized into various types based on their purpose and principle, including mechanical timers, electronic timers, stopwatches, and chronographs. In embedded system design, electronic timers are commonly used to measure time, but these recorded times must be displayed on a dedicated display. Therefore, a new timekeeping method is urgently needed to effectively address the display requirements. Summary of the Invention

[0003] The present invention aims to provide a timing method based on a FLASH chip. The timing method is simple and effective, does not require a dedicated display, and effectively reduces project costs.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is: a timing method based on a FLASH chip, the method comprising:

[0005] Step 1: When the device starts up, read the signature word in the FLASH chip. If the signature word is a valid signature word, determine that the data stored in the timing base area is credible, and proceed to step 2; if the signature word is not a valid signature word, determine that the data stored in the timing base area is untrustworthy, and proceed to step 3; wherein, the signature word is stored in the signature word area and is used to determine whether the data stored in the timing base area is credible; the timing base area is used to store the timing base, which is the number of bits in the FLASH chip that are rewritten from logic "1" to logic "0" when the device is powered on; the signature word area and the timing base area are partitions of the FLASH chip; the valid signature word is a preset value;

[0006] Step 2: sequentially and continuously read the stored data in the timing base area until the last byte of stored data; compare the read stored data with 0x0000 to obtain a first timing base and a second timing base, where the first timing base = the number of 0x0000s in the data read in the timing base area * 16, and the second timing base = the number of bits with logical "0" in the last byte of stored data, and then proceed to step 4; wherein the last byte is the last byte in which the bits of the FLASH chip are written with logical "0" when the power is last turned on;

[0007] Step 3: the first timing base is 0, and the second timing base is 0; proceed to step 4;

[0008] In step 4, the sum of the first and second timing bases is added to the third timing base, resulting in a fourth timing base of 0, and the process proceeds to step 5. The third timing base is the minimum number of timing intervals corresponding to the total time the device was powered on before the current power-on. The fourth timing base is used to record the minimum number of timing intervals corresponding to the cumulative time the device was powered on. The minimum timing interval is a preset time interval for timing.

[0009] Step 5, erasing all sectors of the FLASH chip, writing the valid tag word into the tag word area, and changing the logic "0" of the timing base area to logic "1" by erasing, and then proceeding to step 6;

[0010] Step 6: When the minimum timing interval arrives, the logic "1" of a bit in the timing base area is rewritten to a logic "0", and the fourth timing base is increased by 1; repeat step 6 until power is cut off.

[0011] FLASH chips require an erase operation before writing data, and this erase process typically takes a long time. This invention exploits the principle that the logic level of the memory cells in FLASH chips is irreversible, meaning that a logic "0" in the chip can only be converted to a logic "1" by erasing. Upon power-up, the memory cells of the FLASH chip are erased once. Subsequently, during timing, each bit in the FLASH memory cell is used as a counting scale for the minimum time interval, and logic "0"s are written in sequence. By counting the number of logic "0s" in the memory chip, the total timing time can be obtained.

[0012] According to the embodiments of the present invention, the present invention can be further optimized. The following is the technical solution formed after optimization:

[0013] In one preferred embodiment, step 1 includes: upon device startup, reading a signature word from a timing sector in a FLASH chip; if the signature word in the timing sector is a valid signature word, determining that the data stored in the timing base area of ​​the timing sector is credible, and proceeding to step 2; if the signature word is not a valid signature word, determining that the data stored in the timing base area of ​​the timing sector is untrustworthy, and proceeding to step 3; wherein the timing sector is a sector including the signature word area and the timing base area, and the FLASH chip has at least one such timing sector. Multiple such timing sectors can be provided as timing backups to prevent loss of counting information due to abnormal power failure during power-on erasure.

[0014] In one preferred embodiment, the method further includes: Step 7, obtaining a total timed time = (the third timed time + the fourth timed time) * the minimum timed interval based on the third timed time base and the fourth timed time base, and then proceeding to Step 8; Step 8, converting the total timed time into a format required by the communication protocol of the device and outputting it to an external device. This allows the obtained total timed time value to be transmitted to an external device via bus message output, eliminating the need for a display and reducing project costs.

[0015] Based on the same concept, the present invention also provides a timing device based on a FLASH chip, the device comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned timing method based on a FLASH chip when executing the computer program.

[0016] Based on the same concept, the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the above-mentioned timing method based on a FLASH chip are implemented.

[0017] Compared with the prior art, the present invention has the following beneficial effects: the timing method based on a FLASH chip utilizes the principle that the logic level of the storage cell in the FLASH chip is irreversible, that is, a logic "0" in the chip can only be converted to a logic "1" by erasing. Upon power-on, the FLASH chip's storage cell is erased once. Subsequently, during timing, each bit in the FLASH storage cell is used as a counting scale for the minimum time interval, and a logic "0" is written in sequence. By counting the number of logic "0s" in the storage chip, the total timing time can be obtained, and erasing operations are avoided, effectively extending the chip's service life. The timing method is simple and effective, does not require a dedicated display, and effectively reduces project costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] none DETAILED DESCRIPTION

[0019] The present invention will be described in detail below with reference to the embodiments. It should be noted that the embodiments and features of the embodiments of the present invention can be combined with each other without conflict.

[0020] Example 1

[0021] This embodiment 1 provides a timing method based on a FLASH chip, which is applicable to embedded systems, such as inertial products. This embodiment 1 takes a 16-bit FLASH as an example, and the specific partition design of the timing method is as follows:

[0022] 1. Reserve two FLASH sectors as dual-zone timing backup to avoid counting information loss due to abnormal power failure during power-on erasing; the storage space of each sector is 1MB.

[0023] 2. The first word space of each sector stores a valid signature word. For example, the valid signature word 0x55ee is written when in use. When unused or erased, the data stored in the first word space is 0xFFFF. It may also change to other values ​​if abnormally damaged. The signature word is used to determine whether the recorded timing data is reliable. If the valid signature word recorded in the first word space is different from the preset one (such as 0x55ee preset in this embodiment 1), it indicates that the information of this timing sector is unusable. The size of the first word space can be set according to the specific situation. In this embodiment 1, the first word space is two bytes.

[0024] 3. The remaining word space of each sector is used to store the timing base value. The timing base value will be erased only when the device is powered on and will be rewritten during the subsequent power-on timing process.

[0025] 4. Each bit in the remaining word space of each sector is used as a counting scale for the minimum timing interval, which is equivalent to a ruler for recording time. When each minimum timing interval arrives, the logic "1" of the counting scale, that is, the bit, is rewritten into logic "0" in turn. That is, the write operation of the FLASH chip can only rewrite logic "1" into logic "0", avoiding the erase operation and effectively extending the service life of the chip.

[0026] 5. When reading the timing information, the first timing sector shall prevail. Only when the first timing sector is invalid, the timing information of the backup second timing sector shall be read.

[0027] The steps of the timing method provided in this embodiment 1 specifically include:

[0028] S1. Design global variables gTimeBase and gTimeRemainder as timing variables, where gTimeBase is the minimum number of timing intervals corresponding to the total power-on time of the inertial group product before the current power-on, and gTimeRemainder is the minimum number of timing intervals corresponding to the accumulated power-on time of the inertial group product during the current power-on. The minimum timing interval is a preset time interval for timing, which is set according to specific usage.

[0029] S2. When the inertial group product is powered on and initialized, the first timing sector is read first to determine whether the timing information is valid, that is, whether the signature is a valid signature. If it is a valid signature, the stored data in the remaining word space of the first timing sector is read sequentially and continuously until the last byte of stored data is stored. The read data is compared with 0x0000 to obtain TimeA and TimeB, where TimeA is the number of 0x0000s in the read stored data * 16, and TimeB is the number of bits in the last byte of stored data that are logic "0". A valid flag is returned and the process proceeds to step S4. If it is not a valid signature, an invalid flag is returned and TimeA and TimeB are assigned to 0 and the process proceeds to step S4.

[0030] The last byte is the last byte in which the bit of the FLASH chip is written with logic "0" when the power is last turned on;

[0031] S3. If the reading of the first timing sector 1 returns a valid flag, there is no need to read the second timing sector;

[0032] If reading the first timing sector returns an invalid flag, the second timing sector is read again, following similar steps as in S2. If the signature of the second timing sector is valid, reliable TimeA and TimeB are obtained, and the process proceeds to S4. Otherwise, TimeA and TimeB are assigned 0, and the process proceeds to S4. When the timing method is first used in an inertial group product, the signatures of both timing sectors are not valid. Therefore, valid signatures must be written for subsequent use.

[0033] S4. Obtain the reliable counting information stored in the FLASH chip through S2 and S3, and assign it to the global variables: gTimeBase = gTimeBase + TimeA + TimeB; gTimeRemainder = 0;

[0034] S5, first erase the first timing sector, and write the valid feature word into the first word space in the first timing sector, and change the logic "0" of the remaining word space in the first timing sector into logic "1" by erasing; enter S6;

[0035] Then, the second timing sector is erased and the valid signature is written into the first word space of the second timing sector. The logic "0" in the remaining word space of the second timing sector is changed to logic "1" by erasing. The second timing sector is a backup of the first timing sector and the written data is the same as that of the first timing sector.

[0036] S6. After each counting cycle, that is, when a minimum timing interval arrives, the value of the gTimeRemainder variable is increased by 1, and at the same time, the logic "1" of a bit of the remaining word space in the timing sector is rewritten to logic "0"; S6 is repeated until power is cut off.

[0037] Steps 1 through 6 complete the generation and reading of timing information, storing it in the global variables gTimeBase and gTimeRemain in the time access function. Based on gTimeBase, gTimeRemain, and the minimum timing interval, the total time is easily obtained and converted into the format specified by the inertial control unit's communication protocol for output to the host computer.

[0038] Example 2

[0039] In Example 2, assuming a minimum timing interval of 5 seconds, using the timing method provided in Example 1, when the inertial device is first powered on, both gTimeBase and gTimeRemainder are 0. Every 5 seconds, the timing method writes a single bit of logic "0" to the FLASH memory chip. The gTimeRemainder variable represents the number of logic "0s" written to the FLASH chip. The total timed duration, T, is calculated as (gTimeBase + gTimeRemainder) * 5 seconds. Upon the second power-on, gTimeBase is equal to the last recorded power-on duration, T / 5, and gTimeRemainder restarts from 0, and so on.

[0040] The contents described in the above embodiments should be understood as these embodiments are only used to more clearly illustrate the present invention, and are not used to limit the scope of the present invention. After reading the present invention, various equivalent modifications to the embodiments made by those skilled in the art fall within the scope defined by the claims attached to the present invention.

Claims

1. A timing method based on FLASH chip, characterized in that: The method comprises: Step 1: When the device starts up, read the signature word in the FLASH chip. If the signature word is a valid signature word, determine that the data stored in the timing base area is credible, and proceed to step 2. If the signature word is not a valid signature word, determine that the data stored in the timing base area is untrustworthy, and proceed to step 3. The signature word is stored in the signature word area and is used to determine whether the data stored in the timing base area is credible. The timing base area is used to store the timing base, which is the number of bits in the FLASH chip that are rewritten from logic "1" to logic "0" when the device is powered on. The signature word area and the timing base area are partitions of the FLASH chip. The valid signature word is a preset value. Step 2: sequentially and continuously read the stored data in the timing base area until the last byte of stored data; compare the read stored data with 0x0000 to obtain a first timing base and a second timing base, where the first timing base = the number of 0x0000s in the data read in the timing base area * 16, and the second timing base = the number of bits with logical "0" in the last byte of stored data, and then proceed to step 4; wherein the last byte is the last byte in which the bits of the FLASH chip were written with logical "0" when the power was last turned on; Step 3: the first timing base is 0, and the second timing base is 0; proceed to step 4; In step 4, the sum of the first and second timing bases is added to the third timing base, resulting in a fourth timing base of 0, and the process proceeds to step 5. The third timing base is the minimum number of timing intervals corresponding to the total time the device was powered on before the current power-on. The fourth timing base is used to record the minimum number of timing intervals corresponding to the cumulative time the device was powered on. The minimum timing interval is a preset time interval for timing. Step 5, erase all sectors of the FLASH chip, write the valid tag word into the tag word area, and change the logic "0" of the timing base area into logic "1" by erasing, and then go to step 6; Step 6: When the minimum timing interval arrives, the logic "1" of a bit in the timing base area is rewritten to a logic "0", and the fourth timing base is increased by 1; repeat step 6 until power is cut off.

2. The timing method based on FLASH chip according to claim 1, characterized in that: The step 1 comprises: When the device starts up, the signature word in the timing sector of the FLASH chip is read. If the signature word in the timing sector is a valid signature word, the data stored in the timing base area of ​​the timing sector is determined to be credible, and the process proceeds to step 2. If the signature word is not a valid signature word, the data stored in the timing base area of ​​the timing sector is untrustworthy, and the process proceeds to step 3. The timing sector is a sector including the feature word area and the timing base area, and the FLASH chip has at least one timing sector.

3. The timing method based on FLASH chip according to claim 1 or 2, characterized in that: The method further comprises: Step 7: Obtain the total timing time = (the third timing base + the fourth timing base) * the minimum timing interval based on the third timing base and the fourth timing base, and proceed to step 8; Step 8: Convert the total time into a format required by the communication protocol of the device and output it to the outside.

4. A timing device based on a FLASH chip, characterized in that: The device comprises: memory for storing computer programs; A processor, configured to implement the steps of the FLASH chip-based timing method according to any one of claims 1 to 3 when executing the computer program.

5. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the timing method based on a FLASH chip according to any one of claims 1 to 3 are implemented.