A controller implementation method and controller supporting optical fiber and physical interfaces

Abstract

The application relates to a controller implementation method and a controller supporting optical fibers and physical interfaces, and the method steps comprise the following: a controller host computer completes configuration of interface operation mode, frequency and dead time parameters of the controller and issues an FPGA; the FPGA receives interface data and performs data checking, and a data collection processing module selects optical fiber or physical I / O interface data according to host computer configuration information and outputs the data to a CPU; a control algorithm model is loaded in the controller CPU, modulation waves are generated according to sampling data and are issued to the FPGA; the FPGA generates PWM signals and performs different processing on the PWM signals according to configuration information, and the PWM signals are sent by optical fibers or physical I / O interfaces. Compared with the prior art, the application can realize free switching of two operation modes of optical fibers and physical I / O interfaces under the same real-time architecture, adapt the controller application scene of the optical fibers and the physical I / O according to different modes, and improves the adaptability of the controller under various interface application scenes.

Description

Technical Field

[0001] This invention relates to the field of rapid prototyping control, and in particular to a controller implementation method and controller that supports fiber optic and physical interfaces. Background Technology

[0002] With the rapid development of industrial automation, power electronics, and embedded systems, controllers need to handle larger volumes of data and respond in shorter timeframes. This is especially true in applications such as power system protection, servo control, and real-time simulation, which place higher demands on controller interface compatibility, transmission speed, and flexibility. Fiber optic interfaces offer high-speed data transmission capabilities to meet the needs of low-latency, high-volume data transmission, while physical I / O interfaces are compatible with the access and control of traditional power equipment. Traditional controllers typically support only a single interface (fiber optic or physical I / O) and their configurations are usually fixed, making parameter adjustments difficult and necessitating hardware replacement or redesign for different application scenarios. Summary of the Invention

[0003] The purpose of this invention is to overcome the problem of the single interface mode of existing controllers and provide a controller implementation method and apparatus that supports both optical fiber and physical interfaces.

[0004] The objective of this invention can be achieved through the following technical solutions:

[0005] As a first aspect of the present invention, a method for implementing a controller that supports optical fiber and physical interfaces is provided. The controller includes multiple optical fiber interfaces and physical I / O interfaces, an FPGA, and a CPU. The steps of the implementation method include:

[0006] The controller receives the controller interface operation mode configuration and PWM signal generation parameters sent by the host computer. The interface operation modes include fiber optic interface operation mode and physical I / O interface operation mode.

[0007] The controller receives data from the fiber optic port or physical I / O interface. The data collection and processing module in the FPGA deframes the fiber optic data and, according to the interface operation mode configuration issued by the host computer, uploads the output fiber optic interface data or physical I / O interface data to the CPU through the data upload module.

[0008] The controller CPU is loaded with a control algorithm model, which generates a modulation wave based on the sampled data uploaded by the FPGA and sends it to the FPGA along with the switching frequency and dead time data;

[0009] The FPGA receives data from the CPU, generates a corresponding triangular carrier wave based on the switching frequency and dead time data, and compares the transmitted modulation wave with the triangular carrier wave to generate a PWM signal.

[0010] In the FPGA, the PWM signal transmission module receives the generated PWM signal and selects the PWM signal transmission method according to the interface operation mode: in the fiber optic interface operation mode, the generated PWM signal is framed into fiber optic serial data according to the frame structure and distributed to each fiber optic interface for transmission; in the physical I / O interface operation mode, the generated PWM signal is transmitted in parallel through the physical I / O ports.

[0011] As a preferred technical solution, the FPGA performs bit error and frame loss checks on the received fiber optic data. If a frame loss or erroneous frame is detected, the correct data from the previous frame is retained; if the data is correct, the data is refreshed.

[0012] The FPGA performs noise reduction processing on the received physical I / O interface data and sends the processed data to the data aggregation and processing module.

[0013] As a preferred technical solution, the data aggregation and processing module deframes the fiber optic data, checks whether the frame synchronization packet header and frame header are correct, and if correct, acquires the serial fiber optic data and writes the address into the cache; and converts the deframed serial fiber optic data or the raw data received by the physical I / O interface into a format that the CPU can recognize.

[0014] The data collection and processing module automatically selects to output fiber optic port data or physical I / O port data to the data upload module based on the operating mode configuration signal issued by the host computer.

[0015] As a preferred technical solution, the steps for the FPGA to upload data to the CPU via the data upload module are as follows:

[0016] After the FPGA data upload module detects that the data is ready, it writes the base address of the data collection and processing module and the CPU memory target address into the address register, configures the data transmission length and the corresponding interface name, and starts data transmission.

[0017] The CPU polls the status bits of the data upload module to assert or wait for the data upload module to generate an output interrupt; if it is based on an interrupt, the interrupt source is determined, and the data upload module begins to prepare for the next transmission.

[0018] As a preferred technical solution, the steps for generating the PWM signal using the FPGA are as follows:

[0019] The data receiving module in the FPGA receives the modulation wave, dead time, and switching frequency data sent by the CPU, and sends the data to the PWM signal generation module. The PWM signal generation module generates a corresponding triangular carrier wave based on the switching frequency and dead time data sent by the data receiving module, and compares the modulation wave with the triangular carrier wave to generate a PWM signal.

[0020] As a preferred technical solution, in the optical fiber interface operation mode, the generated PWM signal is framed with a frame header and a frame synchronization packet header according to the optical fiber communication protocol, and then framed into optical fiber serial data and distributed to each optical fiber port for transmission. Each PhaseLeg is 4 bits of data. The first two bits are the complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit. If it is not enabled, the IGBT will not be triggered, and the fourth bit is empty. Every 16 PhaseLeg pulse signals form a 64-bit data, which is sent to the external device through the optical fiber.

[0021] As a second aspect of the present invention, a controller supporting optical fiber and physical interface is provided, the controller comprising:

[0022] Multiple fiber optic interfaces and multiple physical I / O interfaces;

[0023] The FPGA is connected to multiple fiber optic interfaces and physical I / O interfaces, including a data acquisition unit and a signal transmission unit, and has both fiber optic interface operation mode and physical I / O interface operation mode.

[0024] The data acquisition unit receives data from the corresponding fiber optic interface or physical I / O interface based on the set interface operation mode, and uploads the sampled data after collecting and processing the received data.

[0025] The signal transmission unit receives the modulation wave and PWM parameter data sent from the source and generates a PWM signal; according to the set interface operation mode, it adopts the corresponding PWM signal transmission method and sends data through the corresponding optical fiber interface or physical I / O interface.

[0026] The CPU is loaded with a control program. The CPU receives the sampling data uploaded by the FPGA and generates a modulation wave, which is then sent to the FPGA along with the PWM parameter data.

[0027] As a preferred technical solution, the data acquisition unit includes:

[0028] The verification module performs error and frame loss checks on the received fiber optic data. If a frame loss or erroneous frame is detected, the previous frame of correct data is retained; if the data is correct, the data is refreshed; the verified data is then sent to the data aggregation and processing module.

[0029] The noise reduction module performs noise reduction processing on the received physical I / O interface data, and then sends the noise-reduced data to the data aggregation and processing module.

[0030] The data aggregation and processing module deframes the fiber optic data, checks the frame synchronization packet header and frame header for correctness, and if correct, acquires the serial fiber optic data and writes the address into the buffer; it converts the deframed serial fiber optic data or the raw data received by the physical I / O interface into a format recognizable by the CPU; and it automatically selects to output fiber optic port data or physical I / O port data to the data upload module according to the operating mode configuration signal issued by the host computer.

[0031] After detecting that the data is ready, the data upload module writes the base address of the data aggregation and processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission. If the data upload module generates an output interrupt, it determines the interrupt source (transmission completion or transmission error) and starts preparing for the next transmission.

[0032] As a preferred technical solution, the signal transmitting unit includes:

[0033] The data receiving module receives the modulation wave, dead time, and switching frequency data sent by the CPU and sends them to the PWM signal generation module.

[0034] The PWM signal generation module generates a corresponding triangular carrier wave based on the switching frequency and dead time data received by the data receiving module, and compares the modulated wave with the triangular carrier wave to generate a PWM signal.

[0035] The PWM signal transmission module receives the generated PWM signal and selects the PWM signal transmission method according to the interface operation mode: in the fiber optic interface operation mode, the generated PWM signal is framed into fiber optic serial data according to the frame structure and distributed to each fiber optic port for transmission; in the physical I / O interface operation mode, the generated PWM signal is transmitted in parallel through the physical I / O ports.

[0036] As a preferred technical solution, the PWM signal transmitting module, in the optical fiber interface operation mode, adds frame headers and frame synchronization packet headers to the optical fiber data according to the optical fiber communication protocol, frames it into optical fiber serial data, and distributes it to each optical fiber port for transmission.

[0037] Each PhaseLeg consists of 4 bits of data. The first two bits are the complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, and if it is not enabled, the IGBT will not be triggered. The fourth bit is left empty. Every 16 PhaseLeg pulse signals form a 64-bit data, which is sent to external devices via optical fiber.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] This invention configures the interface mode via a host computer, eliminating the need to switch versions or bitstream files. It is compatible with both fiber optic and physical I / O interfaces within the same real-time architecture, enabling seamless switching between these two operating modes. It allows the use of either fiber optic or physical I / O interfaces to receive electrical quantities and generate PWM signals to control power electronic system objects. By adapting to different controller application scenarios using either fiber optic or physical I / O, it enhances the controller's adaptability across various interface application scenarios. This solves the problems of traditional controllers, such as single interface and low data transmission efficiency, providing an efficient, flexible, and reliable solution for industrial control, power electronics, and real-time simulation. Attached Figure Description

[0040] Figure 1 This is a flowchart of a controller implementation method and apparatus that supports optical fiber and physical interface according to the present invention.

[0041] Figure 2 This is a schematic diagram of the controller device in this invention;

[0042] Figure 3 This is a flowchart of the data collection and processing module in this invention;

[0043] Figure 4 This is a flowchart illustrating the operation of the PWM signal transmission module in this invention.

[0044] Figure 5 This is a topology diagram of a five-stage H-bridge cascaded high-voltage frequency converter system in one embodiment of the present invention;

[0045] Figure 6 This is a simulation waveform diagram of the grid-side current in the fiber optic interface operation mode of a five-stage H-bridge cascaded high-voltage frequency converter in one embodiment of the present invention.

[0046] Figure 7 This is a simulation waveform of the grid-side current in the physical I / O interface operation mode of a five-stage H-bridge cascaded high-voltage frequency converter in one embodiment of the present invention. Detailed Implementation

[0047] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0048] Example 1

[0049] This invention addresses the problem that existing controllers have a single interface mode and cannot freely switch between fiber optic and physical I / O interfaces within the same real-time architecture. It proposes a controller implementation method and device that supports both fiber optic and physical interfaces. The solution provided by this invention does not require users to switch bit streams or change versions. It enables the implementation of a controller within the same real-time architecture that can support high-speed and low-latency data interaction of massive electrical data via fiber optics, as well as hardware-in-the-loop testing of all physical I / O interfaces.

[0050] like Figure 1 As shown, the controller implementation method supporting optical fiber and physical interface proposed in this invention includes the following steps:

[0051] Step 1: The host computer of the controller completes the configuration of the controller interface operating mode: fiber optic mode or physical I / O interface mode; and configures parameters such as switching frequency and dead time;

[0052] Specifically, in step 1, the user configures the controller interface operating mode. If the user configuration information Mode is set to 0, the fiber optic mode is selected; if the user configuration information Mode is set to 1, the physical I / O interface mode is selected. The configuration data will be sent to the FPGA. The user sets the carrier frequency and dead time. In this embodiment, the carrier frequency setting range is 1 to 1MHz, and the dead time setting range is 0 to 10us.

[0053] Step 2: The controller receives data from the fiber optic port or physical I / O interface. The FPGA performs error and frame loss checks on the fiber optic data and denoises the physical I / O interface data. The processed data is then sent to the data aggregation and processing module. Specifically, Step 2 includes the following steps:

[0054] Step 2a: The controller receives serial fiber optic data or physical I / O interface data;

[0055] Step 2b: The FPGA performs error and frame loss checks on the received fiber optic data. When checking for lost or erroneous frames, it retains the correct data from the previous frame. If the data is correct, it refreshes the data. The FPGA also performs noise reduction processing on the received physical I / O interface data.

[0056] Step 2c: The FPGA writes the verified and preprocessed data into the data aggregation and processing module.

[0057] Step 3: As Figure 2 As shown, the data aggregation and processing module in the FPGA deframes the fiber optic data and automatically selects to output either fiber optic port data or physical I / O port data to the data upload module based on the operating mode configuration signal issued by the host computer. Specifically, step 3 includes the following steps:

[0058] Step 3a: As Figure 3 As shown, the data aggregation and processing module deframes the fiber optic data, checks whether the frame synchronization packet header and frame header are correct. If correct, it acquires the serial fiber optic data, writes the address into the buffer, and converts the deframed fiber optic data or the raw data received by the physical I / O port into a format that the CPU can recognize (32-bit floating-point number or integer). It performs data type matching to ensure that the data uploaded by the FPGA is consistent with the CPU processing requirements.

[0059] Step 3b: The data aggregation and processing module automatically selects to output fiber optic port data or physical I / O port data to subsequent modules according to the operating mode configuration signal issued by the host computer; when the host computer issues a Mode value of 0, it outputs fiber optic port data, and when the Mode is 1, it outputs physical I / O port data.

[0060] Step 4: The data upload module in the FPGA uploads the data sent by the data aggregation and processing module to the CPU; this includes the following steps:

[0061] Step 4a: After the FPGA data upload module detects that the data is ready, it writes the base address of the data collection and processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission;

[0062] Step 4b: The CPU polls the IDLE status bit of the data upload module to assert and waits for the data upload module to generate an output interrupt; an interrupt occurs when the IDLE status bit goes high; if an output interrupt occurs, the interrupt source (transmission completed or an error occurred) is determined, and the data upload module begins preparing for the next transmission. The specific steps are as follows:

[0063] 4b.1). Verify IDLE=1, then program the IDLE bit to the start of transmission state (IDLE=0).

[0064] 4b.2). Program the IOC_En bit to the start of transmission state (IOC_En = 0) and set error interrupt enabled (ERR_En).

[0065] 4b.3). Write the transfer base address into the base address register. The transfer data at that source address must be valid and ready for transfer.

[0066] 4b.4). Write the destination address to the destination address register.

[0067] 4b.5). Write the number of bytes to be transferred. A maximum of 8,388,607 (8M) bytes can be specified in a single transfer. Write this to the BTT register to begin data transfer.

[0068] 4b.6). Poll the IDLE bit to assert (IDLE=1) and wait for an output interrupt to be generated (IOC_En=1).

[0069] 4b.7). If interrupted, determine the source of the interruption: transmission completed or an error occurred (ERR_En = 1).

[0070] 4b.8). Prepare for another transfer, return to step 4b.1.

[0071] Step 5: The user loads the control algorithm model into the controller CPU. The CPU generates a modulation wave based on the sampled data and sends it to the FPGA. The modulation wave is updated once per CPU cycle.

[0072] Step 6: Each FPGA receives data from the CPU, generates a corresponding triangular carrier wave based on the switching frequency, dead time, and other data sent by the CPU, and compares the modulation wave sent by the CPU with the triangular carrier wave to generate a PWM signal.

[0073] like Figure 2 As shown, in step 6, the data receiving module in the FPGA receives data such as the modulation wave, dead time, and switching frequency sent by the CPU, and sends the data to the PWM signal generation module; the PWM signal generation module generates a corresponding triangular carrier based on the switching frequency and dead time data sent by the data receiving module, and compares the modulation wave with the triangular carrier to generate a PWM signal.

[0074] Step 7: The PWM signal transmission module in the FPGA receives the generated PWM signal and switches the PWM signal transmission mode according to different modes: In fiber optic mode, the generated PWM signal is framed into fiber optic serial data according to the frame structure and distributed to each fiber optic port for transmission; in physical I / O mode, the generated PWM signal is transmitted in parallel through the physical I / O ports.

[0075] like Figure 4 As shown, the PWM signal transmission module in the FPGA switches the PWM signal transmission mode according to different modes: When Mode is 0, that is, in fiber optic mode, the fiber optic data is framed into fiber optic serial data according to the fiber optic communication protocol by adding a frame header and a frame synchronization packet header and distributing it to each fiber optic port for transmission according to different modes. Each bridge arm PhaseLeg is 4 bits of data. The first two bits are the complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit. If it is not enabled, the IGBT will not be triggered. The fourth bit is empty. Every 16 PhaseLeg pulse signals form a 64-bit data. A single fiber optic cable transmits 13 64-bit data signals, which are then sent to external devices via fiber optic cable. The frame structure is shown in the table below.

[0076] Table 1 Single Fiber Frame Format

[0077]

[0078] Table 2 Single Phaseleg Trigger Pulse Format

[0079]

[0080]

[0081] When Mode is 1, i.e. physical I / O interface mode, the generated PWM signal will be sent in parallel through the physical I / O port. The DO daughterboard has 32 channels, and there are a total of 4 DO daughterboards, supporting 128 PWM signals to be sent through the physical I / O interface.

[0082] Example 2

[0083] As another embodiment of the present invention, this embodiment provides a controller supporting optical fiber and physical interface constructed using the above controller implementation method, the controller comprising:

[0084] Multiple fiber optic interfaces and multiple physical I / O interfaces;

[0085] The FPGA is connected to multiple fiber optic interfaces and physical I / O interfaces, including a data acquisition unit and a signal transmission unit, and has both fiber optic interface operation mode and physical I / O interface operation mode.

[0086] The data acquisition unit receives data from the corresponding fiber optic interface or physical I / O interface based on the set interface operation mode, and uploads the sampled data after collecting and processing the received data.

[0087] The signal transmission unit receives the modulation wave and PWM parameter data sent from the source and generates a PWM signal; according to the set interface operation mode, it adopts the corresponding PWM signal transmission method and sends the data through the corresponding optical fiber interface or physical I / O interface;

[0088] The CPU is loaded with a control program. The CPU receives the sampling data uploaded by the FPGA and generates a modulation wave, which is then sent to the FPGA along with the PWM parameter data.

[0089] Specifically, the data acquisition unit includes:

[0090] The verification module performs error and frame loss checks on the received fiber optic data. If a frame loss or erroneous frame is detected, the previous frame of correct data is retained; if the data is correct, the data is refreshed; the verified data is then sent to the data aggregation and processing module.

[0091] The noise reduction module performs noise reduction processing on the received physical I / O interface data, and then sends the noise-reduced data to the data aggregation and processing module.

[0092] The data aggregation and processing module deframes the fiber optic data, checks the frame synchronization packet header and frame header for correctness, and if correct, acquires the serial fiber optic data and writes the address into the buffer; it converts the deframed serial fiber optic data or the raw data received by the physical I / O interface into a format recognizable by the CPU; and it automatically selects to output fiber optic port data or physical I / O port data to the data upload module according to the operating mode configuration signal issued by the host computer.

[0093] After detecting that the data is ready, the data upload module writes the base address of the data aggregation and processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission; if the data upload module generates an output interrupt, it determines the interrupt source and starts preparing for the next transmission.

[0094] Specifically, the signal transmitting unit includes:

[0095] The data receiving module receives the modulation wave, dead time, and switching frequency data sent by the CPU and sends them to the PWM signal generation module.

[0096] The PWM signal generation module generates a corresponding triangular carrier wave based on the switching frequency and dead time data received by the data receiving module, and compares the modulated wave with the triangular carrier wave to generate a PWM signal.

[0097] The PWM signal transmission module receives the generated PWM signal and selects the PWM signal transmission method according to the interface operation mode: in the fiber optic interface operation mode, the generated PWM signal is framed into fiber optic serial data according to the frame structure and distributed to each fiber optic port for transmission; in the physical I / O interface operation mode, the generated PWM signal is transmitted in parallel through the physical I / O ports.

[0098] Specifically, in the fiber optic interface operation mode, the PWM signal transmission module adds frame headers and frame synchronization packet headers to the fiber optic data according to the fiber optic communication protocol, frames it into fiber optic serial data, and distributes it to each fiber optic port for transmission. Each PhaseLeg consists of 4 bits of data. The first two bits are the complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, and if it is not enabled, the IGBT will not be triggered. The fourth bit is left empty. Every 16 PhaseLeg pulse signals form a 64-bit data, and a single fiber has a total of 13 64-bit data, which are sent to external devices through the fiber optic cable.

[0099] Example 3

[0100] This embodiment provides an example of real-time simulation of a five-stage H-bridge cascaded high-voltage frequency converter using the controller implementation method described in the above embodiment to verify the performance of the proposed solution.

[0101] Simulation model parameters: The input voltage is a 6kV medium-voltage power grid with a grid frequency of 50Hz. A series connection of power units is used. Each power module in the front stage employs diodes for full-wave rectification, followed by filtering with a large intermediate capacitor to smooth the voltage waveform and make it more DC-like. The rear stage uses an IGBT inverter bridge to invert DC into pulse-width modulated (PWM) voltage output and controls the fundamental amplitude and frequency of the output voltage waveform. No boost or filtering devices are required, allowing direct driving of ordinary medium-voltage motors. Each power unit is an H-bridge, requiring two Phaseleg signals. A five-stage H-bridge high-voltage frequency converter requires a total of 60 PWM signal inputs, which can be controlled using either fiber optic or physical I / O interfaces. The controller implementation method provided in this patent, supporting both fiber optic and physical interfaces, allows for free switching of controller interface operating modes on the host computer within the same real-time architecture. It can receive electrical quantities and issue PWM signals to control the high-voltage frequency converter system using either fiber optic or physical I / O interfaces.

[0102] like Figure 5 The diagram shown is a topology diagram of a five-stage H-bridge cascaded high-voltage frequency converter system. Figure 6 , 7 The waveforms show the grid-side current results under the controller's host computer sampling fiber optic interface operation mode and the physical I / O interface operation mode, respectively. Figure 6 It can be seen that this controller can freely switch between two operating modes—fiber optic and physical I / O interfaces—under the same real-time architecture. It adapts to different application scenarios of both fiber optic and physical I / O interfaces, and the grid-side current waveform quality of the high-voltage frequency converter is good with small errors in both interface operating modes. Therefore, this invention proposes a controller implementation method and device that supports both fiber optic and physical interfaces. By configuring the interface mode through a host computer, it enables free switching between the two interface operating modes, adapting to the requirements of different equipment and processes, and solving the shortcomings of existing controllers in data transmission and interface adaptation.

[0103] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A controller implementation method supporting fiber optic and physical interfaces, characterized in that, The controller includes multiple fiber optic interfaces and physical I / O interfaces, an FPGA, and a CPU. The implementation method includes the following steps: The controller receives the controller interface operation mode configuration and PWM signal generation parameters sent by the host computer. The interface operation modes include fiber optic interface operation mode and physical I / O interface operation mode. The controller receives data from the fiber optic port or physical I / O interface. The data collection and processing module in the FPGA deframes the fiber optic data and uploads the output fiber optic interface data or physical I / O interface data to the CPU through the data upload module according to the interface operation mode configuration issued by the host computer. The controller CPU is loaded with a control algorithm model, which generates a modulation wave based on the sampled data uploaded by the FPGA and sends it to the FPGA along with the switching frequency and dead time data; The FPGA receives data from the CPU, generates a corresponding triangular carrier wave based on the switching frequency and dead time data, and compares the transmitted modulation wave with the triangular carrier wave to generate a PWM signal. In the FPGA, the PWM signal transmission module receives the generated PWM signal and selects the PWM signal transmission method according to the interface operation mode: in the fiber optic interface operation mode, the generated PWM signal is framed into fiber optic serial data according to the frame structure and distributed to each fiber optic interface for transmission; in the physical I / O interface operation mode, the generated PWM signal is transmitted in parallel through the physical I / O ports.

2. The controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that, The FPGA performs error and frame loss checks on the received fiber optic data. If a frame loss or erroneous frame is detected, the previous frame of correct data is retained; if the data is correct, the data is refreshed. The FPGA performs noise reduction processing on the received physical I / O interface data and sends the processed data to the data aggregation and processing module.

3. The controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that, The data aggregation and processing module deframes the fiber optic data, checks whether the frame synchronization packet header and frame header are correct, and if correct, acquires the serial fiber optic data and writes the address into the buffer; it converts the deframed serial fiber optic data or the raw data received by the physical I / O interface into a format that the CPU can recognize. The data collection and processing module automatically selects to output fiber optic port data or physical I / O port data to the data upload module based on the operating mode configuration signal issued by the host computer.

4. The controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that, The specific steps for the FPGA to upload data to the CPU via the data upload module are as follows: After the FPGA data upload module detects that the data is ready, it writes the base address of the data collection and processing module and the CPU memory target address into the address register, configures the data transmission length and the corresponding interface name, and starts data transmission. The CPU polls the status bits of the data upload module to assert and waits for the data upload module to generate an output interrupt; if an output interrupt occurs, the interrupt source is determined, and the data upload module begins preparing for the next transmission.

5. A controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that, The specific steps for generating PWM signals using the FPGA are as follows: The data receiving module in the FPGA receives the modulation wave, dead time, and switching frequency data sent by the CPU, and sends the data to the PWM signal generation module. The PWM signal generation module generates a corresponding triangular carrier wave based on the switching frequency and dead time data sent by the data receiving module, and compares the modulation wave with the triangular carrier wave to generate a PWM signal.

6. The controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that, In the fiber optic interface operation mode, the generated PWM signal is framed with a frame header and a frame synchronization packet header according to the fiber optic communication protocol, and then framed into fiber optic serial data and distributed to each fiber optic port for transmission. Each bridge arm PhaseLeg consists of 4 bits of data. The first two bits are the complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, and if it is not enabled, it will not be triggered. The fourth bit is left empty. Every 16 bridge arm PhaseLeg pulse signals form a 64-bit data, which is sent to external devices via fiber optic cable.

7. A controller supporting fiber optic and physical interfaces, characterized in that, The controller includes: Multiple fiber optic interfaces and multiple physical I / O interfaces; The FPGA is connected to multiple fiber optic interfaces and physical I / O interfaces, including a data acquisition unit and a signal transmission unit, and has both fiber optic interface operation mode and physical I / O interface operation mode. The data acquisition unit receives data from the corresponding fiber optic interface or physical I / O interface based on the set interface operation mode, and uploads the sampled data after collecting and processing the received data. The signal transmission unit receives the modulation wave and PWM parameter data sent from the source and generates a PWM signal; according to the set interface operation mode, it adopts the corresponding PWM signal transmission method and sends data through the corresponding optical fiber interface or physical I / O interface. The CPU is loaded with a control program. The CPU receives the sampling data uploaded by the FPGA and generates a modulation wave, which is then sent to the FPGA along with the PWM parameter data.

8. A controller supporting fiber optic and physical interfaces according to claim 7, characterized in that, The data acquisition unit includes: The verification module performs error and frame loss checks on the received fiber optic data. If a frame loss or erroneous frame is detected, the previous frame of correct data is retained; if the data is correct, the data is refreshed; the verified data is then sent to the data aggregation and processing module. The noise reduction module performs noise reduction processing on the received physical I / O interface data, and then sends the noise-reduced data to the data aggregation and processing module. The data aggregation and processing module deframes the fiber optic data, checks the frame synchronization packet header and frame header for correctness, and if correct, acquires the serial fiber optic data and writes the address into the buffer; it converts the deframed serial fiber optic data or the raw data received by the physical I / O interface into a format recognizable by the CPU; and it automatically selects to output fiber optic port data or physical I / O port data to the data upload module according to the operating mode configuration signal issued by the host computer. After detecting that the data is ready, the data upload module writes the base address of the data aggregation and processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission; if the data upload module generates an output interrupt, it determines the interrupt source and starts preparing for the next transmission.

9. A controller supporting optical fiber and physical interface according to claim 7, characterized in that, The signal transmitting unit includes: The data receiving module receives the modulation wave, dead time, and switching frequency data sent by the CPU and sends them to the PWM signal generation module. The PWM signal generation module generates a corresponding triangular carrier wave based on the switching frequency and dead time data received by the data receiving module, and compares the modulated wave with the triangular carrier wave to generate a PWM signal. The PWM signal transmission module receives the generated PWM signal and selects the PWM signal transmission method according to the interface operation mode: in the fiber optic interface operation mode, the generated PWM signal is framed into fiber optic serial data according to the frame structure and distributed to each fiber optic port for transmission; in the physical I / O interface operation mode, the generated PWM signal is transmitted in parallel through the physical I / O ports.

10. A controller supporting optical fiber and physical interface according to claim 9, characterized in that, The PWM signal transmission module, in the fiber optic interface operation mode, adds frame headers and frame synchronization packet headers to the fiber optic data according to the fiber optic communication protocol, frames it into fiber optic serial data, and distributes it to each fiber optic port for transmission. Each bridge arm PhaseLeg consists of 4 bits of data. The first two bits are the complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, and if it is not enabled, it will not be triggered. The fourth bit is left empty. Every 16 PhaseLeg pulse signals form a 64-bit data, which is sent to external devices via optical fiber.

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