Instruction execution method, processor, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, and discloses an instruction execution method, a processor, electronic equipment and a storage medium. According to the method, under the condition that a first instruction related to loop operation is in an execution stage, the electronic equipment judges whether a data dependency relationship exists between a second instruction to be executed and the first instruction or not; and if the data dependency relationship does not exist between the second instruction and the first instruction and the execution process of the second instruction does not involve the loop operation, executing the second instruction in the execution process of the first instruction. In this way, the second instruction and the first instruction can be processed in parallel, and the processing efficiency of the instructions can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction execution method, a processor, an electronic device and a storage medium. Background Art

[0002] The processor is the core component of the computer system, responsible for directing and controlling the operation of the computer. For example, the processor can read the instructions in the computer's memory, and then process the instructions (such as executing the instructions) to complete the instructions. Among them, the instruction processing process of the processor can include the following processing stages: decoding stage, operand acquisition stage, and execution stage.

[0003] Specifically, in the decoding stage, the processor splits and interprets the received instructions to obtain the category of the instructions, the method of obtaining the operands involved in the instructions, and the method of writing back (or storing) the instruction execution results. Among them, the operand represents the data involved in the instruction execution process. Then, in the operand acquisition stage, the processor can obtain the operand according to the operand acquisition method obtained in the decoding stage, and then in the execution stage, execute the instruction based on the obtained operand to obtain the instruction execution result. Then, the processor can write back the instruction execution result according to the write-back method obtained in the decoding stage, for example, write the instruction execution result back to the specified register.

[0004] It can be understood that the processor includes a sequential processor. The sequential processor can execute each instruction in the order of the storage or generation time of the instructions in the computer memory. For example, if instruction Inst_0 is generated or stored in the memory before instruction Inst_1, the sequential processor can execute instruction Inst_0 first, and then execute instruction Inst_1. It can be understood that since each instruction in the sequential processor needs to be completed in sequence, for instruction Inst_0 and instruction Inst_1, the sequential processor needs to control instruction Inst_1 to enter a certain processing stage after instruction Inst_0 ends a certain processing stage, that is, first execute instruction Inst_0 in the processing stage, and then execute instruction Inst_1. However, if instruction Inst_0 is an instruction involving a loop (or iteration) operation, the processing time of instruction Inst_0 in the processing stage is relatively long, resulting in a longer waiting time for instruction Inst_1, which results in a smaller number of instructions that can be processed by the sequential processor per unit time, thereby making the processing efficiency of the sequential processor relatively low. Summary of the invention

[0005] Embodiments of the present application provide an instruction execution method, a processor, an electronic device, and a storage medium.

[0006] In a first aspect, the present application provides an instruction execution method, which is applied to an electronic device, and the method includes: executing a first instruction, wherein the execution process of the first instruction involves a loop operation; detecting a second instruction, determining whether there is a data dependency relationship between the second instruction and the first instruction, and whether the execution process of the second instruction involves a loop operation; corresponding to the absence of a data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction does not involve a loop operation, executing the second instruction during the execution process of the first instruction.

[0007] In the method provided by the present application, when there is no data dependency between the second instruction and the first instruction and the second instruction does not involve a loop operation, the second instruction can be executed in parallel with the first instruction without waiting for the first instruction to be executed. This instruction execution method can increase the number of instructions processed by the processor per unit time, thereby improving the processor's processing efficiency of instructions.

[0008] In a possible implementation of the first aspect, determining whether there is a data dependency relationship between the second instruction and the first instruction includes: determining whether execution of the second instruction depends on a first execution result corresponding to the first instruction; if execution of the second instruction depends on the first execution result, determining that there is a data dependency relationship between the second instruction and the first instruction; or, determining whether a second execution result corresponding to the second instruction needs to be written back to the first register after the first execution result is written back to the first register; if the second execution result is written back to the first register after the first execution result is written back to the first register, determining that there is a data dependency relationship between the second instruction and the first instruction.

[0009] It can be understood that if the second instruction indicates: sum the operand A and operand B in register Reg_1 and register Reg_2, divide the sum by the operand C in register Reg_3, and write the second execution result back to register Reg_3, and operand A in register Reg_1 is the first execution result corresponding to the first instruction, then the electronic device can detect based on the target operation detection unit that the second instruction involves a write-after-read operation, that is, the execution of the second instruction needs to depend on the first execution result (that is, operand A) corresponding to the first instruction.

[0010] It can be understood that if the second instruction indicates: write the second execution result back to the register Reg_1, if the first execution result corresponding to the first instruction is also written back to the register Reg_1, then the electronic device can detect based on the target operation detection unit that the second instruction involves a write-after-write operation, that is, the second execution result corresponding to the second instruction needs to be written back to the first register after the first execution result is written back to the first register.

[0011] In a possible implementation of the first aspect, determining whether the execution of the second instruction depends on the first execution result corresponding to the first instruction includes: if the register to which the first execution result needs to be written back is the same as the register corresponding to the data involved in the second instruction, determining that the execution of the second instruction depends on the first execution result corresponding to the first instruction.

[0012] Based on the above example, if the electronic device determines that the register corresponding to operand A (ie, register Reg_1) is the same register as the register to which the first execution result is written back, it can be determined that the execution of the second instruction depends on the first execution result corresponding to the first instruction.

[0013] In a possible implementation of the first aspect, the processor includes at least one first execution unit and at least one second execution unit, the first execution unit is used to execute instructions involving loop operations; the second execution unit is used to execute instructions not involving loop operations.

[0014] In a possible implementation of the first aspect, executing a second instruction during the execution of a first instruction includes: during the execution of the first instruction based on a first execution unit among at least one first execution unit, executing the second instruction based on a second execution unit among at least one second execution unit.

[0015] In a possible implementation of the first aspect, the method also includes: corresponding to the absence of a data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, when the number of at least one first execution unit is one, executing the second instruction after the first execution unit completes the execution of the first instruction; or, executing the first sub-stage corresponding to the second instruction during the execution of the second sub-stage corresponding to the first instruction after the first execution unit completes the execution of the first sub-stage in the execution stage corresponding to the first instruction, wherein the second sub-stage is a sub-stage executed after the first sub-stage.

[0016] As later Figure 5A As shown, if Inst_0 (i.e., the first instruction) experiences the V1 stage corresponding to the first execution unit at time t3-t4, then Inst_1 (i.e., the second instruction) can enter the V1 stage after Inst_0 ends the V1 stage, that is, Inst_1 experiences the V1 stage corresponding to the first execution unit at time t4-t5.

[0017] As later Figure 5B As shown, if Inst_0 experiences the V3 stage corresponding to the first execution unit at time t7-t8, then Inst_1 can enter the V1 stage after Inst_0 ends the V3 stage, that is, Inst_1 experiences the V1 stage at time t8-t9.

[0018] In this way, the execution units of instructions involving loop operations and instructions not involving loop operations are different, so the execution efficiency of different types of instructions can be improved. In addition, when both the first instruction and the second instruction involve loop operations, in some schemes, the second instruction does not need to wait for the first instruction to be fully executed before starting to execute, but starts to execute after the first instruction ends a certain execution sub-stage. This method can also improve the execution efficiency of the instructions.

[0019] In a possible implementation of the first aspect, the method further includes: corresponding to the absence of a data dependency between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, in the case where the number of at least one first execution unit is multiple, in the process of executing the first instruction based on one first execution unit among the multiple first execution units, executing the second instruction based on another first execution unit among the multiple first execution units.

[0020] As later Figure 6 As shown, since both Inst_0 and Inst_1 involve loop operations and the processor has multiple first execution units, Inst_1 can be executed during the execution of Inst_0. In this way, the first instruction can be executed in parallel with the second instruction in different first execution units. This way can also improve the execution efficiency of instructions.

[0021] In a possible implementation of the first aspect, the method also includes: corresponding to the existence of a data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction does not involve a loop operation, after one of the at least one first execution units completes the execution of the first instruction, the second instruction is executed based on one of the at least one second execution units.

[0022] As later Figure 7 As shown, if Inst_0 experiences the V3 stage at time t7-t8, then Inst_1 can enter the V1 stage after Inst_0 ends the V3 stage, that is, Inst_1 experiences the V1 stage corresponding to the first execution unit at time t8-t9.

[0023] In a possible implementation of the first aspect, the method also includes: corresponding to the existence of a data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, when the number of at least one first execution unit is one, executing the second instruction after the first execution unit completes the execution of the first instruction.

[0024] It can be understood that the timing diagram of the first instruction and the second instruction in this case is the same as that in the previous text. Figure 5B The same as shown, no further description is given here.

[0025] In a possible implementation of the first aspect, the method also includes: corresponding to the existence of a data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, when there are multiple first execution units, after one of the multiple first execution units completes the execution of the first instruction, the second instruction is executed based on another first execution unit among the multiple first execution units.

[0026] As later Fig.10 As shown, if Inst_0 experiences the V3 stage at time t7-t8, then Inst_1 can enter the V1 stage after Inst_0 ends the V3 stage, that is, Inst_1 experiences the V1 stage corresponding to the first execution unit at time t8-t9.

[0027] It can be understood that in the above method, there is a data dependency between the second instruction and the first instruction. For example, when the second instruction involves a read-after-write operation, the second instruction must be executed after the first instruction ends. This can avoid the problem that when the first execution result corresponding to the first instruction is not obtained, the second instruction mistakenly executes other data as the first execution result, thereby obtaining an erroneous second execution result.

[0028] In addition, when the second instruction involves a write-after-write operation, this method can also avoid the problem of data storage errors in the register caused by the second instruction mistakenly taking other data as the first execution result when the first execution result corresponding to the first instruction is not obtained, and then writing the second execution result corresponding to the second instruction back to after the first execution result. Therefore, the method provided by the present application can ensure the accuracy of the second execution result.

[0029] In a second aspect, the present application provides a processor, comprising: a first instruction execution unit, used to execute a first instruction, wherein the execution process of the first instruction involves a loop operation; a judgment unit, used to detect a second instruction, and judge whether there is a data dependency relationship between the second instruction and the first instruction, and whether the execution process of the second instruction involves a loop operation; a second instruction execution unit, used to execute the second instruction during the execution process of the first instruction in response to the absence of a data dependency relationship between the second instruction and the first instruction and the fact that the execution process of the second instruction does not involve a loop operation.

[0030] In a third aspect, the present application provides an electronic device, which includes the processor involved in the second aspect.

[0031] In a fourth aspect, the present application provides a readable storage medium having instructions stored thereon, which, when executed on an electronic device, causes the electronic device to execute the first aspect and any possible implementation of the instruction execution method of the first aspect.

[0032] Among them, the beneficial effects of the second to fourth aspects can refer to the beneficial effects of the first aspect and any possible implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A According to some embodiments of the present application, a schematic diagram of a scene in which a mobile phone 100 photographs a target object 102 is shown;

[0034] Figure 1B According to some embodiments of the present application, a schematic diagram of a process of a sequential processor processing instructions is shown;

[0035] Figure 2 According to some embodiments of the present application, a schematic diagram of a process of processing instructions by a processor provided by the present application is shown;

[0036] Figure 3 According to some embodiments of the present application, a flowchart of an instruction execution method provided by the present application is shown;

[0037] Figure 4 According to some embodiments of the present application, a timing diagram of a first instruction and a second instruction of a first type undergoing various processing stages is shown;

[0038] Figure 5A According to some embodiments of the present application, a timing diagram of a second type of first instruction and a second instruction undergoing various processing stages is shown;

[0039] Figure 5B According to some embodiments of the present application, a timing diagram of a third type of first instruction and a second instruction undergoing various processing stages is shown;

[0040] Figure 6 According to some embodiments of the present application, a schematic diagram of the timing of a fourth first instruction and a second instruction undergoing various processing stages is shown;

[0041] Figure 7 According to some embodiments of the present application, a fifth timing diagram of a first instruction and a second instruction undergoing various processing stages is shown;

[0042] Figure 8 According to some embodiments of the present application, a timing diagram of a sixth first instruction and a second instruction undergoing various processing stages is shown;

[0043] Fig. 9 According to some embodiments of the present application, a timing diagram of a seventh first instruction and a second instruction undergoing various processing stages is shown;

[0044] Fig.10According to some embodiments of the present application, a timing diagram of an eighth first instruction and a second instruction undergoing various processing stages is shown;

[0045] Fig.11 According to some embodiments of the present application, a schematic diagram of the hardware structure of an electronic device is shown. DETAILED DESCRIPTION

[0046] The illustrative embodiments of the present application include, but are not limited to, instruction execution methods, processors, electronic devices, and storage media.

[0047] It can be understood that the electronic devices to which the instruction execution method provided in the embodiments of the present application is applicable may include, but are not limited to, mobile phones, smart TVs, wearable devices, tablet computers, computers with wireless transceiver functions, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and the like.

[0048] The following first explains the specific terms involved in the embodiments of the present application.

[0049] Processor: The core component of a computer system that is responsible for executing computer instructions to complete tasks such as computing, storage, and control. The main functions of a processor include instruction fetching, decoding, executing, and writing back results.

[0050] Sequential processor: A type of processor that can execute instructions strictly in the order of operations specified by the computer program. Executing instructions based on a sequential processor can ensure the order of instructions, thereby ensuring the correctness and stability of the program.

[0051] Registers: Small storage areas inside the processor that store data. They are used to temporarily store data, instructions, addresses, and other temporary data involved in operations so that the processor can quickly access and process them. Registers have high read and write speeds and high transfer rates between registers.

[0052] Read after write (RAW): perform a write operation first and then perform a read operation. In this application, taking instruction Inst_0 and instruction Inst_1 as examples, after the first execution result corresponding to instruction Inst_0 is written to a certain register, if the first execution result needs to be read during the execution of instruction Inst_1, it means that instruction Inst_1 involves a read after write operation, which means that the execution of instruction Inst_1 depends on the first execution result corresponding to instruction Inst_0.

[0053] Write after write (WAW): Write operations are performed sequentially. In this application, taking instruction Inst_0 and instruction Inst_1 as examples, if the second execution result corresponding to instruction Inst_1 needs to be written to a register after the first execution result corresponding to instruction Inst_0, it means that instruction Inst_1 involves a write after write operation.

[0054] It can be understood that the instruction execution method involved in this application is applicable to any scenario including but not limited to image processing, audio processing, audio and video communication, industrial data processing (such as machine fault diagnosis), etc. Figure 1A As shown, when the mobile phone 100 detects that the user clicks the shooting control 101 in the camera application (such as a camera), the mobile phone 100 can shoot the target object 102 to obtain a target image corresponding to the target object 102. The processor inside the mobile phone 100 can adjust the parameters of the obtained target image to improve the quality of the target image.

[0055] In some embodiments, taking the case where the mobile phone 100 includes a sequential processor, the sequential processor may first adjust the contrast of the target image based on the contrast adjustment instruction, and store the target image after the contrast adjustment in a register. Then, the sequential processor may obtain the target image after the contrast adjustment from the register based on the exposure adjustment instruction, adjust the exposure of the target image, and then store the target image after the exposure adjustment in a register, and so on.

[0056] The following is a detailed description of the process of sequential processors processing instructions in the related art. It can be understood that for the sake of convenience, the following does not describe the process of sequential processors processing instructions in conjunction with specific application scenarios, but it should be understood that the following Figure 1B The instruction execution method provided in this application can be applied to instruction execution processes in various scenarios.

[0057] Figure 1B FIG. 1 is a schematic diagram showing the process of a sequential processor processing instructions. Figure 1B As shown, the instruction processing process of the sequential processor may include: a decoding (DE) stage, an operand fetching (RF) stage, and an execution (execute) stage. The execution stage may further include three sub-stages, such as a specific operation sub-stage V1, a specific operation sub-stage V2, and an execution result write-back (or storage) sub-stage V3.

[0058] Understandably, Figure 1B The execution phase includes three sub-phases, which is only an exemplary description of the present application. The number of sub-phases included in the execution phase and the execution content of each sub-phase can be flexibly adjusted according to the actual application scenario, and the present application embodiment does not limit this.

[0059] It can be understood that in some embodiments, the operands in the operand acquisition stage are obtained from a register file (RF). Therefore, for the convenience of description, the embodiments of the present application will subsequently use the RF stage to represent the operand acquisition stage to describe the processing process of the sequential processor on the instruction.

[0060] like Figure 1B As shown, taking the sequential processor processing instruction Inst_1 as an example, in the DE stage, the control unit in the sequential processor can control the decoding unit to split and interpret the instruction Inst_1, and obtain the category of the instruction Inst_1, the method of obtaining the operands involved in the instruction Inst_1, and the method of writing back the instruction execution result Res_1, etc. Taking the instruction Inst_1 indicating: sum the operands A and B in registers Reg_1 and Reg_2, divide the sum by the operand C in register Reg_3, and write the result back to register Reg_3 as an example, then in the DE stage, the category of the instruction Inst_1 obtained can be an arithmetic operation category; the method of obtaining the operands is to obtain the operand A from the register Reg_1, obtain the operand B from the register Reg_2, and obtain the operand C from the register Reg_3; the method of writing back the instruction execution result Res_1 is to write the instruction execution result Res_1 back to the register Reg_3.

[0061] In the RF stage, the control unit of the sequential processor can control the target operation detection unit to perform target operation detection on instruction Inst_1, for example, to detect whether instruction Inst_1 involves a write-after-read operation, that is, to detect whether the execution of instruction Inst_1 needs to depend on the execution result corresponding to the instruction executed before instruction Inst_1 (such as instruction Inst_0).

[0062] If yes, that is, the execution of instruction Inst_1 depends on the execution result of instruction Inst_0, the control unit can control the register reading unit to suspend reading the operands involved in instruction Inst_1 from the register. Taking the operand A involved in instruction Inst_1 as the instruction execution result Res_0 of instruction Inst_0 as an example, it can be understood that since the instruction execution result Res_0 has not been written back to the register Reg_1 when the instruction Inst_1 is in the RF stage, in order to avoid mistakenly taking the data in the register Reg_1 as the operand A and obtaining the wrong instruction execution result Res_1, the register reading unit can suspend reading the operands involved in instruction Inst_1 from the register.

[0063] The register reading unit can wait for the instruction Inst_0 to finish the V3 stage, that is, after the instruction execution result Res_0 is written back to the register Reg_1, and then obtain the instruction execution result Res_0, that is, the operand A, from the register Reg_1. Then, the control unit controls each execution unit to execute the instruction Inst_1 in the V1, V2 and V3 stages in sequence to complete the processing of the instruction Inst_1.

[0064] If not, that is, the execution of instruction Inst_1 does not depend on the execution result of instruction Inst_0, then the control unit can control the register reading unit to obtain the operand according to the operand acquisition method obtained in the decoding stage, for example, to obtain the operand A involved in instruction Inst_1 from register Reg_1, obtain the operand B from register Reg_2, and obtain the operand C from register Reg_3. Taking the case where instruction Inst_1 is in the RF stage and instruction Inst_0 is in the V1 stage as an example, the control unit can control the corresponding execution unit to execute instruction Inst_1 in the V1 stage after instruction Inst_0 ends the V1 stage and enters the V2 stage. Similarly, the control unit can control the corresponding execution unit to execute instruction Inst_1 in the V2 stage after instruction Inst_0 ends the V2 stage and enters the V3 stage, and then control the corresponding execution unit to execute instruction Inst_1 in the V3 stage after instruction Inst_0 ends the V3 stage. In this way, instruction Inst_1 can be processed.

[0065] like Figure 1B As shown, Figure 1B There are (N+1) execution units in total, namely, execution unit_0, execution unit_1, ..., execution unit_N. Each execution unit is used to execute instructions of a corresponding category. In this example, the category of instruction Inst_1 is an arithmetic operation category, so the control unit can control the execution unit used to execute instructions of the arithmetic operation category to execute instruction Inst_1.

[0066] Specifically, in the present application, the V1 stage and the V2 stage are used to execute different parts of the specific operation of the instruction. Taking the instruction Inst_1 as an arithmetic operation category, the V1 stage can be used to perform addition and subtraction operations, and the V2 stage can be used to perform multiplication and division operations. For example, in the V1 stage, the control unit can control the corresponding execution unit to perform the process of summing operands A and B; in the V2 stage, the control unit can control the corresponding execution unit to perform the process of dividing the sum result by the operand C in the register Reg_3.

[0067] In the V3 stage, the control unit can control the corresponding execution unit to write the instruction execution result Res_1 back to the corresponding register based on the write-back mode of the instruction execution result Res_1 involved in the instruction Inst_1 parsed in the decoding stage. For example, the instruction execution result Res_1 is written back to the register Reg_3.

[0068] It can be understood that the above only describes in detail the processing process of the sequential processor on the instruction by taking the instruction Inst_1 as an arithmetic operation instruction as an example, but it should be understood that the embodiment of the present application does not limit the category of instructions processed by the sequential processor. For example, the category of the instruction can also be a logical operation instruction, a data transfer instruction, etc.

[0069] Based on the above, in the case where the sequential processor needs to execute instruction Inst_0 first and then execute instruction Inst_1, if the execution of instruction Inst_1 depends on the execution result of instruction Inst_0, instruction Inst_1 needs to wait for instruction Inst_0 to finish the V3 stage before entering the V1 stage. If the execution of instruction Inst_1 does not depend on the execution result of instruction Inst_0, Figure 1B In each stage (i.e. DE stage, RF stage, execution stage (V1 stage, V2 stage, V3 stage)), instruction Inst_1 needs to wait for instruction Inst_0 to finish a stage before entering that stage. For example, instruction Inst_1 needs to wait for instruction Inst_0 to finish V1 stage before entering V1 stage.

[0070] It can be understood that if instruction Inst_0 is an instruction involving a loop (or iteration) operation, the time for instruction Inst_0 in the execution phase will be longer. Therefore, regardless of whether the execution of instruction Inst_1 depends on the execution result of instruction Inst_0, when instruction Inst_0 is a loop instruction, the waiting time for instruction Inst_1 will be longer than when instruction Inst_0 is a non-loop instruction. This situation will reduce the number of instructions that the sequential processor can process per unit time, thereby reducing the processing efficiency of the sequential processor.

[0071] In order to solve the above technical problems, the present application provides an instruction execution method. In this method, when the first instruction involving a loop operation is in the execution stage, the electronic device determines whether there is a data dependency relationship between the second instruction in the RF stage and the first instruction (for example, whether the execution of the second instruction depends on the execution result of the first instruction, or whether the instruction execution result corresponding to the second instruction needs to be written back to the register after the instruction execution result corresponding to the first instruction is written back to a certain register), and determines whether the execution process of the second instruction involves a loop operation. Wherein, the second instruction is the next instruction of the first instruction. If there is no data dependency relationship between the first instruction and the second instruction, and the second instruction does not involve a loop operation, the second instruction is executed during the execution of the first instruction.

[0072] It can be understood that the processor provided in the present application may include at least one first execution unit and at least one second execution unit, wherein the first execution unit is used to execute instructions involving loop operations, and the second execution unit is used to execute instructions not involving loop operations.

[0073] Therefore, in the above scheme, executing the second instruction during the execution of the first instruction may be executing the second instruction based on a second execution unit among at least one second execution unit during the execution of the first instruction based on a first execution unit among at least one first execution unit.

[0074] It can be understood that the first instruction is an instruction involving a loop operation. In some embodiments, the first instruction can instruct to find the quotient of two numerical values. For example, if the first instruction is used to instruct to find the quotient of two 32-bit numerical values ​​(such as A and B) to obtain the result C, since A and B have more bits, the quotient process is more complicated, and the processor cannot obtain the result C through a single operation. Therefore, the processor can obtain the result C through multiple loop iterations. For example, in the first iteration, the values ​​of the highest two digits in the result C (such as C0 and C1) can be obtained; in the second iteration, the values ​​of the last two digits of the highest two digits (such as C2 and C3) are obtained, and so on, until the values ​​of the last two digits (such as C14 and C15) are obtained. In this case, the result C can be expressed as: C = (C0, C1, ..., C14, C15).

[0075] In addition, in the above solution, the second instruction is an instruction that does not involve a loop operation. In some embodiments, the second instruction may indicate the sum of two values ​​(such as D and E). Therefore, in the case where there is no data dependency between the first instruction and the second instruction, the second instruction may be executed during the execution of the first instruction, for example, during the process of finding the quotient of A and B, D and E may be summed.

[0076] In the method provided by the present application, when there is no data dependency between the second instruction and the first instruction and the second instruction does not involve a loop operation, the second instruction can be executed in parallel with the first instruction without waiting for the first instruction to be executed. This instruction execution method can increase the number of instructions processed by the processor per unit time, thereby improving the processor's processing efficiency of instructions.

[0077] In some embodiments, if there is no data dependency between the second instruction and the first instruction, and the second instruction involves a loop operation, when the processor includes only one first execution unit, the second instruction can be controlled to enter the execution stage, i.e., execute the second instruction, after the first instruction ends the execution stage based on the first execution unit.

[0078] In some other embodiments, if there is no data dependency between the second instruction and the first instruction, and the second instruction involves a loop operation, when the processor includes multiple first execution units, since both the first instruction and the second instruction involve a loop operation, and the number of first execution units used to execute instructions involving loop operations is also multiple, the second instruction can be executed based on another first execution unit among the multiple first execution units during the execution of the first instruction based on one first execution unit among the multiple first execution units.

[0079] Take the example that the first instruction instructs to find the quotient of two 32-bit values ​​(such as A and B), and the second instruction instructs to find the quotient of two 32-bit values ​​(such as D and E). In this case, there is no data dependency between the first instruction and the second instruction, and the first instruction involves a loop operation, and the second instruction also involves a loop operation. Therefore, the second instruction can be executed based on different first execution units during the execution of the first instruction, for example, during the process of finding the quotient of A and B based on one first execution unit, the quotient of D and E can be found based on another first execution unit.

[0080] In some other embodiments, if there is a data dependency between the first instruction and the second instruction, and the second instruction does not involve a loop operation, after the first instruction is executed based on one of the at least one first execution units, the second instruction is executed based on one of the at least one second execution units.

[0081] For example, the first instruction instructs to find the quotient of two 32-bit values ​​(such as A and B), and the second instruction instructs to sum the quotient of A and B (such as result C) and value D. In this case, there is a data dependency between the first instruction and the second instruction, and the first instruction involves a loop operation, while the second instruction does not involve a loop operation. Therefore, the second instruction can be executed after the first instruction is executed. For example, after finding the quotient of A and B based on the first execution unit and obtaining the result C, the sum of C and D is calculated based on the second execution unit.

[0082] In some other embodiments, if there is a data dependency between the first instruction and the second instruction, and the second instruction involves a loop operation, when the number of at least one first execution unit is one, the second instruction is executed after the first execution unit completes execution of the first instruction.

[0083] In some other embodiments, if there is a data dependency between the first instruction and the second instruction, and the second instruction involves a loop operation, when there are multiple first execution units, after one of the multiple first execution units completes the execution of the first instruction, the second instruction is executed based on another first execution unit among the multiple first execution units.

[0084] Take, for example, a first instruction instructing to find the quotient of two 32-bit values ​​(such as A and B), and a second instruction instructing to further find the quotient of A and B (such as result C) and value D. In this case, there is a data dependency between the first instruction and the second instruction, and the first instruction involves a loop operation, and the second instruction also involves a loop operation. Therefore, the second instruction can be executed after the first instruction is executed, for example, after finding the quotient of A and B based on one first execution unit and obtaining the result C, the quotient of C and D is found based on another first execution unit.

[0085] Before describing in detail the instruction execution method provided in the present application, the instruction processing process of the processor in the present application is first described.

[0086] Figure 2 A schematic diagram of a process of processing instructions by a processor provided by the present application is shown. Figure 1B The instruction processing process of the sequential processor shown is similar. Figure 2 The instruction processing process of the processor shown also includes: DE stage, RF stage, and execution stage. The execution stage may further include three sub-stages, such as a specific operation sub-stage V1, a specific operation sub-stage V2, and an execution result write-back (or storage) sub-stage V3.

[0087] and Figure 1B The difference is, Figure 2The processor shown includes at least one first execution unit (for example, first execution unit_0, first execution unit_1, etc.) and at least one second execution unit (for example, second execution unit_0, etc.). The first execution unit is used to execute instructions involving loop operations, and the second execution unit is used to execute instructions not involving loop operations.

[0088] The instruction execution method provided by the present application is described in detail below with reference to the accompanying drawings. Figure 3 A flow chart of an instruction execution method provided by the present application is shown. Figure 3 The execution subjects of each step of the process shown are all electronic devices. For the convenience of description, Figure 3 The execution entities of each step will not be described repeatedly in the steps of the process shown. Figure 3 As shown, the method includes but is not limited to the following schemes:

[0089] 301: Execute a first instruction, wherein the execution process of the first instruction involves a loop operation.

[0090] In the embodiment of the present application, the electronic device can execute the first instruction based on the internal processor, and the first instruction is an instruction involving a loop operation. Among them, an example of the first instruction involving a loop operation has been described above and will not be repeated here.

[0091] Understandably, Figure 2 On the basis of, the electronic device executing the first instruction based on the internal processor can mean that the electronic device executes the first instruction based on a first execution unit in the processor.

[0092] 302: Detect a second instruction, determine whether there is a data dependency relationship between the second instruction and the first instruction, and whether the execution process of the second instruction involves a loop operation.

[0093] It can be understood that the electronic device detecting the second instruction can mean that the electronic device based on the processor in the following manner Figure 2 The RF stage is shown detecting the second instruction.

[0094] After detecting the second instruction, the electronic device may determine whether there is a data dependency relationship between the second instruction and the first instruction. For example, the electronic device may determine whether there is a data dependency relationship between the second instruction and the first instruction based on the following example: Figure 2 The target operation detection unit shown detects a target operation involved in the second instruction.

[0095] For example, if it is detected that the target operation involved in the second instruction is a read-after-write operation, that is, the execution of the second instruction needs to depend on the first execution result corresponding to the first instruction, it can be determined that there is a data dependency relationship between the second instruction and the first instruction.

[0096] It can be understood that if the second instruction indicates: sum the operand A and operand B in register Reg_1 and register Reg_2, divide the sum by the operand C in register Reg_3, and write the second execution result back to register Reg_3, and operand A in register Reg_1 is the first execution result corresponding to the first instruction, then the electronic device can detect based on the target operation detection unit that the second instruction involves a write-after-read operation, that is, the execution of the second instruction needs to depend on the first execution result (that is, operand A) corresponding to the first instruction.

[0097] In some embodiments, the electronic device determines that the operand A in register Reg_1 is the first execution result corresponding to the first instruction in a manner including but not limited to that the electronic device determines that the register corresponding to operand A (ie, register Reg_1) is the same register as the register to which the first execution result is written back.

[0098] For another example, if it is detected that the target operation involved in the second instruction is a write-after-write operation, that is, the second execution result corresponding to the second instruction needs to be written back to a register after the first execution result corresponding to the first instruction is written back to the register, then it can be determined that there is a data dependency between the second instruction and the first instruction.

[0099] It can be understood that if the second instruction indicates: write the second execution result back to the register Reg_1, if the first execution result corresponding to the first instruction is also written back to the register Reg_1, then the electronic device can detect based on the target operation detection unit that the second instruction involves a write-after-write operation, that is, the second execution result corresponding to the second instruction needs to be written back to a certain register (as an example of the first register) after the first execution result is written back to the register.

[0100] In some embodiments, the electronic device determines that the second execution result needs to be written back to a certain register after the first execution result is written back to the register. The method of writing back to the register includes but is not limited to that the electronic device determines that the register to which the second execution result needs to be written back is the same register as the register to which the first execution result needs to be written back.

[0101] Based on the foregoing, it can be known that if it is detected that the second instruction involves a read-after-write operation or a write-after-write operation, it can be determined that there is a data dependency relationship between the second instruction and the first instruction. Similarly, if it is detected that the second instruction does not involve a read-after-write operation or a write-after-write operation, it can be determined that there is no data dependency relationship between the second instruction and the first instruction.

[0102] It can be understood that, in different cases of whether there is a data dependency relationship between the second instruction and the first instruction, and whether the second instruction involves a loop operation, the execution method of the second instruction can refer to the description of 303-306 below.

[0103] Among them, taking the application scenario of the first instruction and the second instruction as an image processing scenario as an example, the contents indicated by the first instruction and the second instruction have been explained in the previous text, and will not be repeated hereafter.

[0104] 303: Corresponding to the fact that there is no data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction does not involve a loop operation, the second instruction is executed during the execution process of the first instruction.

[0105] It can be understood that if there is no data dependency between the first instruction and the second instruction, and the second instruction does not involve a loop operation, the electronic device can execute the second instruction during the execution of the first instruction. For example, the electronic device can execute the second instruction based on Figure 2 The first execution unit shown executes the first instruction, and executes the second instruction based on the second execution unit.

[0106] In the embodiment of the present application, when the first execution unit is about to complete the execution of the first instruction involving the loop operation, the first execution unit may Figure 2 The control unit shown sends the target instruction to indicate that the first instruction is about to be executed, and the control unit can control the first execution result to be written back to the corresponding register.

[0107] Specifically, after receiving the target instruction, the control unit can determine whether the reissue instruction issuance condition is currently met. If so, the control unit can send a confirmation instruction to the first execution unit, indicating that the control unit has received the target instruction sent by the first execution unit. In addition, the control unit can also Figure 2 The instruction reissue control subunit shown controls the first execution unit to execute the reissue instruction. It can be understood that the reissue instruction can capture the first execution result and write the first execution result back to the corresponding register.

[0108] If not, the control unit can determine whether the reissue instruction is currently satisfied at a fixed interval. When the reissue instruction is satisfied, the control unit sends a confirmation instruction to the first execution unit, and controls the first execution unit to execute the reissue instruction through the instruction reissue control subunit.

[0109] The embodiment of the present application does not limit the method for determining whether the conditions for issuing the reissued instruction are met. For example, if it is determined that other instructions can be inserted between the instruction currently in the RF stage (i.e., the instruction that is about to enter the execution stage) and the first instruction, it can be determined that the conditions for issuing the reissued instruction are currently met.

[0110] Figure 4 The following is a timing diagram of the first instruction and the second instruction undergoing various processing stages. Figure 2 and Figure 4The timing of each stage experienced by the first instruction and the second instruction in the situation shown in 303 is described in detail.

[0111] Understandably, Figure 4 The first instruction shown involves a loop operation, the second instruction does not involve a loop operation, and there is no data dependency relationship between the first instruction and the second instruction.

[0112] For example, the first instruction is Inst_0 and the second instruction is Inst_1. Figure 4 As shown, for Inst_0, at time t1-t2, Inst_0 experiences the DE stage; at time t2-t3, Inst_0 experiences the RF stage; at time t3-t4, Inst_0 experiences the V1 stage corresponding to the first execution unit; at time t4-t7, Inst_0 experiences the V2 stage corresponding to the first execution unit; at time t7-t8, Inst_0 experiences the V3 stage corresponding to the first execution unit.

[0113] It can be understood that since Inst_0 involves a loop operation, taking Inst_0 performing a loop operation in the V2 stage as an example, the execution time corresponding to the V2 stage (i.e., the time period between moments t4-t7) is longer than the execution time corresponding to the V1 or V3 stage (i.e., the time period between moments t3-t4 or t7-t8).

[0114] Continue as Figure 4 As shown, at time t5-t6, the first execution unit sends a target instruction to the control unit, and the control unit sends an acknowledgement instruction to the first execution unit.

[0115] For Inst_1, since Inst_1 is the instruction after Inst_0, Inst_1 is executed after Inst_0 is executed in the DE stage and the RF stage. For example, at time t2-t3, Inst_1 goes through the DE stage; at time t3-t4, Inst_1 goes through the RF stage.

[0116] It can be understood that since Inst_0 involves a loop operation, Inst_1 does not involve a loop operation, and there is no dependency relationship between Inst_0 and Inst_1, the second execution unit can execute Inst_1 while the first execution unit is executing Inst_0. Figure 4 As shown, at time t4-t5, Inst_1 experiences the V1 stage corresponding to the second execution unit; at time t5-t6, Inst_1 experiences the V2 stage corresponding to the second execution unit; at time t6-t7, Inst_1 experiences the V3 stage corresponding to the second execution unit.

[0117] It can be understood that the method provided by the present application can enable the first instruction involving a loop operation and the second instruction not involving a loop operation to be executed in parallel when there is no dependency relationship between the first instruction and the second instruction. Since the execution units of the first instruction and the second instruction are different, the second instruction does not need to wait for the execution of the first instruction. This instruction execution method can increase the number of instructions processed by the processor per unit time, thereby improving the processor's processing efficiency of instructions.

[0118] 304: Corresponding to the fact that there is no data dependency between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, when the number of at least one first execution unit is one, after the first execution unit completes the execution of the first sub-stage in the execution stage corresponding to the first instruction, during the execution of the second sub-stage corresponding to the first instruction, the first sub-stage corresponding to the second instruction is executed.

[0119] The second sub-stage is a sub-stage executed after the first sub-stage.

[0120] Figure 5A The following is a timing diagram of the second first instruction and the second instruction undergoing various processing stages. Figure 2 and Figure 5A The timing of each stage that the first instruction and the second instruction in this case go through is described in detail.

[0121] like Figure 5A As shown, for Inst_0, at time t1-t2, Inst_0 experiences the DE stage; at time t2-t3, Inst_0 experiences the RF stage; at time t3-t4, Inst_0 experiences the V1 stage corresponding to the first execution unit; at time t4-t7, Inst_0 experiences the V2 stage corresponding to the first execution unit; at time t7-t8, Inst_0 experiences the V3 stage corresponding to the first execution unit.

[0122] Continue as Figure 5A As shown, at time t5-t6, the first execution unit sends the target instruction corresponding to Inst_0 to the control unit, and the control unit sends the confirmation instruction corresponding to Inst_0 to the first execution unit.

[0123] For Inst_1, since Inst_1 is the instruction after Inst_0, Inst_1 is executed after Inst_0 is executed in the DE stage and the RF stage. For example, at time t2-t3, Inst_1 goes through the DE stage; at time t3-t4, Inst_1 goes through the RF stage.

[0124] It can be understood that since Inst_0 involves a loop operation, Inst_1 also involves a loop operation, and the processor has only one first execution unit, Inst_1 needs to be executed after Inst_0 completes a certain processing process. Figure 5A As shown, at time t4-t7, Inst_1 experiences the V1 stage corresponding to the first execution unit; at time t7-t10, Inst_1 experiences the V2 stage corresponding to the first execution unit; at time t10-t11, Inst_1 experiences the V3 stage corresponding to the first execution unit.

[0125] Specifically, in Figure 5A In the example, taking the first sub-stage as the V1 stage and the second sub-stage as the V2 stage, after the first execution unit completes the V1 stage corresponding to Inst_0 at time t4, it begins to enter the V2 stage corresponding to Inst_0. In addition, after the first execution unit completes the V1 stage corresponding to Inst_0 at time t4, Inst_1 may also begin to enter the V1 stage. For another example, taking the first sub-stage as the V2 stage and the second sub-stage as the V3 stage as an example, after the first execution unit completes the V2 stage corresponding to Inst_0 at time t7, it begins to enter the V3 stage corresponding to Inst_0. In addition, after the first execution unit completes the V2 stage corresponding to Inst_0 at time t7, Inst_1 may also begin to enter the V2 stage. And so on, until the execution stages of Inst_0 and Inst_1 are both completed.

[0126] In addition, at time t8-t9, the first execution unit sends the target instruction corresponding to Inst_1 to the control unit, and the control unit sends the confirmation instruction corresponding to Inst_1 to the first execution unit.

[0127] In some other embodiments, there is no data dependency between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation. When the number of at least one first execution unit is one, the second instruction can also be executed after the first instruction is executed based on the first execution unit.

[0128] Figure 5B The third type of timing diagram of the first instruction and the second instruction undergoing various processing stages is shown. Figure 2 and Figure 5B The timing of each stage experienced by the first instruction and the second instruction in the situation shown in 304 is described in detail.

[0129] Understandably, Figure 5B The first instruction and the second instruction shown both involve loop operations, and there is no data dependency relationship between the first instruction and the second instruction.

[0130] For example, the first instruction is Inst_0 and the second instruction is Inst_1. Figure 5B As shown, for Inst_0, at time t1-t2, Inst_0 experiences the DE stage; at time t2-t3, Inst_0 experiences the RF stage; at time t3-t4, Inst_0 experiences the V1 stage corresponding to the first execution unit; at time t4-t7, Inst_0 experiences the V2 stage corresponding to the first execution unit; at time t7-t8, Inst_0 experiences the V3 stage corresponding to the first execution unit.

[0131] Continue as Figure 5B As shown, at time t5-t6, the first execution unit sends the target instruction corresponding to Inst_0 to the control unit, and the control unit sends the confirmation instruction corresponding to Inst_0 to the first execution unit.

[0132] For Inst_1, since Inst_1 is the instruction after Inst_0, Inst_1 is executed after Inst_0 is executed in DE stage and RF stage. For example, at time t2-t3, Inst_1 goes through DE stage; at time t3-t8, Inst_1 goes through RF stage.

[0133] It can be understood that since Inst_0 involves a loop operation, Inst_1 also involves a loop operation, and the processor has only one first execution unit, Inst_1 can be executed after Inst_0 is executed. Figure 5B As shown, at time t8-t9, Inst_1 experiences the V1 stage corresponding to the first execution unit; at time t9-t12, Inst_1 experiences the V2 stage corresponding to the first execution unit; at time t12-t13, Inst_1 experiences the V3 stage corresponding to the first execution unit.

[0134] In addition, at time t10-t11, the first execution unit sends the target instruction corresponding to Inst_1 to the control unit, and the control unit sends the acknowledgement instruction corresponding to Inst_1 to the first execution unit.

[0135] It can be understood that in the method provided in the present application, the execution units of instructions involving loop operations and instructions not involving loop operations are different, which can improve the execution efficiency of different types of instructions.

[0136] 305: Corresponding to the fact that there is no data dependency between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, in the case where the number of at least one first execution unit is multiple, during the process of executing the first instruction based on one first execution unit among the multiple first execution units, the second instruction is executed based on another first execution unit.

[0137] Figure 6 A fourth timing diagram of the first instruction and the second instruction undergoing various processing stages is shown. Figure 2 and Figure 6 The timing of each stage experienced by the first instruction and the second instruction in the situation shown in 305 is described in detail.

[0138] Understandably, Figure 6 The first instruction and the second instruction shown both involve loop operations, and there is no data dependency relationship between the first instruction and the second instruction.

[0139] For example, the first instruction is Inst_0 and the second instruction is Inst_1. Figure 6 As shown, for Inst_0, at time t1-t2, Inst_0 experiences the DE stage; at time t2-t3, Inst_0 experiences the RF stage; at time t3-t4, Inst_0 experiences the V1 stage corresponding to the first execution unit (for example, the first execution unit_0); at time t4-t7, Inst_0 experiences the V2 stage corresponding to the first execution unit_0; at time t7-t8, Inst_0 experiences the V3 stage corresponding to the first execution unit_0.

[0140] Continue as Figure 6 As shown, at time t5-t6, the first execution unit sends the target instruction_0 corresponding to Inst_0 to the control unit, and the control unit sends the acknowledgement instruction_0 corresponding to Inst_0 to the first execution unit.

[0141] For Inst_1, since Inst_1 is the instruction after Inst_0, Inst_1 is executed after Inst_0 is executed in the DE stage and the RF stage. For example, at time t2-t3, Inst_1 goes through the DE stage; at time t3-t4, Inst_1 goes through the RF stage.

[0142] It can be understood that since Inst_0 involves a loop operation, Inst_1 also involves a loop operation, and the processor has multiple first execution units, therefore, Inst_1 can be executed during the execution of Inst_0. Figure 6 As shown, at time t4-t5, Inst_1 experiences the V1 stage corresponding to the first execution unit (for example, the first execution unit_1); at time t5-t8, Inst_1 experiences the V2 stage corresponding to the first execution unit_1; at time t8-t9, Inst_1 experiences the V3 stage corresponding to the first execution unit_1.

[0143] In addition, at time t6-t7, the first execution unit sends the target instruction_1 corresponding to Inst_1 to the control unit, and the control unit sends the acknowledgement instruction_1 corresponding to Inst_1 to the first execution unit.

[0144] It can be understood that in the method provided by the present application, since there are multiple first execution units for executing loop operations in the processor, when multiple instructions involving loop operations (such as the first instruction and the second instruction) need to be executed, the second instruction does not need to wait for the first instruction to be executed before being executed, that is, the first instruction and the second instruction can be executed in parallel in different first execution units. This method can also improve the execution efficiency of instructions.

[0145] 306: Corresponding to the data dependency relationship between the second instruction and the first instruction, the second instruction is executed after the first instruction is executed.

[0146] It can be understood that in the embodiment of the present application, if there is a data dependency relationship between the first instruction and the second instruction, regardless of whether the second instruction involves a loop operation or not, the second instruction can be executed after the first instruction is executed.

[0147] The following describes two situations: the second instruction involves a loop operation and the second instruction does not involve a loop operation.

[0148] The first type: The second instruction does not involve a loop operation.

[0149] Figure 7 The fifth type of first instruction and second instruction undergoing various processing stages is shown in FIG. Figure 2 and Figure 7 The timing of each stage experienced by the first instruction and the second instruction in the situation shown in 306 is described in detail.

[0150] Understandably, Figure 7 The first instruction shown involves a loop operation, the second instruction does not involve a loop operation, and there is a data dependency relationship between the first instruction and the second instruction.

[0151] For example, the first instruction is Inst_0 and the second instruction is Inst_1. Figure 7 As shown, for Inst_0, at time t1-t2, Inst_0 experiences the DE stage; at time t2-t3, Inst_0 experiences the RF stage; at time t3-t4, Inst_0 experiences the V1 stage corresponding to the first execution unit (for example, the first execution unit_0); at time t4-t7, Inst_0 experiences the V2 stage corresponding to the first execution unit_0; at time t7-t8, Inst_0 experiences the V3 stage corresponding to the first execution unit_0.

[0152] Continue as Figure 7 As shown, at time t5-t6, the first execution unit sends a target instruction to the control unit, and the control unit sends an acknowledgement instruction to the first execution unit.

[0153] It can be understood that since Inst_0 involves a loop operation, Inst_1 does not involve a loop operation, and there is a data dependency between the first instruction and the second instruction (for example, the second instruction involves a write-after-read operation), Inst_1 needs to wait for Inst_0 to end the execution phase in the RF phase before entering the execution phase.

[0154] like Figure 7 As shown, at time t2-t3, Inst_1 undergoes the DE stage; at time t3-t8, Inst_1 undergoes the RF stage; at time t8-t9, Inst_1 undergoes the V1 stage corresponding to the second execution unit (for example, the second execution unit_0); at time t9-t10, Inst_1 undergoes the V2 stage corresponding to the second execution unit; at time t10-t11, Inst_1 undergoes the V3 stage corresponding to the second execution unit.

[0155] It can be understood that in the method provided by the present application, there is a data dependency relationship between the second instruction and the first instruction. For example, when the second instruction involves a read-after-write operation, the second instruction needs to be executed after the first instruction ends. This can avoid the problem that when the first execution result corresponding to the first instruction is not obtained, the second instruction mistakenly executes other data as the first execution result, thereby obtaining an erroneous second execution result. Therefore, the method provided by the present application can ensure the accuracy of the second execution result.

[0156] In some other embodiments, if there is a data dependency between the first instruction and the second instruction, and the second instruction involves a write-after-write operation, that is, the second execution result corresponding to the second instruction needs to be written back to a certain register after the first execution result corresponding to the first instruction is written back to the register. In some embodiments, Inst_1 needs to wait for Inst_0 to end the execution phase before entering the execution phase. The timing diagram of the first instruction and the second instruction undergoing each processing phase in this case is similar to the above. Figure 7 The schematic diagrams shown are the same and will not be described again.

[0157] In some other embodiments, since the second instruction involves a write-after-write operation, Inst_1 may not wait for Inst_0 to finish the execution phase before entering the execution phase, as long as the second execution result corresponding to Inst_1 is written back to the register after the first execution result corresponding to Inst_0.

[0158] Figure 8The sixth type of timing diagram of the first instruction and the second instruction undergoing various processing stages is shown. Figure 2 and Figure 8 The timing of each stage experienced by the first instruction and the second instruction in the above case is described in detail.

[0159] and Figure 7 The difference is, Figure 8 , for Inst_1, at time t2-t3, Inst_1 experiences the DE stage; at time t3-t6, Inst_1 experiences the RF stage; at time t6-t7, Inst_1 experiences the V1 stage corresponding to the second execution unit (for example, the second execution unit_0); at time t7-t8, Inst_1 experiences the V2 stage corresponding to the second execution unit; at time t8-t9, Inst_1 experiences the V3 stage corresponding to the second execution unit.

[0160] It can be understood that in the method provided by the present application, when the second instruction involves a write-after-write operation, that is, when there is a data dependency relationship between the first instruction and the second instruction, the second instruction does not need to enter the execution stage (for example, enter the V1 stage) after the first instruction is completely executed (for example, the V3 stage is ended), and the execution completion time of the second instruction (for example, the V3 stage is ended) only needs to be after the execution completion time of the first instruction (for example, the V3 stage is ended). This method can improve the execution efficiency of instructions.

[0161] Second: The second instruction involves a loop operation.

[0162] It can be understood that in the case where the second instruction involves a write-after-read operation, if the first instruction and the second instruction both involve a loop operation, and the processor of the electronic device includes only one first execution unit, then the timing diagrams involved in the first instruction and the second instruction in this case are the same as those described above. Figure 5B The same as shown, no further description is given here.

[0163] In addition, in the case where the second instruction involves a write-after-write operation, if both the first instruction and the second instruction involve a loop operation, and the processor of the electronic device includes only one first execution unit, then in one embodiment, the timing diagrams involved in the first instruction and the second instruction can still be as described above. Figure 5B shown.

[0164] In some other embodiments, since the second instruction involves a write-after-write operation, Inst_1 may not wait for Inst_0 to finish the execution phase before entering the execution phase, as long as the second execution result corresponding to Inst_1 is written back to the register after the first execution result corresponding to Inst_0. This method can improve the processing efficiency of instructions. The timing diagram of the first instruction and the second instruction in this case can be seen in Fig. 9 .

[0165] like Fig. 9 As shown, Figure 5B The difference is that for Inst_1, at time t2-t3, Inst_1 experiences the DE stage; at time t3-t6, Inst_1 experiences the RF stage; at time t6-t7, Inst_1 experiences the V1 stage corresponding to the first execution unit; at time t7-t10, Inst_1 experiences the V2 stage corresponding to the first execution unit; at time t10-t11, Inst_1 experiences the V3 stage corresponding to the first execution unit.

[0166] In some other embodiments, when the second instruction involves a read-after-write operation, if both the first instruction and the second instruction involve a loop operation, and the processor of the electronic device includes a plurality of first execution units (such as a first execution unit_0 and a first execution unit_1), then the timing diagrams involved in the first instruction and the second instruction may be as follows: Fig.10 shown.

[0167] like Fig.10 As shown, for Inst_0, at time t1-t2, Inst_0 experiences the DE stage; at time t2-t3, Inst_0 experiences the RF stage; at time t3-t4, Inst_0 experiences the V1 stage corresponding to the first execution unit (for example, the first execution unit_0); at time t4-t7, Inst_0 experiences the V2 stage corresponding to the first execution unit_0; at time t7-t8, Inst_0 experiences the V3 stage corresponding to the first execution unit_0.

[0168] Continue as Fig.10 As shown, at time t5-t6, the first execution unit sends the target instruction_0 corresponding to Inst_0 to the control unit, and the control unit sends the acknowledgement instruction_0 corresponding to Inst_0 to the first execution unit.

[0169] For Inst_1, since Inst_1 is the instruction after Inst_0, Inst_1 is executed after Inst_0 is executed in the DE stage. For example, at time t2-t3, Inst_1 goes through the DE stage. At time t3-t8, Inst_1 goes through the RF stage.

[0170] It can be understood that since Inst_0 involves a loop operation, Inst_1 also involves a loop operation, and the processor has multiple first execution units, and Inst_1 involves a write-after-read operation, therefore, Fig.10As shown, at time t8-t9, Inst_1 experiences the V1 stage corresponding to the first execution unit (for example, the first execution unit_1); at time t9-t12, Inst_1 experiences the V2 stage corresponding to the first execution unit_1; at time t12-t13, Inst_1 experiences the V3 stage corresponding to the first execution unit_1.

[0171] In addition, at time t10-t11, the first execution unit sends a target instruction_1 corresponding to Inst_1 to the control unit, and the control unit sends a confirmation instruction_1 corresponding to Inst_1 to the first execution unit.

[0172] In some other embodiments, when the second instruction involves a write-after-write operation, if both the first instruction and the second instruction involve a loop operation, and the processor of the electronic device includes a plurality of first execution units (e.g., first execution unit_0 and first execution unit_1), then the timing diagrams involved in the first instruction and the second instruction may be as described above. Fig.10 shown.

[0173] In some other embodiments, since the second instruction involves a write-after-write operation, Inst_1 may not wait for Inst_0 to finish the execution phase before entering the execution phase, as long as it ensures that the second execution result corresponding to Inst_1 is written back to the register after the first execution result corresponding to Inst_0. In some embodiments, the timing diagram of the first instruction and the second instruction in this case can be as shown above. Figure 6 shown.

[0174] In some embodiments, the present application further proposes a processor, the processor comprising: a first instruction execution unit, configured to execute a first instruction, wherein the execution process of the first instruction involves a loop operation;

[0175] A determination unit, configured to detect a second instruction, determine whether there is a data dependency relationship between the second instruction and the first instruction, and whether an execution process of the second instruction involves a loop operation;

[0176] The second instruction execution unit is used to execute the second instruction during the execution of the first instruction when there is no data dependency between the second instruction and the first instruction and the execution process of the second instruction does not involve a loop operation.

[0177] In some embodiments, the embodiments of the present application further provide a readable storage medium, on which instructions are stored, and when the instructions are executed on an electronic device, the electronic device executes the instruction execution method described in the above embodiments.

[0178] In some embodiments, the present application also provides an electronic device, which includes the processor described above.

[0179] Fig.11 FIG. 1 is a schematic diagram showing the structure of an electronic device provided in an embodiment of the present application. Fig.11 As shown, the electronic device may include a processor 110 (the processor 110 may be a processor provided in an embodiment of the present application), an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0180] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0181] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0182] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0183] A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or circulated. If the processor 110 needs to use the instruction or data again, it may be directly called from the above-mentioned memory. Repeated access is avoided, the waiting time of the processor 110 is reduced, and the efficiency of the system is improved. The processor may be used to execute the instruction execution method mentioned in the present application.

[0184] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music and videos can be stored in the external memory card.

[0185] The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor.

[0186] The SIM card interface 195 is used to connect a SIM card.

[0187] It will be understood that, as used herein, the term "module" may refer to or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory that executes one or more software or firmware programs, a combinational logic circuit, and / or other appropriate hardware components that provide the described functionality, or may be part of these hardware components.

[0188] It is understood that in each embodiment of the present application, the processor may be a microprocessor, a digital signal processor, a microcontroller, etc., and / or any combination thereof. According to another aspect, the processor may be a single-core processor, a multi-core processor, etc., and / or any combination thereof.

[0189] The various embodiments disclosed in the present application may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application may be implemented as a computer program or program code executed on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0190] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0191] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0192] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-read-only memories, CD-ROMs), magneto-optical disks, read-only memories (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) using the Internet in electrical, optical, acoustic or other forms of propagation signals. Accordingly, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0193] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0194] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0195] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0196] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. A method for executing an instruction, characterized in that: Applied to electronic equipment, the method comprises: Executing a first instruction, wherein the execution process of the first instruction involves a loop operation; Detecting a second instruction, determining whether there is a data dependency relationship between the second instruction and the first instruction, and whether an execution process of the second instruction involves a loop operation; Corresponding to the fact that there is no data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction does not involve a loop operation, the second instruction is executed during the execution process of the first instruction.

2. The method according to claim 1, characterized in that The determining whether there is a data dependency relationship between the second instruction and the first instruction includes: Determine whether the execution of the second instruction depends on the first execution result corresponding to the first instruction; if the execution of the second instruction depends on the first execution result, determine that there is a data dependency relationship between the second instruction and the first instruction; or, Determine whether a second execution result corresponding to the second instruction needs to be written back to the first register after the first execution result is written back to the first register; if the second execution result is written back to the first register after the first execution result is written back to the first register, determine that there is a data dependency relationship between the second instruction and the first instruction.

3. The method according to claim 2, characterized in that The determining whether the execution of the second instruction depends on the first execution result corresponding to the first instruction includes: If the register to which the first execution result needs to be written back is the same as the register corresponding to the data involved in the second instruction, it is determined that the execution of the second instruction depends on the first execution result corresponding to the first instruction.

4. The method according to claim 1, characterized in that: The electronic device comprises at least one first execution unit and at least one second execution unit, wherein the first execution unit is used to execute instructions involving loop operations; and the second execution unit is used to execute instructions not involving loop operations.

5. The method according to claim 4, characterized in that The executing of the second instruction during the execution of the first instruction includes: In the process of executing the first instruction based on one of the at least one first execution unit, the second instruction is executed based on one of the at least one second execution unit.

6. The method according to claim 4, characterized in that The method further comprises: Corresponding to the fact that there is no data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, In the case that the number of the at least one first execution unit is one, after the first execution unit completes the execution of the first sub-stage in the execution stage corresponding to the first instruction, during the execution of the second sub-stage corresponding to the first instruction, the first sub-stage corresponding to the second instruction is executed, wherein the second sub-stage is a sub-stage executed after the first sub-stage.

7. The method according to claim 4, characterized in that The method further comprises: Corresponding to the fact that there is no data dependency relationship between the second instruction and the first instruction, and the execution process of the second instruction involves a loop operation, In the case that there are multiple at least one first execution units, during the process of executing the first instruction based on one first execution unit among the multiple first execution units, the second instruction is executed based on another first execution unit among the multiple first execution units.

8. A processor, characterized in that: The processor comprises: A first instruction execution unit, configured to execute a first instruction, wherein the execution process of the first instruction involves a loop operation; A determination unit, configured to detect a second instruction, determine whether there is a data dependency relationship between the second instruction and the first instruction, and whether an execution process of the second instruction involves a loop operation; The second instruction execution unit is used to execute the second instruction during the execution of the first instruction when the data dependency relationship does not exist between the second instruction and the first instruction and the execution process of the second instruction does not involve a loop operation.

9. An electronic device, characterized in that: The electronic device comprises the processor of claim 8.

10. A readable storage medium, characterized in that: The readable storage medium stores instructions, and when the instructions are executed on an electronic device, the electronic device executes the instruction execution method according to any one of claims 1 to 7.

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