Optimization method and system for RTL batch test of RISC-VDSP chip and medium
Through the GUI, select the tested items and generate the test item collection folder, traverse and record the test items, and conduct RTL batch testing of the RISC-VDSP chip, solving the problem that test items cannot be classified and batch tested in the existing technology, improving the testing efficiency and realizing the timely processing of test data.
Patent Information
- Application Number
- CN202411858582.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-04-15
AI Technical Summary
Existing chip testing methods cannot classify and batch test all test items, resulting in low testing efficiency.
Select the items under test through the GUI, generate the test item collection folder, traverse the root directory where the test case is located, generate snapshots, record all test items, obtain the test set, and batch test the RTL of the RISC-VDSP chip to obtain the test process data and test results.
It realizes batch testing of all test items, improves testing efficiency, and ensures timely processing and management of test data by generating summary information and real-time transmission to the terminal.
Smart Images
Figure CN119829347A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to an optimization method, system and medium for RTL batch testing of RISC-VDSP chips. Background Art
[0002] The RTL batch automatic testing framework is used to perform batch automatic testing in the scenario of multiple projects / multiple test case sets at the RTL (Register-Transfer Level) level during VERILOG design.
[0003] The RTL batch automatic testing framework includes general configuration and independent configuration information for each project, a set of input stimuli (test cases) for each project, and the RTL design code for each project. It conforms to the test stimulus-test environment-test output architecture design and can be used to test the RTL code of each project, as well as the key data used by the RTL code. It can also test various input stimuli that may have specific functions in subsequent applications.
[0004] The test framework has the characteristics of batch and parallel testing, which can quickly verify the above test purposes and perform rapid migration and regression testing in inherited test projects;
[0005] The existing chip testing method cannot classify all test items and establish different test categories, so it is impossible to batch test all test items according to the RTL simulation program, and the testing efficiency is low. Summary of the invention
[0006] The purpose of the embodiments of the present application is to provide an optimization method, system and medium for RTL batch testing of RISC-VDSP chips, which improves test efficiency by traversing all test items and performing batch testing on the test items.
[0007] The embodiment of the present application also provides an optimization method for RTL batch testing of a RISC-VDSP chip, including:
[0008] Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested;
[0009] Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located;
[0010] Traverse the root directory where the test cases are located, generate snapshots, record all test items, and obtain the test set;
[0011] Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain the test process data and test results;
[0012] When all test sets are run, test logs are obtained, summary information is generated based on the test logs, and the summary information is archived and transmitted to the terminal in real time.
[0013] Optionally, in the RTL batch test optimization method of the RISC-VDSP chip described in the embodiment of the present application, selecting the project to be tested through the GUI and generating a test item set folder based on the project to be tested specifically include:
[0014] Select the tested items through the GUI, classify the tested items based on the classification rules, and obtain multiple test categories;
[0015] Create a separate test subset for each test category;
[0016] Integrate the test sub-collections of all test categories and store them in folders to obtain test item collection folders.
[0017] Optionally, in the RTL batch test optimization method of the RISC-VDSP chip described in the embodiment of the present application, based on the test cases in the test item collection folder, the root directory where the test cases are located is analyzed, specifically including:
[0018] Each project under test contains multiple test item sets, each test item set contains multiple test cases, and each test case includes independent test data;
[0019] The test data includes initialized RAM data, Flash data, ROM data, OTP data, and timing-related external stimulus data;
[0020] Analyze the root directory where the test cases are located based on the data type in the test data package.
[0021] Optionally, in the optimization method for RTL batch testing of the RISC-VDSP chip described in the embodiment of the present application, batch testing is performed on the RTL of the RISC-VDSP chip based on the test set using all the test items in the test set to obtain test process data and test results, specifically including:
[0022] Copy test input data, test criteria code or scripts to the environment under test;
[0023] According to the test input data file, complete the intermediate processing process and generate the final data for use;
[0024] Gather test data, criterion code or script, and the tested environment for compilation to generate a program for RTL simulation;
[0025] The program is executed based on RTL simulation and all the processes from the start of operation to the results are obtained according to the test;
[0026] Collect the test process data and test results and print them into the test result folder.
[0027] Optionally, in the optimization method for RTL batch testing of the RISC-VDSP chip described in the embodiment of the present application, batch testing of the RTL of the RISC-VDSP chip using all test items in the test set based on the test set specifically includes:
[0028] The RTL batch test framework contains configuration data, project test data,
[0029] Configuration data is divided into two categories. One is the general configuration of the framework, which is used to provide the framework's interaction logic, test process control logic, data processing logic, and result summary logic. It is the main part of the framework. The other is the independent configuration of each project, including the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic. The general configuration will load and call the project's independent configuration during operation and apply it to each test item.
[0030] Optionally, in the optimization method for RTL batch testing of RISC-VDSP chips described in the embodiment of the present application, after all test sets are run, a test log is obtained, summary information is generated based on the test log, and the summary information is archived and transmitted to the terminal in real time, specifically including:
[0031] Get all test items in the test set, and based on the test items, get the test data corresponding to each test item;
[0032] Generate a separate test table for the test data corresponding to each test item;
[0033] Based on the test table of all test items, get the test log;
[0034] Summarize the test logs according to the test items to obtain summary information;
[0035] The summary information is archived according to the category of the test items, and the archived test logs are transmitted to the terminal.
[0036] In a second aspect, an embodiment of the present application provides an optimization system for RTL batch testing of a RISC-VDSP chip, the system comprising: a memory and a processor, the memory comprising a program of an optimization method for RTL batch testing of a RISC-VDSP chip, and when the program of the optimization method for RTL batch testing of a RISC-VDSP chip is executed by the processor, the following steps are implemented:
[0037] Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested;
[0038] Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located;
[0039] Traverse the root directory where the test cases are located, generate snapshots, record all test items, and obtain the test set;
[0040] Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain the test process data and test results;
[0041] When all test sets are run, test logs are obtained, summary information is generated based on the test logs, and the summary information is archived and transmitted to the terminal in real time.
[0042] Optionally, in the RTL batch test optimization system of the RISC-VDSP chip described in the embodiment of the present application, selecting a project to be tested through a GUI and generating a test item collection folder based on the project to be tested specifically include:
[0043] Select the tested items through the GUI, classify the tested items based on the classification rules, and obtain multiple test categories;
[0044] Create a separate test subset for each test category;
[0045] Integrate the test sub-collections of all test categories and store them in folders to obtain test item collection folders.
[0046] Optionally, in the RTL batch test optimization system of the RISC-VDSP chip described in the embodiment of the present application, based on the test cases in the test item collection folder, the root directory where the test cases are located is analyzed, specifically including:
[0047] Each project under test contains multiple test item sets, each test item set contains multiple test cases, and each test case includes independent test data;
[0048] The test data includes initialized RAM data, Flash data, ROM data, OTP data, and timing-related external stimulus data;
[0049] Analyze the root directory where the test cases are located based on the data type in the test data package.
[0050] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a method program for optimizing RTL batch testing of RISC-VDSP chips. When the method program for optimizing RTL batch testing of RISC-VDSP chips is executed by a processor, the steps of the method for optimizing RTL batch testing of RISC-VDSP chips as described in any one of the above items are implemented.
[0051] As can be seen from the above, an optimization method, system and medium for RTL batch testing of a RISC-VDSP chip provided in an embodiment of the present application select a project to be tested through a GUI, and generate a test item collection folder based on the project to be tested; based on the test case in the test item collection folder, analyze the root directory where the test case is located; traverse the root directory where the test case is located, generate snapshots, record all test items, and obtain a test set; based on the test set, batch test the RTL of the RISC-VDSP chip using all the test items in the test set to obtain test process data and test results; when all the test sets are run, obtain a test log, generate summary information based on the test log, archive the summary information and transmit it to a terminal in real time; and traverse all test items to batch test the test items to improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0053] Figure 1 A flowchart of an optimization method for RTL batch testing of RISC-VDSP chips provided in an embodiment of the present application;
[0054] Figure 2 A flow chart of a method for obtaining a test item set folder for an optimization method for RTL batch testing of a RISC-VDSP chip provided in an embodiment of the present application;
[0055] Figure 3 A flow chart of a root directory analysis method for test cases of an optimization method for RTL batch testing of RISC-VDSP chips provided in an embodiment of the present application. DETAILED DESCRIPTION
[0056] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0057] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0058] Please refer to Figure 1 , Figure 1 The flowchart of an optimization method for RTL batch testing of a RISC-VDSP chip in some embodiments of the present application. The optimization method for RTL batch testing of a RISC-VDSP chip is used in a terminal device, and the optimization method for RTL batch testing of a RISC-VDSP chip includes the following steps:
[0059] S101, selecting a project to be tested through a GUI, and generating a test item set folder based on the project to be tested;
[0060] S102, analyzing the root directory where the test cases are located based on the test cases in the test item set folder;
[0061] S103, traverse the root directory where the test case is located, generate a snapshot, record all test items, and obtain a test set;
[0062] S104, based on the test set, batch test the RTL of the RISC-VDSP chip using all the test items in the test set to obtain test process data and test results;
[0063] S105, when all test sets are run, a test log is obtained, summary information is generated based on the test log, the summary information is archived and transmitted to the terminal in real time.
[0064] It should be noted that by selecting the project to be tested and generating a test item collection folder, and recording all test items, batch testing is performed on the test items to improve test efficiency. After the test is completed, a test log is generated synchronously to ensure that the test data can be called at any time.
[0065] Please refer to Figure 2 , Figure 2 The present invention is a flowchart of a test item collection folder acquisition method of an optimization method for RTL batch testing of a RISC-VDSP chip in some embodiments of the present invention. According to an embodiment of the present invention, a project to be tested is selected through a GUI, and a test item collection folder is generated based on the project to be tested, specifically including:
[0066] S201, selecting a test item through a GUI, and classifying the test item based on a classification rule to obtain a plurality of test categories;
[0067] S202, establishing a test subset for each test category separately;
[0068] S203: Integrate the test sub-sets of all test categories and store them in a folder to obtain a test item set folder.
[0069] It should be noted that by analyzing the differences between the tested items, the tested items are classified, so as to establish corresponding test sub-collections for test items of different categories, and all test sub-collections are integrated to obtain a complete test item collection folder to ensure data integrity.
[0070] Please refer to Figure 3 , Figure 3 The present invention is a flowchart of a root directory analysis method for a test case in an optimization method for RTL batch testing of a RISC-VDSP chip in some embodiments of the present invention. According to an embodiment of the present invention, based on the test case in the test item collection folder, the root directory where the test case is located is analyzed, specifically including:
[0071] S301, each project under test includes multiple test item sets, each test item set includes multiple test cases, and each test case includes independent test data;
[0072] S302, the test data includes initialized RAM data, Flash data, ROM data, OTP data and timing-related external stimulus data;
[0073] S303, analyzing the root directory where the test case is located based on the data type in the test data packet.
[0074] According to an embodiment of the present invention, based on a test set, all test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain test process data and test results, specifically including:
[0075] Copy test input data, test criteria code or scripts to the environment under test;
[0076] According to the test input data file, complete the intermediate processing process and generate the final data for use;
[0077] Gather test data, criterion code or script, and the tested environment for compilation to generate a program for RTL simulation;
[0078] The program is executed based on RTL simulation and all the processes from the start of operation to the results are obtained according to the test;
[0079] Collect the test process data and test results and print them into the test result folder.
[0080] It should be noted that by analyzing the test items, obtaining test input data, test criterion code or script, testing the test items according to the RTL simulation program, and analyzing the test process and test results, abnormal data in the test process can be dynamically obtained.
[0081] According to an embodiment of the present invention, batch testing is performed on the RTL of the RISC-VDSP chip based on all test items in the test set, specifically including:
[0082] The RTL batch test framework contains configuration data, project test data,
[0083] Configuration data is divided into two categories. One is the general configuration of the framework, which is used to provide the framework's interaction logic, test process control logic, data processing logic, and result summary logic. It is the main part of the framework. The other is the independent configuration of each project, including the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic. The general configuration will load and call the project's independent configuration during operation and apply it to each test item.
[0084] According to an embodiment of the present invention, when all test sets are run, a test log is obtained, summary information is generated based on the test log, and the summary information is archived and transmitted to the terminal in real time, specifically including:
[0085] Get all test items in the test set, and based on the test items, get the test data corresponding to each test item;
[0086] Generate a separate test table for the test data corresponding to each test item;
[0087] Based on the test table of all test items, get the test log;
[0088] Summarize the test logs according to the test items to obtain summary information;
[0089] The summary information is archived according to the category of the test items, and the archived test logs are transmitted to the terminal.
[0090] It should be noted that, in order to facilitate batch testing, each test is performed in units of test item sets, and the test results will also be collected and summarized in the test item set directory and displayed in the form of a summary.
[0091] In a second aspect, an embodiment of the present application provides an optimization system for RTL batch testing of a RISC-VDSP chip, the system comprising: a memory and a processor, the memory comprising a program of an optimization method for RTL batch testing of a RISC-VDSP chip, and when the program of the optimization method for RTL batch testing of a RISC-VDSP chip is executed by the processor, the following steps are implemented:
[0092] Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested;
[0093] Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located;
[0094] Traverse the root directory where the test cases are located, generate snapshots, record all test items, and obtain the test set;
[0095] Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain the test process data and test results;
[0096] When all test sets are run, test logs are obtained, summary information is generated based on the test logs, and the summary information is archived and transmitted to the terminal in real time.
[0097] It should be noted that by selecting the project to be tested and generating a test item collection folder, and recording all test items, batch testing is performed on the test items to improve test efficiency. After the test is completed, a test log is generated synchronously to ensure that the test data can be called at any time.
[0098] According to an embodiment of the present invention, selecting a project to be tested through a GUI and generating a test item set folder based on the project to be tested specifically includes:
[0099] Select the tested items through the GUI, classify the tested items based on the classification rules, and obtain multiple test categories;
[0100] Create a separate test subset for each test category;
[0101] Integrate the test sub-collections of all test categories and store them in folders to obtain test item collection folders.
[0102] It should be noted that by analyzing the differences between the tested items, the tested items are classified, so as to establish corresponding test sub-collections for test items of different categories, and all test sub-collections are integrated to obtain a complete test item collection folder to ensure data integrity.
[0103] According to an embodiment of the present invention, based on the test cases in the test item collection folder, the root directory where the test cases are located is analyzed, specifically including:
[0104] Each project under test contains multiple test item sets, each test item set contains multiple test cases, and each test case includes independent test data;
[0105] The test data includes initialized RAM data, Flash data, ROM data, OTP data, and timing-related external stimulus data;
[0106] Analyze the root directory where the test cases are located based on the data type in the test data package.
[0107] According to an embodiment of the present invention, based on a test set, all test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain test process data and test results, specifically including:
[0108] Copy test input data, test criteria code or scripts to the environment under test;
[0109] According to the test input data file, complete the intermediate processing process and generate the final data for use;
[0110] Gather test data, criterion code or script, and the tested environment for compilation to generate a program for RTL simulation;
[0111] The program is executed based on RTL simulation and all the processes from the start of operation to the results are obtained according to the test;
[0112] Collect the test process data and test results and print them into the test result folder.
[0113] It should be noted that by analyzing the test items, obtaining test input data, test criterion code or script, testing the test items according to the RTL simulation program, and analyzing the test process and test results, abnormal data in the test process can be dynamically obtained.
[0114] According to an embodiment of the present invention, batch testing is performed on the RTL of the RISC-VDSP chip based on all test items in the test set, specifically including:
[0115] The RTL batch test framework contains configuration data, project test data,
[0116] Configuration data is divided into two categories. One is the general configuration of the framework, which is used to provide the framework's interaction logic, test process control logic, data processing logic, and result summary logic. It is the main part of the framework. The other is the independent configuration of each project, including the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic. The general configuration will load and call the project's independent configuration during operation and apply it to each test item.
[0117] According to an embodiment of the present invention, when all test sets are run, a test log is obtained, summary information is generated based on the test log, and the summary information is archived and transmitted to the terminal in real time, specifically including:
[0118] Get all test items in the test set, and based on the test items, get the test data corresponding to each test item;
[0119] Generate a separate test table for the test data corresponding to each test item;
[0120] Based on the test table of all test items, get the test log;
[0121] Summarize the test logs according to the test items to obtain summary information;
[0122] The summary information is archived according to the category of the test items, and the archived test logs are transmitted to the terminal.
[0123] It should be noted that, in order to facilitate batch testing, each test is performed in units of test item sets, and the test results will also be collected and summarized in the test item set directory and displayed in the form of a summary.
[0124] A third aspect of the present invention provides a computer-readable storage medium, which includes an optimization method program for RTL batch testing of RISC-VDSP chips. When the optimization method program for RTL batch testing of RISC-VDSP chips is executed by a processor, the steps of the optimization method for RTL batch testing of RISC-VDSP chips as described in any of the above items are implemented.
[0125] The invention discloses an optimization method, system and medium for RTL batch testing of a RISC-VDSP chip. The method comprises the following steps: selecting a project to be tested through a GUI, generating a test item collection folder based on the project to be tested; analyzing a root directory where the test case is located based on a test case in the test item collection folder; traversing the root directory where the test case is located, generating a snapshot, recording all test items and obtaining a test set; batch testing the RTL of a RISC-VDSP chip using all test items in the test set based on the test set to obtain test process data and test results; obtaining a test log after all the test sets have been run, generating summary information based on the test log, archiving the summary information and transmitting it to a terminal in real time; and batch testing the test items by traversing all test items to improve test efficiency.
[0126] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.
[0127] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0128] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0129] Those skilled in the art can understand that: all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, the aforementioned program can be stored in a readable storage medium, and when the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, and other media that can store program codes.
[0130] Or, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.
Claims
1. An optimization method for RTL batch testing of RISC-VDSP chips, characterized in that: include: Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested; Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located; Traverse the root directory where the test cases are located, generate snapshots, record all test items, and obtain the test set; Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain the test process data and test results; When all test sets are run, test logs are obtained, summary information is generated based on the test logs, and the summary information is archived and transmitted to the terminal in real time. Transfer the test process data and test results to the test result folder and save them to the terminal.
2. The optimization method for RTL batch testing of RISC-VDSP chips according to claim 1, characterized in that: Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested, including: Select the tested items through the GUI, classify the tested items based on the classification rules, and obtain multiple test categories; Create a separate test subset for each test category; Integrate the test sub-collections of all test categories and store them in folders to obtain test item collection folders.
3. The optimization method for RTL batch testing of RISC-VDSP chips according to claim 2, characterized in that: Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located, including Each project under test contains multiple test item sets, each test item set contains multiple test cases, and each test case includes independent test data; The test data includes initialized RAM data, Flash data, ROM data, OTP data, and timing-related external stimulus data; Analyze the root directory where the test cases are located based on the data type in the test data package.
4. The optimization method for RTL batch testing of RISC-VDSP chips according to claim 3, characterized in that: Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain the test process data and test results, including: Copy test input data, test criteria code or scripts to the environment under test; According to the test input data file, complete the intermediate processing process and generate the final data for use; Gather test data, criterion code or script, and the tested environment for compilation to generate a program for RTL simulation; The program is executed based on RTL simulation and all the processes from the start of operation to the results are obtained according to the test; Collect the test process data and test results and print them into the test result folder.
5. The optimization method for RTL batch testing of RISC-VDSP chips according to claim 4, characterized in that: Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip, including: The RTL batch test framework contains configuration data, project test data, Configuration data is divided into two categories. One is the general configuration of the framework, which is used to provide the framework's interaction logic, test process control logic, data processing logic, and result summary logic. It is the main part of the framework. The other is the independent configuration of each project, including the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic. The general configuration will load and call the project's independent configuration during operation and apply it to each test item.
6. The optimization method for RTL batch testing of RISC-VDSP chips according to claim 5, characterized in that: When all test sets are run, test logs are obtained, summary information is generated based on the test logs, and the summary information is archived and transmitted to the terminal in real time, including: Get all test items in the test set, and based on the test items, get the test data corresponding to each test item; Generate a separate test table for the test data corresponding to each test item; Based on the test table of all test items, get the test log; Summarize the test logs according to the test items to obtain summary information; The summary information is archived according to the category of the test items, and the archived test logs are transmitted to the terminal.
7. An optimization system for RTL batch testing of RISC-VDSP chips, characterized in that: The system includes: a memory and a processor, wherein the memory includes a program of an optimization method for RTL batch testing of a RISC-VDSP chip, and when the program of the optimization method for RTL batch testing of a RISC-VDSP chip is executed by the processor, the following steps are implemented: Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested; Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located; Traverse the root directory where the test cases are located, generate snapshots, record all test items, and obtain the test set; Based on the test set, all the test items in the test set are batch tested on the RTL of the RISC-VDSP chip to obtain the test process data and test results; When all test sets are run, test logs are obtained, summary information is generated based on the test logs, and the summary information is archived and transmitted to the terminal in real time.
8. The RTL batch test optimization system of the RISC-VDSP chip according to claim 7, characterized in that: Select the project to be tested through the GUI, and generate a test item collection folder based on the project to be tested, including: Select the tested items through the GUI, classify the tested items based on the classification rules, and obtain multiple test categories; Create a separate test subset for each test category; Integrate the test sub-collections of all test categories and store them in folders to obtain test item collection folders.
9. The RTL batch test optimization system of RISC-VDSP chip according to claim 8, characterized in that: Based on the test cases in the test item collection folder, analyze the root directory where the test cases are located, including Each project under test contains multiple test item sets, each test item set contains multiple test cases, and each test case includes independent test data; The test data includes initialized RAM data, Flash data, ROM data, OTP data, and timing-related external stimulus data; Analyze the root directory where the test cases are located based on the data type in the test data package.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes an optimization method program for RTL batch testing of RISC-VDSP chips. When the optimization method program for RTL batch testing of RISC-VDSP chips is executed by a processor, the steps of the optimization method for RTL batch testing of RISC-VDSP chips as described in any one of claims 1 to 6 are implemented.