Filter Instruction Code Generation Method Applied to a Controller

Abstract

The present application discloses a method for generating a filtering instruction code applied to a controller, which relates to the technical field of controller logic design. Through the present application, since a structured query statement input by a user is obtained, and then the structured query statement input by the user is processed to obtain a first instruction code, and a second instruction code is generated according to the first instruction code, and then a first truth table is generated according to the logical operation in the first instruction code, and a second truth table is generated according to the first truth table. Finally, a third instruction code is generated according to the second instruction code, and a permutation matrix is determined according to the third instruction code; the second instruction code, the second truth table and the permutation matrix are determined as the filtering instruction code applied to the controller, and the filtering instruction code applied to the controller is configured in the controller. By adopting the technical solution, the speed of database calculation operations can be improved, for calculation-intensive operations in the database, the throughput rate of database calculation can be effectively increased, and the latency can be reduced.

Description

Technical Field

[0001] This application relates to the technical field of controller logic design, and particularly to a method for generating filtered instruction codes applied to a controller. Background Art

[0002] Database operations generally require a large amount of computing resources and time. In related technologies, they are executed serially based on a Central Processing Unit (CPU). However, executing based on the CPU can only use the serial computing method, and each computing task in the database is executed one by one. With the continuous growth of data volume, performance bottlenecks will be faced when processing large-scale data sets.

[0003] Therefore, there is an urgent need for a method for generating filtered instruction codes applied to a controller, which can improve the speed of database computing operations, effectively improve the throughput rate of database computing for computing-intensive operations in the database, and reduce latency. Summary of the Invention

[0004] This application provides a method for generating filtered instruction codes applied to a controller to achieve the purpose of improving the speed of database computing operations, effectively improving the throughput rate of database computing for computing-intensive operations in the database, and reducing latency.

[0005] This application provides a method for generating filtered instruction codes applied to a controller, which is executed by the host side. The method includes:

[0006] Obtain a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user;

[0007] Generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code;

[0008] Loop and execute the logical operations in the first instruction code to generate a first truth table, and generate a second truth table according to the first truth table;

[0009] Generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code;

[0010] Determine the second instruction code, the second truth table, and the permutation matrix as the filtered instruction codes applied to the controller, and configure the filtered instruction codes applied to the controller into the controller.

[0011] This application also provides a device for generating filtered instruction codes applied to a controller, which is executed by the host side. The device includes:

[0012] The first acquisition module is used to acquire the structured query statement input by the user and generate a filtering expression according to the structured query statement input by the user;

[0013] The first generation module is used to generate a first instruction code according to the filtering expression and generate a second instruction code according to the first instruction code;

[0014] The second generation module is used to loop and execute the logical operations in the first instruction code, generate a first truth table, and generate a second truth table according to the first truth table;

[0015] The third generation module is used to generate a third instruction code according to the second instruction code and determine a permutation matrix according to the third instruction code;

[0016] The determination module is used to determine the second instruction code, the second truth table, and the permutation matrix as the filtering instruction code applied to the controller and configure the filtering instruction code applied to the controller into the controller.

[0017] This application also provides a host computer, including: a memory for storing a computer program; a processor for implementing the steps of the above-mentioned method for generating a filtering instruction code applied to a controller when executing the computer program.

[0018] This application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for generating a filtering instruction code applied to a controller are implemented.

[0019] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the above-mentioned method for generating a filtering instruction code applied to a controller are implemented.

[0020] Through this application, since the structured query statement input by the user is acquired, and then the structured query statement input by the user is processed to obtain a first instruction code, and a second instruction code is generated according to the first instruction code, and then a first truth table is generated according to the logical operations in the first instruction code, and a second truth table is generated according to the first truth table. Finally, a third instruction code is generated according to the second instruction code, and a permutation matrix is determined according to the third instruction code; the second instruction code, the second truth table, and the permutation matrix are determined as the filtering instruction code applied to the controller, and the filtering instruction code applied to the controller is configured into the controller. By adopting this technical solution, the speed of database calculation operations can be improved, and for the calculation-intensive operations in the database, the throughput rate of database calculation can be effectively increased and the latency can be reduced. Description of the Drawings

[0021] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0022] Figure 1 Schematic diagram of the structural comparison between a multi-core CPU technology and an FPGA hardware acceleration technology provided by an embodiment of the present application;

[0023] Figure 2 Schematic diagram of creating a corresponding hardware circuit in an FPGA provided by an embodiment of the present application;

[0024] Figure 3 Schematic diagram of a circuit structure provided by an embodiment of the present application;

[0025] Figure 4 Schematic diagram of a user-configured circuit structure provided by an embodiment of the present application;

[0026] Figure 5 Schematic diagram of the structural comparison between the hardware acceleration of a structured query language and related technologies provided by an embodiment of the present application;

[0027] Figure 6 Schematic diagram of an overall architecture provided by an embodiment of the present application;

[0028] Figure 7 Schematic diagram of the flow of a method for generating a filtering instruction code applied to a controller provided by an embodiment of the present application;

[0029] Figure 8 Schematic diagram of a filtering expression provided by an embodiment of the present application;

[0030] Figure 9 Schematic diagram of row data parallel processing provided by an embodiment of the present application;

[0031] Figure 10 Schematic diagram of the generation process of a first instruction code provided by an embodiment of the present application;

[0032] Figure 11 Schematic diagram of the generation process of a second instruction code provided by an embodiment of the present application;

[0033] Figure 12 Schematic diagram of the generation process of a second truth table provided by an embodiment of the present application;

[0034] Figure 13 Schematic diagram of the execution process of a filtering expression provided by an embodiment of the present application;

[0035] Figure 14 Schematic diagram of the generation process of a third instruction code provided by an embodiment of the present application;

[0036] Figure 15 Schematic flowchart of a method for generating a filtering instruction code applied to a controller provided by an embodiment of the present application;

[0037] Figure 16 Schematic diagram of the generation process of a valid bit mask provided by an embodiment of the present application;

[0038] Figure 17 Schematic diagram of the generation process of a search code provided by an embodiment of the present application;

[0039] Figure 18 Schematic diagram of the structure of a permutation matrix provided by an embodiment of the present application;

[0040] Figure 19 Schematic diagram of the structure of a filtering instruction code generation device applied to a controller provided by an embodiment of the present disclosure;

[0041] Figure 20 Schematic diagram of the structure of a host computer in an embodiment of the present disclosure. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0043] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0044] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0045] In this embodiment, in the related art, the multi-core CPU technology has alleviated the performance bottleneck of database computing to a certain extent. However, since the design of the CPU is oriented towards general computing, the complexity of its architecture design requires a large amount of logical resources, resulting in a limited number of CPU cores that can be created, and the improvement effect of parallel computing is still not ideal. To improve the speed of database computing operations, the FPGA hardware acceleration technology is used. For the compute-intensive operations in the data, customized dedicated circuits are used, and a large number of dedicated logic circuits are used to form acceleration cores for parallel computing, which can effectively improve the throughput rate of database computing and reduce latency. Specifically, reference can be made to Figure 1 Figure 1 showing a structural comparison diagram of a multi-core CPU technology and an FPGA hardware acceleration technology.

[0046] Specifically, in the related art, for the entire computing process of a structured query statement, a corresponding hardware circuit is created in the FPGA to achieve computing performance acceleration.

[0047] Among them, the structured query statement can be an SQL statement. In this technical solution, for the computing process of a certain structured query statement, a customized circuit is used for computing in the FPGA, obtaining a very high computing throughput rate, showing the great potential of the FPGA in improving database performance. Specifically, reference can be made to Figure 2 Figure 2 showing a schematic diagram of creating a corresponding hardware circuit in an FPGA. Figure 2 For the Q6 query statement in the TPC-H test set, in this technical solution: First, the filtering calculation process of the where clause part is converted into 3 range comparisons and 2 and logical operations, and a corresponding logic circuit is created in the FPGA. Its logic circuit is only 3 range comparators and 2 logical AND operations. Then, the data that meets the conditions is further multiplied, and its logic circuit is only filtering and one multiplication operation. Finally, the data after multiplication calculation is accumulated in the FPGA, and its logic circuit is only one accumulator. The FPGA logic structure in the solution is simple and efficient, occupies extremely small resources, and can perform high-throughput concurrent pipelining operations, thereby obtaining extremely high computing performance.

[0048] Specifically, in the related art, the redundant computing method can also be adopted to achieve dynamic support for structured query statements. This technical solution only processes the where clause part of the structured query statement for accelerating the filtering calculation of the scan query. The circuit structure in the solution consists of multiple parallel comparators and a tree-shaped logic operator. Parallel computing acceleration is achieved by creating multiple comparator circuits. Each comparator circuit contains all possible comparison operations. The comparators are connected by a pipeline to transfer row data. The user selects the data to be used by configuring the selector in the comparator to achieve dynamic support for structured query statements. Reference can be made to Figure 3Schematic diagram of a circuit structure shown. For example, for the filtering conditions where (a = 2020-01-01) and (b>100) or (c<0.5) input by the user, please refer to Figure 4 Schematic diagram of a user-configured circuit structure shown. Figure 4 The configuration method is as follows:

[0049] 1) The first filtering condition: a = 2020-01-01, the column a is of date type, the selector of comparator 1 is configured as date type, and the operator selector is =.

[0050] 2) The second filtering condition: b>100, b is of integer type, the selector of comparator 2 is configured as integer type, and the operator selector is >.

[0051] 3) The third filtering condition: c<0.5, c is of floating-point type, the selector of comparator 2 is configured as floating-point type, and the operator selector is <.

[0052] 4) The fourth filtering condition is the and operation between the first and second filtering conditions. Therefore, the first selector in the first layer of the tree-shaped logic operation circuit is configured as an and calculation.

[0053] 5) The fifth filtering condition is the or operation between the fourth filtering condition and the third filtering condition. Therefore, the selector in the second layer of the tree-shaped logic operation circuit is configured as an or calculation.

[0054] After the circuit in the technical solution starts the operation, all possible operation operations will be executed. The user selects the comparison operations and logical operations used in this structured query statement by configuring the selector in the circuit, thus realizing the dynamic support for the structured query statement.

[0055] In the related technology, using FPGA for database hardware acceleration still faces technical challenges: how to support complex and variable structured query statements in a customized fixed circuit is the core problem that needs to be solved in the related technical field. Since FPGA is a customized circuit, it can only execute fixed-format calculation tasks after the logic design is completed. In related technology one, only fixed-format filtering queries can be supported, and the user can only replace the constant part in the predefined SQL statement, which results in extremely limited application scenarios. In actual applications, the structured query statements input by users are often more complex and variable. Therefore, the problem that needs to be solved urgently at present is how to customize the FPGA circuit so that it can adapt to complex structured query statements.

[0056] How to reduce resource consumption to create more parallel computing units. Each logic circuit in the FPGA needs to consume on-chip logic resources. In order to create more parallel computing units, the FPGA design should minimize the consumption of logic resources.

[0057] In the method of exhaustive search adopted in Related Art 2, all possible computing circuits are designed in each computing unit, and the results used in the current structured query statement are selected from the computing results. Although this design can improve the parallel computing performance by creating a large number of computing units, there are a large number of redundant and invalid logic circuits, resulting in a large consumption of logic resources, and thus limiting the number of supported filtering conditions and the number of created computing units.

[0058] To address the above problems, this embodiment proposes a hardware acceleration method for structured query statements. The computing operations in the structured query statement are split and mapped to the computing units of the FPGA accelerator. The support for dynamic structured query statements is achieved through matrix operations. Through the long-bitwidth data input of the FPGA, parallel computing for multiple rows in the data table is realized, improving the parallel computing performance, while significantly reducing the consumption of redundant circuits and enhancing the overall performance of the accelerator. Specifically, reference can be made to Figure 5 A schematic diagram showing the structural comparison between the hardware acceleration of structured query statements and related technologies.

[0059] In this embodiment, the comparator and the logic arithmetic unit are optimized, specifically including:

[0060] (1) Create a corresponding number or proportion of comparator arithmetic units according to the column field types in the table to be queried.

[0061] (2) In the comparator arithmetic unit, use the maximum data bitwidth of the data bus used by the FPGA as the input of the comparator to achieve the comparison operation of column fields in multiple rows simultaneously.

[0062] (3) The results of all comparison arithmetic units are input to the permutation matrix multiplier as valid values.

[0063] (4) In the permutation matrix multiplier, use parallel matrix multiplication operations to merge the valid computing results in the current calculation to form a search code.

[0064] (5) Use the search code to look up the corresponding result value in the truth table as the value indicating whether the SQL filtering operation result meets the filtering conditions.

[0065] The following is an example: For example, you can refer to the different types of data shown in Table 1. There are a total of 8 column fields, including 2 integer type columns (Column A, Column C), 2 date type columns (Column E, Column G), 3 floating-point type columns (Column B, Column D, Column F), and 1 string type (Column H).

[0066] Table 1 Different Types of Data

[0067]

[0068] In the related art, if full-column comparison filtering is to be supported, a comparison calculation unit is created for each column field. This calculation unit is composed of multiple comparators of different types and includes all possible data types. For Table 1, at least 8 comparison calculation units need to be created. Since each calculation unit has to support comparison operations of integers, floating points, dates, and strings, 8 comparators for integers, dates, floating points, and strings are required respectively, which means a total of 32 comparators are needed.

[0069] It should be noted that in actual products, the types of fields in the database may be far more than the above 4 types. At the same time, there may be wide tables with more fields (including a large number of column fields), which means that a large number of redundant data type comparators need to be created in each comparison calculation unit, and a large number of comparison calculation units need to be created to meet the requirements of hardware acceleration calculation for data tables. This results in a huge consumption of FPGA on-chip logic resources, thus affecting the number of finally achievable calculation units. The required number of comparators is as follows:

[0070] ;

[0071] In this embodiment, according to the field types of the table to be queried, 2 integer comparators, 2 date comparators, 3 floating-point comparators, and 1 string comparator, a total of 8 comparators, are used to form a comparison operation unit, thus greatly reducing the required amount of FPGA logic resources. During the operation, by performing mapping conversion on the structured query statement, the query filtering conditions are mapped into each comparator. For the results of all comparator operations, a permutation matrix multiplier is used to perform parallel calculation to merge the comparison results required by SQL in this calculation to obtain a search code, and the search code is used to determine whether this row meets the conditions in the truth table. The specific method will be described in detail later. The number of comparators required in this embodiment is equal to the number of column fields.

[0072] ;

[0073] It should be noted that in actual products, in the present invention, the number of comparators of each different type in the comparison operation unit can be planned according to the field type ratio in all tables in the database.

[0074] In this embodiment, it is necessary to cooperate between the host side and the FPGA. Refer to Figure 6 a schematic diagram of an overall architecture shown.

[0075] Figure 7 FIG. is a schematic flowchart of a method for generating a filtering instruction code applied to a controller provided by an embodiment of the present disclosure. This method can be executed by the host side. As Figure 7 shown, the method provided in this embodiment includes the following steps:

[0076] S701. Obtain a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user.

[0077] In one example, obtain the structured query statement input by the user from a preset interface.

[0078] In one example, generating a filtering expression according to the structured query statement input by the user includes:

[0079] Process the filtering conditions of the preset clauses in the structured query statement input by the user to generate a filtering expression.

[0080] In one example, in a database, for the filtering conditions of the where clause in the structured query statement input by the user, the filtering condition string in the structured query statement is reconstructed through lexical and syntactic parsing to generate a filtering expression. In the filtering expression, a binary tree structure is used to represent comparison operations, and a linked list structure is used to represent logical operations. The calculation order of each operator in the filtering operation is determined by traversing the linked list + binary tree. For example, the following expression: select A, B from table where (A>10 and B<0.5 and C<100) or (E>2024-01-01) The converted filtering expression can be referred to Figure 8 , Figure 8 shows a schematic diagram of a filtering expression.

[0081] The CPU traverses and executes each operation node on the linked list + binary tree in sequence, performs corresponding comparison or logical operations, and completes the filtering calculation operation. In the related art, by imitating the traversal process of the operation nodes by the CPU, the operation of each node is converted into an FPGA instruction code. In the FPGA, a large number of computing units (CUs) hardware circuits are created. In each computing unit, in a pipelined manner, the target fields in the row are compared and logically operated one by one to achieve parallel calculation of multiple row data, thereby improving the performance of query filtering. Specifically, refer to Figure 9 a schematic diagram of parallel processing of row data shown.

[0082] S702. Generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code.

[0083] In one example, generating a first instruction code according to the filtering expression includes:

[0084] Traverse the filtering expression, and encode the operators on the nodes in the filtering expression to generate the first instruction code.

[0085] In one example, sequentially record the operation information of each node in the filtering expression. The operation information of each node includes necessary parameters required for operations such as the node operation data type, operator, number of parameters, parameter type (column field number or constant), etc. Optionally, the constant can include multiple constants to simplify the in comparison operation in the structured query statement. Optionally, for rows where the column fields are all of fixed length, the column number can be directly expressed as the offset of the column field in the row. Obtain the first instruction code. For a clearer illustration, reference can be made to Figure 10 The schematic diagram showing a generation process of a first instruction code.

[0086] In one example, generating a second instruction code according to the first instruction code includes:

[0087] Traverse the first instruction code, extract the comparison operations, and generate the second instruction code. Specifically, reference can be made to Figure 11 The schematic diagram showing a generation process of a second instruction code.

[0088] S703. Loop to execute the logical operations in the first instruction code, generate a first truth table, and generate a second truth table according to the first truth table.

[0089] In one example, when looping to execute the logical operations in the first instruction code, the input parameter is all possible values of the comparison operation. In this example, there are 4 comparison operations, and there are a total of 2 to the 4th power (16 in total) of possible values. These 16 possible values are used as inputs, and the corresponding logical operation results are used as the truth table. Specifically, reference can be made to the schematic diagram showing a generation process of a first truth table shown in Table 2. In Table 2, 0 represents false and 1 represents true.

[0090] Table 2 First Truth Table

[0091]

[0092] In one example, generating a second truth table according to the first truth table includes:

[0093] Rearrange the columns in the first truth table in the order of the FPGA comparison calculation unit to obtain the second truth table.

[0094] In one example, the columns in the first truth table are rearranged according to the order of the comparison calculation units preset in the FPGA to obtain the second truth table. Assume that in the FPGA, corresponding numbers of comparison calculation units are created according to the data types in the target table. Since data units of the same type are placed under the same bit width, the effect of parallel access can be achieved. Therefore, in the internal design of the FPGA, calculation units of the same type are placed together. In this example, column B needs to be exchanged with column C. Specifically, reference can be made to Figure 12 The schematic diagram showing the generation process of a second truth table as shown.

[0095] In this embodiment, by separating the comparison operation from the logical operation, there is no mutual dependence between the calculation operations in the filtering expression, thus supporting the simultaneous parallel calculation of all comparison operations to utilize the parallel calculation characteristics of the FPGA. For example, in the filtering expression in the example, each operation does not need to be executed sequentially. Specifically, reference can be made to Figure 13 The schematic diagram showing the execution process of a filtering expression as shown.

[0096] S704. Generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code.

[0097] In one example, generating a third instruction code according to the second instruction code includes:

[0098] Rearranging and merging the comparison operation instructions in the second instruction code according to the order of the FPGA comparison calculation units to obtain the third instruction code.

[0099] In one example, rearranging and merging the comparison operation instructions in the second instruction code according to the order of the FPGA comparison calculation units to obtain the third instruction code. For this example, the operation instructions in column B need to be exchanged with the operation instructions in column C. Specifically, reference can be made to Figure 14 The schematic diagram showing the generation process of a third instruction code as shown. Specifically, the instruction code has the following technical features: Figure 14 In 501, it represents that each instruction in the instruction code corresponds to a comparison node in the filtering expression in SQL, including necessary information for comparison operations such as comparison data type, operator, number of parameters, column number, constant, etc. Figure 14 In 502, it represents the order of the comparison instructions in the comparison instruction code, which is generated by rearranging the filtering expression in SQL and arranged according to the order of the comparators set in the FPGA. Comparison instructions of the same data type will be placed together.

[0100] S705. Determine the second instruction code, the second truth table, and the permutation matrix as the filtering instruction code applied to the controller, and configure the filtering instruction code applied to the controller into the controller.

[0101] In one example, the controller can be an FPGA. After configuring the filtering instruction code applied to the FPGA into the relevant registers of the FPGA, the calculation of data can be started, which is only executed once during the entire SQL query process.

[0102] With this application, since the structured query statement input by the user is obtained, and then the structured query statement input by the user is processed to obtain the first instruction code, and based on the first instruction code, the second instruction code is generated, and then based on the logical operations in the first instruction code, the first truth table is generated, and then the second truth table is generated according to the first truth table. Finally, according to the second instruction code, the third instruction code is generated, and according to the third instruction code, the permutation matrix is determined; the second instruction code, the second truth table, and the permutation matrix are determined as the filtering instruction code applied to the FPGA, and the filtering instruction code applied to the FPGA is configured into the FPGA. The advantage of such a setting is that by separating the comparison operation and the logical operation, there is no mutual dependence between the calculation operations in the filtering expression, thus supporting the simultaneous parallel calculation of all comparison operations to give full play to the parallel calculation characteristics of the FPGA.

[0103] Figure 15 The flowchart shows a method for generating a filtering instruction code applied to a controller provided by an embodiment of the present disclosure. The embodiment of the present disclosure is optimized on the basis of the above embodiment, and the embodiment of the present disclosure can be combined with each optional solution in one or more of the above embodiments.

[0104] As Figure 15 shown, the method for generating a filtering instruction code applied to a controller may include the following steps:

[0105] S1501. Obtain the structured query statement input by the user, and generate a filtering expression according to the structured query statement input by the user.

[0106] S1502. Generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code.

[0107] S1503. Loop to execute the logical operations in the first instruction code to generate a first truth table, and generate a second truth table according to the first truth table.

[0108] S1504. Generate a third instruction code according to the second instruction code.

[0109] S1505. Calculate the valid bit mask in the third instruction code.

[0110] In one example, calculating the valid bit mask in the third instruction code includes:

[0111] Calculate the second comparison operation used in the structured query statement input by the user according to the first comparison operation in the third instruction code and the comparator created in the FPGA to obtain a valid bit mask.

[0112] In one example, the comparators created by the FPGA are: 2 integers, 3 floating points, 2 dates, and 1 string. And this SQL query only needs the comparison operation results of 2 integers, 1 floating point, and 1 date. Therefore, a mask is needed to indicate which comparator operation results enter the next operation unit. Specifically, refer to Figure 16 The schematic diagram of a valid bit mask generation process shown.

[0113] In one example, the valid bit mask indicates which positions are valid (i.e., the value is 1), and the purpose of the permutation matrix is to rearrange these valid positions to the front of the matrix for subsequent processing. In this way, the parallel computing characteristics of the FPGA can be utilized to quickly merge the valid calculation results to obtain a shorter lookup code, significantly reducing the memory size required for the truth table. Specifically, refer to Figure 17 The schematic diagram of a lookup code generation process shown.

[0114] S1506. Calculate the permutation matrix according to the valid bit mask.

[0115] In one example, calculating the permutation matrix according to the valid bit mask includes:

[0116] Create a matrix M of size N×N; where the elements in matrix M are initialized to 0; initialize the row index row to 0;

[0117] Use the column traversal index i to traverse the elements mask[i] in the valid bit mask; where i is a value greater than or equal to 0 and less than or equal to N - 1;

[0118] If the current element mask[i] in the valid bit mask is 1, then set the element in the i-th column of the row row in matrix M to 1, and at the same time increment the row index row by 1;

[0119] If the current element mask[i] in the valid bit mask is not 1, determine the permutation matrix according to whether the current element mask[i] in the valid bit mask is the last valid bit mask element.

[0120] In one example, determining the permutation matrix according to whether the current element mask[i] in the valid bit mask is the last valid bit mask element includes:

[0121] If so, obtain the permutation matrix;

[0122] Otherwise, increment the column traversal index i by 1, and perform traversing the elements mask[i] in the valid bitmask using the column traversal index i until a permutation matrix is obtained.

[0123] In one example, through the operation of the permutation matrix, the support for different structured query statements is realized, and at the same time, the on-chip memory space of the FPGA required for the truth table is greatly reduced. The truth table scheme enables logical operations on query results of multiple different data types and has practical value. For example: Since multi-table queries need to be supported, each table will have several fields of different types. Relatively redundant comparators need to be designed in the FPGA. Common comparison operation requirements are: comparison operations of 4 integers, 4 floating-point numbers, 4 dates, and 4 strings. In this requirement, 16 comparison operation results will be generated. If truth tables are created for all comparison operation results, 2^16 bits (8192B) of cache space are required to store the truth tables. In reality, for the structured query statements input by users, the comparison conditions are often very few, usually no more than 8, and 16 filtering comparison conditions are not input at one time. It's just that the data types needed each time will change. The permutation matrix in this embodiment is to solve this problem. For a clearer illustration, reference can be made to Figure 18 the structural schematic diagram of a permutation matrix shown.

[0124] In the example, only 6 comparison operations are used in the structured query statement. Through a 16x16 permutation matrix (occupying 32B of memory space), the comparison results of the valid bits are put together to form a search code. The corresponding truth table only requires 2^6 bits (8B) of memory space.

[0125] It should be noted that in actual products, more comparators are often required. For example: 8 integers, 8 floating-point numbers, 8 dates, 8 strings, which means that 2^32 bits (512MB) of truth table storage space are required, and the on-chip cache of the FPGA is extremely precious, usually only 16MB - 32MB. This makes the traditional truth table scheme not practical for processing logical operations.

[0126] S1507. Determine the second instruction code, the second truth table, and the permutation matrix as the filtering instruction code applied to the controller, and configure the filtering instruction code applied to the controller into the controller.

[0127] In one example, the method further includes:

[0128] Receiving the calculation result of the controller, and finding out the rows that meet the filtering conditions from the calculation result;

[0129] Obtaining the index number of the row in the page, and obtaining the row data from the page row meta information according to the index number.

[0130] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0131] The embodiments of the present application also provide a filtering instruction code generation device applied to a controller. Specifically, reference can be made to Figure 19 FIG. 1900 is a schematic structural diagram of a filtering instruction code generation device applied to a controller provided by an embodiment of the present disclosure. Executed by the host side, the device 1900 includes:

[0132] A first acquisition module 1901, configured to acquire a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user;

[0133] A first generation module 1902, configured to generate a first instruction code according to the filtering expression, and generate a second instruction code according to the first instruction code;

[0134] A second generation module 1903, configured to loop and execute the logical operations in the first instruction code, generate a first truth table, and generate a second truth table according to the first truth table;

[0135] A third generation module 1904, configured to generate a third instruction code according to the second instruction code, and determine a permutation matrix according to the third instruction code;

[0136] A determination module 1905, configured to determine the filtering instruction code applied to the controller based on the second instruction code, the second truth table, and the permutation matrix, and configure the filtering instruction code applied to the controller into the controller.

[0137] In one example, the first acquisition module 1901 is specifically configured to: process the filtering conditions of the preset clauses in the structured query statement input by the user to generate a filtering expression.

[0138] In one example, the first generation module 1902 is configured to:

[0139] Traverse the filtering expression, and encode the operators on the nodes in the filtering expression to generate a first instruction code.

[0140] In one example, the first generation module 1902 is configured to: traverse the first instruction code, extract comparison operations, and generate a second instruction code.

[0141] In one example, the third generation module 1904 is configured to: rearrange the comparison operation instructions in the second instruction code in the order of the controller comparison calculation unit to obtain a third instruction code.

[0142] In one example, the second generation module 1903 is configured to:

[0143] Rearrange the columns in the first truth table according to the order of the controller comparison calculation unit to obtain a second truth table.

[0144] In one example, the third generation module 1904 is configured to:

[0145] Calculate the valid bit mask in the third instruction code;

[0146] Calculate a permutation matrix according to the valid bit mask.

[0147] In one example, the third generation module 1904 is configured to:

[0148] Calculate the second comparison operation used in the structured query statement input by the user according to the first comparison operation in the third instruction code and the comparison operator created in the controller to obtain a valid bit mask.

[0149] In one example, the third generation module 1904 is configured to: create a matrix M of size N×N; where the elements in the matrix M are initialized to 0; initialize the row index row to 0;

[0150] Use the column traversal index i to traverse the elements mask[i] in the valid bit mask; where i is a value greater than or equal to 0 and less than or equal to N - 1;

[0151] If the current element mask[i] in the valid bit mask is 1, set the element in the i-th column of the row row in the matrix M to 1, and at the same time increment the row index row by 1;

[0152] If the current element mask[i] in the valid bit mask is not 1, determine the permutation matrix according to whether the current element mask[i] in the valid bit mask is the last element in the valid bit mask.

[0153] In one example, the third generation module 1904 is configured to: if so, obtain the permutation matrix;

[0154] If not, increment the column traversal index i by 1, and execute using the column traversal index i to traverse the elements mask[i] in the valid bit mask until the permutation matrix is obtained.

[0155] In one example, the apparatus further includes:

[0156] A receiving module 1906, configured to receive the calculation result of the controller and find the rows that meet the filtering condition from the calculation result;

[0157] A second obtaining module 1907, configured to obtain the page index number of the row, and obtain the row data according to the index number in the page row meta-information.

[0158] For the description of the features in the corresponding embodiments of the filtering instruction code generation device applied to the controller, reference may be made to the relevant description in the corresponding embodiments of the filtering instruction code generation method applied to the controller, which will not be elaborated here one by one.

[0159] An embodiment of the present application further provides a host, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the filtering instruction code generation method applied to the controller.

[0160] Exemplarily, Figure 20 is a schematic structural diagram of a host in an embodiment of the present disclosure. Specifically, refer to Figure 20 , which shows a schematic structural diagram suitable for implementing the host 1000 in the embodiment of the present disclosure. The host 1000 in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 20 The host shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0161] As Figure 20 shown, the host 1000 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 1001, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage device 1008 into the random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the host 1000 are also stored. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other through a bus 1004. The input / output (I / O) interface 1005 is also connected to the bus 1004.

[0162] Generally, the following devices may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the host 1000 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 20The host 1000 is shown with various devices, but it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices may be implemented or had.

[0163] In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via the communication device 1009, or installed from the storage device 1008, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0164] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above XX method embodiments when running.

[0165] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), external hard drives, magnetic disks, or optical discs, etc., various media that can store computer programs.

[0166] An embodiment of the present application also provides a computer program product, and the above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any one of the above embodiments of the method for generating a filtering instruction code applied to a controller are implemented.

[0167] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any one of the above embodiments of the method for generating a filtering instruction code applied to a controller are implemented.

[0168] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered as exceeding the scope of this application.

[0169] The above has introduced in detail a method for generating a filtering instruction code applied to a controller provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for generating a filtering instruction code applied to a controller, characterized in that, Executed by the host side, the method includes: Obtain a structured query statement input by the user, and generate a filtering expression according to the structured query statement input by the user; Traverse the filtering expression, encode the operators on the nodes in the filtering expression to generate a first instruction code, and traverse the first instruction code to extract comparison operations and generate a second instruction code; the first instruction code is the node operation information in the filtering expression; the second instruction code is generated after extracting the comparison operations in the first instruction code; Loop and execute the logical operations in the first instruction code to generate a first truth table, and rearrange the columns in the first truth table to obtain a second truth table; the first truth table is the logical operation result obtained from the logical operations in the first instruction code; the second truth table is the result obtained after rearranging and combining the columns in the first truth table; Combine and rearrange the comparison operation instructions in the second instruction code to obtain a third instruction code, and calculate the valid bit mask in the third instruction code; the third instruction code is used to represent the instruction code after combining and rearranging the comparison operation instructions in the second instruction code; Calculate a permutation matrix according to the valid bit mask; Determine the second instruction code, the second truth table, and the permutation matrix as the filtering instruction code applied to the controller, and configure the filtering instruction code applied to the controller into the controller.

2. The method according to claim 1, characterized in that, The generating a filtering expression according to the structured query statement input by the user includes: Process the filtering conditions of the preset clauses in the structured query statement input by the user to generate the filtering expression.

3. The method according to claim 1, characterized in that, The combining and rearranging the comparison operation instructions in the second instruction code to obtain a third instruction code includes: Combine and rearrange the comparison operation instructions in the second instruction code in the order of the controller comparison calculation unit to obtain the third instruction code.

4. The method according to claim 1, characterized in that, The rearranging the columns in the first truth table to obtain a second truth table includes: Rearrange and combine the columns in the first truth table in the order of the controller comparison calculation unit to obtain the second truth table.

5. The method according to claim 1, wherein The calculating the valid bit mask in the third instruction code includes: According to the first comparison operation in the third instruction code and the comparison calculator created in the controller, calculate the second comparison operation used in the structured query statement input by the user to obtain the valid bit mask.

6. The method according to claim 1, wherein The calculating the permutation matrix according to the valid bit mask includes: Create a matrix M with a size of N×N; where the elements in the matrix M are initialized to 0; initialize the row index row to 0; Use the column traversal index i to traverse the elements mask[i] in the valid bit mask; where i is a value greater than or equal to 0 and less than or equal to N-1; If the element mask[i] in the current valid bit mask is 1, set the element in the i-th column of the row row in the matrix M to 1, and at the same time increment the row index row by 1; If the element mask[i] in the current valid bit mask is not 1, determine the permutation matrix according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element.

7. The method according to claim 6, wherein The determining the permutation matrix according to whether the element mask[i] in the current valid bit mask is the last valid bit mask element includes: If so, obtain the permutation matrix; If not, increment the column traversal index i by 1, and execute traversing the element mask[i] in the valid bit mask using the column traversal index i until the permutation matrix is obtained.

8. The method according to claim 1, characterized in that The method further includes: Receiving the calculation result of the controller, and finding the rows that meet the filtering condition from the calculation result; Obtaining the row index number in the page, and obtaining row data according to the index number in the page row meta-information.

9. A filtering instruction code generation device applied to a controller, characterized in that, Executed by the host side, the device includes: A first obtaining module, configured to obtain a structured query statement input by a user, and generate a filtering expression according to the structured query statement input by the user; A first generating module, configured to traverse the filtering expression, encode the operators on the nodes in the filtering expression to generate a first instruction code, and traverse the first instruction code to extract comparison operations and generate a second instruction code; the first instruction code is the node operation information in the filtering expression; the second instruction code is generated after extracting the comparison operations in the first instruction code; A second generating module, configured to repeatedly execute the logical operations in the first instruction code to generate a first truth table, and rearrange the columns in the first truth table to obtain a second truth table; the first truth table is the logical operation result obtained from the logical operations in the first instruction code; the second truth table is the result obtained after rearranging and combining the columns in the first truth table; A third generating module, configured to rearrange and combine the comparison operation instructions in the second instruction code to obtain a third instruction code, and calculate the valid bit mask in the third instruction code; the third instruction code is used to represent the instruction code after rearranging and combining the comparison operation instructions in the second instruction code; and calculate a permutation matrix according to the valid bit mask; A determining module, configured to determine the second instruction code, the second truth table, and the permutation matrix as filtering instruction codes applied to the controller, and configure the filtering instruction codes applied to the controller into the controller.

10. A host for executing a method of generating a filtering instruction code applied to a controller, characterized in that, Includes: A memory, configured to store a computer program; A processor, configured to implement the steps of the method for generating filtering instruction codes applied to the controller according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the method for generating filtering instruction codes applied to the controller according to any one of claims 1 to 8.

12. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method for generating filtering instruction codes applied to the controller according to any one of claims 1 to 8.

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