An early multi-process corner timing prediction method based on deep learning, electronic device and storage medium

Abstract

The present invention discloses an early multi-process corner timing prediction method, electronic device and storage medium based on deep learning. In order to capture the interaction relationship between units in the path, the early timing prediction process of the present invention is built based on a bidirectional long short-term memory network, and the timing and physical information of each level unit in the path are represented as a sequence. The information in the sequence is transmitted and represented through BLSTM to learn the mutual influence between units in the path, thereby accurately predicting the path delay after layout. On this basis, the present invention uses a multi-layer perceptron network to learn the impact of the global characteristics of the path on the timing of the path after layout, improving the prediction accuracy while adapting the early timing prediction framework to the scenario of multiple process corners. Based on the prediction results, the present invention reduces the iteration of the design and reduces the time cost of chip design.

Description

Technical Field

[0001] The present invention relates to an early multi-process corner timing prediction method based on deep learning, an electronic device and a storage medium, and belongs to the technical field of electronic design automation. Background Art

[0002] Static Timing Analysis (STA) can fully and comprehensively verify the timing requirements of digital integrated circuit designs and plays a vital role in the IC design process. Static timing analysis is required during both logic synthesis and physical design to ensure chip convergence at each stage of the design process. However, due to the unpredictable challenges of IC design, the results of static timing analysis can lack reliability, leading to design iterations.

[0003] With the development of integrated circuits and advancements in process nodes, timing unpredictability has become a major challenge in integrated circuit design. This unpredictability can arise from differences between different timing analysis tools. For example, dedicated timing analysis tools can perform more accurate path-based timing analysis (PBA), while some place-and-route tools with integrated timing analysis engines, while capable of timing analysis, only perform graph-based timing analysis (GBA) due to time constraints. Timing unpredictability can also arise from inaccurate timing estimates from the current design stage for downstream design stages. For example, the logic synthesis stage only includes information about the logical layer of the design, leaving the physical layer unknown. This lack of physical information can lead to inaccurate timing estimates in the early stages of the design, resulting in significant discrepancies between the timing results of paths after logic synthesis and after layout.

[0004] The timing results for paths after logic synthesis and after layout differ significantly. On the one hand, poor timing predictions for downstream design stages in the early stages of the design process can result in timing violations not being discovered until later in the design process. In severe cases, this can cause the design to be returned to the front-end process, leading to design iterations and increasing the chip design cycle. On the other hand, logic synthesis converts register transfer level (RTL) designs into gate-level netlists. Different logic synthesis schemes result in different power consumption, performance, and area (PPA). Inaccurate timing estimates early on cannot guide the synthesis tool to generate high-quality netlists, and more design iterations are still required to achieve a more ideal quality of results (QoR).

[0005] The lack of physical information makes timing prediction in the early stages of design challenging. In the digital integrated circuit design process, the following two methods are usually used to alleviate the problem of inaccurate timing estimation caused by the lack of physical information in the early stages of design. The first method is to introduce a wire load model to estimate the wire length. This method simply estimates the wire length based on the number of fan-outs of the cells in the path. Although it supplements the physical information to a certain extent, it still cannot effectively improve the predictability of the logic synthesis stage due to the lack of accuracy in the wire length estimation. The second method is to perform physically-aware logic synthesis. This method integrates the layout engine in the physical design tool into the logic synthesis tool. By performing a simple layout during the logic synthesis process to obtain physical location information, it achieves a close correlation with the quality of the subsequent physical design stage. However, directly calling the layout engine during the synthesis process is very time-consuming and costly.

[0006] The majority of static timing analysis time is spent analyzing timing at multiple process corners under different process, voltage, and temperature (PVT) conditions. With advancements in process nodes and increasing complexity in design scenarios, the number of process corners requiring IC acceptance is rapidly increasing, consuming significant computing resources and runtime.

[0007] Therefore, the problem of timing acceleration in multi-process corner scenarios has been widely studied. Machine learning models are trained using timing information from certain process corners, operating modes, and timing analysis modes to predict timing information for other scenarios, thereby obtaining timing results for all scenarios. Compared to the time required for timing analysis, the prediction time of machine learning models is significantly reduced, thus achieving the goal of accelerating timing analysis. Currently, most cross-process corner timing prediction work focuses on the same design stage, operating mode, and timing analysis mode. This type of research accelerates timing analysis in multi-process corner scenarios by reducing the number of process corners that require simulation. In addition, a small number of studies have investigated timing prediction for multiple process corners in different timing analysis modes and operating modes. This research adapts timing prediction across timing analysis modes and operating modes to multi-process corner scenarios, avoiding the need to develop separate timing prediction models for each process corner, thereby accelerating the time required for timing prediction in these timing prediction problems due to the timing analysis requirements for multiple process corners.

[0008] However, there are still some shortcomings in existing research work:

[0009] (1) The timing prediction of existing methods is performed at the unit level or circuit level. The former method of accumulating the overall timing of the path leads to the accumulation of errors and ignores the influence of the interaction between the units in the path. The latter cannot provide more detailed information for repairing timing violations or optimizing circuits.

[0010] (2) Existing methods do not fully consider the factors that affect the timing of the downstream design stage and are unable to fully characterize the effective information of the path.

[0011] (3) In almost all existing studies across design stages, there is no discussion on how to adapt the proposed work to the scenario requirements of multiple process corners, and it is obviously unrealistic to establish a separate prediction model for each process corner.

[0012] Therefore, in order to improve the predictability of the early design stage and reduce the design time under the requirements of multi-process corner timing analysis, an efficient and accurate early timing estimation method that adapts to the requirements of multi-process corner scenarios is needed. Summary of the Invention

[0013] Purpose: To overcome the shortcomings of existing technologies, this invention provides a deep learning-based early multi-process corner timing prediction method, electronic device, and storage medium. These methods provide designers with post-layout path delay values ​​for various process corners during the logic synthesis phase. Based on these predictions, the invention implements an optimization process to guide designers or tools in optimization, reducing design iterations and ultimately lowering the time cost of chip design.

[0014] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0015] First, a deep learning-based early multi-process corner timing prediction method specifically includes:

[0016] Step S1: Obtain a circuit netlist after logic synthesis and a circuit netlist after layout, perform static timing analysis on the circuit netlist after logic synthesis and the circuit netlist after layout respectively, obtain a static timing report of the circuit after logic synthesis and a static timing report of the circuit after layout, extract the timing, physical information and path delay value of each level of units in the path of the circuit after logic synthesis from the static timing report of the circuit after logic synthesis, extract the path delay value information of the circuit after layout from the static timing report of the circuit after layout, and use the difference between the path delay value after layout and the path delay value after logic synthesis as a label.

[0017] Step S2: Preprocessing is performed based on the timing and physical information of each level of units in the path of the circuit after logic synthesis to obtain the sequence characteristics and global characteristics of the path.

[0018] Step S3: Input the sequence features and global features into the extreme gradient boosting model for process corner selection to obtain optimized sequence features and global features.

[0019] Step S4: Input the optimized sequence features into the bidirectional long short-term memory network for learning to obtain the sequence feature representation vector of the path, and input the optimized global features into the multi-layer perceptron network for learning to obtain the global feature representation vector of the path.

[0020] Step S5: Merge the sequence feature representation vector of the path and the global feature representation vector of the path, use the merged representation vector and the label as training samples, and use the training samples to train the time series prediction model to obtain a trained time series prediction model.

[0021] Step S6: Input the circuit netlist to be predicted after logic synthesis into the trained timing prediction model to obtain the path delay prediction value after layout.

[0022] As a preferred solution, the method further includes: Step S7: obtaining an optimized circuit netlist using a logic synthesis tool according to the predicted path delay values ​​after layout.

[0023] As a preferred solution, step S2 specifically includes:

[0024] For discrete non-numeric variables of the path's unit type, a word segmenter is used to create a numeric variable that is mapped one-to-one with the unit type variable.

[0025] For the continuous numerical variables of the path unit delay, input conversion time, output load capacitance, and semi-period, the variables are mapped to different bins through binning operations for discretization, obtaining discrete numerical variables whose relative size relationships remain unchanged before and after the numerical conversion.

[0026] A discrete numeric variable that gets the cell fanout of the path.

[0027] The above numerical variables are combined into the sequence characteristics of the path.

[0028] The process features and values ​​in the PVT features of the path are mapped one by one and merged with the values ​​in the PVT features into PVT numerical variables. The sequence features, PVT numerical variables and the path delay value after logic synthesis are spliced ​​to obtain the global features of the path.

[0029] As a preferred solution, the dimensions of the sequence features and global features of each path are the same, and the parts where the sequence features are insufficient are filled with zeros.

[0030] As a preferred solution, step S3 specifically includes:

[0031] The sequence features and global features of the path are input into the extreme gradient boosting model for representation learning to obtain the delay values ​​of the path under different process angle types.

[0032] The sequence features and global features of the path under a certain process angle are iteratively deleted according to the delay values ​​of the paths under different process angle types.

[0033] The sequence characteristics and global characteristics of the path with a balanced number of process corner types are obtained as the optimized sequence characteristics and global characteristics.

[0034] As a preferred solution, the bidirectional long short-term memory network includes: two opposite unidirectional LSTM layers, the input sequence {x1, x2, ..., x k} Input into the forward LSTM layer to get the forward output f of each level k , input into the reverse LSTM layer to obtain the reverse output b of each level k , the final output of each level of the BLSTM layer is composed of the forward output f k and reverse output b k For multiple BLSTM layers, the output vectors of each level after splicing form a new sequence as the input of the next BLSTM layer. For the last BLSTM layer, the output vector f of the last level of the forward LSTM layer is k The concatenation of the output vector b1 of the last level of the reverse LSTM layer is used as the representation vector of the entire sequence.

[0035] As a preferred solution, the multilayer perceptron network consists of two fully connected layers and one dropout layer. The fully connected layer learns potential information by performing dimensionality transformation on the initial global features, and the dropout layer randomly deletes some neurons in the fully connected layer to obtain a global feature representation vector.

[0036] As a preferred solution, the time series prediction model adopts an artificial neural network.

[0037] As a preferred solution, step S7 specifically includes:

[0038] According to the path delay prediction value after layout, the path with the path delay prediction value greater than the threshold is regarded as the critical path, and the timing constraint command corresponding to the logic synthesis tool is generated for the critical path;

[0039] According to the timing constraint commands corresponding to the logic synthesis tool, the logic synthesis tool is used to perform incremental optimization to obtain an optimized circuit netlist.

[0040] In a second aspect, a computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements an early multi-process corner timing prediction method based on deep learning as described in any one of the first aspects.

[0041] According to a third aspect, a computer device includes:

[0042] Memory, used to store instructions.

[0043] A processor is configured to execute the instructions so that the computer device performs the operations of the deep learning-based early multi-process corner timing prediction method as described in any one of the first aspects.

[0044] Beneficial effects: The present invention provides an early multi-process corner timing prediction method, electronic device, and storage medium based on deep learning. In order to capture the interaction relationship between units in the path, the early timing prediction process of the present invention is built based on a bidirectional long short-term memory network (Bi-directional Long Short-Term Memory, BLSTM), and the timing and physical information of each level of units in the path are represented as a sequence. The information in the sequence is transmitted and represented by BLSTM to learn the mutual influence between units in the path, thereby accurately predicting the path delay after layout. On this basis, the present invention uses a multi-layer perceptron (Multilayer Perceptron, MLP) network to learn the impact of the global characteristics of the path on the timing of the path after layout, improving the prediction accuracy while adapting the early timing prediction framework to the scenario of multiple process corners. Based on the prediction results, the present invention implements an optimization process to guide designers or tools to optimize, reduce design iterations, and reduce the time cost of chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a flowchart of the early multi-process corner delay prediction based on BLSTM in the present invention.

[0046] Figure 2 Flowchart of sequence feature preprocessing of the present invention.

[0047] Figure 3 Schematic diagram of the selection process of the process angle of the training set of the present invention.

[0048] Figure 4 This is a structural diagram of the BLSTM layer of the present invention. DETAILED DESCRIPTION

[0049] The following is a clear and complete description of the technical solutions in the examples of the present invention, in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0050] The present invention will be further described below with reference to specific embodiments.

[0051] Example 1:

[0052] This embodiment introduces a method for early multi-process corner timing prediction based on deep learning. The method predicts the timing of the path after layout under various process corners based on the timing after logic synthesis and physical information, thereby improving the predictability of the early design. Figure 1 As shown, it specifically includes: physical design, feature selection and data preprocessing, training set process angle selection, model representation learning, path delay value generation and optimization process:

[0053] S1: First, the physical design phase. The circuit netlist after logic synthesis undergoes physical design to obtain the circuit netlist after layout. Static timing analysis is performed on both the logic synthesis netlist and the layout netlist, respectively, to obtain static timing reports for the circuit after logic synthesis and the circuit after layout. The timing, physical information, and path delay values ​​of each level of the path are extracted from the static timing report of the circuit after logic synthesis. The path delay value information is extracted from the static timing report of the circuit after layout. Based on this, the difference between the path delay value after layout and the path delay value after synthesis is used as the label for the timing prediction model.

[0054] Furthermore, the physical design includes layout planning and layout.

[0055] S2: Next comes feature selection and data preprocessing. The timing and physical information of each cell in the path, extracted from the static timing report of the circuit after logic synthesis in S1, is preprocessed to obtain sequence features and global features related to the path timing after layout. The preprocessed data is divided into training and test data sets. The training data is used for model training, and the test data is used to verify the model's prediction accuracy and efficiency.

[0056] Furthermore, the preprocessing includes extracting the timing and physical information of each unit in each path for preprocessing to obtain the sequence characteristics of the path, and splicing the sequence characteristics of the path with the process, voltage, temperature and path delay value after logic synthesis of the path to obtain the global characteristics of the path.

[0057] After preprocessing, the sequence feature lengths of all paths are consistent to ensure compatibility with the subsequent bidirectional long short-term memory (BLSTM) network. Furthermore, process, voltage, and temperature (PVT) information, as well as path delays after logic synthesis, also affect the path timing after placement. These are combined to form the global path features.

[0058] S3: Based on step S2, process corner selection is performed for the training set. Drawing on the principles of the greedy algorithm, this step feeds the sequence features and global features preprocessed in step S2 into the Extreme Gradient Boosting (XGBoost) model for representation learning. Based on the model's prediction results, path data for a specific process corner is iteratively removed from the training set to obtain a subset of the training set that achieves the best prediction results for model training.

[0059] S4: The sequence features and global features from the subset of the training set obtained in step S3 are input into the model for representation learning. The sequence features of the path are input into a bidirectional long short-term memory network to learn and obtain the sequence feature representation vector of the path. The network consists of two reverse long short-term memory (LSTM) layers to provide the network with the previous and next connections between the units in the path. The global features of the path are input into a multilayer perceptron (MLP) network to learn and obtain the global feature representation vector of the path.

[0060] S5: Path delay value generation. The representation vectors containing path sequence information and global information obtained from model representation learning in step S4 are combined and input into an artificial neural network (ANN) to obtain the path delay changes during the logic synthesis and layout stages. The path delay changes during the layout stage are added to the path delay values ​​during the logic synthesis stage to obtain the post-layout path delay prediction value.

[0061] S6: Finally, the optimization process. Based on the prediction results from step S5, the present invention implements an optimization process to guide the logic synthesis tool (IC Compiler) to generate a higher-quality circuit netlist, improving the design's power consumption, performance, and area (PPA), thereby reducing design iterations and lowering the time cost of chip design.

[0062] Furthermore, the step S2 is as follows: Figure 2 As shown, the specific steps include:

[0063] S21: Path sequence feature extraction: The local information of each level of units or the network driven by the units in the path is spliced ​​into a sequence to reflect the overall timing of the path.

[0064] The present invention selects path sequence characteristics such as cell type, cell delay, input conversion time, output load capacitance and cell fan-out.

[0065] The cell type reflects the cell's logical function and drive strength. The timing library provides different delay lookup tables for different cell types. Delays vary with function and drive strength. Cell delay is a component of path delay. Cell delay during synthesis serves as a benchmark for post-layout delay. Input transition time is one of the indexes in the lookup table for cell delay and output transition time in the timing library. It directly affects cell delay and output transition time, and further influences the delay of subsequent cells through the propagation of transition time. Output load capacitance, another index in the lookup table, determines cell delay and output transition time. The cell fanout represents the number of load cells driven by the cell. A larger fanout increases the output capacitance and, consequently, the cell delay. The cell type, cell delay, input transition time, output load capacitance, and fanout in the path sequence characteristics are directly derived from the post-synthesis timing report.

[0066] The global characteristics of a path directly affect the overall timing of the path.

[0067] The present invention selects the process, voltage, temperature conditions of the circuit operation and the path global characteristics such as the path delay in the synthesis stage.

[0068] Timing analysis needs to be performed under specific operating conditions. PVT information such as process, voltage, and temperature, as circuit operating conditions, directly affects the path timing after layout. The path delay in the synthesis stage provides a benchmark for path delay prediction after layout.

[0069] The timing prediction framework of the present invention calibrates the path delay after synthesis to obtain the path delay after layout, so the difference between the path delay after layout and the path delay after synthesis is used as the label of the timing prediction model. The final predicted value of the path delay after layout is It can be calculated by formula (1), where represents the path delay after synthesis, Represents the path delay change predicted by the model;

[0070] (1)

[0071] S22: In order to convert the extracted features into a form that can be processed by subsequent machine learning models, the feature data needs to be preprocessed. Path sequence features and global features are represented and learned by different models and are processed differently.

[0072] Preprocessing method of sequence features: For discrete non-numeric variables such as unit types, the present invention draws on the method of processing text sequences in the field of natural language processing, and uses a tokenizer to establish a one-to-one mapping relationship between unit type variables and numbers, thereby converting discrete non-numeric variables into discrete numeric variables; for continuous numeric variables such as unit delay, input conversion time, output load capacitance, and semi-period, the variables are mapped to different bins through binning operations for discretization, thereby converting continuous numeric variables into discrete numeric variables, and the relative size relationship before and after the numeric conversion remains unchanged; fan-out itself is a discrete numeric variable, and no tokenization or binning is required. For each timing path, the relevant features of each level of unit or unit-driven network in the path are subjected to the above-mentioned preprocessing operations to form a feature sequence.

[0073] However, the varying lengths of each path in the circuit result in inconsistent dimensionality in the input feature sequence, making it impossible to directly input it into the BLSTM model for learning. Therefore, the feature sequence needs to be padded or truncated to a uniform length. Considering that in path timing problems, eigenvalues ​​of zero have little impact on the final timing results, this paper pads the feature sequence with zeros. The final sequence length is determined by the longest timing path in the dataset.

[0074] Global features need to be converted into numerical features for subsequent learning by the multi-layer perceptron model. For the process features within the PVT signature, this paper performs a simple one-to-one mapping from strings to numerical values, mapping the fast (FF), typical (TT), and slow (SS) process models to the numerical values ​​1, 2, and 3, respectively. The voltage and temperature within the PVT signature, as well as the integrated path delay, are inherently numerical features, requiring no special preprocessing.

[0075] Furthermore, the step S3 is as follows: Figure 3 As shown, the specific steps include:

[0076] S31: The selection of process corners in the training set, as another preparatory step for the delay prediction model, is crucial to model accuracy. The early multi-process corner delay prediction model of this invention can adapt to multi-process corner scenarios. The model is trained on path data corresponding to a limited number of process corners and used to predict the timing of other paths under known and unknown process corners. Known process corners refer to those used in the training set, while unknown process corners refer to those not included in the training set. From an empirical perspective, if the training set data only covers the SS (Slow N Slow P) process corner, the prediction results for paths under the SS process corner may be excellent, but the timing prediction results for paths under the TT (Typical N Typical P) or even FF (Fast N Fast P) process corners may be poor. Therefore, for the same number of training set process corners, a model with relatively uniform coverage of all process corners may achieve better performance. In order to screen the subset of training set process angles that can achieve the best prediction effect, the present invention regards the problem of selecting the training set process angle subset as an optimization problem, and uses a greedy search algorithm to iteratively delete the training data under a certain process angle from the training set to find the optimal process angle subset under the condition that the number of training set process angles is determined.

[0077] Furthermore, the step S4 is as follows: Figure 4 As shown, the specific steps include:

[0078] S41: Path sequence features are input into a BLSTM network for representation learning. A traditional LSTM network consists of a series of LSTM cells. Each LSTM cell learns information from its own level and passes it on to the next level, sequentially learning the interactions between elements in the input sequence and obtaining a vector representation of the entire input sequence. This LSTM network's sequence learning is unidirectional. However, in path timing problems, the influence between gate cells is mutual and bidirectional. The timing of the current gate cell is affected not only by the previous and preceding cells, but also by the next and subsequent cells. For example, the input transition time of each cell in the path affects the output transition time of the current cell, which in turn affects the input transition time of the next cell. This influence in the path closely correlates the timing information of the previous cell with that of the subsequent cell. Line length is closely related to line capacitance. Changes in line length lead to changes in load capacitance, which in turn affects the timing of the previous cell and even the cells before it. This influence causes the timing information of the previous cell to be affected by information related to the next cell. Therefore, in the problem of path time series prediction, simply using a unidirectional LSTM network will cause information loss and lead to a decrease in prediction accuracy;

[0079] In order to better learn the mutual influence relationship between units at all levels in the path, this paper uses a bidirectional long short-term memory network to represent the path sequence features. The bidirectional LSTM consists of two opposite unidirectional LSTM layers. Its forward and reverse memory transmission characteristics enable the influence between units in the path to be transmitted to the previous and next levels. The structure of the BLSTM layer: Input sequence {x1, x2, ..., x k} Input into the forward LSTM layer to get the forward output f of each level k , input into the reverse LSTM layer to obtain the reverse output b of each level k , the final output of each level of the BLSTM layer is composed of the forward output f k and reverse output b k For multiple BLSTM layers, the output vectors of each level after splicing form a new sequence as the input of the next BLSTM layer. For the last BLSTM layer, the output vector f of the last level of the forward LSTM layer is k The concatenation of the output vector b1 of the last level of the reverse LSTM layer is used as the representation vector of the entire sequence.

[0080] S42: The impact of the global characteristics of the path on the path timing after layout cannot be ignored. Global characteristics such as process, voltage, temperature and integrated path delay constitute a feature matrix. After processing by feature engineering, an effective path global feature representation can be obtained. Unlike complex path sequence characteristics, the global characteristics of the path can be described by a data matrix. Therefore, the present invention uses a simple MLP network to characterize and learn the extracted global features. The MLP network used in the present invention is composed of two fully connected layers and one discarding layer (dropout layer). The fully connected layer learns the potential information by performing dimensional transformation on the initial global features. The dropout layer randomly deletes some neurons in the fully connected layer to reduce the occurrence of overfitting. After learning through the MLP network, a global feature representation vector is obtained.

[0081] Finally, the global feature representation vector learned by the MLP network and the sequence feature representation vector learned by the BLSTM network are combined to form the final path representation vector. This vector is then input into the artificial neural network to predict the path delay changes during the logic synthesis and layout stages. The predicted path delay changes are then added to the path delay values ​​after logic synthesis to estimate the path delay value after layout.

[0082] Furthermore, the step S6 specifically includes the following steps:

[0083] S61: This optimization process embeds the delay prediction model proposed in the present invention into the chip design process, and uses the path delay values ​​after layout predicted by the delay prediction model to guide further PPA optimization in the logic synthesis stage to generate a higher quality circuit netlist.

[0084] To maintain a certain margin, the present invention considers paths with predicted post-layout path delays greater than 90% of the clock cycle as critical paths. It then uses the set_max_delay command to generate a timing constraint file based on the TCL (Tool Command Language) language to constrain these critical paths that require further optimization. Design Compiler is then used for incremental optimization to generate a higher-quality circuit netlist, improving the design's power consumption, performance, and area (PPA), thereby reducing design iterations and lowering the time cost of chip design.

[0085] Example 2:

[0086] A computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements an early multi-process corner timing prediction method based on deep learning as described in any one of Embodiment 1.

[0087] Example 3:

[0088] A computer device comprising:

[0089] Memory, used to store instructions.

[0090] A processor is used to execute the instructions so that the computer device performs the operations of the early multi-process corner timing prediction method based on deep learning as described in any one of Example 1.

[0091] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0092] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0095] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A deep learning-based early multi-process corner timing prediction method, characterized by: Specifically include: Step S1: Obtain a circuit netlist after logic synthesis and a circuit netlist after layout, perform static timing analysis on the circuit netlist after logic synthesis and the circuit netlist after layout, obtain a static timing report of the circuit after logic synthesis and a static timing report of the circuit after layout, extract the timing, physical information and path delay value of each level of units in the path of the circuit after logic synthesis from the static timing report of the circuit after logic synthesis, extract the path delay value information of the circuit after layout from the static timing report of the circuit after layout, and use the difference between the path delay value after layout and the path delay value after logic synthesis as a label; Step S2: pre-processing the timing and physical information of each unit in the path of the circuit after logic synthesis to obtain the sequence characteristics and global characteristics of the path; Step S3: Inputting the sequence features and global features into the extreme gradient boosting model for process corner selection to obtain optimized sequence features and global features; Step S4: Input the optimized sequence features into the bidirectional long short-term memory network for learning to obtain the sequence feature representation vector of the path, and input the optimized global features into the multi-layer perceptron network for learning to obtain the global feature representation vector of the path; Step S5: Merge the sequence feature representation vector of the path and the global feature representation vector of the path. The merged representation vector and the label are used as training samples. The time series prediction model is trained using the training samples to obtain a trained time series prediction model. Step S6: Input the circuit netlist to be predicted after logic synthesis into the trained timing prediction model to obtain the path delay prediction value after layout; The step S2 specifically includes: For discrete non-numeric variables of the path's unit type, a word segmenter is used to create a numeric variable that is mapped one-to-one with the unit type variable; For the continuous numerical variables of the path unit delay, input conversion time, output load capacitance, and half-period, the variables are mapped to different bins through binning operations for discretization, and the resulting discrete numerical variables are obtained whose relative size relationships before and after the numerical conversion remain unchanged. Get the discrete numeric variable of the cell fanout of the path; The above numerical variables are combined into the sequence characteristics of the path; The process features and values ​​in the PVT features of the path are mapped one by one and merged with the values ​​in the PVT features into PVT numerical variables. The sequence features, PVT numerical variables and the path delay value after logic synthesis are spliced ​​to obtain the global features of the path.

2. The method for early multi-process corner timing prediction based on deep learning according to claim 1, characterized in that: Also includes: Step S7: Based on the predicted path delay values ​​after layout, a logic synthesis tool is used to obtain an optimized circuit netlist.

3. The method for early multi-process corner timing prediction based on deep learning according to claim 1, characterized in that: The dimensions of the sequence features and global features of each path are the same, and the parts with insufficient sequence features are filled with zeros.

4. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: The step S3 specifically includes: The sequence features and global features of the path are input into the extreme gradient boosting model for representation learning to obtain the delay values ​​of the path under different process corner types; Iteratively delete the sequence features and global features of the path under a certain process angle according to the delay values ​​of the paths under different process angle types; The sequence characteristics and global characteristics of the path with a balanced number of process corner types are obtained as the optimized sequence characteristics and global characteristics.

5. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: The bidirectional long short-term memory network includes two opposite unidirectional LSTM layers, the input sequence {x 1 ,x 2 ,…,x k } Input into the forward LSTM layer to get the forward output of each level f k , input into the reverse LSTM layer to get the reverse output of each level b k , the final output of each level of the BLSTM layer is the forward output f k and reverse output b k For multiple BLSTM layers, the output vectors of each level after splicing form a new sequence as the input of the next BLSTM layer. For the last BLSTM layer, the output vector of the last level of the forward LSTM layer is f k and the output vector of the last level of the reverse LSTM layer b 1 The concatenation of is used as the representation vector of the entire sequence; The multilayer perceptron network consists of two fully connected layers and one dropout layer. The fully connected layer learns potential information by performing dimensionality transformation on the initial global features. The dropout layer randomly deletes some neurons in the fully connected layer to obtain a global feature representation vector.

6. The method for early multi-process corner timing prediction based on deep learning according to claim 1 or 2, characterized in that: The time series prediction model adopts an artificial neural network.

7. The method for early multi-process corner timing prediction based on deep learning according to claim 2, characterized in that: The step S7 specifically includes: According to the path delay prediction value after layout, the path with the path delay prediction value greater than the threshold is regarded as the critical path, and the timing constraint command corresponding to the logic synthesis tool is generated for the critical path; According to the timing constraint commands corresponding to the logic synthesis tool, the logic synthesis tool is used to perform incremental optimization to obtain an optimized circuit netlist.

8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, an early multi-process corner timing prediction method based on deep learning as described in any one of claims 1 to 7 is implemented.

9. A computer device, characterized in that: include: a memory for storing instructions; A processor is configured to execute the instructions so that the computer device performs the operations of the deep learning-based early multi-process corner timing prediction method as described in any one of claims 1 to 7.

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