High-speed bus physical planning method, integrated circuit, computer equipment and medium

Abstract

The present invention provides a high-speed bus physical planning method, integrated circuit, computer equipment and medium, including the steps of: obtaining a first correspondence between high-speed bus layout parameters and unit transmission distance through a benchmark test; obtaining a second correspondence between routing distance and transmission path level under different bus bit numbers and clock cycles; determining the optimal mapping relationship between routing distance, transmission path level and layout parameters under different bus bit numbers and clock cycles according to the first correspondence and the second correspondence; obtaining the physical positions of two modules, and determining the shortest path of the bus according to the physical positions; determining the optimal layout parameters and optimal transmission path level of the bus according to the shortest path and the optimal mapping relationship; determining the register placement position and performing bus layout according to the optimal layout parameters and the optimal transmission path level. The scheme can quickly realize the physical planning of the high-speed bus, and provide the optimal bus layout scheme to ensure the performance of the bus and the integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-speed bus physical planning method, an integrated circuit, a computer device and a medium. Background Art

[0002] The rapid development of integrated circuits not only makes the functions of each sub-functional module of integrated circuits more and more complex, but also makes the number of connections between each sub-module increase, the routing distance becomes longer and longer, and the frequency of data changes on these connections becomes higher and higher, which will generate a large-scale high-speed bus over long distances. The implementation of such a bus is very simple at the logical level, but there will be great challenges in physical implementation. In order to achieve accurate signal propagation, these buses need to add multi-level pipeline registers and a large number of buffers. The placement of a large number of registers and buffers in space, and the crosstalk between each high-speed bus, will affect the performance of the bus and the integrated circuit. Therefore, there is an urgent need for a solution that can quickly realize high-speed bus path planning, device placement, and bus parameter selection. Summary of the invention

[0003] The purpose of the present invention is to provide a high-speed bus physical planning method, integrated circuit, computer equipment and medium, which can quickly realize the physical planning of the high-speed bus and provide the optimal bus layout plan to ensure the performance of the bus and the integrated circuit.

[0004] The technical solution provided by the present invention is as follows:

[0005] In a first aspect, the present application provides a high-speed bus physical planning method, comprising the steps of:

[0006] Obtaining a first correspondence between a layout parameter of a high-speed bus and a unit transmission distance through a benchmark test, wherein the unit transmission distance is a transmission distance of each bit of data within each preset time length;

[0007] Obtain a second corresponding relationship between the routing distance and the number of transmission path levels under different bus bit numbers and clock cycles;

[0008] Determine the optimal mapping relationship between the routing distance, the transmission path level, and the layout parameter under different bus bit numbers and clock cycles according to the first corresponding relationship and the second corresponding relationship;

[0009] Obtaining the physical locations of two modules connected by a bus, and determining the shortest path of the bus according to the physical locations;

[0010] Determine the optimal layout parameters of the bus and the optimal transmission path level according to the shortest path and the optimal mapping relationship;

[0011] The register placement position is determined according to the optimal layout parameters and the optimal transmission path level, and the bus arrangement is performed.

[0012] In some implementations, the layout parameters include the number of routing lines of each row unit, the width of the row unit, and the bus wiring density.

[0013] In some implementations, the obtaining of the physical locations of the two modules connected by the bus and determining the shortest path of the bus according to the physical locations specifically includes:

[0014] Divide the placement area of ​​the top surface of the chip except for the area occupied by each module into a plurality of cells according to a predetermined size;

[0015] Determine the number of groups of buses used to connect the two modules;

[0016] Determine the first starting cell area and the second starting cell area of ​​the corresponding communication channel widths respectively connected to the two modules according to each group of buses in turn;

[0017] Starting from the first starting cell area or the second starting cell area, traverse combinations of cell areas that can respectively connect the first starting cell area and the second starting cell area and have the same width, and determine the shortest path of each group of buses according to the Manhattan distance of each combination.

[0018] In some implementations, determining the register placement position and performing bus arrangement according to the optimal layout parameter and the optimal transmission path level includes:

[0019] Recording the connectivity shape information of the shortest path of each group of buses, and the starting point coordinates of the starting point line segments of the first starting cell area and the second starting cell area;

[0020] The average routing distance of each level of transmission path of each group of buses is obtained by dividing the shortest path of each group of buses by N+1, where N is the number of levels of the optimal transmission path;

[0021] Determine the coordinate information of each level of transmission path of each group of buses according to the connectivity shape information of the shortest path of each group of buses, the average routing distance of each level of transmission path, and the starting point coordinates;

[0022] The register placement position is determined according to the coordinate information.

[0023] In some embodiments, it further comprises:

[0024] Determining bus winding density according to the optimal layout parameters;

[0025] Determine a first number of registers to be placed in each row of a path in the horizontal direction of the shortest path according to the bus winding density, and determine a second number of registers to be placed in each row of a path in the vertical direction of the shortest path according to the bus winding density and the width of the connecting channel;

[0026] The registers are placed according to the register placement positions, the first quantity and the second quantity.

[0027] In some implementations, register placement is performed using EDA tools.

[0028] In some embodiments, the bus winding density is between 45% and 65%.

[0029] In a second aspect, the present application provides an integrated circuit, comprising a high-speed bus set up by the high-speed bus physical planning method described in the first aspect.

[0030] In a third aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the high-speed bus physical planning method described in the first aspect.

[0031] In a fourth aspect, the present application provides a computer storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implements the steps of the high-speed bus physical planning method described in the first aspect.

[0032] Through the high-speed bus physical planning method, integrated circuit, computer equipment and medium provided by the present invention, the physical planning of the high-speed bus can be quickly implemented, the optimal bus layout plan can be given, and the precise position of the register can be determined under the optimal solution, avoiding the uncertainty of automatic placement of EDA tools, thereby ensuring the performance of the bus and the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present solution.

[0034] Figure 1 It is a schematic diagram of the logic connection between the top modules of the integrated circuit of the present invention;

[0035] Figure 2 This is a situation in which the EDA default algorithm in the prior art plans the bus path;

[0036] Figure 3 It is an overall schematic diagram of a bus path planning scheme in the prior art;

[0037] Figure 4It is a schematic diagram of register distribution of a bus path planning scheme in the prior art;

[0038] Figure 5 It is a schematic diagram of the overall process of an embodiment of the present invention;

[0039] Figure 6 is a schematic diagram of a benchmark test of an embodiment of the present invention;

[0040] Figure 7 is a schematic diagram of cell division according to an embodiment of the present invention;

[0041] Figure 8 is a schematic diagram of a first starting cell region and a second starting cell region according to an embodiment of the present invention;

[0042] Fig. 9 is a bus path planning schematic diagram of an embodiment of the present invention;

[0043] Fig.10 is a schematic diagram of a bus path connection shape according to an embodiment of the present invention;

[0044] Fig.11 is a schematic diagram of multiple bus path planning according to an embodiment of the present invention;

[0045] Fig.12 It is a schematic diagram of register placement in the horizontal direction according to an embodiment of the present invention;

[0046] Fig.13 It is a schematic diagram of register placement in the vertical direction according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0048] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0049] The rapid development of integrated circuits not only makes the functions of each sub-functional module in the integrated circuit more and more complex, but also makes the number of connections between the sub-modules increase, the wiring distance increases, and the frequency of data changes on these connections increases, which will generate a large-scale high-speed bus (BUS) over long distances. Such a bus is very simple to implement at the logical level, but it will be very challenging in physical implementation. In order to achieve accurate signal propagation, these buses need to add multi-level pipeline registers and a large number of buffers. For example, Figure 1 As shown, a large number of BUS connections with clear high-speed structures are required between module A (BlockA) and module B (BlockB) at the top of an integrated circuit. In order to correctly realize the propagation therein, it is also necessary to add multi-stage pipeline registers (PipelineReg) and a large number of buffers (Buffer). The placement of a large number of registers and buffers in space and the crosstalk between each high-speed bus will affect the performance of the bus and the integrated circuit. How to obtain an accurate optimal bus physical implementation scheme as soon as possible is the purpose of the present invention. In particular, when this problem is applied to ultra-large-scale integrated circuits, due to the larger circuit scale of ultra-large-scale integrated circuits and the huge number of routings, each round of optimization takes a very long time, which has a greater impact on the design cycle of the entire integrated circuit. For a large number of registers and buffers, the placement of the buffer is relatively simple, and it only needs to be placed evenly or unevenly along the bus path, while the placement of the register is related to the number of levels of the entire bus transmission path. Therefore, the determination of the placement position of the register is particularly important in the physical implementation of the bus.

[0050] In the prior art, the planning of high-speed buses in the top-level circuit is usually performed through EDA tools. However, under the default algorithm of EDA, when there are a large number of high-speed buses in the top-level circuit, the tool still encounters the following problems while optimizing all paths as much as possible: Figure 2 The path planning situation shown in the figure results in different Manhattan distances for different bits in the BUS between BlockA and BlockB, and some bits have longer Manhattan distances, which affects the overall performance of the entire BUS. In addition, the default behavior of EDA also includes making the distances between registers of different levels related to the same bit differ greatly. For example, the distance between the registers from the first level to the second level is 1000um, and the distance between the registers from the second level to the third level is 2000um. The timing may be close to being met during the placement stage, but after the wiring is combined with the influence of crosstalk, the timing between the two-level buses with too long distances will be violated, affecting the overall performance.

[0051] To solve the above problems, Figure 3As shown in the figure, we can draw a boundary box for each level of pipeline registers in each group of BUS on the top level according to the better straight-line distance route and the fixed distance between the two-level pipeline registers, so that each level of registers related to each bit in the same group of BUS can be placed in a relatively concentrated position. This not only ensures that the performance of different bits in a group of BUS tends to be consistent, and there will be no situation where some bits are optimized very well and some bits are poorly optimized; it also ensures that the registers between the two levels can be fixedly placed at a distance that meets the timing. However, if Figure 4 As shown, even if the above solution is used, the default behavior of the EDA tool will cause the pipeline registers to be unevenly distributed locally within a bounding box, and a large number of registers are easily concentrated at the edge of the bounding box, while the register density in the middle part of the bounding box is low, resulting in greater crosstalk between bus bits in densely packed areas at the edge, and less crosstalk between bus bits in areas with lower density. Therefore, even if the layout is relatively close, the timing performance will still be quite different due to the large difference in the routing environment. In addition, when there are many similar BUSs at the top level and they are far apart, the overall SOC needs to plan more pipeline register groups and organize more bounding boxes, which requires a large amount of manual work and has a great impact on the schedule of the entire design. In addition, when the entire design changes and needs to be adjusted and optimized, this part of the manual work also needs to be repeated to varying degrees, resulting in a waste of human and machine resources.

[0052] This solution is based on the basic data of how far the next-level pipeline register can support data transmission at a certain winding density. It uses the method of first completing the path planning of the entire BUS, and then accurately calculating the placement position of each group of pipeline registers on this path, so as to automatically complete the precise placement of all pipeline registers in the form of M*N Martrix, so that there is no need to organize the boundary box, and it can avoid random placement of registers, which is conducive to ensuring bus performance. The following will describe this solution in detail with the accompanying drawings:

[0053] In one embodiment, the reference specification Figure 5 The present application provides a high-speed bus physical planning method, comprising the steps of:

[0054] S100, obtaining a first correspondence between a layout parameter of a high-speed bus and a unit transmission distance through a benchmark test, where the unit transmission distance is a transmission distance of each bit of data within each preset time length;

[0055] S200, obtaining a second corresponding relationship between the routing distance and the number of transmission path levels under different bus bit numbers and clock cycles;

[0056] S300, determining the optimal mapping relationship between routing distance, transmission path level and layout parameters under different bus bit numbers and clock cycles according to the first corresponding relationship and the second corresponding relationship;

[0057] S400, obtaining the physical locations of two modules connected by a bus, and determining the shortest path of the bus according to the physical locations;

[0058] S500, determining the optimal layout parameters of the bus and the optimal transmission path level according to the shortest path and the optimal mapping relationship;

[0059] S600: Determine the register placement position and perform bus layout according to the optimal layout parameters and the optimal transmission path level.

[0060] Specifically, the layout parameters include the number of lines per row unit, the width of the row unit, the bus winding density, etc. To avoid bus crosstalk, the bus winding density is set between 45% and 65%. Through benchmark tests, a set of BUS registers are placed from left to right in a regular manner, and different winding densities are traversed to calculate the basic data of the transmission distance of each bit of data within each preset time. In a specific implementation, such as Figure 6 As shown, benchmark tests are performed with a winding density of 45%, i.e., 4 wires per Site Row (row unit), a winding density of 52%, i.e., 5 wires per Site Row (row unit), and a winding density of 58%, i.e., 6 wires per Site Row (row unit). The transmission distance of each bit of data within each preset time length (e.g., 0.8ns, 1ns, etc.) under each layout parameter is calculated, and the first corresponding relationship between the layout parameters of the high-speed bus and the unit transmission distance can be obtained, as shown in the example in Table 1 below.

[0061] Table 1:

[0062]

[0063] On the other hand, this solution needs to count the clock cycles of all buses in the entire design, the required routing distances, and the number of pipeline registers that can be used under performance requirements. That is, it is necessary to obtain the second correspondence between routing distances and transmission path levels under different bus bit numbers and clock cycles. In a specific implementation, the second correspondence is shown in Table 2 below.

[0064] Table 2:

[0065]

[0066] According to the first corresponding relationship and the second corresponding relationship, the optimal mapping relationship among routing distance, transmission path level and layout parameters under different bus bit numbers and clock cycles can be determined. For example, for Bus1 in the example of Table 2, because the routing distance is 7000um and only two pipeline registers can be added, the routing distance of each level is 2333um. According to Table 1, a winding density of 52% can be used to achieve this performance requirement with the minimum width; for another example, for Bus2 in the example of Table 2, because the routing distance is 7500um, the routing distance of each level must be greater than 2500um, and according to Table 1, only a winding density of 45% can be selected; for another example, for Bus3 in the example of Table 2, because the clock cycle of Bus3 is 0.8ns, and only two pipeline registers can be added, the routing distance of each level must be 2000um. According to Table 1, this performance can be achieved by selecting a winding density of 45% without adding a pipeline; for another example, for Bus4 in the example of Table 2, because a three-stage pipeline can be used, it can be achieved even with a winding density of 58% according to Table 1, so the goal can be achieved with the minimum area cost. The optimal mapping relationship is shown in Table 3 below.

[0067] Table 3:

[0068]

[0069] The aforementioned first corresponding relationship, second corresponding relationship and optimal mapping relationship can be performed before the specific bus planning. When performing the specific bus planning, first obtain the physical positions of the two modules connected by the bus, and determine the shortest path of the bus based on the physical position. The shortest path is the routing distance of the bus. The optimal layout parameters and the optimal transmission path level of the bus under the routing distance can be determined based on the shortest path and the optimal mapping relationship; the register placement position can be determined based on the optimal layout parameters and the optimal transmission path level, and the bus layout can be completed by placing the register at the register placement position. This solution can quickly realize the physical planning of the high-speed bus, provide the optimal bus layout plan, and achieve the precise position determination of the register under the optimal solution, avoiding the uncertainty of automatic placement of the EDA tool, thereby ensuring the performance of the bus and the integrated circuit.

[0070] In one embodiment, obtaining the physical locations of two modules connected by a bus and determining the shortest path of the bus according to the physical locations specifically includes:

[0071] S410, dividing the placement area of ​​the top surface of the chip except for the area occupied by each module into a plurality of cells according to a predetermined size; for example, Figure 7As shown, the area in the entire design where cells can be placed is divided into a large number of cells that can be used to place cells according to a certain size, such as 10um*10um, and no cells are allocated to the areas that have been occupied by various modules.

[0072] S420: Determine the number of bus groups used to connect two modules.

[0073] S430, determining in sequence according to each group of buses a first starting cell region and a second starting cell region corresponding to the width of the communication channels respectively connected to two modules.

[0074] S440, starting from the first starting cell area or the second starting cell area, traverse combinations of cell areas that can respectively connect the first starting cell area and the second starting cell area and have the same width, and determine the shortest path of each group of buses according to the Manhattan distance of each combination.

[0075] In one example, if Figure 8 As shown, for the first group of Bus1 from ABus1 to BBus1 that needs to be implemented, first find the nearest placement cell area corresponding to the winding width according to the location of ABus1 and BBus1, and divide it into the first starting cell area and the second starting cell area, select the first starting cell area or the second starting cell area as the starting point, and use the cell area to continuously traverse the combination of adjacent connected cell areas with the same width, and finally find the shortest path from ABus1 to BBus1 according to the Manhattan distance of each combination, as shown in Fig. 9 The figure shows a shortest path for Bus1 (when there are multiple shortest paths, just select one of them). Record the total number of Pipeline levels required for this group of Bus1 and the information of all connected shapes. The format of recording the information of connected shapes is as follows: {shape direction (horizontal H / vertical V), coordinates of the starting line segment {sx0 sy0, sx1 sy1}, coordinates of the end line segment {ex0 ey0, ex1 ey1}}, as shown in the figure below: Fig.10 After finding the shortest path for a group of buses, the same method is used to obtain the shortest path for the next group of buses, as shown in Fig.11 As shown, until all the paths of the bus groups used to connect the two modules are found.

[0076] Preferably, determining the register placement position and performing bus arrangement according to the optimal layout parameters and the optimal transmission path level includes:

[0077] S510, recording the connectivity shape information of the shortest path of each group of buses, and the starting point coordinates of the starting line segments of the first starting cell area and the second starting cell area;

[0078] S520, obtaining an average routing distance of each level of transmission path of each group of buses by dividing the shortest path of each group of buses by N+1, where N is the number of levels of the optimal transmission path;

[0079] S530, determining the coordinate information of each level of transmission path of each group of buses according to the connectivity shape information of the shortest path of each group of buses, the average routing distance of each level of transmission path, and the starting point coordinates;

[0080] S540: Determine the register placement position according to the coordinate information.

[0081] Further preferably, after determining the register placement position, the method further includes:

[0082] S550, determining the bus winding density according to the optimal layout parameters;

[0083] S560, determining a first number of registers to be placed in each row of a path in the horizontal direction of the shortest path according to the bus winding density, and determining a second number of registers to be placed in each row of a path in the vertical direction of the shortest path according to the bus winding density and the width of the connecting channel;

[0084] S570. Place the registers according to the register placement positions, the first quantity, and the second quantity. Preferably, place the registers using an EDA tool.

[0085] For each level of the transmission path, the registers are arranged horizontally and vertically as follows: Fig.12 and Fig.13 As shown, the number of registers placed in each row in the horizontal direction is determined by the number of registers placed in one row unit according to the winding density; the number of registers placed in each row in the vertical direction is determined by the width of the connecting channel divided by the width of the register itself. The two directions are guaranteed to be consistent in terms of the winding density and the width of the entire channel. After determining the overall position of each level of registers relative to the origin coordinate information and the placement of the register array in each level of transmission path, the specific position of all registers can be obtained. According to the position information, each register can be placed to complete the placement of all registers.

[0086] In one embodiment, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the high-speed bus physical planning method of the aforementioned embodiment.

[0087] In one embodiment, the present application provides a computer storage medium having a computer program or instruction stored thereon, and when the computer program or instruction is executed by a processor, the steps of the high-speed bus physical planning method of the aforementioned embodiment are implemented.

[0088] In one embodiment, the present application provides a computer program product, including a computer program or instructions, which implements the steps of the high-speed bus physical planning method of the aforementioned embodiment when the computer program or instructions are executed by a processor.

[0089] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0090] The memory may be an internal storage unit of the simulation system, such as a hard disk or memory of an intelligent device. The memory may also be an external storage device of the intelligent device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the intelligent device. Further, the memory is used to store the computer program and other programs and data required by the verification method of the FPGA. The memory may also be used to temporarily store data that has been output or is to be output.

[0091] The communication bus is a circuit that connects the elements described and implements transmission between these elements. For example, the central processing unit receives commands from other elements through the communication bus, decrypts the received commands, and performs calculations or data processing according to the decrypted commands. The memory may include program modules, such as a kernel, middleware, an application programming interface (API) and an application. The program module may be composed of software, firmware or hardware, or at least two of them. The input / output interface forwards commands or data entered by the user through the input / output interface (such as a sensor, keyboard, touch screen). The communication interface connects the speed measurement device of the artificial heart with other network devices, user devices, and networks. For example, the communication interface can be connected to the network via wired or wireless connection to connect to other external network devices or user devices. Wireless communication may include at least one of the following: wireless fidelity (WiFi), Bluetooth (BT), near field communication technology (NFC), global satellite positioning system (GPS) and cellular communication, etc. Wired communication may include at least one of the following: universal serial bus (USB), high-definition multimedia interface (HDMI), asynchronous transmission standard interface (RS-232), etc. The network may be a telecommunication network and a communication network. The communication network may be a computer network, the Internet, the Internet of Things, or a telephone network. The verification device of the FPGA may be connected to the network via a communication interface, and the protocol used by the speed measuring device of the artificial heart and other network devices to communicate may be supported by at least one of an application, an application programming interface (API), a middleware, a kernel, and a communication interface.

[0092] The high-speed bus physical planning method of the present application can be implemented with program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0093] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A high-speed bus physical planning method, characterized in that: Includes steps: Obtaining a first correspondence between a layout parameter of a high-speed bus and a unit transmission distance through a benchmark test, wherein the unit transmission distance is a transmission distance of each bit of data within each preset time length; Obtain a second corresponding relationship between the routing distance and the number of transmission path levels under different bus bit numbers and clock cycles; Determine the optimal mapping relationship between the routing distance, the transmission path level, and the layout parameter under different bus bit numbers and clock cycles according to the first corresponding relationship and the second corresponding relationship; Obtaining the physical locations of two modules connected by a bus, and determining the shortest path of the bus according to the physical locations; Determine the optimal layout parameters of the bus and the optimal transmission path level according to the shortest path and the optimal mapping relationship; The register placement position is determined according to the optimal layout parameters and the optimal transmission path level, and the bus arrangement is performed.

2. The high-speed bus physical planning method according to claim 1, characterized in that: The layout parameters include the number of routing lines of each row unit, the width of the row unit, and the bus winding density.

3. The high-speed bus physical planning method according to claim 1, characterized in that: The obtaining of the physical positions of the two modules connected by the bus and determining the shortest path of the bus according to the physical positions specifically includes: Divide the placement area of ​​the top surface of the chip except for the area occupied by each module into a plurality of cells according to a predetermined size; Determine the number of groups of buses used to connect the two modules; Determine the first starting cell area and the second starting cell area of ​​the corresponding communication channel widths respectively connected to the two modules according to each group of buses in turn; Starting from the first starting cell area or the second starting cell area, traverse combinations of cell areas that can respectively connect the first starting cell area and the second starting cell area and have the same width, and determine the shortest path of each group of buses according to the Manhattan distance of each combination.

4. The high-speed bus physical planning method according to claim 3, characterized in that: The step of determining the register placement position and performing bus arrangement according to the optimal layout parameters and the optimal transmission path level comprises: Recording the connectivity shape information of the shortest path of each group of buses, and the starting point coordinates of the starting point line segments of the first starting cell area and the second starting cell area; The average routing distance of each level of transmission path of each group of buses is obtained by dividing the shortest path of each group of buses by N+1, where N is the number of levels of the optimal transmission path; Determine the coordinate information of each level of transmission path of each group of buses according to the connectivity shape information of the shortest path of each group of buses, the average routing distance of each level of transmission path, and the starting point coordinates; The register placement position is determined according to the coordinate information.

5. The high-speed bus physical planning method according to claim 4, characterized in that: Also includes: Determining bus winding density according to the optimal layout parameters; Determine a first number of registers to be placed in each row of a path in the horizontal direction of the shortest path according to the bus winding density, and determine a second number of registers to be placed in each row of a path in the vertical direction of the shortest path according to the bus winding density and the width of the connecting channel; The registers are placed according to the register placement positions, the first quantity and the second quantity.

6. The high-speed bus physical planning method according to claim 5, characterized in that: Registers are placed using EDA tools.

7. The high-speed bus physical planning method according to claim 2, characterized in that: The bus winding density is between 45% and 65%.

8. An integrated circuit, characterized in that: It comprises a high-speed bus set up by the high-speed bus physical planning method described in any one of claims 1-7.

9. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the high-speed bus physical planning method according to any one of claims 1 to 7.

10. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the high-speed bus physical planning method according to any one of claims 1 to 7 are implemented.

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