Self-correcting chained computing device and method for on-chip quantization vector MAC (Media Access Control) operation based on DSP (Digital Signal Processor)

Abstract

The invention discloses an on-chip quantization vector MAC (Media Access Control) operation-oriented self-correcting chain computing device and method based on a DSP (Digital Signal Processor). The device comprises a cascade structure formed by a plurality of cascaded DSP48E2 units; each stage of DSP48E2 unit is in cascade connection with calculation results of the upper and lower stages of DSP48E2 units and accumulative input; each stage of DSP48E2 unit receives the symbol condition of superior input data and also detects the symbol condition of the calculation result of the lower half part of the superior DSP48E2 unit; on the basis of a pre-established correction mechanism, generating upper half part calculation result correction data of packaging calculation of the superior DSP48E2 unit; and inputting the obtained correction data of the calculation result of the upper half part into the ALU subunit in the DSP48E2 unit at the same level to participate in the addition stage of the upper half part so as to realize the self-correction of the calculation result of the upper half part of the upper-level DSP48E2 unit. According to the method, the connection mode of the DSP calculation chain is improved, and an error correction mechanism is added, so that packaging MAC calculation of low-precision input data with symbols can be processed under the condition that errors are not generated.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA data processing, and more specifically, relates to a self-correcting chain computing device and method for on-chip quantized vector MAC operation based on DSP. Background Art

[0002] In the neural network computing scenario, vector-matrix multiplication operations frequently appear in the computing data flow, and such operations have high requirements on the computing power of the hardware. When performing such calculations on FPGA devices, a large number of digital signal processor units (DSPs) are usually called for processing, but the number of DSP resources available on the chip is often quite limited. Therefore, making full use of DSP resources is crucial to the computing performance, power and area of ​​FPGA hardware. However, the DSPs available in Xilinx devices are all implemented as large-bit-width operators (such as 48-bit accumulators or 18 by 27-bit multipliers). Directly using such DSPs to process relatively low-precision input data will result in insufficient utilization of the DSP's computing resources. Therefore, for lower-precision fixed-point multiplication and addition operations, the prior art proposes a method for packing and calculating two or more multiplication operations in a single clock cycle on a single DSP, and a method for packing and calculating two addition operations.

[0003] However, although this calculation packing method has been used, it still has defects. When the existing solution processes the packing calculation of signed numbers, the sign bit of the lower half of the calculation result may overflow, resulting in deviations in the upper half of the calculation result. When several such DSPs are cascaded into a calculation chain and perform packing calculation operations, the resulting calculation deviations will accumulate, thereby causing non-negligible errors in the final calculation result.

[0004] The prior art also proposes to correct this calculation error, but in its solution, the generation mechanism and correction method of the packed multiplication error and the packed addition error are analyzed separately, and the error generation mechanism and correction method of the packed MAC operation, which is more common in neural network calculation, are not fully analyzed. In addition, the error correction method proposed is only applicable to the error correction of the multiplication or addition packing calculation of a single-stage DSP, and the proposed addition calculation error correction scheme cannot be applied to the packed DSP MAC calculation, and cannot be extended to the error correction of the cascaded DSP chain calculation. Therefore, there is currently a lack of a DSP packed MAC calculation error correction method and corresponding calculation structure that can be applied to cascade scale. Summary of the invention

[0005] The present invention provides a DSP-based self-correcting chain computing device and method for on-chip quantized vector MAC operations to overcome the problem that the prior art cannot process packed MAC computing of signed low-precision input data without generating errors.

[0006] The primary purpose of the present invention is to solve the above technical problems. The technical solutions of the present invention are as follows:

[0007] The first aspect of the present invention provides a self-correcting chain computing device for on-chip quantized vector MAC operation based on DSP, comprising: a plurality of cascade-connected DSP48E2 units, each level of DSP48E2 unit comprising a correction data input terminal, a cascade data input terminal, a DSP48E2 module, a cascade data output terminal, a correction generation logic module, a weight data input terminal and an activation value data input terminal; the specific connection relationship is: the calculation result of the upper level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level are respectively input into the cascade data of the DSP48E2 module of the current level; The weight data and activation value data of this level are respectively input into the weight data input and activation value data input of the DSP48E2 module of this level. The output of the DSP48E2 module of this level is passed through the cascade data output to obtain the calculation result of this level. The calculation result of this level, the weight data of this level and the activation value data of this level are input into the correction generation logic module to obtain the correction data of the upper half of the calculation result of the DSP48E2 unit of this level. The correction data and the calculation result of this level are respectively input into the correction data input and the cascade data input of the lower-level DSP48E2 unit.

[0008] Furthermore, the PCIN port of each stage DSP48E2 unit is cascade-connected to the PCOUT port of the upper stage DSP48E2 unit for inputting the calculation result of the upper stage DSP48E2 unit.

[0009] Furthermore, through the C port of the DSP48E2 unit at this stage, the correction data of the calculation result of the upper half of the upper stage is input into the ALU subunit inside the DSP48E2 unit at this stage to participate in the addition stage of the upper half.

[0010] Furthermore, the device also includes: a weight buffer and an activation value buffer; the weight values ​​in the neural network calculation are input into the weight buffer, and the weight buffer inputs the weight values ​​of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; the activation values ​​in the neural network calculation are input into the activation value buffer, and the activation value buffer inputs the activation values ​​of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

[0011] Furthermore, the device also includes: a final correction unit; the final correction unit is connected to the cascade data output end of the last stage DSP48E2 unit, and the last stage DSP48E2 unit is corrected by the final correction unit.

[0012] The second aspect of the present invention provides a self-correcting chain computing method for on-chip quantized vector MAC operations based on DSP. The method is applied to a self-correcting chain computing device for on-chip quantized vector MAC operations based on DSP. The method includes the following steps: inputting the first weight input data (W0) and the second weight input data (W1) of this stage into the first-stage adder of the DSP48E2 unit of this stage for shift addition, inputting the addition result and the activation value data (ACTSHare) of this stage into the multiplier for multiplication, inputting the multiplication result and the calculation result of the upper-level DSP48E2 unit and the correction data of the upper-level upper half calculation result generated by a preset correction mechanism into the second-stage adder, and outputting the calculation result of the DSP48E2 unit of this stage.

[0013] Furthermore, the specific method of using the preset correction mechanism to generate correction data for the upper half calculation result of the upper level is: using the upper level symbol situation and the current level symbol situation to determine in turn whether the upper level DSP48E2 unit generates a +1 error, whether the upper level DSP48E2 unit generates a -1 error, whether there is an error in the upper half calculation of the upper level DSP48E2 unit, and the current level DSP48E2 unit generates correction data for the upper half calculation of the upper level DSP48E2 unit.

[0014] Furthermore, the symbol conditions include:

[0015] The first mark is based on the positive or negative sign of the multiplication result of the lower half of the multiplication stage calculated by each DSP48E2 unit. If the result sign is negative, it is recorded as the first mark; if the result sign is positive, it is recorded as the second mark;

[0016] The second flag is calculated according to the result of the sign of another addend other than the multiplication result in the second half of the addition stage by each DSP48E2 unit. If the result is negative, it is recorded as the first flag; if the result is positive, it is recorded as the second flag.

[0017] Furthermore, in a cascade structure composed of several cascade-connected DSP48E2 units, the DSP48E2 unit at the first stage is not corrected.

[0018] Furthermore, the method also includes: calculating the neural network calculation load by accessing the corresponding weight buffer and activation value buffer; inputting the weight value in the neural network calculation into the weight buffer, and the weight buffer inputs the weight value of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; inputting the activation value in the neural network calculation into the activation value buffer, and the activation value buffer inputs the activation value of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0020] The present invention improves the connection mode of the DSP calculation chain and adds an error correction mechanism, so that it can process the packed MAC calculation of signed low-precision input data without generating errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the purpose and technical solution of the present invention clearer, the present invention provides the following drawings and descriptions:

[0022] Figure 1 This is the DSP48E2 unit framework diagram.

[0023] Figure 2 It is a schematic diagram of the conventional quantitative data packaging calculation method.

[0024] Figure 3 It is a schematic diagram of the calculation error generated during the quantized data multiplication packing calculation process.

[0025] Figure 4 It is a schematic diagram of the calculation error generated during the quantized data addition and packaging calculation process.

[0026] Figure 5 It is a schematic diagram of a self-correcting chain computing device for on-chip quantized vector MAC operation proposed by the present invention.

[0027] Figure 6 It is a schematic diagram of the principle of a single DSP48E2 computing unit.

[0028] Figure 7 It is a schematic diagram of the computational data flow for quantized vector inner product calculation in a neural network.

[0029] Figure 8 It is a schematic diagram of the principle of using a self-correcting chain-chain computing device to realize the quantized vector inner product calculation. DETAILED DESCRIPTION

[0030] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0032] Embodiment 1:

[0033] In FPGA devices, the architecture block diagram of DSP48E2 in MACC (Multiply-Accumulate) mode is as follows Figure 1 As shown in the figure, after the data of ports A and D are added, they are multiplied with the data of port B, and then added with the data of port C, and finally the 48-bit calculation result is output from port P. In order to efficiently process the MAC calculation of low-precision data, two or more multiplication and addition operations are usually packaged into a single group of inputs to complete multiple multiplication and addition operations in a single DSP within a single cycle; for example, the calculation of two 8-bit data, c×b=X and c×a=Y, is done with c×(a×2 18 +b)=(Y×2 18 +X) and sent to the corresponding data port, and finally the calculation results of the two calculations are obtained at the corresponding position of the output port, such as Figure 2 In addition, in some accelerated calculations, the addition part calculation will also be packaged into the above calculation according to the needs; for example, on the basis of the above calculation, the calculation X+B=P is continued 0 and Y+A=P 1 , this addition will be packaged and calculated using the formula: (A×2 18 +X)+c×(a×2 18 + b) = (A × 2 18 +B)+(Y×2 18 + X) = P 1 ×2 18 +P 0 , and (A×2 18 +B) After being packaged, it is sent from the C port of the DSP to the 48-bit ALU in the DSP for addition, so as to make full use of the computing unit in the DSP to realize DSP chain calculation.

[0034] However, conventional packing calculation methods may cause calculation errors when processing signed data. The calculation errors are analyzed as follows:

[0035] As shown in the above packing calculation formula, the calculation can be divided into two steps: packing multiplication stage c×(a×2 18 +b) and the packed addition stage (A×2 18 +B)+(Y×2 18 +X); the calculation error generated in the packing multiplication stage is as follows: Figure 3 As shown, when the b input as the lower half of the packing is a non-negative number, there will be no problem with the direct packing calculation. However, when the data in the lower half is a negative number, its sign bit will overflow to the upper half during the packing calculation, causing errors in the data in the upper half during the addition stage. In addition, when the data of the multiplication input port B is a signed number, once the multiplication result of the lower half generated by the multiplier is a negative number, it will also cause errors in the upper half of the multiplication calculation. It can be seen from the binary multiplication operation rules that when the multiplication result of the lower half is a negative number, the multiplication result of the upper half will have a deviation of -1.

[0036] In addition, in the packing addition stage, if Figure 4 As shown, if the addition of the lower half will generate a carry, the carry will cause the result of the addition of the upper half to have a deviation of +1. Under the premise of reserving enough bit width for accumulation, the carry will only be generated by the sign bit carry, and will not be generated by data overflow. Therefore, when the two addends of the addition of the lower half are both positive, no carry overflow will occur; when the two addends of the addition of the lower half are both negative, since their highest sign bits are both 1, a carry will definitely occur; when the two addends of the addition of the lower half are one positive and one negative, according to the binary addition carry rule, a carry will occur if and only if the addition result is positive or 0, otherwise, if the addition result is negative, no carry will occur.

[0037] Therefore, to implement complete DSP packed MAC calculation, the errors of the two parts of calculation need to be processed, but the existing packed calculation error processing solution cannot handle this situation.

[0038] To this end, the present invention provides a self-correcting chain computing device for on-chip quantized vector MAC operations based on DSP, such as Figure 5As shown, the device includes: a plurality of cascade-connected DSP48E2 units, each level of DSP48E2 unit includes a correction data input terminal, a cascade data input terminal, a DSP48E2 module, a cascade data output terminal, a correction generation logic module, a weight data input terminal and an activation value data input terminal; the specific connection relationship is: the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level are respectively input into the cascade data input terminal and the correction data input terminal of the DSP48E2 module of this level, the weight data and the activation value data of this level are respectively input into the weight data input terminal and the activation value data input terminal of the DSP48E2 module of this level, and the output of the DSP48E2 module of this level is obtained through the cascade data output terminal to obtain the calculation result of this level; the calculation result of this level, the weight data of this level, and the activation value data of this level are input into the correction generation logic module to obtain the correction data of the upper half of the calculation result of the DSP48E2 unit of this level; the correction data and the calculation result of this level are respectively input into the correction data input terminal and the cascade data input terminal of the lower-level DSP48E2 unit.

[0039] More specifically, the PCIN port of each DSP48E2 unit is cascaded to the PCOUT port of the upper DSP48E2 unit for inputting the calculation result of the upper DSP48E2 unit. Through the C port of the DSP48E2 unit at this level, the correction data of the calculation result of the upper half of the upper level is input into the ALU subunit inside the DSP48E2 unit at this level to participate in the addition stage of the upper half.

[0040] The self-correcting chain computing device of the present invention maintains the original packed data input unchanged, and inputs the generated upper half of the calculation result correction data through the C input port of the DSP, so as to maximize the use of the internal resources of the DSP unit to solve the correction problem without using additional computing units. In addition, the self-correcting computing device of the present invention can be cascaded into a chain structure, using the PCIN and PCOUT ports of the DSP unit to cascade the calculation results and accumulated inputs of the upper and lower calculation stages, and design a corresponding pipeline structure, so as to finally realize the packed MAC calculation of low-precision signed input data with high efficiency without errors.

[0041] More specifically, the device also includes: a weight buffer and an activation value buffer; the weight values ​​in the neural network calculation are input into the weight buffer, and the weight buffer inputs the weight values ​​of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; the activation values ​​in the neural network calculation are input into the activation value buffer, and the activation value buffer inputs the activation values ​​of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

[0042] More specifically, the device further includes: a final correction unit; the final correction unit is connected to the cascade data output terminal of the last stage DSP48E2 unit, and the last stage DSP48E2 unit is corrected by the final correction unit.

[0043] Embodiment 2:

[0044] This embodiment provides a self-correcting chained computing method for on-chip quantized vector MAC operations based on DSP. Based on the above-mentioned self-correcting chained computing device for on-chip quantized vector MAC operations based on DSP, the computing method includes the following steps:

[0045] The first weight input data (W0) and the second weight input data (W1) of this level are input into the first-level adder of the DSP48E2 unit of this level for shift addition, the addition result and the activation value data (ACT SHare) of this level are input into the multiplier for multiplication, the multiplication result and the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level generated by the preset correction mechanism are input into the second-level adder, and the calculation result of the DSP48E2 unit of this level is output.

[0046] More specifically, the specific method of using the preset correction mechanism to generate correction data for the upper half calculation result of the upper level is: using the upper level symbol situation and the current level symbol situation to determine in turn whether the upper level DSP48E2 unit generates a +1 error, whether the upper level DSP48E2 unit generates a -1 error, whether there is an error in the upper half calculation of the upper level DSP48E2 unit, and the current level DSP48E2 unit generates correction data for the upper half calculation of the upper level DSP48E2 unit.

[0047] The symbol conditions include:

[0048] The first mark is based on the positive or negative sign of the multiplication result of the lower half of the multiplication stage calculated by each DSP48E2 unit. If the result sign is negative, it is recorded as the first mark; if the result sign is positive, it is recorded as the second mark;

[0049] The second flag is calculated according to the result of the sign of another addend other than the multiplication result in the second half of the addition stage by each DSP48E2 unit. If the result is negative, it is recorded as the first flag; if the result is positive, it is recorded as the second flag.

[0050] In a specific embodiment, by calculating (A×2 18 +B)+c×(a×2 18 + b) = (A × 2 18 +B)+(Y×2 18 + X) = P 1 ×2 18 +P0 Take as an example, and consider the calculation error analysis and correction. That is, consider the error impact of the two parts of the calculation on the calculation result of the upper half. As mentioned above, in the packed multiplication stage, if the multiplication result of the lower half is a negative number, the upper half result will have an error of -1; in the packed addition stage, if the addition of the lower half will produce a carry, the upper half result will have an error of +1.

[0051] Therefore, the error analysis should consider the sign of the multiplication result of the lower half of the multiplication part and the sign of another addend in the lower half of the addition part other than the multiplication result. For the convenience of expression, {last_negative, local_negative} is used to represent the sign; when the sign of the multiplication result of the lower half of the multiplication part calculated at this level is negative, local_negative=1 is marked, otherwise local_negative=0 is marked; when the sign of another addend in the lower half of the addition part of this level other than the multiplication result is negative, last_negative=1 is marked, otherwise last_negative=0 is marked.

[0052] Therefore, at each level, the error of the calculation results of the upper half caused by the calculation of the lower half can be summarized as follows: Table 1 is an analysis of the error of the calculation results of the upper half of each level:

[0053] Table 1

[0054]

[0055]

[0056] According to the above analysis, if it is necessary to know whether a carry-up will occur in the cases of {01} and {10}, resulting in a +1 error, it can be known from the sign of the addition calculation result in the lower half. Therefore, without adding additional calculation units as much as possible, through the self-correcting chain calculation device of the present invention, the calculation result correction of the upper DSP unit will be completed in the lower DSP unit.

[0057] Since the DSP48E2 unit at the first stage does not perform correction in a cascade structure composed of several cascade-connected DSP48E2 units, in the self-correction chain computing device proposed by the present invention, the data input symbol status of the upper-level DSP48E2 unit will be transmitted to the next stage, and the upper-level result will be corrected at the next stage.

[0058] The present invention proposes a correction mechanism for the self-correcting chain computing structure based on DSP for on-chip quantized vector MAC operation. The following Table 2 shows the error analysis of the previous level calculation result under the cascade structure. For the convenience of expression, X is a don't care situation, that is, it has no effect on the generation of the previous level correction input, and the situation marked as (X) is impossible to occur:

[0059] Table 2

[0060]

[0061]

[0062] In Table 2, for a DSP of the first level, it can be observed at its input whether the multiplication result is negative (of course, this multiplication result is also used as an addend in the addition stage) and whether the other addend in the addition stage is negative. Then, for this level, it can be obtained that sign_situation = {a, b} according to these two sign conditions. When the multiplication result of this level is negative, b = 1; when the other addend in the addition stage is negative, a = 1. Therefore, the last_negative mentioned here refers to the sign_situation of the previous level, and the local_negative refers to the sign_situation of this level.

[0063] The following is to calculate PIN+ACT Share×(W 1 ×2 18 +W 0 ) as an example to show the calculation process implemented by the present invention. Among them, PIN is the result of the upper-level package calculation, which is cascaded to the current level for the package MAC operation.

[0064] like Figure 6 As shown in the figure, it is a rough block diagram of a single computing unit. Its working principle is as follows: sign situation indicates the sign situation of the input data; in the first-stage adder, W0 and W1 are shifted and added to realize splicing, and then multiplied with ACT SHARE in the multiplier, and then added with the PIN input from the upper stage in the second-stage adder to realize accumulation. At the same time, the correction input generated by the sign situation also participates in the addition of this stage to realize the calculation correction. Finally, the calculation output of this stage is connected to the next stage through the P and PCOUT ports, and the sign situation of the input data of this stage is passed to the next stage as the sign situation to participate in the generation of the correction input.

[0065] In a specific embodiment, considering the scarcity of computing resources of FPGA devices, in order not to increase computing units other than DSP Slice, the design of the present invention sends the sign of the input data of this level to the next level, and analyzes the actual error generated by the packing calculation of this level in combination with the sign of the calculation result of the lower half of this level at the next level, and generates corresponding correction data, which is input into the ALU unit inside the DSP through the C port of the DSP device to participate in the addition of the upper half, so as to realize the correction of the calculation result of the upper half of the upper DSP48E2 unit. The calculation result of the previous level is cascaded through the PCOUT and PCIN cascade ports to be sent to the ALU unit of the DSP to realize the MAC calculation of PIN+mult.

[0066] In a specific embodiment, the device further includes a final addition correction unit located at the PCOUT port of the last DSP48E2 unit in the cascade structure composed of several cascade-connected DSP48E2 units, and the last DSP48E2 unit is corrected by the final addition correction unit.

[0067] Based on a single computing unit, the present invention expands the computing device into Figure 5 As shown, assuming that the computing device has N levels in total, the computing device can self-correct the calculation results of the first N-1 level computing units without consuming additional computing resources, and only the upper half of the calculation results of the last level DSP48E2 unit remain uncorrected, with a probability of a calculation error of ±1. The present invention only needs to add an additional final addition correction unit to eliminate the error, so as to achieve correction without consuming additional computing resources to the maximum extent.

[0068] In a specific embodiment, in the FPGA computing acceleration scenario, facing the neural network computing load, vector-matrix multiplication operations will appear frequently in the calculation, which can be decomposed into several N-dimensional vector inner product operations. When facing such a computing load, the self-correcting chain computing device for on-chip quantized vector MAC operations with a length of N proposed by the present invention can be implemented, such as Figure 7 , Figure 8As shown, the method also includes: calculating the neural network calculation load by accessing the corresponding weight buffer and activation value buffer; inputting the weight value in the neural network calculation into the weight buffer, and the weight buffer inputs the weight value of each level into the DSP48E2 unit through the first weight data input terminal (A) and the second weight data input port (D) of the DSP48E2 unit at each level and participates in the package calculation; inputting the activation value in the neural network calculation into the activation value buffer, and the activation value buffer inputs the activation value of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation. Assume that the current calculation load is the activation value A of several N-dimensional vectors after calculation and quantization 0 ,A 1 ,A 2 ,…,A i and two columns of N-dimensional vector weights W 0 ,W 1 The inner product of A is convenient for expression. ij With W ij That is, the jth element of the corresponding vector i, and A i W j It means A i With W j The inner product result of X represents the data bubble in the pipeline, and its calculation data flow can be as shown in the following figure. Figure 7 As shown in the figure, each element in the weight and activation value vector is input into the calculation chain in time sequence, and then the vector inner product result of W and A is output at the end of the calculation chain.

[0069] By accessing the corresponding weight buffer area and activation value buffer area, the present invention can use the self-correcting chain computing device for on-chip quantized vector MAC operation based on DSP48E2 proposed by the present invention for processing, and its calculation result will not have errors caused by sign bit overflow in signed number packing calculation, nor will there be error accumulation of conventional chain computing devices.

[0070] Table 3 below is a horizontal comparison with related prior art:

[0071] Table 3

[0072]

[0073]

[0074] From the comparison results, it can be concluded that the self-correcting chain calculation method proposed in the present invention can completely eliminate the calculation error of packed MAC calculation with a very small consumption of hardware resources, while supporting cascading into a chain calculation structure, and further can support packed MAC operations such as vector inner product that are common in neural network calculations, so that the calculation throughput of each DSP is increased by 1.75x to 2x times, greatly improving the calculation efficiency.

[0075] Table 4 below shows the change in resource usage of the self-correcting chain computing device proposed by the present invention as the computing chain grows:

[0076] Table 4

[0077] Calculate chain level LUT Usage FF usage 1 5 3 4 6 7 8 18 7 16 34 7 32 66 7

[0078] It can be concluded from the test results that the growth rate of the hardware resource usage of the self-correcting chain computing device proposed in the present invention is basically linearly related to the growth rate of its computing level, which proves that the self-correcting chain computing device proposed in the present invention has strong scalability and can be expanded to larger computing devices within a relatively low hardware budget.

[0079] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A self-correcting chain computing device for on-chip quantized vector MAC operation based on DSP, characterized in that: include: A plurality of cascade-connected DSP48E2 units, each level of DSP48E2 unit includes a correction data input terminal, a cascade data input terminal, a DSP48E2 module, a cascade data output terminal, a correction generation logic module, a weight data input terminal and an activation value data input terminal; the specific connection relationship is: the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level are respectively input into the cascade data input terminal and the correction data input terminal of the DSP48E2 module of this level, the weight data and activation value data of this level are respectively input into the weight data input terminal and the activation value data input terminal of the DSP48E2 module of this level, and the output of the DSP48E2 module of this level is obtained through the cascade data output terminal to obtain the calculation result of this level; The calculation results of this level, the weight data of this level, and the activation value data of this level are input into the correction generation logic module to obtain the correction data of the upper half of the calculation results of the DSP48E2 unit of this level; the correction data and the calculation results of this level are respectively input into the correction data input terminal and the cascade data input terminal of the lower-level DSP48E2 unit.

2. A DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: The PCIN port of each DSP48E2 unit is cascade-connected to the PCOUT port of the upper DSP48E2 unit for inputting the calculation results of the upper DSP48E2 unit.

3. A DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: Through the C port of the DSP48E2 unit at this level, the correction data of the calculation result of the upper half of the previous level is input into the ALU subunit inside the DSP48E2 unit at this level to participate in the addition stage of the upper half.

4. A DSP-based self-correcting chain computing device for on-chip quantized vector MAC operations according to claim 1, characterized in that: The device also includes: a weight buffer and an activation value buffer; the weight values ​​in the neural network calculation are input into the weight buffer, and the weight buffer inputs the weight values ​​of each level into the DSP48E2 unit through the first weight data input terminal and the second weight data input port of the DSP48E2 unit at each level and participates in the package calculation; the activation values ​​in the neural network calculation are input into the activation value buffer, and the activation value buffer inputs the activation values ​​of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

5. The self-correcting chain computing device for on-chip quantized vector MAC operation based on DSP according to claim 1, characterized in that: The device further comprises: a final correction unit; the final correction unit is connected to the cascade data output terminal of the last stage DSP48E2 unit, and the last stage DSP48E2 unit is corrected by the final correction unit.

6. A DSP-based self-correcting chained computing method for on-chip quantized vector MAC operations, using a DSP-based self-correcting chained computing device for on-chip quantized vector MAC operations as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: The first weight input data and the second weight input data of this level are input into the first-level adder of the DSP48E2 unit of this level for shift addition, the addition result and the activation value data of this level are input into the multiplier for multiplication, the multiplication result and the calculation result of the upper-level DSP48E2 unit and the correction data of the upper half of the calculation result of the upper level generated by the preset correction mechanism are input into the second-level adder, and the calculation result of the DSP48E2 unit of this level is output.

7. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 6, characterized in that: The specific method of using the preset correction mechanism to generate correction data for the upper half calculation result of the upper level is: using the upper symbol situation and the current symbol situation to determine in turn whether the upper DSP48E2 unit generates a +1 error, whether the upper DSP48E2 unit generates a -1 error, whether there is an error in the upper half calculation of the upper DSP48E2 unit, and the current DSP48E2 unit generates correction data for the upper half calculation of the upper DSP48E2 unit.

8. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 7, characterized in that: The symbol conditions include: The first mark is based on the positive or negative sign of the multiplication result of the lower half of the multiplication stage calculated by each DSP48E2 unit. If the result sign is negative, it is recorded as the first mark; if the result sign is positive, it is recorded as the second mark; The second flag is calculated according to the result of the sign of another addend other than the multiplication result in the second half of the addition stage by each DSP48E2 unit. If the result is negative, it is recorded as the first flag; if the result is positive, it is recorded as the second flag.

9. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 6, characterized in that: In a cascade structure composed of several cascade-connected DSP48E2 units, the DSP48E2 unit at the first stage is not corrected.

10. The self-correcting chain calculation method for on-chip quantized vector MAC operation based on DSP according to claim 6, characterized in that: The method also includes: calculating the neural network calculation load by accessing the corresponding weight buffer and activation value buffer; inputting the weight value in the neural network calculation into the weight buffer, and the weight buffer inputs the weight value of each level into the DSP48E2 unit through the first weight data input terminal and the second weight data input port of the DSP48E2 unit at each level and participates in the package calculation; inputting the activation value in the neural network calculation into the activation value buffer, and the activation value buffer inputs the activation value of each level into the DSP48E2 unit through the activation value data input terminal of the DSP48E2 unit at each level and participates in the package calculation.

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