System for setting a bias voltage and method for setting a bias voltage

Abstract

Embodiments of the present disclosure provide a system for setting a bias voltage and a method for setting a bias voltage of a driver integrated circuit (which supplies a voltage to a display panel) by a computing device. The method includes selecting one of a plurality of pre-stored scenes based on a change in a flicker index, and applying a bias voltage to a display panel according to a level based on the selected one scene; and recording the level of the bias voltage corresponding to the minimum value in the fitted quadratic function to the driver integrated circuit. A system for setting a bias voltage according to an embodiment of the present disclosure and a method for setting a bias voltage of a driver integrated circuit (which supplies a voltage to a display panel) by a computing device, the level of the bias voltage, which minimizes a flicker phenomenon by minimizing a change in brightness of the display panel based on the bias voltage, can be calculated by a minimum of measurements.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0136135, filed on October 12, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a system for setting a bias voltage and a method for setting, by a computing device, a bias voltage of a driver integrated circuit that supplies a voltage to a display panel. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has become prominent. Therefore, the use of display devices such as liquid crystal display devices and organic light emitting diode display devices has been increasing.

[0005] Images of various contents can be displayed by a display device. To this end, some display devices can provide a user of the display device with a smooth image transition by displaying images at a high refresh rate, or the display device can reduce power consumption by displaying images at a low refresh rate.

[0006] In some cases, when the display device displays an image at a low refresh rate, a constant voltage may be continuously applied to a transistor disposed in the display panel. Therefore, the hysteresis characteristic of the transistor may change. When the hysteresis characteristic of the transistor changes, the current driving capability of the transistor may change, and therefore, the image may be perceived as flickering by a user of the display device. As described herein, the phenomenon in which an image is perceived as flickering may be referred to as a flicker phenomenon.

[0007] In order to mitigate (or prevent) the flicker phenomenon, some methods may apply a bias voltage to the transistor to mitigate the change in the hysteresis characteristics of the transistor. However, the level of the bias voltage that can minimize the flicker phenomenon may be different for each display panel. It is desirable to measure the change in the brightness of the display panel based on the bias voltage and calculate the appropriate level of the bias voltage by minimizing the number of times the change in the brightness of the display panel is measured. Summary of the invention

[0008] Embodiments of the present disclosure provide a system for setting a bias voltage that can calculate, through minimal measurements, a level of the bias voltage that minimizes a flicker phenomenon by minimizing a change in brightness of a display panel based on the bias voltage.

[0009] An embodiment of the present disclosure provides a method for setting a bias voltage of a driver integrated circuit by a computing device, the driver integrated circuit supplying a voltage to a display panel, the method comprising: applying the bias voltage to the display panel according to a first level; receiving a first flicker index corresponding to the bias voltage according to the first level from the display panel; applying the bias voltage to the display panel according to a second level different from the first level; receiving a second flicker index corresponding to the bias voltage according to the second level; calculating a change in the flicker index based on a change (e.g., increase) in the level of the bias voltage; selecting one of a plurality of pre-stored scenes based on the calculated change in the flicker index, and applying the bias voltage to the display panel according to a third level based on the selected one scene; receiving a third flicker index corresponding to the bias voltage according to the third level; fitting a quadratic function based on the bias voltage according to the first level, the bias voltage according to the second level, and the bias voltage according to the third level, as well as the first flicker index, the second flicker index, and the third flicker index; and recording the level of the bias voltage corresponding to the minimum value in the fitted quadratic function to the driver integrated circuit.

[0010] The fitting of the quadratic function may include: when the third flicker index is a value between the first flicker index and the second flicker index, fitting the quadratic function only based on the bias voltage according to the first level, the bias voltage according to the second level, and the bias voltage according to the third level, as well as the first flicker index, the second flicker index, and the third flicker index.

[0011] The method may further include: when the flicker index increases as the level of the bias voltage increases in calculating the change in the flicker index based on the change (e.g., the increase) in the level of the bias voltage, based on a first scene among the multiple pre-stored scenes, applying the bias voltage according to the third level, which is smaller than the bias voltage according to the first level and the bias voltage according to the second level, to the display panel.

[0012] The method may further include: when the flicker index decreases as the level of the bias voltage increases in the calculation of the change in the flicker index based on the change (e.g., the increase) in the level of the bias voltage, based on a second scene among the multiple pre-stored scenes, applying the bias voltage according to the third level, which is larger than the bias voltage according to the first level and the bias voltage according to the second level, to the display panel.

[0013] The method for setting the bias voltage may also include: when the third flicker index is smaller than the first flicker index and the second flicker index, applying the bias voltage to the display panel according to a fourth level greater than the third level based on a third scene among the multiple pre-stored scenes; and receiving a fourth flicker index corresponding to the bias voltage according to the fourth level.

[0014] The fitting the quadratic function may include further fitting the quadratic function based on the bias voltage according to the fourth level and the fourth flicker index.

[0015] The bias voltage according to the second level may be greater than the bias voltage according to the first level.

[0016] Applying the bias voltage to the display panel according to the first level may include the computing device outputting a bias voltage control signal to the voltage controller. Applying the bias voltage to the display panel according to the first level may include the voltage controller receiving the bias voltage control signal as input.

[0017] The method may include outputting the first flicker index generated based on a change in brightness of the display panel by a brightness meter while the bias voltage according to the first level is applied to the display panel. Receiving the first flicker index may include receiving the first flicker index from the brightness meter by the computing device.

[0018] An embodiment of the present disclosure provides a system for setting a bias voltage, the system comprising: a voltage controller configured to apply the bias voltage based on a bias voltage control signal; a display panel, in which a plurality of sub-pixels are arranged, and the bias voltage is commonly applied to the plurality of sub-pixels, wherein a change in brightness associated with the display panel varies based on a level of the bias voltage applied to the plurality of sub-pixels; a luminance meter configured to capture one or more images of the display panel, and the luminance meter generates a flicker index based on the change in brightness of the display panel, the change in brightness of the display panel being determined based on the one or more images; a driver integrated circuit; and a computing device. The computing device is configured to: store a plurality of scenes in a memory; output the bias voltage control signal; receive the flicker index; calculate a change in the flicker index based on a change (e.g., increase) in the level of the bias voltage; change and output the bias voltage control signal according to one of the plurality of pre-stored scenes based on the calculated change in the flicker index; fit a quadratic function based on the level of the bias voltage and the flicker index corresponding to the level of the bias voltage; and record the level of the bias voltage corresponding to the minimum value in the quadratic function fitted by the computing device to the driver integrated circuit.

[0019] The voltage controller may output the bias voltage according to a first level and output the bias voltage according to a second level based on the bias voltage control signal. The calculation device may receive a first flicker index corresponding to the bias voltage output according to the first level and a second flicker index corresponding to the bias voltage output according to the second level from the brightness meter. The calculation device may calculate the change in the flicker index based on the change (e.g., increase) in the level of the bias voltage based on the bias voltage according to the first level, the bias voltage according to the second level, the first flicker index, and the second flicker index.

[0020] The computing device may select the one of the plurality of pre-stored scenes based on the change in the flicker index, and change and output the bias voltage control signal based on the selected one scene so that the bias voltage is applied to the display panel according to a third level.

[0021] When a third flicker index corresponding to the bias voltage according to the third level is a value between the first flicker index and the second flicker index, the computing device may fit the quadratic function based only on the bias voltage according to the first level, the bias voltage according to the second level, and the bias voltage according to the third level, as well as the first flicker index, the second flicker index, and the third flicker index.

[0022] When the flicker index increases as the level of the bias voltage increases, the computing device may output the bias voltage control signal based on a first scene among the plurality of pre-stored scenes to control the voltage controller to apply the bias voltage to the display panel according to the third level, wherein the bias voltage according to the third level is smaller than the bias voltage according to the first level and the bias voltage according to the second level.

[0023] When the flicker index decreases as the level of the bias voltage increases, the computing device may output the bias voltage control signal based on a second scene among the plurality of pre-stored scenes to control the voltage controller to apply the bias voltage to the display panel according to the third level, wherein the bias voltage of the third level is greater than the bias voltage according to the first level and the bias voltage according to the second level.

[0024] When the third flicker index corresponding to the bias voltage according to the third level is a value smaller than the first flicker index and the second flicker index, the computing device can output the bias voltage control signal based on a third scene among the multiple pre-stored scenes to control the voltage controller to apply the bias voltage according to a fourth level greater than the third level, and the computing device can receive a fourth flicker index corresponding to the bias voltage according to the fourth level.

[0025] The calculation device may further fit the quadratic function based on the bias voltage according to the fourth level and the fourth flicker index.

[0026] At least one of the plurality of sub-pixels may include: a sub-pixel circuit connected to a first power line, a first power voltage being applied to the first power line; and a light-emitting element including an anode electrode connected to the sub-pixel circuit, a cathode electrode connected to a second power line, and a light-emitting structure disposed between the anode electrode and the cathode electrode, a second power voltage being applied to the second power line, and the sub-pixel circuit may include: a first transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first sub-gate line, and the second transistor being configured to switch an electrical connection between the third node and a data line; a third transistor including a gate electrode connected to a second sub-gate line, and the third transistor being configured to switch an electrical connection between the first node and the second node; and a fourth transistor , including a gate electrode connected to a third sub-gate line, and the fourth transistor is configured to switch the electrical connection between the second node and the third power line, and the first initialization voltage is applied to the third power line; a fifth transistor is configured to switch the electrical connection between the third node and the first power line; a sixth transistor is configured to switch the electrical connection between the first node and the anode electrode of the light-emitting element; a seventh transistor includes a gate electrode connected to a fourth sub-gate line, and the seventh transistor is configured to switch the electrical connection between the anode electrode of the light-emitting element and the fourth power line, and the second initialization voltage is applied to the fourth power line; and an eighth transistor includes a gate electrode connected to the fourth sub-gate line, and the eighth transistor is configured to switch the electrical connection between the third node and the fifth power line, and the bias voltage is applied to the fifth power line.

[0027] The first transistor, the second transistor, and the fifth to eighth transistors may be transistors including a P-type semiconductor. The third transistor and the fourth transistor may be transistors including an N-type semiconductor.

[0028] A gate electrode of each of the fifth transistor and the sixth transistor may be connected to one emission control line. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a system block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 Block diagram of an embodiment of a sub-pixel.

[0031] Figure 3 is based on Figure 2An equivalent circuit diagram of an embodiment of a sub-pixel.

[0032] Figure 4 is an example showing a flicker index of a display panel based on a change in the level of a bias voltage.

[0033] Figure 5 is another example showing a flicker index of a display panel based on a change in the level of a bias voltage.

[0034] Figure 6 is a system block diagram of a system for setting a bias voltage according to an embodiment of the present disclosure.

[0035] Figure 7 An embodiment is shown in which a bias voltage according to a third level is applied when a first scene is selected in the system for setting a bias voltage.

[0036] Figure 8 An embodiment is shown in which a bias voltage according to a third level is applied when a second scenario is selected in the system for setting a bias voltage.

[0037] Fig. 9 An embodiment is shown in which a bias voltage according to a third level and a bias voltage according to a fourth level are applied when a third scenario is selected in the system for setting a bias voltage.

[0038] Fig.10 is a flow chart of a method for setting a bias voltage according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0040] In order to clearly illustrate the present disclosure, parts not related to the description are omitted, and the same or similar constituent elements are given the same reference numerals throughout the specification. Therefore, the above reference numerals may be used in other drawings.

[0041] In addition, since the size and thickness of each configuration shown in the drawings are arbitrarily shown for better understanding and ease of description, the present disclosure is not necessarily limited to the size and thickness of each configuration shown. In the drawings, the sizes of layers and regions are exaggerated for clarity of illustration.

[0042] In addition, the expression "same" in the specification may mean "substantially the same". That is, the expression "same" may be the same (identical) degree to which a person of ordinary skill can be convinced that it is the same. Other expressions may be expressions in which "substantially" is omitted. The term "substantially" as used herein means approximately or actually. The term "substantially the same" as used herein means (e.g., within a threshold difference) approximately the same or actually the same.

[0043] The terms "first" and "second" etc. may be used only to describe various constituent elements, but those meanings may not be limited to the restricted meanings. The above terms are used only to distinguish one constituent element from other constituent elements. For example, within the scope of the appended claims, the first constituent element may be referred to as the second constituent element, and similarly, the second constituent element may be referred to as the first constituent element. When the singular is described, the singular may be interpreted as the plural meaning unless explicitly described to the contrary.

[0044] Terms such as "below", "beneath", "on", and "over" are used to describe the relationship of elements shown in the drawings. These terms are relative concepts and are made based on the directions shown in the drawings.

[0045] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formalized meaning.

[0046] The terms “comprising” or “having” are used to illustrate the existence of a feature, number (quantity), process, operation, constituent element, component or a combination thereof, and it will be understood that the possibility of the existence or addition of one or more other features or numbers (quantity), processes, operations, constituent elements, components or a combination thereof is not precluded.

[0047] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Figure 1 is a system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0049] Reference Figure 1 , a display device 100 according to an embodiment of the present disclosure includes a display panel 110 , a gate driving circuit 120 , a data driver 130 , a voltage generator 140 , a controller 150 , and a temperature sensor 160 .

[0050] The display panel 110 (e.g., the display panel 110 including a substrate SUB and elements disposed on the substrate SUB) may include a plurality of sub-pixels SP. First to m-th gate lines GL1 to GLm (m is an integer of 2 or more) connected to the plurality of sub-pixels SP may be disposed in the display panel 110. First to n-th data lines DL1 to DLn (n is an integer of 2 or more) connected to the plurality of sub-pixels SP may be disposed in the display panel 110.

[0051] The plurality of subpixels SP may be connected (eg, electrically connected) to the gate driving circuit 120 through first to m-th gate lines GL1 to GLm. The plurality of subpixels SP may be connected (eg, electrically connected) to the data driver 130 through first to n-th data lines DL1 to DLn.

[0052] Each of the plurality of sub-pixels SP may include at least one light emitting element configured to generate light. Each of the plurality of sub-pixels SP may generate light of a color (e.g., a specific color or a specific wavelength band) such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels SP among the plurality of sub-pixels SP may constitute one pixel PXL. For example, Figure 1 As shown in FIG. 4 , three sub-pixels SP may constitute one pixel PXL.

[0053] The gate driving circuit 120 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged in a first direction DR1 as a whole) through the first gate line GL1 to the m-th gate line GLm. For example, the first direction DR1 may be a direction crossing from one side (e.g., the left side) of the display panel 110 to the other side (e.g., the right side) of the display panel 110. For example, the first direction DR1 may be a row direction.

[0054] The gate driving circuit 120 may output a gate signal (e.g., a gate signal at an on level or an off level) to the first gate line GL1 to the mth gate line GLm in response to the gate control signal GCS. According to one or more embodiments of the present disclosure, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and / or one or more other signals supporting features of the display device 100.

[0055] According to one or more embodiments of the present disclosure, first to m-th emission control lines EL1 to ELm connected to a plurality of sub-pixels SP may be further provided in the display panel 110. The first to m-th emission control lines EL1 to ELm may be provided so that the first to m-th emission control lines EL1 to ELm extend in a row direction in the display panel 110. A plurality of sub-pixels SP may be connected (e.g., electrically connected) to the first to m-th emission control lines EL1 to ELm. In the embodiments described herein, the gate drive circuit 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm. The emission control driver may operate under the control of the controller 150.

[0056] The gate drive circuit 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate drive circuit 120 may be divided into two or more drive circuits that are physically and / or logically separated, and such a drive circuit may be disposed on one side and the other side of the display panel 110 (e.g., the opposite side of the display panel 110 facing the one side). In this way, the gate drive circuit 120 may be disposed in or around the display panel 110 in various forms according to the embodiment.

[0057] The data driver 130 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged in a second direction DR2 as a whole) through the first to n-th data lines DL1 to DLn. For example, the second direction DR2 may be a direction crossing from one side (e.g., the lower side) of the display panel 110 to the other side (e.g., the upper side) of the display panel 110. For example, the second direction DR2 may be a column direction.

[0058] The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. According to one or more embodiments of the present disclosure, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, or one or more other signals supporting aspects of the present disclosure.

[0059] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data line DL1 to the nth data line DLn using a voltage (e.g., a gamma voltage Vgamma) from the voltage generator 140. In an example in which a gate signal (e.g., a gate signal at an on level) is applied to each of the first gate line GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA is applied to the data lines DL1 to DLn. Each of the plurality of sub-pixels SP may receive a data signal applied at a corresponding timing in response to the gate signal (e.g., a gate signal at an on level). The plurality of sub-pixels SP may generate light of a brightness corresponding to the input data signal. Thus, an image may be displayed in the display panel 110.

[0060] According to one or more embodiments of the present disclosure, each of the gate driving circuit 120 and the data driver 130 may include a complementary metal oxide semiconductor (CMOS) circuit element.

[0061] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from outside the display device 100. The voltage generator 140 may adjust (e.g., reduce) the level of the received voltage and manage the voltage after the level adjustment. The voltage generator 140 may be configured to generate a plurality of voltages.

[0062] For example, the voltage generator 140 may generate a first power voltage VDD, a second power voltage VSS, a gamma voltage Vgamma, a bias voltage VBIAS, or other voltages supporting aspects of the present disclosure. The generated first power voltage VDD, the second power voltage VSS, and the bias voltage VBIAS may be applied (e.g., commonly applied) to a plurality of sub-pixels SP. The first power voltage VDD may have a relatively high voltage level. The second power voltage VSS may have a lower voltage level than the first power voltage VDD. The bias voltage VBIAS may be set to an appropriate level to support the mitigation of the characteristic change of the switching element (e.g., transistor) included in the sub-pixel SP. The generated gamma voltage Vgamma may be provided to the data driver 130. In other embodiments, at least one of the first power voltage VDD, the second power voltage VSS, and the bias voltage VBIAS may be provided by an external device (e.g., a power management integrated circuit (PMIC)) of the display device 100.

[0063] According to an embodiment, the voltage generator 140 may generate other voltages. For example, the voltage generator 140 may generate initialization voltages (e.g., first initialization voltages and second initialization voltages, etc.) applied (e.g., commonly applied) to the plurality of sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of transistors and / or light emitting elements (multiple light emitting elements) of the plurality of sub-pixels SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate the predetermined reference voltage.

[0064] The controller 150 may be configured to control various operations of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling display of an image corresponding to the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the received control signal CTRL.

[0065] The controller 150 may convert the input image data IMG to match the display device 100 or the display panel 110 and output the image data DATA. According to one or more embodiments of the present disclosure, the controller 150 may output the image data DATA by aligning the input image data IMG to match the sub-pixels SP in a row unit.

[0066] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on (or in) one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separated components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be installed in the driver integrated circuit DIC, and another one of the data driver 130, the voltage generator 140, and the controller 150 may be provided while being installed in an integrated circuit other than the driver integrated circuit DIC.

[0067] The temperature sensor 160 may be configured to sense a temperature (e.g., a temperature of the periphery of the temperature sensor 160) and generate temperature data TEP representing the sensed temperature. According to an embodiment, the temperature sensor 160 may be disposed in the display panel 110. According to an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC. According to an embodiment, the display device 100 may include two or more temperature sensors 160.

[0068] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. According to one or more embodiments of the present disclosure, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140, for example, to adjust at least one of the data signal input to the display panel 110, the first power voltage VDD, and the second power voltage VSS.

[0069] Figure 2 It is shown Figure 1 Block diagram of an embodiment of a sub-pixel SPij.

[0070] exist Figure 2 As an example, it is shown Figure 1 The sub-pixel SPij arranged in the i-th (i is an integer greater than or equal to 1 and less than or equal to m) row and the j-th (j is an integer greater than or equal to 1 and less than or equal to n) column among the plurality of sub-pixels SP shown in .

[0071] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0072] The light emitting element LD may be connected (eg, electrically connected) between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN may be Figure 1 The first power voltage VDD is applied to the node. The second power voltage node VSSN may be Figure 1 The second power voltage VSS is applied to the node.

[0073] The light emitting element LD may include a first electrode, a light emitting structure EMS, and a second electrode. The first electrode may be one of the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD. The second electrode may be the other of the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD. For ease of description, it will be described below as an example that the first electrode of the light emitting element LD is the anode electrode AE, and the second electrode of the light emitting element LD is the cathode electrode CE.

[0074] The anode electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected (e.g., electrically connected) to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0075] The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The j-th data line DLj among the first to n-th data lines DL1 to DLn. The sub-pixel circuit SPC may be configured to control emission timing and / or emission brightness of the light emitting element LD based on (or in response to) a signal received through a signal line described herein.

[0076] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi.

[0077] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage of the data signal (or a voltage corresponding to the data signal) in response to a gate signal (e.g., a gate signal at a conduction level) received through the i-th gate line GLi. The sub-pixel circuit SPC may adjust the timing of the current flowing in the light-emitting element LD in response to an emission control signal (e.g., an emission control signal at a conduction level) applied through the i-th emission control line ELi. The magnitude of the current flowing through the light-emitting element LD may vary based on the voltage stored in the sub-pixel circuit SPC. The light-emitting element LD may generate light having a brightness corresponding to the data signal.

[0078] Figure 3 is based on Figure 2 Equivalent circuit diagram of an embodiment of a sub-pixel SPij.

[0079] According to the embodiment of the present disclosure, the sub-pixel circuit SPC (see Figure 3 ) may include two or more switching elements (e.g., transistors) and one or more storage elements (e.g., capacitors). For example, the sub-pixel circuit SPC according to an embodiment of the present disclosure may include eight transistors and one capacitor. However, the embodiments of the present disclosure are not limited thereto. Below, for ease of description, an embodiment of the present disclosure will be described with reference to an example embodiment including eight transistors and one capacitor as an example.

[0080] Reference Figure 3, the sub-pixel circuit SPC according to an embodiment of the present disclosure may include first to eighth transistors TR1 to TR8 and a storage capacitor Cst.

[0081] The first transistor TR1 may include a first electrode connected (e.g., electrically connected) to the first node N1, a gate electrode connected (e.g., electrically connected) to the second node N2, and a second electrode connected (e.g., electrically connected) to the third node N3. The first electrode may be one of the source electrode and the drain electrode (e.g., the drain electrode). The second electrode may be the other of the source electrode and the drain electrode (e.g., the source electrode). The first transistor TR1 may be configured to supply a current (e.g., a drive current) corresponding to the magnitude of the voltage applied to the second node N2 (or the gate electrode).

[0082] The second transistor TR2 may be configured to switch the electrical connection between the third node N3 and the j-th data line DLj. The second transistor TR2 may include a gate electrode connected (e.g., electrically connected) to the i-th first sub-gate line SGL1i (hereinafter, also referred to as the first sub-gate line SGL1i) to which the first gate signal GW[i] is applied. The second transistor TR2 may electrically connect the j-th data line DLj and the third node N3 in response to the first gate signal GW[i] at a turn-on level and transmit a voltage Vdata corresponding to the data signal to the third node N3.

[0083] The third transistor TR3 may be configured to switch the electrical connection between the first node N1 and the second node N2 (e.g., electrically connect or disconnect the first node N1 and the second node N2). The third transistor TR3 may include a gate electrode connected (e.g., electrically connected) to the i-th second sub-gate line SGL2i (hereinafter, also referred to as the second sub-gate line SGL2i) to which the second gate signal GC[i] is applied. The third transistor TR3 may electrically connect the first node N1 and the second node N2 in response to the second gate signal GC[i] at the on level. When the third transistor TR3 is turned on, the first transistor TR1 may be connected in a diode form.

[0084] The fourth transistor TR4 may be configured to switch the electrical connection between the second node N2 and the third power line PL3 to which the first initialization voltage VINT is applied (e.g., electrically connect or electrically disconnect the second node N2 from the third power line PL3 to which the first initialization voltage VINT is applied). The fourth transistor TR4 may include a gate electrode connected (e.g., electrically connected) to the i-th third sub-gate line SGL3i (hereinafter, also referred to as the third sub-gate line SGL3i) to which the third gate signal GI[i] is applied. The fourth transistor TR4 may electrically connect the second node N2 and the third power line PL3 in response to the third gate signal GI[i] being at a turn-on level.

[0085] The fifth transistor TR5 may be configured to switch the electrical connection between the third node N3 and the first power line PL1 to which the first power voltage VDD is applied (e.g., electrically connect or disconnect the third node N3 to the first power line PL1 to which the first power voltage VDD is applied). The fifth transistor TR5 may include a gate electrode connected (e.g., electrically connected) to the i-th emission control line ELi (hereinafter, also referred to as the emission control line ELi) to which the emission control signal EM[i] is applied. The fifth transistor TR5 may electrically connect the first power line PL1 and the third node N3 in response to the emission control signal EM[i] being at the on level.

[0086] The sixth transistor TR6 may be configured to switch the electrical connection between the first node N1 and the fourth node N4 (e.g., electrically connect or disconnect the first node N1 and the fourth node N4). The sixth transistor TR6 may include a gate electrode connected (e.g., electrically connected) to the emission control line ELi. The sixth transistor TR6 may electrically connect the first node N1 and the fourth node N4 in response to the emission control signal EM[i] at the on level.

[0087] The seventh transistor TR7 may be configured to switch the electrical connection between the fourth node N4 and the fourth power line PL4 to which the second initialization voltage VAINT is applied (e.g., electrically connect or electrically disconnect the fourth node N4 from the fourth power line PL4 to which the second initialization voltage VAINT is applied). The seventh transistor TR7 may include a gate electrode connected (e.g., electrically connected) to the i-th fourth sub-gate line SGL4i (hereinafter, also referred to as the fourth sub-gate line SGL4i) to which the fourth gate signal GB[i] is applied. The seventh transistor TR7 may electrically connect the fourth node N4 and the fourth power line PL4 in response to the fourth gate signal GB[i] being at a conduction level. The anode of the light emitting element LD may be connected (e.g., electrically connected) to the fourth node N4, and the cathode of the light emitting element LD may be connected (e.g., electrically connected) to the second power line PL2 to which the second power voltage VSS is applied.

[0088] The eighth transistor TR8 may be configured to switch the electrical connection between the third node N3 and the fifth power line PL5 to which the bias voltage VBIAS is applied (e.g., electrically connect or electrically disconnect the third node N3 and the fifth power line PL5 to which the bias voltage VBIAS is applied). The eighth transistor TR8 may include a gate electrode connected (e.g., electrically connected) to the fourth sub-gate line SGL4i. The eighth transistor TR8 may electrically connect the third node N3 and the fifth power line PL5 in response to the fourth gate signal GB[i] at the on level.

[0089] Reference Figure 3 , shows an embodiment in which the gate electrode of the fifth transistor TR5 and the gate electrode of the sixth transistor TR6 are connected to the same emission control line ELi. However, the embodiments of the present disclosure are not limited thereto, and the gate electrode of the fifth transistor TR5 and the gate electrode of the sixth transistor TR6 may be connected to different corresponding emission control lines.

[0090] Reference Figure 3 , shows an embodiment in which the gate electrode of the seventh transistor TR7 and the gate electrode of the eighth transistor TR8 are connected to the same fourth sub-gate line SGL4i. However, the embodiments of the present disclosure are not limited thereto, and the gate electrode of the seventh transistor TR7 and the gate electrode of the eighth transistor TR8 may be connected to different corresponding sub-gate lines. In an embodiment, the i-th gate line GLi may include a first sub-gate line SGL1i, a second sub-gate line SGL2i, a third sub-gate line SGL3i, and a fourth sub-gate line SGL4i.

[0091] Reference Figure 3 Each of the first to eighth transistors TR1 to TR8 may include a semiconductor layer. The semiconductor layer may include a channel region overlapping the gate electrode, a source region disposed on one side of the channel region, and a drain region disposed on the other side of the channel region.

[0092] Reference Figure 3 , the third transistor TR3 and the fourth transistor TR4 may include an N-type semiconductor layer. The first transistor TR1, the second transistor TR2, and the fifth transistor TR5 to the eighth transistor TR8 may include a P-type semiconductor layer. However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the third transistor TR3 and the fourth transistor TR4 may include a P-type semiconductor layer. In another example, at least one of the first transistor TR1, the second transistor TR2, and the fifth transistor TR5 to the eighth transistor TR8 may include an N-type semiconductor layer.

[0093] The third transistor TR3 and the fourth transistor TR4 may include an oxide semiconductor. The first transistor TR1, the second transistor TR2, and the fifth to eighth transistors TR5 to TR8 may include a silicon semiconductor (eg, a low temperature polysilicon (LTPS) semiconductor).

[0094] In an embodiment where the third transistor TR3 and the fourth transistor TR4 include an oxide semiconductor, the third transistor TR3 and the fourth transistor TR4 may be advantageous in reducing leakage current. Therefore, the voltage of the second node N2 may be maintained for a relatively long time (e.g., greater than a threshold time duration) to allow an image to be displayed at various refresh rates (e.g., a low refresh rate).

[0095] In some cases, when the image is continuously displayed at a low refresh rate, the high potential first power voltage VDD may be continuously applied to the source electrode of the first transistor TR1, thereby changing the current driving capability of the first transistor TR1. In some cases, the current driving capability of the first transistor TR1 may fluctuate. The change in the current driving capability of the first transistor TR1 may be perceived by the user as a change in brightness (or flicker phenomenon). The degree to which the flicker phenomenon is perceived by the user can be measured, for example, by a flicker index used in the prior art.

[0096] The bias voltage VBIAS may be applied to the source electrode of the first transistor TR1 to improve a change in current driving capability (or a change in hysteresis characteristics) of the first transistor TR1 .

[0097] However, the level of the bias voltage VBIAS for mitigating the change in the current driving capability of the first transistor TR1 (eg, the level of the optimal bias voltage VBIAS) may be based on the display panel 110 (see Figure 1 ) is changed. Therefore, it is necessary to change based on the display panel 110 (see Figure 1 ) adaptively sets the level of the bias voltage VBIAS.

[0098] Figure 4 is an example showing a flicker index of a display panel based on a change in the level of a bias voltage VBIAS.

[0099] Reference Figure 4 , the level of the bias voltage VBIAS is shown with respect to the x-axis, and the flicker index is shown with respect to the y-axis.

[0100] The Illuminating Engineering Society (IES), which corresponds to the industry, defines flicker index as a measure of a cyclic variable that takes into account the shape of a waveform. In this specification, flicker index is interpreted as a value measured according to the way flicker index is defined in IES. Flicker index can have a value between 0 and 1.

[0101] Embodiments of the present disclosure include applying a bias voltage VBIAS according to a selected level (voltage level) that results in a target flicker index (e.g., a minimum flicker index among flicker indices corresponding to candidate levels for the bias voltage VBIAS). According to experiments, it is known that the relationship between the bias voltage VBIAS and the flicker index is similar to a quadratic function. Therefore, for example, embodiments of the present disclosure support selecting the x value at the vertex 410 of the calculated quadratic function as the level of the bias voltage VBIAS. Therefore, embodiments of the present disclosure described herein support effective selection of a bias voltage VBIAS that results in a level of the minimum flicker index.

[0102] According to one or more embodiments of the present disclosure, a quadratic function y=f1(x) representing the relationship between the bias voltage VBIAS and the flicker index may be defined as y=ax^2+bx+c. In some aspects, the techniques described herein apply principles for determining unknowns (e.g., a, b, and c) for a case in which the coordinates of three points through which the quadratic function passes are known.

[0103] Reference Figure 4 , a first point (x1, y1), a second point (x2, y2), and a third point (x3, y3) are shown as three points through which the quadratic function passes. Each of x1, x2, and x3 may correspond to a level of the bias voltage VBIAS. Each of y1, y2, and y3 may correspond to a flicker index measured at a corresponding level of the bias voltage VBIAS.

[0104] The three points may be set within a measurement range MR (or a predetermined measurement range MR) of the bias voltage VBIAS. For example, the measurement range MR may be between the bias voltage VBIAS of the first reference level (t1) and the bias voltage VBIAS of the second reference level (t2). Figure 4 , the bias voltage (x1) according to the first level (e.g., at the first level) may be greater than the first reference level (t1), and the bias voltage (x3) according to the third level (e.g., at the third level) may be less than the second reference level (t2).

[0105] At this time, it is preferred that the vertex 410 is set between the three measurement points. For example, the technology described herein may include identifying a vertex (e.g., vertex 410) between the three measurement points. In the example, in the relationship between the first point (x1, y1) and the second point (x2, y2), as the voltage level of the bias voltage VBIAS increases, the flicker index decreases. And, in the relationship between the second point (x2, y2) and the third point (x3, y3), as the voltage level of the bias voltage VBIAS increases, the flicker index also increases. In the above relationship, the vertex 410 of the quadratic function can be set between the first point (x1, y1) and the third point (x3, y3). In the embodiments described herein, the position of the vertex 410 where the flicker index is minimized can be more clearly estimated.

[0106] Figure 5 is another example showing a flicker index of a display panel based on a change in the level of the bias voltage VBIAS.

[0107] Reference Figure 5 , a quadratic function y=f2(x) can be defined to represent the relationship between the bias voltage VBIAS and the flicker index. Figure 5 , a first point (x1, y1), a second point (x2, y2), and a third point (x3, y3) are shown as three points through which the quadratic function passes. Each of x1, x2, and x3 corresponds to a level of the bias voltage VBIAS. Each of y1, y2, and y3 corresponds to a flicker index measured at a corresponding level of the bias voltage VBIAS.

[0108] The three points may be set within a measurement range MR (or a predetermined measurement range MR) of the bias voltage VBIAS. For example, the measurement range MR may be between the bias voltage VBIAS of the first reference level (t1) and the bias voltage VBIAS of the second reference level (t2). Figure 5 , the bias voltage (x1) according to the first level may be greater than the first reference level (t1), and the bias voltage (x3) according to the third level may be less than the second reference level (t2).

[0109] Reference Figure 5, in some cases, the vertex of the quadratic function may not be set between the three measurement points. For example, in the relationship between the first point (x1, y1) and the second point (x2, y2), as the voltage level of the bias voltage VBIAS increases, the flicker index increases. And, in the relationship between the second point (x2, y2) and the third point (x3, y3), as the voltage level of the bias voltage VBIAS increases, the flicker index increases. In the above relationship, the vertex of the quadratic function may not be set between the first point (x1, y1) and the third point (x3, y3). In the example embodiments described herein, when y=f2(x) is calculated using three measurement points and in the absence of other measurement points (for example, only three measurement points are used), the error in the position of the vertex may be greater than Figure 4 Examples in .

[0110] Aspects of the disclosure described herein support methods of calculating a bias voltage VBIAS according to a level that results in a minimum flicker index through a minimum number of measurements (eg, measurements below a threshold value).

[0111] Figure 6 is used to set the bias voltage VBIAS (see Figure 1 ) is a system block diagram of system 600.

[0112] Reference Figure 6 The system 600 for setting the bias voltage VBIAS according to an embodiment of the present disclosure may include a display panel 110 , a voltage controller 610 , a luminance meter 620 , a computing device 630 , a driver integrated circuit DIC, and other suitable components that support features of the system 600 .

[0113] System 600 may support applying bias voltage VBIAS to display panel 110. A change in brightness of display panel 110 may change based on a level (voltage level) of applied bias voltage VBIAS. A change in brightness of display panel 110 may be measured as a flicker index FI.

[0114] The voltage controller 610 may output the bias voltage VBIAS at a level corresponding to the bias voltage control signal BCS in response to the bias voltage control signal BCS.

[0115] The luminance meter 620 may capture one or more images of the display panel 110 and detect a change in brightness of the display panel 110 based on the one or more images. The luminance meter 620 may generate a flicker index FI based on the detected change in brightness of the display panel 110.

[0116] The calculation device 630 may output a bias voltage control signal BCS. The calculation device 630 may receive a flicker index FI corresponding to the bias voltage VBIAS. The calculation device 630 may calculate a change in the flicker index FI based on a change (eg, increase) in the level of the bias voltage VBIAS.

[0117] The calculation device 630 may select one of a plurality of pre-stored scenes based on (e.g., in response to) a change in the calculated flicker index FI. The calculation device 630 may output a bias voltage control signal BCS associated with changing the level of the bias voltage VBIAS to the voltage controller 610 based on the selected scene. The calculation device 630 may receive the flicker index FI corresponding to the changed level of the bias voltage VBIAS.

[0118] The calculation device 630 may calculate a quadratic function corresponding to the relationship between the bias voltage VBIAS and the flicker index FI based on the bias voltage VBIAS and the flicker index FI.

[0119] The calculation device 630 may record the bias voltage VBIAS at which the flicker index FI becomes minimum in the calculated quadratic function to the driver integrated circuit DIC.

[0120] The computing device 630 may include a processor configured to perform the operations described herein. The computing device 630 may include a memory (e.g., a buffer memory) for storing values ​​calculated based on the operations of the processor. The computing device 630 may also include a memory (e.g., a non-volatile memory) in which a plurality of scenarios are pre-stored.

[0121] The computing device 630 may further include a communicator (eg, a communication circuit) (not shown) for communicating with the voltage controller 610 and / or the brightness meter 620. For example, the communicator may communicate with the voltage controller 610 and / or the brightness meter 620 via a wired communication interface or a wireless communication interface.

[0122] The driving method of the system 600 for setting a bias voltage according to one or more embodiments of the present disclosure is briefly described as follows.

[0123] When applying the voltage ( S640 ), the voltage controller 610 may apply the bias voltage VBIAS corresponding to the bias voltage control signal BCS.

[0124] When generating the flicker index FI (S650), the luminance meter 620 can capture one or more images of the display panel 110 on the stage STG, determine the change in brightness of the display panel 110 based on the one or more images, and generate the flicker index FI based on the change in brightness of the display panel 110.

[0125] When changing the bias voltage control signal BCS (S660), the computing device 630 may select one of the pre-stored scenes based on the change of the flicker index FI based on the increase of the bias voltage VBIAS. The computing device 630 may change and output the bias voltage control signal BCS so that the bias voltage VBIAS changes based on the selected scene. For example, the computing device 630 may change and output the bias voltage control signal BCS based on the selected scene, and the bias voltage VBIAS output by the voltage controller 610 may change based on the bias voltage control signal BCS.

[0126] When recording the bias voltage (S670), the calculation device 630 may calculate a quadratic function corresponding to the relationship between the bias voltage VBIAS and the input flicker index FI based on the bias voltage VBIAS and the input flicker index FI. The calculation device 630 may calculate the bias voltage VBIAS at which the flicker index FI is minimized (e.g., the bias voltage VBIAS at which the calculated flicker index FI is less than or equal to a threshold value), and the calculation device 630 may record the value of the calculated bias voltage VBIAS to the driver integrated circuit DIC.

[0127] Figure 7 1 shows a system for setting a bias voltage (eg, system 600 (see Figure 6 )) in which a bias voltage VBIAS of a third level is applied when the first scene is selected.

[0128] Reference Figure 7 , shows the first scene (scene 1) among the multiple scenes. The first scene may correspond to a situation where the flicker index increases as the level of the bias voltage VBIAS increases. Figure 7 , referring to the first point (x1, y1) and the second point (x2, y2), the flicker index may increase as the bias voltage VBIAS increases. x1 may correspond to the bias voltage VBIAS according to the first level, and x2 may correspond to the bias voltage VBIAS according to (e.g., at) the second level.

[0129] In the first scenario, the bias voltage VBIAS according to the third level may be set within a range smaller than the bias voltage VBIAS according to the first level. The flicker index corresponding to the bias voltage VBIAS according to the third level may be a third flicker index (y3). The third flicker index (y3) may be a value between the first flicker index (y1) and the second flicker index (y2).

[0130] Therefore, the vertex of the quadratic function can be set between the third point (x3, y3) and the second point (x2, y2). Figure 7In the example of , the vertex is set at the first point (x1, y1). Therefore, the bias voltage VBIAS according to the level that minimizes the flicker index (for example, the bias voltage VBIAS corresponding to x1) can be accurately calculated.

[0131] Figure 8 An embodiment is shown in which the bias voltage VBIAS according to the third level is applied when the second scenario is selected in the system for setting the bias voltage VBIAS.

[0132] Reference Figure 8 , shows a second scenario (scenario 2) among the multiple scenarios. The second scenario may correspond to a situation where the flicker index decreases as the level of the bias voltage VBIAS increases. Figure 8 , referring to the first point (x1, y1) and the second point (x2, y2), the flicker index may decrease as the bias voltage VBIAS increases. x1 may correspond to the bias voltage VBIAS according to the first level, and x2 may correspond to the bias voltage VBIAS according to the second level.

[0133] In the second scenario, the bias voltage VBIAS according to the third level may be set within a range greater than the bias voltage VBIAS according to the second level. The flicker index corresponding to the bias voltage VBIAS according to the third level may be a third flicker index (y3). The third flicker index (y3) may be a value between the first flicker index (y1) and the second flicker index (y2).

[0134] Therefore, the vertex of the quadratic function may be set between the first point (x1, y1) and the third point (x3, y3). Therefore, the bias voltage VBIAS at a level that minimizes the flicker index (eg, the bias voltage VBIAS corresponding to x2) may be accurately calculated.

[0135] Fig. 9 An embodiment is shown in which the bias voltage VBIAS according to the third level and the bias voltage VBIAS according to the fourth level are applied when the third scenario is selected in the system for setting the bias voltage VBIAS.

[0136] Reference Fig. 9 , shows a third scenario (scenario 3) among the multiple scenarios. The third scenario may correspond to a situation where the flicker index decreases as the level of the bias voltage VBIAS increases. Fig. 9 , referring to the first point (x1, y1) and the second point (x2, y2), the flicker index may decrease as the bias voltage VBIAS increases. x1 may correspond to the bias voltage VBIAS according to the first level, and x2 may correspond to the bias voltage VBIAS according to the second level.

[0137] In the third scenario, the bias voltage VBIAS according to the third level may be set within a range greater than the bias voltage VBIAS according to the second level. The flicker index corresponding to the bias voltage VBIAS according to the third level may be a third flicker index (y3). The third flicker index (y3) may be less than the second flicker index (y2).

[0138] In the above case, the third point (x3, y3) may not be between the first point (x1, y1) and the second point (x2, y2). The third point (x3, y3) may be outside the first point (x1, y1) and the second point (x2, y2).

[0139] In the third scenario, the bias voltage VBIAS according to the fourth level may be set within a range greater than the bias voltage VBIAS according to the third level. The flicker index corresponding to the bias voltage VBIAS according to the fourth level may be a fourth flicker index (y4). The fourth flicker index (y4) may be greater than the third flicker index (y3).

[0140] Therefore, the vertex of the quadratic function may be set between the first point (x1, y1) and the fourth point (x4, y4). Therefore, the bias voltage VBIAS at a level that minimizes the flicker index (eg, the bias voltage VBIAS corresponding to x3) may be accurately calculated.

[0141] Fig.10 is a flow chart of a method 1000 for setting a bias voltage according to an embodiment of the present disclosure.

[0142] Reference Fig.10 According to an embodiment of the present disclosure, the method 1000 for setting the bias voltage includes: applying a bias voltage of a first level (S1010); measuring a first flicker index corresponding to the bias voltage applied according to the first level (S1020); applying a bias voltage according to a second level (S1030); measuring a second flicker index corresponding to the bias voltage applied according to the second level (S1040); calculating a change in the flicker index based on a change (e.g., increase) in the level of the bias voltage (S1050); and calculating a change in the flicker index based on a field corresponding to the calculated change. A bias voltage is applied according to a third level (S1060); a third flicker index corresponding to the bias voltage applied according to the third level is measured (S1070); a quadratic function is fitted based on the bias voltage at the first level, the bias voltage at the second level, and the bias voltage at the third level, as well as the first flicker index, the second flicker index, and the third flicker index (S1080); and a level of the bias voltage corresponding to the minimum value (e.g., the lowest flicker index) in the fitted quadratic function is recorded to the driver integrated circuit (S1090).

[0143] Further references Figure 7 In the method 1000 for setting the bias voltage according to an embodiment of the present disclosure, fitting the quadratic function (S1080) includes: if the third flicker index (y3) is a value between the first flicker index (y1) and the second flicker index (y2), fitting the quadratic function only based on the bias voltage (x1) at the first level, the bias voltage (x2) at the second level, and the bias voltage (x3) at the third level, and the first flicker index (y1), the second flicker index (y2), and the third flicker index (y3). For example, based on determining that the third flicker index (y3) is between the first flicker index (y1) and the second flicker index (y2), the method 1000 for setting the bias voltage may include: fitting the quadratic function based on (for example, only based on) the bias voltage (x1) applied according to the first level, the bias voltage (x2) applied according to the second level, and the bias voltage (x3) applied according to the third level, and the first flicker index (y1), the second flicker index (y2), and the third flicker index (y3).

[0144] Further references Figure 7 , the method 1000 for setting the bias voltage according to an embodiment of the present disclosure may include: if the flicker index increases as the level of the bias voltage increases when calculating the change of the flicker index based on the change (e.g., increase) of the level of the bias voltage (S1050), then based on a first scene among a plurality of pre-stored scenes, applying a bias voltage (x3) according to a third level that is smaller than the bias voltage (x1) applied according to the first level and the bias voltage (x2) applied according to the second level to the display panel 110 (see Figure 1 ). For example, based on determining that the flicker index increases as the bias voltage increases, the method 1000 for setting the bias voltage may include applying a bias voltage according to a third level based on a first scene among a plurality of pre-stored scenes (x3).

[0145] Further references Figure 8 and Fig. 9 , the method 1000 for setting the bias voltage according to an embodiment of the present disclosure may include: if the flicker index decreases as the level of the bias voltage increases when calculating the change of the flicker index based on the change (e.g., increase) of the level of the bias voltage (S1050), then based on a second scene among a plurality of pre-stored scenes, applying a bias voltage (x3) according to a third level greater than the bias voltage (x1) applied according to the first level and the bias voltage (x2) applied according to the second level to the display panel 110 (see Figure 1 ). For example, based on determining that the flicker index decreases as the bias voltage increases, the method 1000 for setting the bias voltage may include applying a bias voltage according to a third level based on a second scene among a plurality of pre-stored scenes (x3).

[0146] Further references Fig. 9 The method 1000 for setting the bias voltage according to the embodiment of the present disclosure may further include: if the third flicker index (y3) is less than the first flicker index (y1) and the second flicker index (y2), based on a third scene among a plurality of pre-stored scenes, applying a bias voltage (x4) according to a fourth level greater than the third level to the display panel 110 (see Figure 1 ). The method 1000 for setting the bias voltage may include: by the computing device 630 (see Figure 6 ) receives a fourth flicker index (y4) corresponding to a bias voltage (x4) applied according to a fourth level.

[0147] Further references Fig. 9 In the method 1000 for setting a bias voltage according to an embodiment of the present disclosure, fitting the quadratic function (S1080) may include further fitting the quadratic function based on the bias voltage (x4) applied according to the fourth level and the fourth flicker index (y4).

[0148] Further references Figures 7 to 9 , the bias voltage (x2) applied according to the second level may be greater than the bias voltage (x1) applied according to the first level. However, the embodiments of the present disclosure are not limited thereto, and the bias voltage (x2) applied according to the second level may be less than the bias voltage (x1) applied according to the first level.

[0149] Further references Figure 6 , when applying a bias voltage according to a first level to the display panel 110 (see Figure 1 )(S1010), the computing device 630 may output the bias voltage control signal BCS to the voltage controller 610. The voltage controller 610 may apply a bias voltage according to a first level to the display panel 110 based on the bias voltage control signal BCS input to the voltage controller 610.

[0150] Further references Figure 6, when measuring the first flicker index (S1020), the computing device 630 may receive the first flicker index from the luminance meter 620. While a bias voltage according to a first level is applied to the display panel 110, the luminance meter 620 may output a first flicker index generated based on a change in the brightness of the display panel 110. Thus, for example, the method 1000 for setting the bias voltage may include: when a bias voltage according to a first level is applied to the display panel 110, the luminance meter 620 outputs a first flicker index generated based on a change in the brightness of the display panel 110. In the description of the methods and processes herein, operations may be performed in a different order than shown and / or described, or operations may be performed in a different order or at a different time. Some operations may also be omitted from the flowchart, one or more operations may be repeated, or other operations may be added.

[0151] According to the system for setting the bias voltage and the method for setting the bias voltage according to the embodiments of the present disclosure, the system can be configured to set the bias voltage by a minimum of measurements (for example, a reduced amount of measurements including the flicker index and the bias voltage VBIAS (see Fig. 9 ) is used to calculate the level of the bias voltage that minimizes the flicker phenomenon by minimizing the change in brightness of the display panel based on the bias voltage.

[0152] The drawings and descriptions of the present disclosure are intended to be illustrative. The drawings and descriptions will not be used to limit the meaning or scope of the present disclosure described in the claims, but are only used to illustrate the aspects supported by the present disclosure. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments are possible therefrom. Therefore, the actual protection scope of the present invention should be determined by the technical scope of the attached claims.

Claims

1. A method for setting a bias voltage of a driver integrated circuit by a computing device, the driver integrated circuit supplying a voltage to a display panel, wherein: The method comprises: applying the bias voltage to the display panel according to a first level; receiving, from the display panel, a first flicker index corresponding to the bias voltage according to the first level; applying the bias voltage to the display panel according to a second level different from the first level; receiving a second flicker index corresponding to the bias voltage according to the second level; calculating a change in a flicker index based on a change in a level of the bias voltage; selecting one of a plurality of pre-stored scenes based on the change in the calculation of the flicker index, and applying the bias voltage to the display panel according to a third level based on the selected one of the scenes; receiving a third flicker index corresponding to the bias voltage according to the third level; fitting a quadratic function based on the bias voltage according to the first level, the bias voltage according to the second level, and the bias voltage according to the third level and the first flicker index, the second flicker index, and the third flicker index; and The level of the bias voltage corresponding to the minimum value in the fitted quadratic function is recorded to the driver integrated circuit.

2. The method according to claim 1, wherein: The fitting of the quadratic function comprises: When the third flicker index is a value between the first flicker index and the second flicker index, The quadratic function is fitted based only on the bias voltage according to the first level, the bias voltage according to the second level, and the bias voltage according to the third level, and the first flicker index, the second flicker index, and the third flicker index.

3. The method according to claim 1, wherein: The method further comprises: When, in the calculating of the change in the flicker index based on the change in the level of the bias voltage, the flicker index increases as the level of the bias voltage increases, applying the bias voltage according to the third level, which is smaller than the bias voltage according to the first level and the bias voltage according to the second level, to the display panel based on a first scene among the plurality of pre-stored scenes; When, in the calculation of the change in the flicker index based on the change in the level of the bias voltage, the flicker index decreases as the level of the bias voltage increases, The bias voltage according to the third level, which is greater than the bias voltage according to the first level and the bias voltage according to the second level, is applied to the display panel based on a second scene among the plurality of pre-stored scenes.

4. The method according to claim 3, wherein: The method further comprises: When the third flicker index is smaller than the first flicker index and the second flicker index, applying the bias voltage to the display panel according to a fourth level greater than the third level based on a third scene among the plurality of pre-stored scenes; and receiving a fourth flicker index corresponding to the bias voltage according to the fourth level, The fitting of the quadratic function includes further fitting the quadratic function based on the bias voltage according to the fourth level and the fourth flicker index.

5. The method according to claim 1, wherein: The bias voltage according to the second level is greater than the bias voltage according to the first level.

6. A system for setting a bias voltage, wherein: The system comprises: a voltage controller configured to apply the bias voltage based on a bias voltage control signal; a display panel in which a plurality of sub-pixels are disposed, the bias voltage being commonly applied to the plurality of sub-pixels, wherein a change in brightness associated with the display panel varies based on a level of the bias voltage applied to the plurality of sub-pixels; a brightness meter configured to capture one or more images of the display panel, and the brightness meter generates a flicker index based on the change in the brightness of the display panel, the change in the brightness of the display panel being determined based on the one or more images; driver integrated circuit; and A computing device configured to: storing multiple scenes in memory; outputting the bias voltage control signal; receiving the scintillation index; calculating a change in the flicker index based on a change in the level of the bias voltage; changing and outputting the bias voltage control signal according to one of the plurality of pre-stored scenes based on the calculated change in the flicker index; fitting a quadratic function based on the level of the bias voltage and the flicker index corresponding to the level of the bias voltage; and The level of the bias voltage corresponding to the minimum value in the quadratic function fitted by the calculation device is recorded to the driver integrated circuit.

7. The system of claim 6, wherein: The voltage controller outputs the bias voltage according to a first level and outputs the bias voltage according to a second level based on the bias voltage control signal, The calculation device receives, from the brightness meter, a first flicker index corresponding to the bias voltage output according to the first level and a second flicker index corresponding to the bias voltage output according to the second level, and The calculation device calculates the change in the flicker index based on the change in the level of the bias voltage based on the bias voltage according to the first level, the bias voltage according to the second level, the first flicker index, and the second flicker index.

8. The system according to claim 7, wherein: The calculation device selects the one of the plurality of pre-stored scenes based on the change in the flicker index, and changes and outputs the bias voltage control signal based on the selected one scene so that the bias voltage is applied to the display panel according to a third level.

9. The system of claim 8, wherein: When a third flicker index corresponding to the bias voltage according to the third level is a value between the first flicker index and the second flicker index, The calculation device fits the quadratic function based only on the bias voltage according to the first level, the bias voltage according to the second level, and the bias voltage according to the third level and the first flicker index, the second flicker index, and the third flicker index, and in: When the flicker index increases as the level of the bias voltage increases, The computing device outputs the bias voltage control signal based on a first scene among the multiple pre-stored scenes to control the voltage controller to apply the bias voltage to the display panel according to the third level, and the bias voltage according to the third level is smaller than the bias voltage according to the first level and the bias voltage according to the second level.

10. The system of claim 6, wherein: At least one of the plurality of sub-pixels comprises: a sub-pixel circuit connected to a first power line to which a first power voltage is applied; and a light emitting element including an anode electrode connected to the sub-pixel circuit, a cathode electrode connected to a second power line, and a light emitting structure disposed between the anode electrode and the cathode electrode, a second power voltage being applied to the second power line, and The sub-pixel circuit comprises: a first transistor including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to the first sub-gate line, and the second transistor is configured to switch an electrical connection between the third node and the data line; a third transistor including a gate electrode connected to the second sub-gate line, and the third transistor is configured to switch an electrical connection between the first node and the second node; a fourth transistor including a gate electrode connected to a third sub-gate line, and the fourth transistor is configured to switch an electrical connection between the second node and a third power line to which a first initialization voltage is applied; a fifth transistor configured to switch an electrical connection between the third node and the first power line; a sixth transistor configured to switch an electrical connection between the first node and the anode electrode of the light emitting element; a seventh transistor including a gate electrode connected to a fourth sub-gate line, and the seventh transistor is configured to switch an electrical connection between the anode electrode of the light emitting element and a fourth power line to which a second initialization voltage is applied; and An eighth transistor includes a gate electrode connected to the fourth sub-gate line, and the eighth transistor is configured to switch the electrical connection between the third node and a fifth power line to which the bias voltage is applied.

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