Shift register, gate drive circuit and display panel

Abstract

The invention relates to the technical field of display, and particularly discloses a shift register, a gate drive circuit and a display panel, the shift register comprises a first input module, a second input module, a first output module and a second output module, the output end of the first input module is connected with the first control end of the first output module, and the output end of the second input module is connected with the second control end of the second output module; the input end of the second input module is connected with the second control end of the first output module, the output end of the second input module is connected with the first control end of the second output module, and the second control end of the second output module is connected with the first output module. According to the shift register, through the arrangement of the first input module, the second input module, the first output module and the second output module, one shift register can output two different pulse signals, the number of shift registers arranged in a screen body is reduced, the layout space occupied by the shift registers in the screen body is reduced, and furthermore, the layout space occupied by the shift registers in the screen body is reduced. And screen body frame reduction and screen body power consumption reduction are facilitated.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit and a display panel. Background Art

[0002] At present, the driving circuits around small and medium-sized screens usually require two or more groups of Scan circuits to output different pulse signals. However, the more Scan circuit groups are needed, the more CLK (Clock) signals and TFT (Thin Film Transistor) devices will be needed, which will lead to an increase in the screen frame. How to achieve a narrow frame of the screen is currently a hot research direction in the field of display technology, so it is necessary to reduce the number of Scan circuits in the screen. Summary of the invention

[0003] Based on this, it is necessary to provide a shift register, a gate drive circuit and a display panel to address the problem of how to reduce the number of Scan circuits in the screen.

[0004] A shift register comprises a first input module, a second input module, a first output module and a second output module, wherein the control end of the first output module comprises a first control end and a second control end, the control end of the second output module comprises a first control end and a second control end, the output end of the first input module is connected to the first control end of the first output module, and the first input module is configured to transmit a first input signal to the first control end of the first output module according to a first clock signal; the input end of the second input module is connected to the second control end of the first output module, the output end of the second input module is connected to the first control end of the second output module, and the second input module is configured to transmit a second input signal to the first control end of the second output module according to a second clock signal; the first output module is configured to output a first output signal according to a signal at the control end of the first output module; the second control end of the second output module is connected to the first output module, and the second output module is configured to output a second output signal according to a signal at the control end of the second output module.

[0005] In one embodiment, the first output module includes a first output control unit, a second output control unit, a first output unit and a second output unit, the control end of the first output control unit serves as the first control end of the first output module, the control end of the second output control module serves as the second control end of the first output module, the first end of the first output control unit is connected to a second clock signal, the control end of the first output control unit is connected to the output end of the first input module, the second end of the first output control unit is respectively connected to the control end of the first output unit and the control end of the second output unit, the first output control unit is configured to transmit the second clock signal to the control end of the first output unit and the control end of the second output unit according to the signal at the control end of the first output control unit; the first end of the second output control unit is connected to a first level signal, the control end of the second output control unit is connected to the second input module The first output unit is connected to the input end of the block, the second end of the second output control unit is respectively connected to the control end of the first output unit and the control end of the second output unit, and the second output control unit is configured to transmit the first level signal to the control end of the first output unit and the control end of the second output unit according to the signal at the control end of the second output control unit; the first end of the first output unit is connected to the first level signal, the second end of the first output unit is connected to the output end of the first output module, and the first output unit is configured to transmit the first level signal to the output end of the first output module according to the signal at the control end of the first output unit; the first end of the second output unit is connected to the second level signal, the second end of the second output unit is connected to the output end of the first output module, and the second output unit is configured to transmit the second level signal to the output end of the first output module according to the signal at the control end of the second output unit.

[0006] In one embodiment, the first output control unit includes a third transistor, the first electrode of the third transistor serves as the first end of the first output control unit, the gate of the third transistor serves as the control end of the first output control unit, and the second electrode of the third transistor serves as the second end of the first output control unit; the second output control unit includes a fourth transistor, the first electrode of the fourth transistor serves as the first end of the second output control unit, the gate of the fourth transistor serves as the control end of the second output control unit, and the second electrode of the fourth transistor serves as the second end of the second output control unit; the first output unit includes a fifth transistor, the first electrode of the fifth transistor serves as the first end of the first output unit, the gate of the fifth transistor serves as the control end of the first output unit, and the second electrode of the fifth transistor serves as the second end of the first output unit; the second output unit includes a sixth transistor, the first electrode of the sixth transistor serves as the first end of the second output unit, the gate of the sixth transistor serves as the control end of the second output unit, and the second electrode of the sixth transistor serves as the second end of the second output unit.

[0007] In one embodiment, a conduction level of the fifth transistor is different from a conduction level of the sixth transistor.

[0008] In one embodiment, a pulse width of the first output signal is different from a pulse width of the second output signal.

[0009] In one embodiment, the first potential holding unit includes a first capacitor, a first end of the first capacitor is connected to a control end of the second output control unit, and a second end of the first capacitor is connected to a second end of the second output control unit.

[0010] In one embodiment, the second output module includes a third output control unit, a fourth output control unit, a third output unit and a fourth output unit, the control end of the third output control unit serves as the first control end of the second output module, the control end of the fourth output control module serves as the second control end of the second output module, the first end of the third output control unit is connected to a first level signal, the control end of the third output control unit is connected to the output end of the second input module, the second end of the third output control unit is connected to the control end of the fourth output unit, and the third output control unit is configured to transmit the first level signal to the control end of the fourth output unit according to the signal at the control end of the third output control unit; the first end of the fourth output control unit is connected to a second level signal, the control end of the fourth output control unit is connected to the first output module, and the fourth output control unit The second end of the element is connected to the control end of the fourth output unit, and the fourth output control unit is configured to transmit the second level signal to the control end of the fourth output unit according to the signal at the control end of the fourth output control unit; the first end of the third output unit is connected to the second level signal, the control end of the third output unit is connected to the output end of the second input module, the second end of the third output unit is connected to the output end of the second output module, and the third output unit is configured to transmit the second level signal to the output end of the second output module according to the signal at the control end of the third output unit; the first end of the fourth output unit is connected to the first level signal, the second end of the fourth output unit is connected to the output end of the second output module, and the fourth output unit is configured to transmit the first level signal to the output end of the second output module according to the signal at the control end of the fourth output unit.

[0011] In one embodiment, the third output control unit includes a seventh transistor, the first electrode of the seventh transistor serves as the first end of the third output control unit, the gate of the seventh transistor serves as the control end of the third output control unit, and the second electrode of the seventh transistor serves as the second end of the third output control unit; the fourth output control unit includes an eighth transistor, the first electrode of the eighth transistor serves as the first end of the fourth output control unit, the gate of the eighth transistor serves as the control end of the fourth output control unit, and the second electrode of the eighth transistor serves as the second end of the fourth output control unit; the third output unit includes a ninth transistor, the first electrode of the ninth transistor serves as the first end of the third output unit, the gate of the ninth transistor serves as the control end of the third output unit, and the second electrode of the ninth transistor serves as the second end of the third output unit; the fourth output unit includes a tenth transistor, the first electrode of the tenth transistor serves as the first end of the fourth output unit, the gate of the tenth transistor serves as the control end of the fourth output unit, and the second electrode of the tenth transistor serves as the second end of the fourth output unit.

[0012] In one embodiment, the second output module further includes a second potential holding unit, which is connected between the first end of the fourth output unit and the control end of the fourth output unit, and is used to maintain the potential between the first end of the fourth output unit and the control end of the fourth output unit.

[0013] In one embodiment, the second potential holding unit includes a second capacitor, a first end of the second capacitor is connected to the first end of the fourth output unit, and a second end of the second capacitor is connected to the control end of the fourth output unit.

[0014] In one embodiment, the first input module includes a first transistor, a first electrode of the first transistor is connected to the first input signal, a gate of the first transistor is connected to the first clock signal, and a second electrode of the first transistor serves as an output end of the first input module; the second input module includes a second transistor, a first electrode of the second transistor is connected to the second input signal, a gate of the second transistor is connected to the second clock signal, and a second electrode of the second transistor serves as an output end of the second input module.

[0015] In one embodiment, the shift register further includes a cascade module, an input end of the cascade module is connected to a first level signal, an output end of the cascade module is connected to the first output module, and the cascade module is configured to transmit the first level signal to the first output module according to the cascade signal.

[0016] In one embodiment, the cascade module includes an eleventh transistor, a first electrode of the eleventh transistor serves as an input end of the cascade module, a gate of the eleventh transistor is connected to the cascade signal, and a second electrode of the eleventh transistor serves as an output end of the cascade module.

[0017] A gate drive circuit comprises n cascaded shift registers as described in any one of the above embodiments, wherein, except for the shift register of the nth stage, the signal output by the first output control module of the shift register of the i-th stage serves as the first input signal of the shift register of the i+1th stage, and the second output signal output by the second output module of the shift register of the i-th stage serves as the second input signal of the shift register of the i+1th stage; wherein n is an integer greater than zero, i=1, 2, 3, ..., n.

[0018] In one embodiment, in addition to the shift register at the nth stage and the shift register at the n-1th stage, the signal output by the first output control module of the shift register at the i+2th stage serves as a cascade signal connected to the shift register at the ith stage.

[0019] A display panel comprises the gate driving circuit described in any one of the above embodiments.

[0020] In the above-mentioned shift register, the first input module transmits the first input signal to the first control end of the first output module according to the first clock signal, and the second input module transmits the second input signal to the first control end of the second output module according to the second clock signal. The first output module can output the first output signal according to the signal at the control end of the first output module, and the second output module can output the second output signal according to the potential at the control end of the second output module. The above-mentioned shift register can enable one shift register to output two different pulse signals through the setting of the first input module, the second input module, the first output module and the second output module. By making one shift register output two different pulse signals, the number of shift registers set in the screen body can be reduced, thereby reducing the layout space occupied by the shift register in the screen body, and further, it is conducive to reducing the screen body frame and reducing the power consumption of the screen body. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the implementation methods of this specification or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1This is a schematic diagram of the structure of a shift register in one of the embodiments of the present application;

[0023] Figure 2 This is a schematic diagram of the structure of a shift register in another embodiment of the present application;

[0024] Figure 3 This is a schematic diagram of the circuit structure of a shift register in one of the embodiments of the present application;

[0025] Figure 4 This is a structural diagram of a shift register in another embodiment of the present application;

[0026] Figure 5 This is a schematic diagram of the circuit structure of a shift register in another embodiment of the present application;

[0027] Figure 6 This is a timing diagram of various signals in a shift register in one embodiment of the present application;

[0028] Figure 7 This is a schematic diagram of the structure of a gate driving circuit in one of the embodiments of the present application. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to understand the disclosure of the present invention more thoroughly and comprehensively.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0031] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be construed as being one in number.

[0032] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0033] In this application, unless otherwise clearly specified and limited, the terms "connected", "connection" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] The existing scheme usually requires two groups of Scan circuits to generate two different gate drive signals, and the two groups of Scan circuits occupy more layout space, and the number of CLK signals and TFT devices required in the two groups of Scan circuits is also large. The shift register provided in the present application can realize the output of two different gate drive signals by a first-level Scan circuit. Compared with the scheme of using two groups of Scan circuits in the prior art, the shift register provided in the present application has the advantages of occupying less layout space, less CLK number, and less TFT device number, while being able to realize the function of outputting two different pulse signals.

[0035] Figure 1 This is a schematic diagram of the structure of a shift register in one embodiment of the present application. In one embodiment, the shift register 10 may include a first input module 100, a second input module 200, a first output module 300, and a second output module 400. The control end of the first output module 300 may include a first control end and a second control end, and the control end of the second output module 400 may include a first control end and a second control end.

[0036] The output end of the first input module 100 can be connected to the first control end of the first output module 300, and the first input module 100 can be configured to transmit the first input signal SIN to the first control end of the first output module 300 according to the first clock signal SCK1. The input end of the first input module 100 can be connected to the first input signal line, and the control end of the first input module 100 can be connected to the first clock end, that is, the first input module 100 can access the first input signal SIN through the first input signal line, and access the first clock signal SCK1 through the first clock end, so that the first input module 100 can transmit the first input signal SIN to the first control end of the first output module 300 according to the first clock signal SCK1.

[0037] The output end of the second input module 200 can be connected to the first control end of the second output module 400, and the second input module 200 can be configured to transmit the second input signal EIN to the first control end of the second output module 400 according to the second clock signal SCK2. The input end of the second input module 200 can be connected to the second input signal line, and the control end of the second input module 200 can be connected to the second clock end, that is, the second input module 200 can access the second input signal EIN through the second input signal line, and access the second clock signal SCK2 through the second clock end, so that the second input module 200 can transmit the second input signal EIN to the control end of the second output module 400 according to the second clock signal SCK2.

[0038] The second control terminal of the first output module 300 can be connected to the input terminal of the second input module 200, the output terminal of the first output module 300 can be defined as the first output terminal of the shift register 10, and the signal output by the first output terminal can be defined as the first output signal Sn_out. The first output module 300 can be configured to output the first output signal Sn_out according to the signal at the control terminal of the first output module 300, that is, the first output module 300 can output the first output signal Sn_out according to the second input signal EIN and / or the signal output by the first input module 100.

[0039] The second control terminal of the second output module 400 can be connected to the first output module 300, the output terminal of the second output module 400 can be defined as the second output terminal of the shift register 10, and the signal output by the second output terminal can be defined as the second output signal Em_out. The second output module 400 can be configured to output the second output signal Em_out according to the signal at the control terminal of the second output module 400, that is, the second output module 400 can output the second output signal Em_out according to the signal output by the second input module 200 and / or the signal at the first output module 300. In some optional embodiments, the pulse width of the first output signal Sn_out is different from the pulse width of the second output signal Em_out.

[0040] In the shift register 10 provided in the present application, the first input module 100 transmits the first input signal SIN to the control end of the first output module 300 according to the first clock signal SCK1, and the first input module 100 transmits the second input signal EIN to the control end of the second output module 400 according to the second clock signal SCK2, the first output module 300 can output the first output signal Sn_out according to the signal at the control end of the first output module 300, and the second output module 400 can output the second output signal Em_out according to the signal at the control end of the second output module 400. The pulse width of the first output signal Sn_out and the pulse width of the second output signal Em_out can be the same or different.

[0041] The first output terminal and the second output terminal of the shift register 10 can be used to output two different signals, namely, the first output signal Sn_out and the second output signal Em_out, respectively. That is, the shift register 10 can use a one-stage shift register to realize the pulse signal function that can be realized by a two-stage shift register in the prior art. By making one shift register output two different pulse signals, the number of shift registers set in the screen can be reduced while ensuring the normal operation of the pixel circuit in the screen, thereby reducing the layout space occupied by the shift register in the screen, and further, it is conducive to reducing the screen frame and reducing the power consumption of the screen.

[0042] Figure 2 This is a schematic diagram of the structure of a shift register in another embodiment of the present application. Figure 2 In the figure, the connection point between the output end of the first input module 100, the control end of the first output control unit 310 and the first end of the first potential holding unit 350 is defined as the first node N1, the connection point between the output end of the second input module 200, the control end of the third output control unit 410 and the control end of the third output unit 430 is defined as the second node N2, the connection point between the output end of the third output control unit 410, the output end of the fourth output control unit 420, the control end of the fourth output unit 440 and the second end of the second potential holding unit 450 is defined as the third node N3, and the connection point between the output end of the first output control unit 310, the output end of the second output control unit 320, the control end of the first output unit 330 and the control end of the second output unit 340 is defined as the fourth node N4.

[0043] In one embodiment, the first output module 300 may further include a first output control unit 310, a second output control unit 320, a first output unit 330, and a second output unit 340. The control end of the first output control unit 310 may serve as the first control end of the first output module 300, and the control end of the second output control module 320 may serve as the second control end of the first output module 300.

[0044] The first end of the first output control unit 310 can be connected to the second clock signal SCK2, and the first end of the second output control unit 320 can be connected to the second clock end to access the second clock signal SCK2. The control end of the first output control unit 310 can be connected to the output end of the first input module 100, and the second end of the first output control unit 310 can be connected to the control end of the first output unit 330 and the control end of the second output unit 340 respectively. The first output control unit 310 can be configured to transmit the second clock signal SCK2 to the control end of the first output unit 330 and the control end of the second output unit 340 according to the signal at the control end of the first output control unit 310. Specifically, when the level at the first node N1 is the conduction level, the first output control unit 310 can be turned on according to the level at the gate of the first output control unit 310, so that the first output control unit 310 can transmit the second clock signal SCK2 to the control end of the first output unit 330 and the control end of the second output unit 340.

[0045] The first terminal of the second output control unit 320 can be connected to the first level signal VGH, and the first terminal of the second output control unit 320 can be connected to the first voltage terminal to connect to the first level signal VGH. In this embodiment, the first voltage terminal can be connected to a high level signal source, and the high level signal source can continuously provide the first level signal VGH, and the first level signal VGH can be a high level signal.

[0046] The control end of the second output control unit 320 can be connected to the input end of the second input module 200, and the second end of the second output control unit 320 can be connected to the control end of the first output unit 330 and the control end of the second output unit 340 respectively. The second output control unit 320 can be configured to transmit the first level signal VGH to the control end of the first output unit 330 and the control end of the second output unit 340 according to the signal at the control end of the second output control unit 320. Specifically, since the input end of the second input module 200 is connected to the second input signal EIN, the second output control unit 320 is turned on or off according to the second input signal EIN. When the level of the second input signal EIN is the on level, the second output control unit 320 can be turned on according to the second input signal EIN, so that the second output control unit 320 can transmit the first level signal VGH to the control end of the first output unit 330 and the control end of the second output unit 340.

[0047] The first end of the first output unit 330 can be connected to the first level signal VGH, and the first end of the first output unit 330 can be connected to the first voltage end to connect to the first level signal VGH. The second end of the first output unit 330 can be connected to the output end of the first output module 300, and the first output unit 330 can be configured to transmit the first level signal VGH to the output end of the first output module 300 according to the signal at the control end of the first output unit 330. Specifically, when the first output control unit 310 outputs a signal and / or the second output control unit 320 outputs a signal to make the potential of the fourth node N4 to be the conduction level, the first output unit 330 can be turned on according to the potential at the control end of the first output unit 330, thereby transmitting the first level signal VGH to the output end of the first output module 300.

[0048] The first end of the second output unit 340 can be connected to the second level signal VGL, and the first end of the second output unit 340 can be connected to the second voltage end to connect the second level signal VGL. In this embodiment, the second voltage end can be connected to a low level signal source, and the low level signal source can continuously provide the second level signal VGL, and the second level signal VGL can be a low level signal.

[0049] The second end of the second output unit 340 may be connected to the output end of the first output module 300, and the second output unit 340 may be configured to transmit the second level signal VGL to the output end of the first output module 300 according to the signal at the control end of the second output unit 340. Specifically, when the first output control unit 310 outputs a signal and / or the second output control unit 320 outputs a signal so that the potential at the fourth node N4 is at a conduction level, the second output unit 340 may be turned on according to the potential at the control end of the second output unit 340, thereby transmitting the second level signal VGL to the output end of the first output module 300.

[0050] Figure 3 This is a schematic diagram of the circuit structure of a shift register in one of the embodiments of the present application. Figure 3 In the figure, a connection point between the second electrode of the first transistor M1, the gate of the fourth transistor M4 and the first end of the first capacitor C1 is defined as a first node N1, a connection point between the second electrode of the second transistor M2, the gate of the seventh transistor M7 and the gate of the ninth transistor M9 is defined as a second node N2, a connection point between the second electrode of the seventh transistor M7, the second electrode of the eighth transistor M8, the gate of the tenth transistor M10 and the second end of the second capacitor C2 is defined as a third node N3, and a connection point between the second electrode of the third transistor M3, the second electrode of the fourth transistor M4, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 is defined as a fourth node N4.

[0051] In one embodiment, the first input module 100 may include a first transistor M1 , and the second input module 200 may include a second transistor M2 .

[0052] In the embodiments of the present disclosure, a transistor refers to a component including at least a gate, a drain, and a source. In the present disclosure, the first electrode of the transistor may be a drain, the second electrode may be a source, or the first electrode may be a source, and the second electrode may be a drain. In the case of using transistors with opposite polarities or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In the embodiments of the present disclosure, the gate of all or part of the transistors may be used as the control electrode of the transistor, and the first electrode and the second electrode may be interchangeable as needed.

[0053] The first electrode of the first transistor M1 can be connected to the first input signal SIN, and the first electrode of the first transistor M1 can be connected to the first input signal line to access the first input signal SIN. The gate of the first transistor M1 can be connected to the first clock signal SCK1, and the gate of the first transistor M1 can be connected to the first clock terminal to access the first clock signal SCK1. The second electrode of the first transistor M1 can serve as the output terminal of the first input module 100. When the level of the first clock signal SCK1 is the on level, the first transistor M1 can be turned on according to the first clock signal SCK1, thereby outputting the first input signal SIN.

[0054] The first electrode of the second transistor M2 can be connected to the second input signal EIN, and the first electrode of the second transistor M2 can be connected to the second input signal line to access the second input signal EIN. The gate of the second transistor M2 can be connected to the second clock signal SCK2, and the gate of the second transistor M2 can be connected to the second clock terminal to access the second clock signal SCK2. The second electrode of the second transistor M2 can serve as the output terminal of the second input module 200. When the level of the second clock signal SCK2 is the on level, the second transistor M2 can be turned on according to the second clock signal SCK2, thereby outputting the second input signal EIN.

[0055] In one embodiment, see Figure 3 , the first output control unit 310 may include a third transistor M3, the second output control unit 320 may include a fourth transistor M4, the first output unit 330 may include a fifth transistor M5, and the second output unit 340 may include a sixth transistor M6.

[0056] The first electrode of the third transistor M3 can be connected to the second clock signal SCK2 as the first end of the first output control unit 310. The gate of the third transistor M3 can be connected to the output end of the first input module 100 as the control end of the first output control unit 310. The second electrode of the third transistor M3 can be connected to the control end of the first output unit 330 and the control end of the second output unit 340 as the second end of the first output control unit 310. Specifically, the gate of the third transistor M3 is connected to the second electrode of the first transistor M1, and the second electrode of the third transistor M3 is connected to the gate of the fifth transistor M5 and the gate of the sixth transistor M6.

[0057] The first electrode of the fourth transistor M4 can be connected to the first level signal VGH as the first end of the second output control unit 320, the gate of the fourth transistor M4 can be connected to the input end of the second input module 200 as the control end of the second output control unit 320, and the second electrode of the fourth transistor M4 can be connected to the control end of the first output unit 330 and the control end of the second output unit 340 as the second end of the second output control unit 320. Specifically, the gate of the fourth transistor M4 is connected to the first electrode of the second transistor M2, and the second electrode of the fourth transistor M4 is connected to the gate of the fifth transistor M5 and the gate of the sixth transistor M6.

[0058] The first electrode of the fifth transistor M5 can be used as the first end of the first output unit 330 to connect to the first level signal VGH, the gate of the fifth transistor M5 can be used as the control end of the first output unit 330, and the second electrode of the fifth transistor M5 can be used as the second end of the first output unit 330 to connect to the output end of the first output module 300.

[0059] The first electrode of the sixth transistor M6 can be used as the first end of the second output unit 340 to connect to the second level signal VGL, the gate of the sixth transistor M6 can be used as the control end of the second output unit 340, and the second electrode of the sixth transistor M6 can be used as the second end of the second output unit 340 to connect to the output end of the first output module 300.

[0060] In a preferred embodiment, the conduction level of the fifth transistor M5 is different from the conduction level of the sixth transistor M6. For example, the fifth transistor M5 may be a P-type transistor, and the sixth transistor M6 may be an N-type transistor, that is, the conduction level of the fifth transistor M5 is a low level, and the conduction level of the sixth transistor M6 is a high level; or, the fifth transistor M5 may be an N-type transistor, and the sixth transistor M6 may be a P-type transistor, that is, the conduction level of the fifth transistor M5 is a high level, and the conduction level of the sixth transistor M6 is a low level.

[0061] Since the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are both connected to the fourth node N4, that is, the fifth transistor M5 and the sixth transistor M6 are both turned on or off according to the potential at the fourth node N4, by making the turn-on level of the fifth transistor M5 different from the turn-on level of the sixth transistor M6, it can be ensured that the fifth transistor M5 and the sixth transistor M6 will not be turned on at the same time according to the potential at the fourth node N4, so that the first output module 300 can stably output the corresponding pulse signal.

[0062] In one embodiment, see Figure 2, the first output module 300 may further include a first voltage holding unit 350. The first potential holding unit 350 may be connected between the control end of the second output control unit 320 and the second end of the second output control unit 320, and the first potential holding unit 350 may be used to hold the potential between the control end of the second output control unit 320 and the second end of the second output control unit 320. The potential at the fourth node N4 may be adjusted by the first potential holding unit 350 to ensure that the second output control unit 320 can stably output the control signal.

[0063] In one embodiment, see Figure 3 , the first potential holding unit 350 may include a first capacitor C1. The first end of the first capacitor C1 may be connected to the control end of the second output control unit 320, and the second end of the first capacitor C1 may be connected to the second end of the second output control unit 320. Specifically, the first end of the first capacitor C1 may be connected to the gate of the fourth transistor M4, and the second end of the first capacitor C1 may be connected to the second electrode of the fourth transistor M4. The first capacitor C1 may be used to stabilize the potential at the fourth node N4.

[0064] In one embodiment, see Figure 2 The second output module 400 may include a third output control unit 410, a fourth output control unit 420, a third output unit 430, and a fourth output unit 440. The control end of the third output control unit 410 may serve as the first control end of the second output module 400, and the control end of the fourth output control module 420 may serve as the second control end of the second output module 400.

[0065] The first end of the third output control unit 410 can be connected to the first level signal VGH, and the first end of the third output control unit 410 can be connected to the first voltage end to connect to the first level signal VGH. The control end of the third output control unit 410 can be connected to the output end of the second input module 200, and the second end of the third output control unit 410 can be connected to the control end of the fourth output unit 440. The third output control unit 410 can be configured to transmit the first level signal VGH to the control end of the fourth output unit 440 according to the signal at the control end of the third output control unit 440. Specifically, when the level of the output signal of the second input module 200 is the conduction level, the third output control unit 410 can be turned on according to the output signal of the second input module 200, so that the third output control unit 410 can transmit the first level signal VGH to the control end of the fourth output unit 440.

[0066] The first end of the fourth output control unit 420 can be connected to the second level signal VGL, and the first end of the fourth output control unit 420 can be connected to the second voltage end to connect the second level signal VGL. The control end of the fourth output control unit 420 can be connected to the first output module 300. Specifically, the control end of the fourth output control unit 420 can be connected to the fourth node N4, that is, the fourth output control unit 420 is turned on or off according to the potential at the fourth node N4. The second end of the fourth output control unit 420 can be connected to the control end of the fourth output unit 440. The fourth output control unit 420 can be configured to transmit the second level signal VGL to the control end of the fourth output unit 440 according to the signal at the control end of the fourth output control unit 420. Specifically, when the level at the fourth node N4 is the on level, the fourth output control unit 420 can be turned on according to the level at the control end of the fourth output control unit 420, so that the fourth output control unit 420 can transmit the second level signal VGL to the control end of the fourth output unit 440.

[0067] The first end of the third output unit 430 can be connected to the second level signal VGL, and the first end of the third output unit 430 can be connected to the second voltage end to connect the second level signal VGL. The control end of the third output unit 430 can be connected to the output end of the second input module 200, and the second end of the third output unit 430 can be connected to the output end of the second output module 400. The third output unit 430 can be configured to transmit the second level signal VGL to the output end of the second output module 400 according to the signal at the control end of the third output unit 430. Specifically, when the level of the output signal of the second input module 200 is the conduction level, the third output unit 430 can be turned on according to the output signal of the second input module 200, thereby transmitting the second level signal VGL to the output end of the second output module 400.

[0068] The first end of the fourth output unit 440 can be connected to the first level signal VGH, and the first end of the fourth output unit 440 can be connected to the first voltage end to connect to the first level signal VGH. The control end of the fourth output unit 440 can be connected to the third node N3, the second end of the fourth output unit 440 can be connected to the output end of the second output module 400, and the fourth output unit 440 can be configured to transmit the first level signal VGH to the output end of the second output module 400 according to the signal at the control end of the fourth output unit 440. Specifically, when the potential at the third node N3 is the conduction level, the fourth output unit 440 can be turned on according to the potential at the control end of the fourth output unit 440, thereby transmitting the first level signal VGH to the output end of the second output module 400.

[0069] In one embodiment, see Figure 3, the third output control unit 410 may include a seventh transistor M7, the fourth output control unit 420 may include an eighth transistor M8, the third output unit 430 may include a ninth transistor M9, and the fourth output unit 440 may include a tenth transistor M10.

[0070] The first electrode of the seventh transistor M7 can be connected to the first level signal VGH as the first end of the third output control unit 410, the gate of the seventh transistor M7 can be connected to the output end of the second input module 200 as the control end of the third output control unit 410, and the second electrode of the seventh transistor M7 can be connected to the control end of the fourth output unit 440 as the second end of the third output control unit 410. Specifically, the gate of the seventh transistor M7 is connected to the second electrode of the second transistor M2, and the second electrode of the seventh transistor M7 is connected to the gate of the tenth transistor M10.

[0071] The first electrode of the eighth transistor M8 can be used as the first end of the fourth output control unit 420 to access the second level signal VGL and connect to the first output module 300, the gate of the eighth transistor M8 can be used as the control end of the fourth output control unit 420, and the second electrode of the eighth transistor M8 can be used as the second end of the fourth output control unit 420 to connect to the control end of the fourth output unit 440. Specifically, the gate of the eighth transistor M8 is connected to the second electrode of the third transistor M3 and the second electrode of the fourth transistor M4, and the second electrode of the eighth transistor M8 is connected to the gate of the tenth transistor M10.

[0072] The first electrode of the ninth transistor M9 can be connected to the second level signal VGL as the first end of the third output unit 430, the gate of the ninth transistor M9 can be connected to the output end of the second input module 200 as the control end of the third output unit 430, and the second electrode of the ninth transistor M9 can be connected to the output end of the second output module 400 as the second end of the third output unit 430. Specifically, the gate of the ninth transistor M9 is connected to the second electrode of the second transistor M2.

[0073] The first electrode of the tenth transistor M10 can be used as the first end of the fourth output unit 440 to connect to the first level signal VGH, the gate of the tenth transistor M10 can be used as the control end of the fourth output unit 440, and the second electrode of the tenth transistor M10 can be used as the second end of the fourth output unit 440 to connect to the output end of the second output module 400.

[0074] In one embodiment, see Figure 2, the second output module 400 may further include a second potential holding unit 450. The second potential holding unit 450 may be connected between the first end of the fourth output unit 440 and the control end of the fourth output unit 440, and the second potential holding unit 450 may be used to hold the potential between the first end of the fourth output unit 440 and the control end of the fourth output unit 440. The potential at the third node N3 may be adjusted by the second potential holding unit 450 to ensure that the fourth output unit 440 may stably output the first level signal VGH according to the potential at the third node N3.

[0075] In one embodiment, see Figure 3 The second potential holding unit 450 may include a second capacitor C2, a first end of the second capacitor C2 may be connected to a first end of the fourth output unit 440, and a second end of the second capacitor C2 may be connected to a control end of the fourth output unit 440. Specifically, a first end of the second capacitor C2 may be connected to a gate of the tenth transistor M10, and a second end of the second capacitor C2 may be connected to a second electrode of the tenth transistor M10. The second capacitor C2 may stabilize the potential at the third node N3.

[0076] Figure 4 This is a schematic diagram of the structure of a shift register in another embodiment of the present application. Figure 4 The fourth node N4 is also connected to the output end of the cascade module 500. In one embodiment, the shift register 10 may further include a cascade module 500. The input end of the cascade module 500 may be connected to the first level signal VGH, and the output end of the cascade module 500 may be connected to the first output module 300. Specifically, the output end of the cascade module 500 may be connected to the control end of the first output unit 330 and the control end of the second output unit 340. The cascade module 500 may be configured to transmit the first level signal VGH to the first output module 300 according to the cascade signal Cn. The cascade control between the shift registers 10 at various levels may be implemented by using the cascade module 500.

[0077] In some preferred embodiments, the signal waveform of the cascade signal Cn connected to the control end of the cascade module 500 in the i-th (i=1, 2, 3, ..., n)-th level shift register 10 can be the same as the potential waveform at the fourth node N4_2 in the i+2-th level shift register 10. In this case, the control end of the cascade module 500 in the i-th level shift register 10 can be connected to the fourth node N4 in the i+2-th level shift register 10, so that the potential at the fourth node N4 in the i+2-th level shift register 10 can be used to control the working state of the cascade module 500 in the i-th level shift register 10.

[0078] In some preferred embodiments, the potential waveform at the fourth node N4 in the i-th stage shift register 10 may be the same as the signal waveform of the first input signal SIN in the i+1-th stage shift register 10. In this case, the fourth node N4 in the i-th stage shift register 10 may be connected to the input end of the first input module 100 in the i+1-th stage shift register 10, so that the potential at the fourth node N4 in the i-th stage shift register 10 may be used as the first input signal SIN in the i+1-th stage shift register 10.

[0079] For example, the fourth node N4 in the third-level shift register 10 can be connected to the control end of the cascade module 500 in the first-level shift register 10, that is, the cascade module 500 in the first-level shift register 10 operates according to the potential at the fourth node N4 in the third-level shift register 10; the fourth node N4 in the third-level shift register 10 can also be connected to the input end of the first input module 100 in the fourth-level shift register 10, that is, the potential at the fourth node N4 in the third-level shift register 10 serves as the first input signal SIN in the fourth-level shift register 10.

[0080] In some preferred embodiments, the signal waveform of the second output signal Em_out output by the second output module 400 in the i-th stage shift register 10 may be the same as the signal waveform of the first input signal SIN in the i+1-th stage shift register 10. In this case, the output end of the second output module 400 in the i-th stage shift register 10 may be connected to the input end of the second input module 100 in the i+1-th stage shift register 10, so that the second output signal Em_out output by the second output module 400 in the i-th stage shift register 10 may be used as the second input signal EIN in the i+1-th stage shift register 10.

[0081] For example, the output end of the second output module 400 in the third-stage shift register 10 can be connected to the input end of the second input module 100 in the fourth-stage shift register 10, that is, the second output signal Em_out in the third-stage shift register 10 serves as the first input signal SIN in the fourth-stage shift register 10.

[0082] Figure 5 This is a schematic diagram of the circuit structure of a shift register in another embodiment of the present application. Figure 5The fourth node N4 is also connected to the second electrode of the eleventh transistor M11. In one embodiment, the cascade module 500 may include the eleventh transistor M11. The first electrode of the eleventh transistor M11 may be connected to the first level signal VGH as the input end of the cascade module 500, the gate of the eleventh transistor M11 may be connected to the cascade signal Cn, and the second electrode of the eleventh transistor M11 may be connected to the first output module 300 as the output end of the cascade module 500. Specifically, the second electrode of the eleventh transistor M11 may be connected to the gate of the fifth transistor M5 and the gate of the sixth transistor M6.

[0083] In a preferred embodiment, the gate of the eleventh transistor M11 in the i-th stage shift register 10 can be connected to the fourth node N4_2 in the i+2-th stage shift register 10, and the fourth node N4 in the i-th stage shift register 10 can be connected to the first electrode of the first transistor M1 in the i+1-th stage shift register 10. Figure 4 As shown, when the gate of the eleventh transistor M11 in the i-th shift register 10 can be connected to the fourth node N4_2 in the (i+2)-th shift register 10, the cascade signal connected to the gate of the eleventh transistor M11 in the i-th shift register 10 is N4_2, that is, the signal at the fourth node N4_2.

[0084] In some other embodiments, the cascade signal Cn connected to the cascade module 500 in each level of the shift register 10, the first input signal SIN connected to the first input module 100, and the second input signal EIN connected to the second input module 200 can also be independent input signals. In specific applications, the corresponding signal waveforms are designed according to the requirements of different application scenarios. At the same time, the fourth node N4 in each level of the shift register 10 can also be connected to other circuits to provide signal waveforms required by other circuits.

[0085] In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 in the shift register 10 provided in the present application can all be P-type transistors, for example, they can be polycrystalline silicon thin film transistors. The sixth transistor M6 can be an N-type transistor, for example, it can be a polycrystalline silicon thin film transistor. For example, it can be an oxide thin film transistor, and illustratively, it can be an indium gallium zinc oxide thin film transistor. In some other embodiments, the device selection of each unit in the circuit can also select other suitable functional elements according to actual application requirements.

[0086] An embodiment of the present invention may also provide a driving method for driving the shift register 10 as described in any of the above embodiments. A working cycle of the shift register 10 may include a first stage T1, a second stage T2, a third stage T3, a fourth stage T4, a fifth stage T5, a sixth stage T6, a seventh stage T7, and an eighth stage T8.

[0087] Figure 6 This is a timing diagram of various signals in a shift register in one embodiment of the present application. Figure 6 In the embodiment, SIN represents the first input signal, EIN represents the second input signal, SCK1 represents the first clock signal, SCK2 represents the second clock signal, Sn_out represents the first output signal, i.e., the signal output at the first output terminal of the shift register 10, and Em_out represents the second output signal, i.e., the signal output at the second output terminal of the shift register 10. Figure 5 The shift register 10 shown in FIG. Figure 6 The timing diagram shown in FIG. 1 describes in detail the working process of the shift register 10 in one working cycle.

[0088] Figure 5 In the shift register 10 shown, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all P-type transistors, the sixth transistor M6 is an N-type transistor, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all turned on according to a low level and turned off according to a high level; the sixth transistor M6 is turned on according to a high level and turned off according to a low level.

[0089] In the first stage T1 , the level of the first input signal SIN is controlled to be low, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0090] When the shift register 10 operates in the first stage T1, since the first clock signal SCK1 is a low-level signal, the second clock signal SCK2 is a high-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0091] After the first transistor M1 is turned on, the first transistor M1 transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a low-level signal, so that the potential at the first node N1 is VN1=VGL-Vth. The third transistor M3 is turned on according to the potential at the first node N1, and the second clock signal SCK2 is transmitted to the fourth node N4 through the third transistor M3. At this time, the second clock signal SCK2 is a high-level signal, so that the potential at the fourth node N4 is VN4=VGH. Since the potential at the fourth node N4 is a high level, the fifth transistor M5 is turned off and the sixth transistor M6 is turned on. After the sixth transistor M6 is turned on, the second level signal VGL is transmitted to the output end of the first output module 300. Since the fifth transistor M5 is turned off, the fifth transistor M5 cannot transmit the first level signal VGH to the output end of the first output module 300, that is, in the first stage T1, the first output signal Sn_out output by the first output end of the shift register 10 is a low-level signal.

[0092] At the same time, since the potential at the fourth node N4 is a high level VGH, the eighth transistor M8 is turned off according to the potential at the fourth node N4. At this time, the potential at the second node N2 is VN2=VGL-Vth, so the seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2. After the seventh transistor M7 is turned on, the first level signal VGH is transmitted to the third node N3, and the potential at the second node N2 is VN3=VGH, so that the tenth transistor M10 is turned off according to the potential at the third node N3, and the tenth transistor M10 cannot transmit the first level signal VGH to the output end of the second output module 400. After the ninth transistor M9 is turned on, the second level signal VGL is transmitted to the output end of the second output module 400, that is, in the first stage T1, the second output signal Em_out output by the second output end of the shift register 10 is also a low level signal.

[0093] In the second stage T2, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0094] When the shift register 10 operates in the second stage T2, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0095] After the first transistor M1 is turned off, due to the potential holding effect of the first capacitor C1, the first node N1 is still a low level signal at the beginning, so the third transistor M3 is turned on according to the potential at the first node N1, and transmits the second clock signal SCK2 to the fourth node N4. At this time, the second clock signal SCK2 is a low level signal, so the potential at the fourth node N4 becomes VN4=VGL. Due to the potential holding effect of the first capacitor C1, that is, the potential difference between the two plates of the first capacitor C1 remains unchanged, therefore, when the potential at the second end of the first capacitor C1 changes to VGL as the potential of the fourth node N4 changes, the potential at the first end of the first capacitor C1 will also change accordingly, that is, the potential at the first node N1 will become VN1≈VGL-Vth+(Cgs1+1) / ((Cgs1+C1+Cother)*(VGH-VGL)). Wherein, Cgs1 represents the parasitic capacitance between the gate and the source and drain of the third transistor M3, Cother represents other parasitic capacitances in the circuit, and C1 represents the first capacitor.

[0096] Since the potential at the fourth node N4 is at a low level, the fifth transistor M5 is turned on according to the potential at the fourth node N4, and the sixth transistor M6 is turned off according to the potential at the fourth node N4. After the fifth transistor M5 is turned on, the fifth transistor M5 transmits the first level signal VGH to the output end of the first output module 300. Since the sixth transistor M6 is turned off, the sixth transistor M6 cannot transmit the second level signal VGL to the output end of the first output module 300, that is, in the second stage T2, the first output signal Sn_out outputted by the first output end of the shift register 10 is a high level signal.

[0097] After the second transistor M2 is turned on, the second transistor M2 transmits the second input signal EIN to the second node N2. Since the second input signal EIN is a high-level signal, the potential of the second node N2 is VN2=VGH. The seventh transistor M7 and the ninth transistor M9 are both cut off according to the potential at the second node N2, so that the seventh transistor M7 cannot transmit the first-level signal VGH to the third node N3, and the ninth transistor M9 cannot transmit the second-level signal VGL to the output end of the second output module 400. At the same time, since the potential at the fourth node N4 is a low level, the eighth transistor M8 is turned on according to the potential at the fourth node N4, and transmits the second-level signal VGL to the third node N3, that is, the potential at the third node N3 becomes VN3=VGL. The tenth transistor M10 is turned on according to the potential at the third node N3, and transmits the first-level signal VGH to the output end of the second output module 400, that is, in the second stage T2, the second output signal Em_out output by the second output end of the shift register 10 is also a high-level signal.

[0098] In the third stage T3 , the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0099] When the shift register 10 operates in the third stage T3, since the first clock signal SCK1 is a low level signal, the second clock signal SCK2 is a high level signal, and the second input signal EIN is a high level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0100] After the first transistor M1 is turned on, the first transistor M1 transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a high-level signal, so that the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. Due to the potential holding effect of the first capacitor C1, when the potential at the first end of the first capacitor C1 increases with the potential of the fourth node N4, the potential at the second end of the first capacitor C1 will also increase accordingly, so the level at the fourth node N4 is also a high level. The fifth transistor M5 is turned off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. After the fifth transistor M5 is turned off, it is unable to transmit the first-level signal VGH to the output end of the first output module 300. After the sixth transistor M6 is turned on, the second-level signal VGL is transmitted to the output end of the first output module 300, that is, in the third stage T3, the first output signal Sn_out output by the first output end of the shift register 10 is a low-level signal.

[0101] The second transistor M2 is turned off, and the potential of the second node N2 is maintained, that is, the same as in the second stage T2, and the potential at the second node N2 is VN2=VGH. The seventh transistor M7 and the ninth transistor M9 are both turned off according to the potential at the second node N2, so that the seventh transistor M7 cannot transmit the first level signal VGH to the third node N3, and the ninth transistor M9 cannot transmit the second level signal VGL to the output end of the second output module 400. At the same time, since the potential at the fourth node N4 is high, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and the eighth transistor M8 cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is also maintained, the same as in the second stage T2, and the potential at the third node N3 is VN3=VGL. The tenth transistor M10 is turned on according to the potential at the third node N3, and transmits the first level signal VGH to the output end of the second output module 400, that is, in the third stage T3, the second output signal Em_out output by the second output end of the shift register 10 is still a high level signal.

[0102] In the fourth stage T4, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0103] When the shift register 10 operates in the fourth stage T4, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0104] After the first transistor M1 is turned off, the potential at the first node N1 remains the same as that in the third stage T3, and the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. In this embodiment, since the fourth node N4 of the i-th shift register 10 is connected to the input end of the first input module 100 of the i+1-th shift register 10, and the electrical signal at the fourth node N4 of the i-th shift register 10 is a signal of the first input signal SIN of the i-th shift register 10 delayed by one clock unit, the electrical signal at the fourth node N4 of the i+2-th shift register 10 is a signal of the first input signal SIN of the i-th shift register 10 delayed by two clock units.

[0105] At the same time, since the gate of the eleventh transistor M11 in the i-th shift register 10 is connected to the fourth node N4 in the i+2-th stage shift register 10, the potential at the gate of the eleventh transistor M11 in the i-th shift register 10 in the fourth stage T4 is the same as the potential at the fourth node N4 in the i-th shift register 10 in the second stage T2. The potential at the fourth node N4 in the second stage T2 is a low level, so that the potential at the gate of the eleventh transistor M11 in the fourth node T4 is a low level. The eleventh transistor M11 is turned on according to the potential at the gate, and transmits the first level signal VGH to the fourth node N4, that is, the potential at the fourth node N4 is VN4=VGH.

[0106] The fifth transistor M5 is turned off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. After the fifth transistor M5 is turned off, it cannot transmit the first level signal VGH to the output end of the first output module 300, and after the sixth transistor M6 is turned on, it transmits the second level signal VGL to the output end of the first output module 300, that is, in the fourth stage T4, the first output signal Sn_out outputted by the first output end of the shift register 10 is still a low level signal.

[0107] The second transistor M2 is turned on, and the second transistor M2 transmits the second input signal EIN to the second node N2, and the second input signal EIN is at a high level, that is, the potential at the second node N2 is VN2=VGH. The seventh transistor M7 and the ninth transistor M9 are both turned off according to the potential at the second node N2, so that the seventh transistor M7 cannot transmit the first level signal VGH to the third node N3, and the ninth transistor M9 cannot transmit the second level signal VGL to the output end of the second output module 400. At the same time, since the potential at the fourth node N4 is at a high level, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and the eighth transistor M8 cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is still maintained, the same as in the third stage T3, and the potential at the third node N3 is VN3=VGL. The tenth transistor M10 is turned on according to the potential at the third node N3 and transmits the first level signal VGH to the output end of the second output module 400 , that is, in the third stage T3 , the second output signal Em_out outputted by the second output end of the shift register 10 is still a high level signal.

[0108] In the fifth stage T5 , the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0109] When the shift register 10 operates in the fifth stage T5, since the first clock signal SCK1 is a low level signal, the second clock signal SCK2 is a high level signal, and the second input signal EIN is a low level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0110] After the first transistor M1 is turned on, the first transistor M1 transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a high-level signal, so that the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. After the fourth transistor M4 is turned on, the fourth transistor M4 transmits the first-level signal VGH to the fourth node N4, that is, the potential of the fourth node N4 is VN4=VGH. The fifth transistor M5 is turned off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. After the fifth transistor M5 is turned off, it is unable to transmit the first-level signal VGH to the output end of the first output module 300. After the sixth transistor M6 is turned on, it transmits the second-level signal VGL to the output end of the first output module 300, that is, in the fifth stage T5, the first output signal Sn_out output by the first output end of the shift register 10 is still a low-level signal.

[0111] The second transistor M2 is turned off, and the potential of the second node N2 is maintained, that is, the same as in the fourth stage T4, and the potential at the second node N2 is VN2=VGH. The seventh transistor M7 and the ninth transistor M9 are both turned off according to the potential at the second node N2. At the same time, since the potential at the fourth node N4 is a high level, the eighth transistor M8 is turned off according to the potential at the fourth node N4. That is, the potential at the third node N3 is also maintained, the same as in the second stage T2, and the potential at the third node N3 is VN3=VGL. The tenth transistor M10 is turned on according to the potential at the third node N3, and transmits the first level signal VGH to the output end of the second output module 400, that is, in the third stage T3, the second output signal Em_out output by the second output end of the shift register 10 is still a high level signal.

[0112] In the sixth stage T6 , the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0113] When the shift register 10 operates in the sixth stage T6, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a low-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0114] After the first transistor M1 is turned off, the potential at the first node N1 is maintained, which is the same as in the fifth stage T5, and the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. Due to the potential holding effect of the first capacitor C1, the potential at the fourth node N1 is also maintained, which is the same as in the fifth stage T5, and the potential at the fourth node N4 is VN4=VGH. The fifth transistor M5 is turned off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. After the fifth transistor M5 is turned off, it is unable to transmit the first level signal VGH to the output end of the first output module 300. After the sixth transistor M6 is turned on, the second level signal VGL is transmitted to the output end of the first output module 300, that is, in the sixth stage T6, the first output signal Sn_out outputted by the first output end of the shift register 10 is still a low level signal.

[0115] The second transistor M2 is turned on, and the second transistor M2 transmits the second input signal EIN to the second node N2, and the second input signal EIN is at a low level, that is, the potential at the second node N2 is VN2=VGL-Vth. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2, the seventh transistor M7 transmits the first level signal VGH to the third node N3, and the ninth transistor M9 transmits the second level signal VGL to the output end of the second output module 400. At the same time, since the potential at the fourth node N4 is at a high level, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and the eighth transistor M8 cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is VN3=VGH. The tenth transistor M10 is turned off according to the potential at the third node N3. In the sixth stage T6, the second output signal Em_out output by the second output end of the shift register 10 is a low level signal.

[0116] In the seventh stage T7 , the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0117] When the shift register 10 operates in the seventh stage T7, since the first clock signal SCK1 is a low level signal, the second clock signal SCK2 is a high level signal, and the second input signal EIN is a low level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0118] After the first transistor M1 is turned on, the first transistor M1 transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a high-level signal, and the potential at the first node N1 is VN1=VGH. The third transistor M3 is cut off according to the potential at the first node N1. After the fourth transistor M4 is turned on, the fourth transistor M4 transmits the first-level signal VGH to the fourth node N4, that is, the potential of the fourth node N4 is VN4=VGH. The fifth transistor M5 is cut off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. In the fifth stage T5, the first output signal Sn_out outputted by the first output terminal of the shift register 10 is still a low-level signal.

[0119] The second transistor M2 is turned off, and the potential of the second node N2 is maintained, that is, the same as in the sixth stage T6, and the potential at the second node N2 is VN2=VGL-Vth. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2, and the seventh transistor M7 transmits the first level signal VGH to the third node N3, and the ninth transistor M9 transmits the second level signal VGL to the output end of the second output module 400. At the same time, since the potential at the fourth node N4 is a high level, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and the eighth transistor M8 cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is VN3=VGH. The tenth transistor M10 is turned off according to the potential at the third node N3. In the sixth stage T6, the second output signal Em_out output by the second output end of the shift register 10 is a low level signal.

[0120] In the eighth stage T8 , the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0121] When the shift register 10 operates in the eighth stage T8, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a low-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0122] After the first transistor M1 is turned off, the potential at the first node N1 is maintained, which is the same as in the fifth stage T5, and the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. Due to the potential holding effect of the first capacitor C1, the potential at the fourth node N1 is also maintained, which is the same as in the fifth stage T5, and the potential at the fourth node N4 is VN4=VGH. The fifth transistor M5 is turned off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. After the fifth transistor M5 is turned off, it is unable to transmit the first level signal VGH to the output end of the first output module 300. After the sixth transistor M6 is turned on, the second level signal VGL is transmitted to the output end of the first output module 300, that is, in the eighth stage T8, the first output signal Sn_out outputted by the first output end of the shift register 10 is still a low level signal.

[0123] The second transistor M2 is turned on, and the second transistor M2 transmits the second input signal EIN to the second node N2, and the second input signal EIN is at a low level, that is, the potential at the second node N2 is VN2=VGL-Vth. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2, the seventh transistor M7 transmits the first level signal VGH to the third node N3, and the ninth transistor M9 transmits the second level signal VGL to the output end of the second output module 400. At the same time, since the potential at the fourth node N4 is at a high level, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and the eighth transistor M8 cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is VN3=VGH. The tenth transistor M10 is turned off according to the potential at the third node N3. In the eighth stage T8, the second output signal Em_out output by the second output end of the shift register 10 is a low level signal.

[0124] In this embodiment, preferably, the fourth node N4 in the i-th stage shift register 10 is connected to the input end of the first input module 100 in the i+1-th stage shift register 10, and the output end of the second output module 400 in the i-th stage shift register 10 is connected to the input end of the second input module 200 in the i+1-th stage shift register 10.

[0125] The driving method of the shift register is applied to the shift register 10 described in any one of the above embodiments, and the first input module 100 and the first output module 300 cooperate to output the first output signal Sn_out. The first output signal Sn_out can be transmitted to the pixel circuit as a gate drive signal to drive the functional module in the pixel circuit to work; the second input module 200 and the second output module 200 cooperate to output the second output signal Em_out, and the second output signal Em_out can also be transmitted to the pixel circuit as a gate drive signal to drive the functional module in the pixel circuit to work.

[0126] according to Figure 6 As shown in the timing diagram, the first output signal Sn_out and the second output signal Em_out are both high-level pulse signals, the difference being that the pulse width of the first output signal Sn_out is different from the pulse width of the second output signal Em_out. At the same time, the pulse width of the second output signal Em_out output by the shift register 10 is controlled by the second input signal EIN, so the high-level output time of the second output signal Em_out can be adjusted by adjusting the high-level duration of the second input signal EIN. By making the high-level time of the second output signal Em_out adjustable, the lighting effect of the screen can be ensured by adjusting the high-level duration of the second output signal Em_out when debugging the screen later.

[0127] The present application provides a novel circuit structure of a shift register 10, which can realize the simultaneous output of high-level pulse signals with different pulse widths, and ensure the output reliability of the shift register 10 while ensuring that the pixel circuit in the screen can work normally. Compared with the existing solution that requires two Scan circuits to realize the simultaneous output of high-level pulse signals with different pulse widths, only one shift register 10 is needed in the present application. Therefore, when the shift register 10 provided by the present application is applied to a display device, the number of shift register 10 groups, CLK signals and TFT devices in the display device can be reduced, thereby reducing the layout space occupied by the shift register 10, which is conducive to achieving the technical effects of narrow borders and low power consumption.

[0128] It should be understood that, although the steps in the flowcharts of the accompanying drawings of the specification are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts of the accompanying drawings of the specification may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0129] An embodiment of the present invention further provides a gate driving circuit, which may include a plurality of cascaded shift registers as described in any one of the above embodiments. Figure 7 This is a schematic diagram of the structure of the gate drive circuit in one embodiment of the present application. In one embodiment, the gate drive circuit may include an n-stage shift register 10, where n is an integer greater than zero. Each stage of the shift register 10 may include a first input module 100, a second input module 200, a first output module 300, and a second output module 400, and the first output module 300 may include a first output control module 310. In the n-stage shift register 10, except for the n-stage shift register 10, the signal output by the first output control module 310 of the i-stage shift register is used as the first input signal SIN of the i+1-stage shift register 10, and the second output signal Em_out output by the second output module 400 of the i-stage shift register 10 can be used as the second input signal EIN of the i+1-stage shift register 10; wherein n is an integer greater than zero, i=1,2,3,...,n.

[0130] like Figure 7 As shown, the first output signal Sn_out output by the first output module 300 in the first-stage shift register 10 can be used as the first input signal SIN connected to the first input module 100 in the second-stage shift register 10; the second output signal Em_out output by the second output module 400 in the first-stage shift register 10 can be used as the second input signal connected to the second input module 200 in the second-stage shift register 10.

[0131] In the above gate drive circuit, the first input signal SIN connected to the input end of the first input module 100 in the first stage shift register 10 may be an independent input signal, or a signal output by the first output control module 310 in the nth stage shift register 10; the second input signal EIN connected to the input end of the second input module 200 in the first stage shift register 10 may be an independent input signal, or a second output signal Em_out output by the second output module 400 in the nth stage shift register 10. The first input signal SIN connected to the input end of the first input module 100 in the i-th stage shift register 10 may be a signal output by the first output control module 310 in the i-1th stage shift register 10 (where i=2, 3, 4, ..., n); the second input signal EIN connected to the input end of the second input module 200 in the i-th stage shift register 10 may be a second output signal Em_out output by the second output module 400 in the i-1th stage shift register 10.

[0132] In the above-mentioned gate drive circuit, each level of shift register 10 can output two pulse signals with different pulse widths, which reduces the space occupied by the gate drive circuit. When the above-mentioned gate drive circuit is applied to a display panel, the left and right borders can be greatly saved, and the technical effect of a narrow border can be achieved. At the same time, the cascade shift trigger between each level of shift register 10 has a high circuit stability.

[0133] In one embodiment, in addition to the nth stage shift register 10 and the n-1th stage shift register 10, the signal N4_2 output by the first output control module 310 of the i+2th stage shift register 10 can be used as the cascade signal Cn connected to the i-th stage shift register 10. That is, the fourth node N4 of the i+2th stage shift register 10 can be connected to the control end of the cascade module 500 in the i-th stage shift register 10. For example, Figure 7 As shown, the signal at the fourth node N4 in the third-stage shift register 10 serves as the cascade signal Cn connected to the i-th-stage shift register 10 .

[0134] In the above gate driving circuit, the cascade signal Cn connected to the control end of the cascade module 500 in the n-1th stage shift register 10 can be an independent input signal, or it can be the signal output by the first output control module 310 in the first stage shift register 10; the cascade signal Cn connected to the control end of the cascade module 500 in the nth stage shift register 10 can be an independent input signal, or it can be the signal output by the first output control module 310 in the second stage shift register 10. The cascade signal Cn connected to the control end of the cascade module 500 in the i-th stage shift register 10 can be the signal output by the first output control module 310 in the i+2th stage shift register 10 (where i=2, 3, 4, ..., n).

[0135] An embodiment of the present invention further provides a display panel, which includes the gate drive circuit described in any one of the above embodiments. The display panel may include one or more groups of gate drive circuits. Among them, the gate drive circuit can be configured to generate a gate drive signal and use the gate drive signal to change the conduction state of the switch device in the pixel circuit. The display panel can be applied to any product or component with a display function, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop displays, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiments of the present invention do not specifically limit this.

[0136] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0137] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.

Claims

1. A shift register, characterized in that: It includes a first input module, a second input module, a first output module and a second output module, wherein the control end of the first output module includes a first control end and a second control end, and the control end of the second output module includes a first control end and a second control end, The output end of the first input module is connected to the first control end of the first output module, and the first input module is configured to transmit the first input signal to the first control end of the first output module according to the first clock signal; The input end of the second input module is connected to the second control end of the first output module, the output end of the second input module is connected to the first control end of the second output module, and the second input module is configured to transmit the second input signal to the first control end of the second output module according to the second clock signal; The first output module is configured to output a first output signal according to a signal at a control terminal of the first output module; The second control end of the second output module is connected to the first output module, and the second output module is configured to output a second output signal according to a signal at the control end of the second output module.

2. The shift register according to claim 1, characterized in that: The first output module includes a first output control unit, a second output control unit, a first output unit, and a second output unit. The control end of the first output control unit serves as the first control end of the first output module, and the control end of the second output control module serves as the second control end of the first output module. The first end of the first output control unit is connected to the second clock signal, the control end of the first output control unit is connected to the output end of the first input module, the second end of the first output control unit is connected to the control end of the first output unit and the control end of the second output unit respectively, and the first output control unit is configured to transmit the second clock signal to the control end of the first output unit and the control end of the second output unit according to the signal at the control end of the first output control unit; The first end of the second output control unit is connected to the first level signal, the control end of the second output control unit is connected to the input end of the second input module, the second end of the second output control unit is respectively connected to the control end of the first output unit and the control end of the second output unit, and the second output control unit is configured to transmit the first level signal to the control end of the first output unit and the control end of the second output unit according to the signal at the control end of the second output control unit; The first end of the first output unit is connected to a first level signal, the second end of the first output unit is connected to an output end of the first output module, and the first output unit is configured to transmit the first level signal to the output end of the first output module according to a signal at a control end of the first output unit; The first end of the second output unit is connected to the second level signal, the second end of the second output unit is connected to the output end of the first output module, and the second output unit is configured to transmit the second level signal to the output end of the first output module according to the signal at the control end of the second output unit; Preferably, the first output control unit includes a third transistor, a first electrode of the third transistor serves as a first end of the first output control unit, a gate of the third transistor serves as a control end of the first output control unit, and a second electrode of the third transistor serves as a second end of the first output control unit; The second output control unit includes a fourth transistor, a first electrode of the fourth transistor serves as a first end of the second output control unit, a gate of the fourth transistor serves as a control end of the second output control unit, and a second electrode of the fourth transistor serves as a second end of the second output control unit; The first output unit includes a fifth transistor, a first electrode of the fifth transistor serves as a first end of the first output unit, a gate of the fifth transistor serves as a control end of the first output unit, and a second electrode of the fifth transistor serves as a second end of the first output unit; The second output unit includes a sixth transistor, a first electrode of the sixth transistor serves as a first end of the second output unit, a gate of the sixth transistor serves as a control end of the second output unit, and a second electrode of the sixth transistor serves as a second end of the second output unit; Preferably, the conduction level of the fifth transistor is different from the conduction level of the sixth transistor; Preferably, a pulse width of the first output signal is different from a pulse width of the second output signal.

3. The shift register according to claim 2, characterized in that: The first output module further includes a first voltage holding unit, the first potential holding unit being connected between the control end of the second output control unit and the second end of the second output control unit, and being used to hold the potential between the control end of the second output control unit and the second end of the second output control unit; Preferably, the first potential holding unit includes a first capacitor, a first end of the first capacitor is connected to a control end of the second output control unit, and a second end of the first capacitor is connected to a second end of the second output control unit.

4. The shift register according to claim 1 or 2, characterized in that: The second output module includes a third output control unit, a fourth output control unit, a third output unit and a fourth output unit, the control end of the third output control unit serves as the first control end of the second output module, and the control end of the fourth output control module serves as the second control end of the second output module. The first end of the third output control unit is connected to the first level signal, the control end of the third output control unit is connected to the output end of the second input module, the second end of the third output control unit is connected to the control end of the fourth output unit, and the third output control unit is configured to transmit the first level signal to the control end of the fourth output unit according to the signal at the control end of the third output control unit; The first end of the fourth output control unit is connected to the second level signal, the control end of the fourth output control unit is connected to the first output module, the second end of the fourth output control unit is connected to the control end of the fourth output unit, and the fourth output control unit is configured to transmit the second level signal to the control end of the fourth output unit according to the signal at the control end of the fourth output control unit; The first end of the third output unit is connected to the second level signal, the control end of the third output unit is connected to the output end of the second input module, the second end of the third output unit is connected to the output end of the second output module, and the third output unit is configured to transmit the second level signal to the output end of the second output module according to the signal at the control end of the third output unit; The first end of the fourth output unit is connected to the first level signal, the second end of the fourth output unit is connected to the output end of the second output module, and the fourth output unit is configured to transmit the first level signal to the output end of the second output module according to the signal at the control end of the fourth output unit; Preferably, the third output control unit includes a seventh transistor, the first electrode of the seventh transistor serves as the first end of the third output control unit, the gate of the seventh transistor serves as the control end of the third output control unit, and the second electrode of the seventh transistor serves as the second end of the third output control unit; The fourth output control unit includes an eighth transistor, the first electrode of the eighth transistor serves as the first end of the fourth output control unit, the gate of the eighth transistor serves as the control end of the fourth output control unit, and the second electrode of the eighth transistor serves as the second end of the fourth output control unit; The third output unit includes a ninth transistor, a first electrode of the ninth transistor serves as a first end of the third output unit, a gate of the ninth transistor serves as a control end of the third output unit, and a second electrode of the ninth transistor serves as a second end of the third output unit; The fourth output unit includes a tenth transistor, a first electrode of the tenth transistor serves as a first end of the fourth output unit, a gate of the tenth transistor serves as a control end of the fourth output unit, and a second electrode of the tenth transistor serves as a second end of the fourth output unit.

5. The shift register according to claim 4, characterized in that: The second output module further includes a second potential holding unit, which is connected between the first end of the fourth output unit and the control end of the fourth output unit and is used to hold the potential between the first end of the fourth output unit and the control end of the fourth output unit; Preferably, the second potential holding unit comprises a second capacitor, a first end of the second capacitor is connected to the first end of the fourth output unit, and a second end of the second capacitor is connected to the control end of the fourth output unit.

6. The shift register according to claim 2, characterized in that: The first input module comprises a first transistor, a first electrode of the first transistor is connected to the first input signal, a gate of the first transistor is connected to the first clock signal, and a second electrode of the first transistor serves as an output end of the first input module; The second input module includes a second transistor, a first electrode of the second transistor is connected to the second input signal, a gate of the second transistor is connected to the second clock signal, and a second electrode of the second transistor serves as an output end of the second input module.

7. The shift register according to claim 1 or 2, characterized in that: The shift register further includes a cascade module, an input end of the cascade module is connected to a first level signal, an output end of the cascade module is connected to the first output module, and the cascade module is configured to transmit the first level signal to the first output module according to the cascade signal; Preferably, the cascade module includes an eleventh transistor, a first electrode of the eleventh transistor serves as an input end of the cascade module, a gate of the eleventh transistor is connected to the cascade signal, and a second electrode of the eleventh transistor serves as an output end of the cascade module.

8. A gate drive circuit, characterized in that: Comprising n cascaded shift registers as described in any one of claims 1 to 7, except for the shift register of the nth stage, the signal output by the first output control module of the shift register of the i-th stage serves as the first input signal of the shift register of the i+1th stage, and the second output signal output by the second output module of the shift register of the i-th stage serves as the second input signal of the shift register of the i+1th stage; wherein n is an integer greater than zero, i=1,2,3,...,n.

9. The gate driving circuit according to claim 8, characterized in that: In addition to the shift register at the nth stage and the shift register at the n-1th stage, the signal output by the first output control module of the shift register at the i+2th stage serves as the cascade signal connected to the shift register at the ith stage.

10. A display panel, characterized in that: Comprising the gate drive circuit as described in any one of claims 8 to 9.

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