Display panel, driving method thereof and display device

Abstract

The invention relates to a display panel, a driving method thereof and a display device, and relates to the technical field of display. The display panel comprises a gate drive circuit, at least two starting signal lines and pixel circuits arranged in an array. The gate driving circuit comprises at least two gate driving modules, and each gate driving module is connected with the starting signal line and the pixel circuit; each gate driving module comprises N + m cascaded gate driving units, in each gate driving module, the first-stage gate driving unit is connected with a corresponding starting signal line, the ith-stage gate driving unit is connected with the jth-row pixel circuit, the ith-stage gate driving unit provides a first scanning signal for the jth-row pixel circuit, and the ith-stage gate driving unit provides a second scanning signal for the jth-row pixel circuit; and the (i + m) th-level gate driving unit is connected with the jth row of pixel circuits, and provides a second scanning signal for the jth row of pixel circuits. According to the display panel provided by the invention, partitioned multi-frequency display and a narrow frame can be realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] At present, display panel technology is constantly developing, and OLED (Organic Light-Emitting Diode) devices and other light-emitting devices have gradually been applied to various display panel products such as mobile phones, tablets, and notebooks.

[0003] With the gradual promotion of OLED foldable technology, the proportion of foldable screens in display panel products is also gradually increasing. Since foldable screen products can be folded during use, the overall display area is divided into multiple different display areas, and split-screen display or overall display of each display area is realized according to different display content and different application scenarios. In scenarios such as partitioned display, there are multiple display scenarios on the same screen. Reducing the refresh frequency of some display areas without affecting the display effect can reduce the power consumption of electronic devices.

[0004] The display panel provides a scanning signal to the pixel circuit through the gate driving circuit, and controls the pixel circuit in the display panel to drive row by row. However, in order to realize the partition multi-frequency display, it is usually necessary to set multiple groups of gate driving circuits, which will lead to an increase in the frame. Summary of the invention

[0005] Based on this, it is necessary to provide a display panel and a driving method and a display device thereof that can achieve partitioned multi-frequency display and narrow bezel in order to address the above technical problems.

[0006] In a first aspect, the present application provides a display panel, comprising a gate driving circuit, at least two start signal lines, and pixel circuits arranged in an array;

[0007] The gate driving circuit comprises at least two gate driving modules, each of which is connected to the start signal line and the pixel circuit respectively, and different gate driving modules are connected to different start signal lines and pixel circuits;

[0008] Each of the gate driving modules includes N+m cascaded gate driving units, in each of the gate driving modules, the first-level gate driving unit is connected to the corresponding start signal line, the i-th-level gate driving unit is connected to the j-th row pixel circuit, the i-th-level gate driving unit provides a first scanning signal for the j-th row pixel circuit, the i+m-th-level gate driving unit is connected to the j-th row pixel circuit, and the i+m-th-level gate driving unit provides a second scanning signal for the j-th row pixel circuit, wherein 1≤m≤N-1, i traverses from 1 to N, j traverses from P to P+N-1, P represents the number of rows of the first row of pixel circuits connected to the gate driving module in the display panel, and N represents the number of pixel circuit rows connected to the gate driving module.

[0009] In one embodiment, the frequencies of the start signals provided by at least two of the start signal lines are different.

[0010] In one embodiment, the start signal lines provide start signals with the same frequency.

[0011] In one of the embodiments, the display panel further includes a clock signal line, and the clock signal line is connected to each of the gate driving units respectively.

[0012] In one embodiment, the display panel further includes a first power signal line and a second power signal line, the first power signal line is connected to each of the gate driving units respectively, and the second power signal line is connected to each of the gate driving units respectively.

[0013] In one embodiment, the gate driving unit includes a first output end and a second output end, the first output end is used to provide the first scanning signal, and the second output end is used to provide the second scanning signal, wherein, in each of the gate driving modules, the first output end of the first m-level gate driving unit is connected to the corresponding pixel circuit, the second output end of the first m-level gate driving unit is in a suspended state or connected to the virtual pixel circuit, the first output end of the rear m-level gate driving unit is in a suspended state or connected to the virtual pixel circuit, and the second output end of the rear m-level gate driving unit is connected to the corresponding pixel circuit.

[0014] In one embodiment, the gate driving units in the gate driving circuit are arranged along a column direction of the pixel circuit, and a distance between any two adjacent gate driving units is the same.

[0015] In one of the embodiments, in the gate driving circuit, the first gate driving unit in the direction of the pixel circuit column is flush with the first row of pixel circuits in the direction of the pixel circuit row, the last gate driving unit in the direction of the pixel circuit column is flush with the last row of pixel circuits in the direction of the pixel circuit row, and the remaining gate driving units and the remaining pixel circuits are staggered row by row in the direction of the pixel circuit row.

[0016] In one of the embodiments, in the gate driving module, N+m cascaded gate driving units are evenly spaced and distributed, and the distance between any adjacent gate driving units is the same.

[0017] In one embodiment, the distance between adjacent gate driving modules is the same as the distance between adjacent gate driving units.

[0018] In one embodiment, the display panel also includes a plurality of connection line groups, each of the connection line groups includes a main connection line and at least one branch connection line, in each of the connection line groups, the main connection line is respectively connected to the output end of the gate driving unit and each of the branch connection lines, different main connection lines are connected to different gate driving units, the main connection lines extend along the row direction of the pixel circuit, and the branch connection lines extend along the column direction of the pixel circuit; wherein each of the gate driving units is connected to the pixel circuit via at least one branch connection line.

[0019] In one embodiment, the display panel includes a first connection line group and a second connection line group, wherein the first connection line group includes the main connection line and a target branch connection line, the second connection line group includes the main connection line, a first branch connection line and a second branch connection line, a first end of the first branch connection line and a first end of the second branch connection line are respectively connected to the main connection line in the same second connection line group, the second end of the first branch connection line and the second end of the second branch connection line extend in opposite directions, and the target branch connection line includes the first branch connection line or the second branch connection line;

[0020] In each of the gate driving modules, the first m-level gate driving units are connected to the pixel circuits of the corresponding rows through the target branch connection lines, the second m-level gate driving units are connected to the pixel circuits of the corresponding rows through the target branch connection lines, the k+m-th level gate driving units are connected to the pixel circuits of the r+m-th row through the first branch connection lines, and the k+m-th level gate driving units are connected to the pixel circuits of the r-th row through the second branch connection lines, wherein k traverses from 1 to Nm, and r traverses from P to P+Nm;

[0021] In one of the embodiments, the target connection lines of each of the gate driving units are parallel to each other, and the target connection lines include at least one of the main connection lines and the branch connection lines.

[0022] In one embodiment, in each of the gate driving modules, the distances between the target connection lines of any two adjacent gate driving units are equal.

[0023] In one embodiment, the display panel also includes a plurality of first scan lines and a plurality of second scan lines, the first scan lines are connected to pixel circuits located in the same row, the second scan lines are connected to pixel circuits located in the same row, the first scan lines provide the first scan signals to the pixel circuits, and the second scan lines provide the second scan signals to the pixel circuits, wherein the j-th row pixel circuits are connected to the i-th level gate driving unit through the first scan lines and the branch connection lines, and the j-th row pixel circuits are connected to the i+m-th level gate driving unit through the second scan lines and the branch connection lines.

[0024] In one embodiment, the pixel circuit includes a first initialization module and a threshold compensation module, wherein the first scan line is connected to the first initialization module of the pixel circuit located in the same row, and the first scan line provides the first scan signal to the first initialization module, and the second scan line is connected to the threshold compensation module of the pixel circuit located in the same row, and the second scan line provides the second scan line to the threshold compensation module.

[0025] In one embodiment, the pixel circuit includes a low temperature polysilicon transistor.

[0026] In one embodiment, the pixel circuit includes a low temperature polysilicon transistor and a low temperature polycrystalline oxide transistor.

[0027] In a second aspect, an embodiment of the present application provides a method for driving a display panel, which is applied to the above-mentioned display panel, and the method includes:

[0028] Controlling at least two start signal lines to provide start signals to the corresponding first-stage gate drive units respectively, so as to start at least two gate drive modules respectively;

[0029] In each of the at least two gate driving modules, the i-th level gate driving unit is controlled to provide a first scanning signal for the j-th row pixel circuit, and the i+m-th level gate driving unit is controlled to provide a second scanning signal for the j-th row pixel circuit, wherein 1≤m≤N-1, i traverses from 1 to N, and from P to P+N-1, P represents the number of rows of the first row of pixel circuits connected to the gate driving module, and N represents the number of pixel circuit rows connected to the gate driving module.

[0030] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel as described above.

[0031] The display panel and its driving method and display device include a gate driving circuit, at least two start signal lines and a pixel circuit arranged in an array. The gate driving circuit includes at least two gate driving modules, each of which is connected to the start signal line and the pixel circuit respectively. Different gate driving modules are connected to different start signal lines and pixel circuits. Therefore, the frequencies of scanning signals generated by different gate driving modules can be controlled respectively by different start signal lines, so that different gate driving modules can generate scanning signals of different frequencies under the action of the start signal lines to achieve partitioned multi-frequency display; and each gate driving module includes N+m cascaded gate driving units, and in each gate driving module, the first-stage gate driving unit is connected to The corresponding start signal lines are connected, the i-th level gate driving unit is connected to the j-th row pixel circuit, the i-th level gate driving unit provides a first scanning signal for the j-th row pixel circuit, the i+m-th level gate driving unit is connected to the j-th row pixel circuit, and the i+m-th level gate driving unit provides a second scanning signal for the j-th row pixel circuit. Since the m+1-th to Nm-th level gate driving units in each gate driving module can generate two scanning signals, that is, the staggered interconnection method is adopted to realize the multiplexing of some gate driving units in each gate driving module, and the corresponding gate driving modules are independently controlled in combination with different start signal lines. While realizing partition multi-frequency, the number of gate driving units is greatly reduced, and a narrow frame can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic diagram of the structure of a display panel;

[0034] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of the structure of a gate driving unit and a connecting wire group provided in an embodiment of the present application;

[0038] Figure 6 A schematic diagram of the structure of another gate driving unit and a connecting wire group provided in an embodiment of the present application;

[0039] Figure 7 A schematic diagram of the structure of another gate driving unit and a connecting wire group provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0041] Fig. 9 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of waveforms of a first scanning signal, a second scanning signal and a light-emitting control signal provided in an embodiment of the present application;

[0043] Fig.11 A schematic diagram of waveforms of a first scanning signal, a second scanning signal, and a third scanning signal provided in an embodiment of the present application;

[0044] Fig.12 A schematic diagram of a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0045] Fig.13 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0046] Description of reference numerals:

[0047] 1-display panel, 10-gate driving circuit, 110-gate driving module, 111-first gate driving module, 112-second gate driving module, 1100-gate driving unit, 20-start signal line, 21-first start signal line, 22-second start signal line, 31-first sub-display area, 32-second sub-display area, 300-pixel circuit, 301-first initialization module, 302-threshold compensation module, 40-virtual pixel circuit, 50-connecting line group, 51-first connecting line group, 52-second connecting line group, 510-main connecting line, 520-branch connecting line, 521-first branch connecting line, 522-second branch connecting line, 61-first scanning line, 62-second scanning line, 1000-gate driving unit, 2000-pixel circuit, 10000-display device. DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0051] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0052] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0053] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0054] When a statement such as "at least one (of)..." is located after a list of elements, it modifies the entire list of elements rather than the individual elements in the list. The term "and / or" as used herein includes any and all combinations of one or more related listed items. As used in the application documents, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0055] Electronic or electrical devices and / or any other related devices or components according to the embodiments of the concepts of the present application described herein (for example, a display device including a display panel and a display panel driver, wherein the display panel driver also includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and an emission driver) can be implemented using any appropriate hardware, firmware (such as a dedicated integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using standard storage devices (e.g., such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., such as CD-ROMs, flash drives, etc.). Moreover, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the concepts of the present application.

[0056] Although exemplary embodiments of display modules and display devices including display modules have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that display modules and display devices including display modules constructed according to the principles of the present application may be implemented in addition to those specifically described herein. The present application is also defined in the claims and their equivalents.

[0057] As described in the background technology, a gate drive circuit (GIP) is provided in the display panel, and the gate drive circuit includes a plurality of cascaded gate drive units, each of which is used to provide a scan signal to the pixel circuit, and control the pixel circuit in the display panel to drive row by row. In the related art, there is multiplexing of scan signals in the pixel circuit, that is, the signal is multiplexed by staggering the timing, so that one gate drive unit generates two scan signals. However, in the partition multi-frequency application, one gate drive unit needs to provide two scan signals with different frequencies at the partition position, and the current solution cannot achieve the problem of signal multiplexing.

[0058] by Figure 1 Taking the two partition display scenes shown as an example, when the third-level gate driving unit 1000 at the dividing line position is reused, it will drive the pixel circuits 2000 of the upper and lower partitions, that is, the second row of pixel circuits 2000 and the third row of pixel circuits 2000, respectively, to provide the scanning signal S1' to the second row of pixel circuits 2000 in the upper partition and the scanning signal S2' to the third row of pixel circuits 2000 in the lower partition. However, in the partition display scenario, the frequencies of the scanning signals S1' of the upper and lower partitions are different, and the frequencies of the scanning signals S2' of the upper and lower partitions are also different. Therefore, the third-level gate driving unit 1000 reused at the dividing line position needs to generate two scanning signals S1' and scanning signals S2' of different frequencies, which is not feasible. Therefore, in the related art, each partition needs to be provided with 2 groups of gate driving units 1000 to generate scanning signals S1' and scanning signals S2' respectively, a total of 4 groups of gate driving units 1000, and no signal reuse is performed, which will lead to an increase in the border.

[0059] In order to solve the above technical problems, the embodiments of the present application provide a display panel, a driving method thereof, and a display device, wherein redundant gate driving units are added to each partition at the boundary position of the partition multi-frequency display, and a plurality of different start signals are used to respectively start the gate driving units of each partition part, so that one gate driving unit generates two scanning signals, and partition multi-frequency display is realized, thereby realizing a narrow frame. The display panel, a driving method thereof, and a display device provided by the embodiments of the present application are described below in conjunction with the accompanying drawings.

[0060] Figure 2 and Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 2 and Figure 3As shown, in one embodiment, a display panel 1 is provided, which includes a gate drive circuit 10, at least two start signal lines 20, and pixel circuits 300 arranged in an array. Optionally, the display panel 1 includes a display area and a non-display area, wherein the display area includes a pixel circuit 300, and the non-display area includes a gate drive circuit 10 and at least two start signal lines 20. Exemplarily, the display area includes at least two sub-display areas, each sub-display area includes a plurality of rows of pixel circuits 300, and the refresh frequencies of different sub-display areas are different or the same, that is, partitioned multi-frequency display or full-screen same-frequency display is achieved through different sub-display areas.

[0061] The gate driving circuit 10 includes at least two gate driving modules 110. The number of gate driving modules 110 is greater than or equal to 2, and can be set accordingly according to the partition multi-frequency requirements of the display panel 1. Each gate driving module 110 is respectively connected to the start signal line 20 and the pixel circuit 300, and different gate driving modules 110 are connected to different start signal lines 20 and pixel circuits 300. Optionally, the gate driving module 110 corresponds to a sub-display area, that is, the gate driving module 110 is connected to the pixel circuit 300 located in the sub-display area. Different gate driving modules 110 correspond to different sub-display areas. Among them, the start signal line 20 is used to provide a start signal. The number of start signal lines 20 is greater than or equal to 2, and can be set accordingly according to the partition multi-frequency requirements of the display panel 1. Exemplarily, the number of gate driving modules 110 and the number of start signal lines 20 are respectively the number of sub-display areas for partition multi-frequency display. For example, Figure 2 and Figure 3 As shown, the gate driving circuit 10 includes a first gate driving module 111 and a second gate driving module 112, wherein the first-level gate driving unit 1100 of the first gate driving module 111 is connected to the first start signal line 21, and the first start signal line 21 provides a first start signal SIN1 for the first-level gate driving unit 1100 in the first gate driving module 111; the first-level gate driving unit 1100 of the second gate driving module 112 is connected to the second start signal line 22, and the second start signal line 22 provides a second start signal SIN2 for the first-level gate driving unit 1100 in the second gate driving module 112.

[0062] Each gate driving module 110 includes N+m cascaded gate driving units 1100. Wherein, N represents the number of pixel circuit 300 rows connected to the gate driving module 110, or, N represents the number of pixel circuit 300 rows in the sub-display area corresponding to the gate driving module 110. The number of pixel circuit 300 rows connected to different gate driving modules 110 may be the same or different. Exemplarily, the gate driving circuit 10 includes a first gate driving module 111 and a second gate driving module 112, and the display area includes a first sub-display area 31 and a second sub-display area 32, wherein the number of pixel circuit 300 rows in the first sub-display area 31 connected to the first gate driving module 111 is N1, and accordingly, the first gate driving module 111 includes N1+m cascaded gate driving units 1100; the number of pixel circuit 300 rows in the second sub-display area 32 connected to the second gate driving module 112 is N2, and accordingly, the second gate driving module 112 includes N2+m cascaded gate driving units 1100.

[0063] In each gate driving module 110, the first-level gate driving unit 1100 is connected to the corresponding start signal line 20. Different first-level gate driving units 1100 are connected to different start signal lines 20. The start signal line 20 provides a start signal for the first-level gate driving unit 1100 to drive the gate driving module 110 to generate a scan signal. The i-th level gate driving unit 1100 is connected to the j-th row pixel circuit 300, and the i-th level gate driving unit 1100 provides a first scan signal S1 for the j-th row pixel circuit 300. The i+m-th level gate driving unit 1100 is connected to the j-th row pixel circuit 300, and the i+m-th level gate driving unit 1100 provides a second scan signal S2 for the j-th row pixel circuit 300. That is, the first m-level gate driving units 1100 are respectively connected to a row of pixel circuits 300, and the first m-level gate driving units 1100 respectively provide the first scan signal S1 for the corresponding row of pixel circuits 300. The latter m-level gate driving units 1100 are respectively connected to a row of pixel circuits 300, and the latter m-level gate driving units 1100 respectively provide the second scanning signal S2 for the corresponding row of pixel circuits 300. Among the remaining N-2m gate driving units 1100, i.e., the 1+m-th to Nm-th level gate driving units 1100, each gate driving unit 1100 is respectively connected to two rows of pixel circuits 300 spaced m apart, and provides the second scanning signal S2 for the front row of the two rows of pixel circuits 300 connected thereto, and provides the first scanning signal S1 for the rear row of pixel circuits 300.

[0064] Wherein, 1≤m≤N-1, m represents the row time of the first scanning signal S1 and the second scanning signal S2 of the same row of pixel circuits 300, or in other words, m represents the row interval between the two rows of pixel circuits 300 connected to the gate driving unit 1100. m is a fixed value. The value of m in different gate driving modules 110 is the same. In the application, the value of m can be set according to the display driving requirements. For example, m can be 1, 2, 3 or other suitable values, which are not limited here. i traverses from 1 to N, that is, 1≤i≤N, and i increases from 1 to N one by one. j traverses from 1 to N, that is, P≤j≤P+N-1, and j increases from P to P+N-1 one by one, and P, N, m, and j are positive integers. Wherein, P represents the number of rows of the first row of pixel circuits 300 connected to the gate driving module 110 in the display panel 1. The P corresponding to different gate driving modules 110 is different. For example, the gate driving circuit 10 includes a first gate driving module 111 and a second gate driving module 112, wherein the first row of pixel circuits 300 connected to the first gate driving module 111 is the first row of pixel circuits 300, then its P=1; the first row of pixel circuits 300 connected to the second gate driving module 112 is the eighth row of pixel circuits 300, then its P=8.

[0065] For example, Figure 2 and Figure 3As shown, the gate driving circuit 10 includes a first gate driving module 111 and a second gate driving module 112, m=1, the first sub-display area 31 includes the pixel circuits 300 of the 1st to 4th rows, and the second sub-display area 32 includes the pixel circuits 300 of the 5th to 8th rows. Then, among the 5 gate driving units 1100 of the first gate driving module 111, the 1st to 4th level gate driving units 1100 are respectively connected to the pixel circuits 300 of the 1st to 4th rows in a one-to-one correspondence, so that the pixels of the corresponding rows The circuit 300 provides a first scanning signal S1, and the second to fifth gate driving units 1100 are respectively connected to the first to fourth rows of pixel circuits 300 in a one-to-one correspondence to provide the second scanning signal S2 to the pixel circuits 300 of the corresponding rows; in other words, the first-stage gate driving unit 1100 is connected to the first row of pixel circuits 300, and the first-stage gate driving unit 1100 provides the first scanning signal S1 to the first row of pixel circuits 300; the second-stage gate driving unit 1100 is respectively connected to the first row of pixel circuits 300, and the second-stage gate driving unit 1100 provides the first scanning signal S2 to the first row of pixel circuits 300; The first pixel circuit 300 and the second pixel circuit 300 are connected, and the second gate driving unit 1100 provides the second scanning signal S2 for the first pixel circuit 300, and provides the first scanning signal S1 for the second pixel circuit 300; the third gate driving unit 1100 is connected to the second pixel circuit 300 and the third pixel circuit 300, respectively, and the third gate driving unit 1100 provides the second scanning signal S2 for the second pixel circuit 300, and provides the first scanning signal S1 for the third pixel circuit 300. The first scanning signal S1 is provided to the 4th level gate driving unit 1100; the 4th level gate driving unit 1100 is connected to the 3rd row pixel circuit 300 and the 4th row pixel circuit 300 respectively, and the 4th level gate driving unit 1100 provides the 3rd row pixel circuit 300 with the second scanning signal S2, and provides the 4th row pixel circuit 300 with the first scanning signal S1; the 5th level gate driving unit 1100 is connected to the 4th row pixel circuit 300, and the 5th level gate driving unit 1100 provides the 4th row pixel circuit 300 with the second scanning signal S2. Among the 5 gate driving units 1100 of the second gate driving module 112, the 1st to 4th level gate driving units 1100 are connected to the 5th to 8th row pixel circuits 300 in a one-to-one correspondence, respectively, to provide the first scanning signal S1 to the corresponding row pixel circuits 300, and the 2nd to 5th level gate driving units 1100 are connected to the 5th to 8th row pixel circuits 300 in a one-to-one correspondence, respectively, to provide the second scanning signal S2 to the corresponding row pixel circuits 300. That is, the gate driving circuit 10 requires a total of 10 gate driving units 1100 .

[0066] It can be understood that in the related art, if the two sub-display areas in the above example are to be divided into multiple frequency display zones, that is, the first scanning signal S1 and the second scanning signal S2 need to be provided to the aforementioned 8 rows of pixel circuits 300 respectively, then four groups of gate driving units 1100 are required, wherein the first group of gate driving units 1100 includes 8 gate driving units 1100 to provide the first scanning signal S1 to the 8 rows of pixel circuits 300 in the first sub-display area 31, and the second group of gate driving units 1100 includes 8 gate driving units 1100 to provide the first scanning signal S1 to the 8 rows of pixel circuits 300 in the first sub-display area 31. The row pixel circuit 300 provides a second scanning signal S2, the third group of gate driving units 1100 includes 8 gate driving units 1100 to provide the first scanning signal S1 for the 8 rows of pixel circuits 300 in the second sub-display area 32, and the fourth group of gate driving units 1100 includes 8 gate driving units 1100 to provide the second scanning signal S2 for the 8 rows of pixel circuits 300 in the second sub-display area 32. A total of 32 gate driving units 1100 are required, and the number of gate driving units 1100 is much larger than the number of gate driving units 1100 of the present application.

[0067] In addition, for the 8 rows of pixel circuits 300 in the above example, in the application of the whole screen with the same frequency display in the related technology (partitioned multi-frequency display is not possible), the first scanning signal S1 and the second scanning signal S2 provided to the 8 rows of pixel circuits 300 are respectively provided by the gate driving unit 1100 in a staggered manner, and 9 cascaded gate driving units 1100 are required. It can be seen that the number of gate driving units 1100 in the present application is only increased by one compared with this. Compared with this, the gate driving circuit 10 provided in the present application is equivalent to replacing the 5th level gate driving unit 1100 in the related technology with the 5th level gate driving unit 1100 of the first gate driving module 111 provided in the embodiment of the present application, and the 1st level gate driving unit 1100 in the second gate driving module 112. It should be noted that the above description is only based on a small number of gate driving units 1100 as an example to help understand that in the application, the number of rows of pixel circuits 300 in each sub-display area can be set according to the actual partition display requirements.

[0068] In combination with the above examples, the display panel 1 capable of realizing partitioned multi-frequency display provided in the embodiment of the present application adopts the form of staggered multiplexing to realize the multiplexing of part of the gate driving units 1100 in each display partition. Compared with the scheme in the related art that cannot realize frequency division and multi-frequency and adopts staggered multiplexing, the number of gate driving units 1100 added in the present application is equal to the product of the number of partitions of partitioned multi-frequency display and the number of rows of staggered row time minus one; and, compared with the scheme for realizing frequency division and multi-frequency in the related art, the number of gate driving units 1100 is greatly reduced in the present application.

[0069] The display panel 1 includes a gate driving circuit 10, at least two start signal lines 20, and a pixel circuit 300 arranged in an array. The gate driving circuit 10 includes at least two gate driving modules 110. Each gate driving module 110 is connected to the start signal line 20 and the pixel circuit 300, respectively. Different gate driving modules 110 are connected to different start signal lines 20 and pixel circuits 300. Therefore, the frequencies of the scanning signals generated by different gate driving modules 110 can be controlled by different start signal lines 20, so that different gate driving modules 110 can generate scanning signals of different frequencies under the action of the start signal line 20 to achieve partitioned multi-frequency display. In addition, each gate driving module 110 includes N+m cascaded gate driving units 1100. In each gate driving module 110, the first-level gate driving unit 1100 is connected to the corresponding start signal line 20. 20 is connected, the i-th gate driving unit 1100 is connected to the j-th row pixel circuit 300, the i-th gate driving unit 1100 provides the first scanning signal S1 for the j-th row pixel circuit 300, the i+m-th gate driving unit 1100 is connected to the j-th row pixel circuit 300, and the i+m-th gate driving unit 1100 provides the second scanning signal S2 for the j-th row pixel circuit 300. Since the m+1-th to Nm-th gate driving units 1100 in each gate driving module 110 can generate two scanning signals, that is, the staggered interconnection method is adopted to realize the multiplexing of part of the gate driving units 1100 in each gate driving module 110, and the corresponding gate driving modules 110 are independently controlled in combination with different start signal lines 20. While realizing partition multi-frequency, the number of gate driving units 110 is also greatly reduced, and a narrow frame can be achieved.

[0070] Please continue reading Figure 2 and Figure 3 In one embodiment, the frequencies of the start signals provided by at least two start signal lines 20 are different. Since the frequency of the scan signal generated by the gate driving module 110 is related to the frequency of the start signal, the present application uses different start signal lines 20 to be connected to different gate driving modules 110 in a one-to-one correspondence, and start signals of different frequencies are provided through the start signal lines 20, so that different gate driving modules 110 can generate scan signals of different frequencies, thereby driving the pixel circuit 300 through scan signals of different frequencies, thereby realizing partitioned multi-frequency display and improving the display effect of the display panel 1. For example, Figure 2 and Figure 3Taking the display panel shown as an example, the display area includes a first sub-display area 31 and a second sub-display area 32. The display panel includes a first start signal line 21 and a second start signal line 22. The first start signal SIN1 is provided through the first start signal line 21 to control the frequency of the scan signal generated by the first gate drive module 111, so that the refresh frequency of the first sub-display area 31 corresponding to the first gate drive module 111 is 120Hz; at the same time, the second start signal SIN2 is provided through the second start signal line 22 to control the frequency of the scan signal generated by the second gate drive module 112, so that the refresh frequency of the second sub-display area 32 corresponding to the second gate drive module 112 is 1Hz, thereby realizing partitioned multi-frequency display and reducing power consumption.

[0071] Please continue reading Figure 2 and Figure 3 In one embodiment, the start signals provided by the start signal lines 20 have the same frequency. Based on this, the start signals of the same frequency are provided by the start signal lines 20, respectively, so that different gate driving modules 110 can generate scanning signals of the same frequency, thereby driving the pixel circuits 300 of each row of the entire display area through the scanning signals of the same frequency, thereby achieving the same frequency display of the entire screen and improving the display effect of the display panel 1.

[0072] In one embodiment, the display panel 1 further includes a clock signal line, and the clock signal line is respectively connected to each gate driving unit 1100. The clock signal line provides a clock signal to each gate driving unit 1100. In this way, each gate driving unit 1100 of different gate driving modules 110 can share the clock signal line, thereby realizing multiplexing of the clock signal line. There is no need to separately configure a clock signal line for each gate driving module 110, which is conducive to further realizing a narrow frame and can also reduce costs and process complexity.

[0073] In one embodiment, the display panel 1 further includes a first power signal line and a second power signal line, wherein the first power signal line is connected to each gate driving unit 1100, and the second power signal line is connected to each gate driving unit 1100. The first power signal line is used to provide a first power signal, and the second power signal line is used to provide a second power signal. In this way, each gate driving unit 1100 of different gate driving modules 110 can share the first power signal line and the second power signal line, thereby realizing the multiplexing of the first power signal line and the second power signal line. There is no need to separately configure the first power signal line and the second power signal line for each gate driving module 110, which is conducive to further realizing a narrow frame and can also reduce costs and process complexity.

[0074] Please continue reading Figure 2 and Figure 3In one embodiment, the gate driving unit 1100 includes a first output terminal and a second output terminal, the first output terminal is used to provide a first scanning signal, and the second output terminal is used to provide a second scanning signal. In each gate driving module 110, the first output terminal of the first m-level gate driving unit 1100 is connected to the corresponding pixel circuit, the second output terminal of the first m-level gate driving unit 1100 is in a suspended state or connected to a virtual pixel circuit 40 (Dummy), the first output terminal of the rear m-level gate driving unit 1100 is in a suspended state or connected to the virtual pixel circuit 40, and the second output terminal of the rear m-level gate driving unit 1100 is connected to the corresponding pixel circuit. Among them, the virtual pixel circuit 40 can be arranged along the row direction of the pixel circuit to form a row of virtual pixel circuits 40, and the gate driving unit 1100 can be connected to the row of virtual pixel circuits 40 to improve the uniformity of the display panel.

[0075] For example, Figure 2 The display panel 1 provided is taken as an example, wherein the display panel 1 includes a first start signal line 21 and a second start signal line 22, m=1, and a first gate drive module 111 of the gate drive circuit 10 includes five gate drive units 1100. Then, in the first gate drive module 111, a first output end of the first-level gate drive unit 1100 is connected to the first row pixel circuit 300, a second output end of the first-level gate drive unit 1100 and a first output end of the fifth-level gate drive unit 1100 are respectively in a suspended state, and the fifth-level gate drive unit 1100 is The second output end of 100 is connected to the 4th row pixel circuit 300; the second gate driving module 112 of the gate driving circuit 10 includes 5 gate driving units 1100, then in the second gate driving module 112, the first output end of the 1st level gate driving unit 1100 is connected to the 1st row pixel circuit 300, the second output end of the 1st level gate driving unit 1100 and the first output end of the 5th level gate driving unit 1100 are respectively in a suspended state, and the second output end of the 5th level gate driving unit 1100 is connected to the 4th row pixel circuit 300.

[0076] For example, Figure 3The display panel 1 provided is taken as an example, wherein the display panel 1 includes a first start signal line 21 and a second start signal line 22, m=1, and a first gate driving module 111 of the gate driving circuit 10 includes five gate driving units 1100. In the first gate driving module 111, a first output end of the first-level gate driving unit 1100 is connected to a first-row pixel circuit 300, a second output end of the first-level gate driving unit 1100 is connected to a virtual pixel circuit 40, a first output end of the fifth-level gate driving unit 1100 is in a suspended state, and the fifth-level gate driving unit 1100 is in a suspended state. The second output end of 100 is connected to the 4th row pixel circuit 300; the second gate driving module 112 of the gate driving circuit 10 includes 5 gate driving units 1100, in which the first output end of the 1st level gate driving unit 1100 is connected to the 1st row pixel circuit 300, the second output end of the 1st level gate driving unit 1100 is in a suspended state, the first output end of the 5th level gate driving unit 1100 is respectively connected to the virtual pixel circuit 40, and the second output end of the 5th level gate driving unit 1100 is connected to the 4th row pixel circuit 300.

[0077] It should be noted that the above is only an exemplary description. In an application, in any gate driving module 110, one output end of some gate driving units 1100 may be in a suspended state, and one output end of the remaining gate driving units 1100 may be connected to the virtual pixel circuit 40; or one output end of the front m-level and rear m-level gate driving units 1100 may be in a suspended state or connected to the virtual pixel circuit 40, which is not limited here.

[0078] Since the number of gate driving units 1100 in each gate driving module 110 is greater than the number of pixel circuits 300 rows connected thereto, when the staggered multiplexing gate driving unit 1100 is used to provide two scanning signals for the pixel circuit 300, there are 2m gate driving units 1100 that only need to provide one scanning signal. In this regard, the present application sets the output ends that are not connected to the pixel circuit in the front m-level and rear m-level gate driving units 1100 in a suspended state, without the need to set up an additional connection structure, which can reduce costs; or, the present application sets the output ends that are not connected to the pixel circuit in the front m-level and rear m-level gate driving units 1100 to be connected to the virtual pixel circuit 40, which can improve the uniformity and symmetry of the circuit structure in the display panel 1, thereby improving the performance and reliability of the overall circuit. In practical applications, a suitable setting method can be selected according to specific needs, and no excessive restrictions are made here.

[0079] Please continue reading Figure 2 and Figure 3In one embodiment, the gate driving units 1100 in the gate driving circuit 10 are arranged along the column direction of the pixel circuit 300, and the spacing between any two adjacent gate driving units 1100 is the same. In this way, the gate driving units 1100 in the gate driving circuit 10 are evenly arranged in columns, ensuring the uniformity of the arrangement of the multiple gate driving units 1100 in the display panel 1, avoiding optical unevenness (mura) caused by non-uniform arrangement, and improving the display effect of the display panel 1.

[0080] Figure 4 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 4 In one embodiment, in the gate driving circuit 10, the first gate driving unit 1100 in the column direction of the pixel circuit 300 is flush with the first row of pixel circuits 300 in the row direction of the pixel circuit 300, the last gate driving unit 1100 in the column direction of the pixel circuit 300 is flush with the last row of pixel circuits 300 in the row direction of the pixel circuit 300, and the remaining gate driving units 1100 and the remaining pixel circuits 300 are staggered row by row in the row direction of the pixel circuit 300. That is, the width of the gate driving circuit 10 in the column direction of the pixel circuit 300 is equal to the width of a column of pixel circuits 300.

[0081] In the gate driving module 110, N+m cascaded gate driving units 1100 are evenly spaced, and the distance between any adjacent gate driving units 1100 is the same, so as to avoid excessive difference in the distance between the connection lines of the pixel circuit and inconsistent signal transmission due to different distances between the gate driving units 1100.

[0082] The distance between adjacent gate driving modules 110 is the same as the distance between adjacent gate driving units 1100, that is, the distance between the gate driving unit 1100 at the last level of the previous gate driving module 110 and the first level gate driving unit 1100 of the next gate driving module 110 is consistent with the distance between adjacent gate driving units 1100 in the gate driving module 110, further achieving uniform distribution of all gate driving units 1100 and ensuring consistency of signal transmission.

[0083] For example, Figure 4Taking the display panel 1 shown in the figure as an example, the display panel 1 includes 12 rows of pixel circuits 300, a third gate driving module 113 and a fourth gate driving module 114, wherein the third gate driving module 113 includes 8 gate driving units 1100, and the third gate driving module 113 includes 8 gate driving units 1100, then the 8 gate driving units 1100 of the fourth gate driving module 114 and the 8 gate driving units 1100 of the fourth gate driving module 114 are arranged in a row in the direction of the pixel circuit 300 with equal spacing, wherein the 8th level gate driving unit 1100 of the third gate driving module 113 is adjacent to the 1st level gate driving unit 1100 of the fourth gate driving module 114; and the 1st level gate driving unit 1100 in the third gate driving module 113 is adjacent to the first row of pixel circuits 300 in the row direction. The fourth gate driving module 114 is flush with the 8th-level gate driving unit 1100 and the 12th-row pixel circuit 300 in the row direction; the remaining gate driving units 1100 and the remaining pixel circuits 300 are staggered and arranged in the row direction, that is, the 2nd to 8th-level gate driving units 1100 in the third gate driving module 113 and the 1st to 7th-level gate driving units 1100 in the fourth gate driving module 114 are respectively staggered and arranged in the row direction with the 11th-row pixel circuit 300 of the 2nd row, for example, the 2nd-level gate driving unit 1100 in the third gate driving module 113 is staggered and arranged with the 2nd-row pixel circuit 300, that is, they are not at the same height in the row direction; the 3rd-level gate driving unit 1100 in the third gate driving module 113 is staggered and arranged with the 3rd-row pixel circuit 300, and so on. Figure 4 Compared with the display panel 1 in the related art that cannot realize partitioned multi-frequency display (using a group of 13 cascaded gate driving units 1100), the display panel 1 shown is equivalent to removing the 7th-level gate driving unit 1100 at the boundary position in the related art, and adding a 7th-level gate driving unit 1100 and an 8th-level gate driving unit 1100 (belonging to the third gate driving module 113) to the upper partition part; and adding a 1st-level gate driving unit 1100 and a 2nd-level gate driving unit 1100 (belonging to the fourth gate driving module 114) to the lower partition part.

[0084] It can be understood that the width of the display panel 1 in the row direction of the pixel circuit 300 is generally fixed. Since the number of gate driving units 1100 is greater than the number of pixel circuits 300 in a column, the gate driving units 1100 cannot be aligned with the pixel circuits 300 row by row. In this regard, the embodiment of the present application aligns the first gate driving unit 1100 with the first row of pixel circuits 300, and aligns the last gate driving unit 1100 with the last row of pixel circuits 300. The remaining gate driving units 1100 and the remaining pixel circuits 300 are staggered and arranged row by row in the row direction, and the gate driving units 1100 are arranged at equal intervals in columns, which is beneficial to ensure the uniformity of the wiring (Layout) between the gate driving circuit 10 and the pixel circuit 300, avoid optical mura, and improve the display effect of the display panel 1.

[0085] It can be understood that the width of the gate driving circuit 10 in the column direction of the pixel circuit 300 may also be different from the width of a column of pixel circuits 300 in the column direction of the pixel circuit 300. Since the gate driving circuit 10 is located in the non-display area and the pixel circuit 300 is located in the display area, in some cases, the width of the non-display area in the column direction of the pixel circuit 300 may be different from the width of the display area in the column direction of the pixel circuit 300. In this regard, the arrangement of each gate driving unit 1100 in the gate driving circuit 10 can be adaptively adjusted. For example, the first gate driving unit 1100 in the gate driving circuit 10 in the column direction of the pixel circuit 300 is flush with the first row of pixel circuits 300 in the row direction of the pixel circuit 300, or the last gate driving unit 1100 in the gate driving circuit 10 in the column direction of the pixel circuit 300 is flush with the last row of pixel circuits 300 in the row direction of the pixel circuit 300. Other arrangements are also possible and are not limited too much here.

[0086] Figures 5 to 7 The following are schematic diagrams of the structures of the gate drive unit and the connecting wire group provided in the embodiments of the present application. Figures 4 to 7In one embodiment, the display panel 1 further includes a plurality of connection line groups 50. Each connection line group 50 includes a main connection line 510 and at least one branch connection line 520. In each connection line group 50, the main connection line 510 is respectively connected to the output end of the gate driving unit 1100 and at least one branch connection line 520. Different main connection lines 510 are connected to different gate driving units 1100, that is, each gate driving unit 1100 is connected to a main connection line 510 in a connection line group 50. Based on this, the number of connection line groups 50 can be equal to the number of gate driving units 1100 in the gate driving circuit 10. The main connection line 510 extends along the row direction of the pixel circuit 300. The branch connection line 520 extends along the column direction of the pixel circuit 300. The number of branch connection lines 520 can be determined according to the number of rows of the pixel circuit 300 connected to the corresponding gate driving unit 1100. Exemplarily, the number of branch connection lines 520 can be 1 or 2. Among them, the shapes of the main connecting line 510 and the branch connecting line 520 can be straight, broken line, curved or any other suitable shape. For example, the shape of the main connecting line 510 includes a straight line or a broken line, and the shape of the branch connecting line 520 includes a straight line. It can be specifically set according to the positional relationship between the gate driving unit 1100 and the pixel circuit 300 and the layout design of the display panel 1, and no excessive restrictions are made here.

[0087] Each gate driving unit 1100 is connected to the pixel circuit 300 through at least one branch connection line 520. In each gate driving module 110, the gate driving unit 1100 connected to a row of pixel circuits 300 can be connected to the corresponding row of pixel circuits 300 through one branch connection line 520, and the gate driving unit 1100 connected to two rows can be connected to the corresponding two rows of pixel circuits 300 through two branch connection lines 520. Among them, for the gate driving unit 1100 connected to a row of pixel circuits 300, the connection line group 50 connected to the gate driving unit 1100 includes a main connection line 510 and at least one branch connection line 520, and the branch connection line 520 in the connection line group 50 can be one or two. For the gate driving unit 1100 connected to two rows, the connection line group 50 connected to the gate driving unit 1100 includes a main connection line 510 and two branch connection lines 520.

[0088] The display panel 1 is provided with a plurality of connection line groups 50, so that each gate driving unit 1100 can be connected to the corresponding pixel circuit 300 through the connection line group 50, which helps to realize the connection between the gate driving unit 1100 and the pixel circuit 300. Each connection line group 50 includes a main connection line 510 and at least one branch connection line 520, wherein the main connection line 510 is respectively connected to the output end of the gate driving unit 1100 and at least one branch connection line 520, that is, each branch connection line 520. The main connection line 510 acts as a bridge between the gate driving unit 1100 and each branch connection line 520, and, Each gate driving unit 1100 is connected to the pixel circuit 300 through at least one branch connection line 520. The branch connection line 520 provides the pixel circuit 300 with a first scanning signal S1 or a second scanning signal S2. The branch connection line 520 serves to shunt the signal of the main connection line 510. In this way, by connecting the gate driving circuit 10 and the pixel circuit 300 through the connection line group 50, the uniformity of the wiring in the display panel 1 can be further improved, and the optical mura caused by the irregularity of the row-by-row staggered interconnection between the gate driving circuit 10 and the pixel circuit 300 can be avoided, thereby improving the display effect of the display panel 1.

[0089] Please continue reading Figures 4 to 7 In one embodiment, the display panel 1 includes a first connection line group 51 and a second connection line group 52. The first connection line group 51 includes a main connection line 510 and a target branch connection line. The second connection line group 52 includes a main connection line 510, a first branch connection line 521 and a second branch connection line 522. Among them, the target branch connection line includes a first branch connection line 521 or a second branch connection line 522. The first end of the first branch connection line 521 and the first end of the second branch connection line 522 are respectively connected to the main connection line 510 in the same second connection line group 52. The second end of the first branch connection line 521 and the second end of the second branch connection line 522 extend in opposite directions. For example, Figures 5 to 7 As shown, the second end of the first branch connection line 521 extends in the positive direction of the Y axis, and the second end of the second branch connection line 522 extends in the negative direction of the Y axis. The lengths of the first branch connection line 521 and the second branch connection line 522 can be set accordingly according to the positional relationship between the gate driving unit 1100 and the pixel circuit 300, which is not limited here.

[0090] In each gate driving module 110, the first m-level gate driving unit 1100 is connected to the pixel circuit 300 of the corresponding row through the target branch connection line, and the second m-level gate driving unit 1100 is connected to the pixel circuit 300 of the corresponding row through the target branch connection line. In the application, the first branch connection line 521 and the second branch connection line 522 can be selected to achieve interconnection according to the positional relationship between the gate driving unit 1100 and the pixel circuit 300, which is not limited here. The k+m-level gate driving unit 1100 is connected to the r+m-th row pixel circuit 300 through the first branch connection line 521, and the k+m-th level gate driving unit 1100 is connected to the r-th row pixel circuit 300 through the second branch connection line 522, wherein the first branch connection line 521 and the second branch connection line 522 belong to the same connection line group 50. Among them, k traverses from 1 to Nm, that is, 1≤k≤Nm, and k increases one by one from 1 to Nm. r traverses from P to P+Nm, that is, P≤r≤P+Nm, and r increases one by one from P to P+Nm.

[0091] For example, Figure 4 Taking the display panel shown in FIG. 1 as an example, the third gate driving module 113 and the fourth gate driving module 114 respectively include 8 gate driving units 1100, m=2, in the third gate driving module 113, the first-level gate driving unit 1100 is connected to the first row of pixel circuits 300 through the first branch connection line 521, the second-level gate driving unit 1100 is connected to the second row of pixel circuits 300 through the second branch connection line 522, the third-level gate driving unit 1100 is connected to the first row of pixel circuits 300 through the first branch connection line 521, and the third-level gate driving unit 1100 is connected to the first row of pixel circuits 300 through the first branch connection line 521. The 4th level gate driving unit 1100 is connected to the 3rd row pixel circuit 300 through the second branch connection line 522, the 4th level gate driving unit 1100 is connected to the 2nd row pixel circuit 300 through the first branch connection line 521, the 4th level gate driving unit 1100 is connected to the 4th row pixel circuit 300 through the second branch connection line 522, and so on to the 6th level gate driving unit 1100, the 7th level gate driving unit 1100 is connected to the 5th row pixel circuit 300 through the first branch connection line 521, and the 8th level gate driving unit 1100 is connected to the 6th row pixel circuit 300 through the first branch connection line 521. The type of scanning signal provided by the first branch connection line 521 to the pixel circuit 300 and the type of scanning signal provided by the second branch connection line 522 to the pixel circuit 300 are specifically determined according to the corresponding relationship between the gate driving unit 1100 and the pixel circuit 300.

[0092] In the above-mentioned display panel 1, for the gate driving unit 1100 connecting two rows, it is connected to the corresponding rear row pixel circuit 300 through a branch connecting line 520 (such as the first branch connecting line 521), and is connected to the corresponding front row pixel circuit 300 through another branch connecting line 520 (such as the second branch connecting line 522), that is, the branch connecting line 520 with one extension direction is used to provide the first scanning signal S1 for the pixel circuit 300, and the branch connecting line 520 with another extension direction is used to provide the second scanning signal S2 for the pixel circuit 300, which further improves the wiring uniformity between the gate driving unit 1100 and the pixel circuit 300, avoids optical mura caused by the staggered arrangement between the gate driving unit 1100 and the pixel circuit 300, and can further improve the display effect of the display panel 1.

[0093] Please continue reading Figure 4 In one embodiment, the target connection lines of each gate driving unit 1100 are parallel to each other, and the target connection lines include at least one of the main connection lines 510 and the branch connection lines 520. Exemplarily, when the branch connection lines 520 include the first branch connection lines 521 and the second branch connection lines 522, the first branch connection lines 521 and the second branch connection lines 522 are parallel to each other. Based on this, the main connection lines 510 in each connection line group 50 are arranged in parallel, and the branch connection lines 520 in each connection line group 50 are arranged in parallel, which improves the uniformity of the routing in the display panel 1 and helps to improve the display effect of the display panel 1.

[0094] Please continue reading Figure 4 In one embodiment, in each gate driving module 110, the spacing between the target connection lines of any two adjacent gate driving units 1100 is equal. Exemplarily, in the gate driving circuit 10, the spacing between the main connection lines 510 in the connection line group 50 connected to any two adjacent gate driving units 1100 is equal, and / or, the spacing between the sub-main connection lines 510 in the connection line group 50 connected to any two adjacent gate driving units 1100 is equal. Based on this, two adjacent main connection lines 510 in the same gate driving module 110 are arranged at an equal distance, and two adjacent sub-connection lines 520 in the same gate driving module 110 are arranged at an equal distance, which further improves the uniformity of the routing in the display panel 1, thereby improving the display effect of the display panel 1.

[0095] Please continue reading Figure 2 , Figure 3 and Figure 4In one embodiment, the display panel 1 further includes a plurality of first scan lines 61 and a plurality of second scan lines 62. The number of the first scan lines 61 and the second scan lines 62 are respectively the same as the number of pixel circuits 300 in a column of pixel circuits 300. The first scan lines 61 and the second scan lines 62 are arranged in the same row as the pixel circuits 300. The first scan lines 61 are connected to the pixel circuits 300 located in the same row, and the first scan lines 61 provide the pixel circuits 300 with a first scan signal S1. The second scan lines 62 are connected to the pixel circuits 300 located in the same row, and the second scan lines 62 provide the pixel circuits 300 with a second scan signal S2. The pixel circuits 300 in the jth row are connected to a branch connection line 520 in the connection line group 50 connected to the i-th gate driving unit 1100 through the first scan lines 61, and the pixel circuits 300 in the jth row are connected to a branch connection line 520 in the connection line group 50 connected to the i+m-th gate driving unit 1100 through the second scan lines 62.

[0096] For example, Figure 4 As shown, in order to clearly illustrate the various structures Figure 4 The unmarked connecting wire set 50 can be combined with Figures 5 to 7 In the third gate driving module 113, the first-stage gate driving unit 1100 is electrically connected to the first scanning line 61 connected to the first row of pixel circuits 300 through the first branch connecting line 521, the second-stage gate driving unit 1100 is electrically connected to the first scanning line 61 connected to the second row of pixel circuits 300 through the second branch connecting line 522, the third-stage gate driving unit 1100 is electrically connected to the second scanning line 62 connected to the first row of pixel circuits 300 through the first branch connecting line 521, the third-stage gate driving unit 1100 is electrically connected to the first scanning line 61 connected to the third row of pixel circuits 300 through the second branch connecting line 522, and the fourth-stage gate driving unit 1100 is electrically connected to the first scanning line 61 connected to the third row of pixel circuits 300 through the second branch connecting line 522. The first-level gate driving unit 1100 is electrically connected to the second scanning line 62 connected to the second row of pixel circuits 300 through the first branch connecting line 521, the fourth-level gate driving unit 1100 is electrically connected to the first scanning line 61 connected to the fourth row of pixel circuits 300 through the second branch connecting line 522, and so on to the sixth-level gate driving unit 1100, the seventh-level gate driving unit 1100 is electrically connected to the second scanning line 62 connected to the fifth row of pixel circuits 300 through the first branch connecting line 521, and the eighth-level gate driving unit 1100 is electrically connected to the second scanning line 62 connected to the sixth row of pixel circuits 300 through the first branch connecting line 521.

[0097] In the above-mentioned display panel 1, for each row of pixel circuits 300, the first scan line 61 and the connecting line group 50 are connected to the gate driving unit 1100, and the second scan line 62 and the other connecting line group 50 are connected to another gate driving unit 1100. The first scan line 61 and the branch connecting line 520 in the connecting line group 50 jointly play a role in shunting the signal on the main connecting line 510, and the second scan line 62 and the branch connecting line 520 in the connecting line group 50 jointly play a role in shunting the signal on the main connecting line 510, so that one gate driving unit 1100 can provide the first scanning signal S1 and the second scanning signal S2 for two rows of pixel circuits 300 respectively, realize the multiplexing of the gate driving unit 1100, and provide two scanning signals respectively through two scanning lines, further improve the regularity of the wiring of the display panel 1, avoid optical mura caused by the staggered arrangement between the gate driving unit 1100 and the pixel circuit 300, thereby improving the display effect of the display panel 1.

[0098] Please continue reading Figure 2 , Figure 3 and Figure 4 In one embodiment, the spacing between the first scan line 61 and the second scan line 62 connected to each pixel circuit 300 is equal, the first scan lines 61 are parallel to each other, and the second scan lines 62 are parallel to each other, which can further improve the uniformity of the routing in the display panel 1, thereby improving the display effect of the display panel 1.

[0099] Figure 8 and Fig. 9 They are schematic diagrams of the structure of the pixel circuit provided in the embodiments of the present application. Figure 8 and Fig. 9 As shown, in one embodiment, the pixel circuit 300 includes a first initialization module 301 and a threshold compensation module 302. The first scan line 61 is connected to the first initialization module 301 of the pixel circuit 300 located in the same row, and the first scan signal S1 provides the first initialization module 301 with the first scan signal S1. The second scan line 62 is connected to the threshold compensation module 302 of the pixel circuit 300 located in the same row, and the second scan line 62 provides the threshold compensation module 302 with the second scan signal S2. Based on this, the multiplexed gate driving unit 1100 can generate the first scan signal S1 to drive the first initialization module 301 of a row of pixel circuits 300, and can also generate the second scan signal S2 to drive the threshold compensation module 302 of another row of pixel circuits 300, thereby realizing signal multiplexing between the initialization module and the threshold compensation module 302 in the pixel circuit 300, and further realizing the narrow frame under the partition multi-frequency display application.

[0100] Exemplarily, the pixel circuit 300 further includes a driving transistor M1, the first initialization module 301 includes a first initialization transistor M4, and the threshold compensation module 302 includes a threshold compensation transistor M3. Exemplarily, the first initialization transistor M4 includes a dual-gate transistor (such as Figure 8 M4-1 and M4-2 shown) or a single-gate transistor (such as Fig. 9 Exemplarily, the first initialization transistor M4 includes a dual-gate transistor (such as Figure 8 M3-1 and M3-2 shown) or a single-gate transistor (such as Fig. 9 M3-0 shown). In the pixel circuit 300 of the i-th row, the first electrode of the first initialization transistor M4 is respectively connected to the gate of the driving transistor M1 and the first electrode of the threshold compensation transistor M3, the second electrode of the first initialization transistor M4 is used to receive the first initialization signal Vref, and the gate of the first initialization transistor is connected to the first scan line 61; the second electrode of the threshold compensation transistor M3 is connected to the second electrode of the driving transistor M1, and the gate of the threshold compensation transistor M3 is connected to the second scan line 62.

[0101] Exemplarily, the pixel circuit 300 further includes a data writing transistor M2, a first light emission control transistor M5, a second light emission control transistor M6, a second initialization transistor M7 and a capacitor Cst, wherein the first electrode of the data writing transistor M2 is used to receive the data signal Data, the second electrode of the data writing transistor M2 is respectively connected to the first electrode of the driving transistor M1, the first electrode of the first light emission control transistor M5, and the anode of the light emitting element D, the gate of the data writing transistor M2 is used to receive the third scanning signal S3, the second electrode of the first light emission control transistor M5 is connected to the first end of the capacitor Cst and is used to receive the first power supply signal VDD, the gate of the first light emission control transistor M5 is connected to the first end of the capacitor Cst and is used to receive the first power supply signal VDD, and the gate of the first light emission control transistor M5 is connected to the first end of the capacitor Cst and is used to receive the first power supply signal VDD. The first electrode of the second light emitting control transistor M6 is connected to the first electrode of the second initialization transistor M7, the second electrode of the second light emitting control transistor M6 is respectively connected to the second electrode of the driving transistor M1 and the second electrode of the threshold compensation transistor, the gate of the second light emitting control transistor M6 is used to receive the fourth scanning signal S4, the second electrode of the second initialization transistor M7 is used to receive the initialization signal Vref, the gate of the second initialization transistor M7 is used to receive the fourth scanning signal S4, the second end of the capacitor Cst is respectively connected to the gate of the driving transistor M1 and the first electrode of the threshold compensation transistor M3, and the cathode of the light emitting element D receives the second power supply signal VSS.

[0102] It should be noted that the above is only a 7T1C structure of the pixel circuit 300 provided in the embodiment of the present application. The pixel circuit 300 may also be an 8T1C, 9T2C or other types, which are not limited too much here.

[0103] Fig.10 The waveform diagram of the first scanning signal S1, the second scanning signal S2 and the light emitting control signal EM provided in the embodiment of the present application is shown in FIG. Figure 8 and Fig.10 As shown, in one embodiment, the pixel circuit 300 includes a low temperature polysilicon (LTPS) transistor. Exemplarily, each transistor in the pixel circuit 300 is an LTPS transistor, including but not limited to a driving transistor M1, a first initialization transistor M4, a threshold compensation transistor M3, a data write transistor M2, a first light emission control transistor M5, a second light emission control transistor M6, and a second initialization transistor M7. Exemplarily, the third scan signal S3 received by the gate of the data write transistor M2 is the same as the first scan signal S1 received by the gate of the threshold compensation transistor M3, that is, the scan signals driving the data write transistor M2 and the threshold compensation transistor M3 can be further multiplexed, which helps to further achieve a narrow border. In this way, the present application can be applied to LTPS products, and can achieve a narrow border while realizing a partitioned multi-frequency display of LTPS products.

[0104] Fig.11 A schematic diagram of the waveforms of the first scanning signal S1, the second scanning signal S2 and the third scanning signal S3 provided in the embodiment of the present application. Fig. 9 and Fig.11 As shown, in one embodiment, Fig. 9 As shown, the pixel circuit 300 includes a low-temperature polysilicon transistor and a low-temperature polycrystalline oxide (LTPO) transistor. The pixel circuit 300 includes an LTPS transistor and an LTPO transistor. Exemplarily, the first initialization transistor M4 and the threshold compensation transistor M3 are LTPO transistors. The data write transistor M2, the first light-emitting control transistor M5, the second light-emitting control transistor M6 and the second initialization transistor M7 are LTPS transistors. Exemplarily, the third scan signal S3 received by the gate of the data write transistor M2 is the same as the fourth scan signal S4 received by the gate of the second initialization transistor M7, that is, the scan signals driving the data write transistor M2 and the second initialization transistor M7 can be further multiplexed, which helps to further achieve a narrow border. In this way, the present application can be applied to LTPO products, and can achieve a narrow border while realizing a partitioned multi-frequency display of LTPO products.

[0105] Based on the same inventive concept, the embodiment of the present application also provides a method for driving a display panel, which is applied to the display panel provided in the above embodiment. The implementation solution provided by the method for solving the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more method embodiments provided below can refer to the above limitations on the display panel, and will not be repeated here.

[0106] In one embodiment, Fig.12 As shown, a display panel driving method is provided, which can be applied to Figure 2 , Figure 3 and Figure 4 The display panel shown in FIG. 1 includes steps S1102 and S1104 in the driving method of the display panel.

[0107] S1102: Control at least two start signal lines to provide start signals to the corresponding first-stage gate driving units respectively, so as to start at least two gate driving modules respectively.

[0108] S1104: In each of the at least two gate driving modules, control the i-th gate driving unit to provide a first scanning signal for the j-th row of pixel circuits, and control the i+m-th gate driving unit to provide a second scanning signal for the j-th row of pixel circuits.

[0109] Exemplarily, the frequencies of the start signals provided by at least two start signal lines are different or the same. Wherein, 1≤m≤N-1, i traverses from 1 to N, and traverses from P to P+N-1, P represents the number of rows of the first row of pixel circuits connected to the gate drive module, and N represents the number of pixel circuit rows connected to the gate drive module.

[0110] The driving method of the display panel controls at least two start signal lines to provide start signals to the corresponding first-level gate drive units respectively, so as to start at least two gate drive modules respectively, and in each gate drive module of the at least two gate drive modules, the i-th level gate drive unit is controlled to provide a first scanning signal for the j-th row pixel circuit, and the i+m-th level gate drive unit is controlled to provide a second scanning signal for the j-th row pixel circuit. Therefore, the frequencies of the scanning signals generated by different gate drive modules can be controlled respectively by different start signal lines, so that different gate drive modules can generate scanning signals of different frequencies under the action of the start signal lines to achieve partitioned multi-frequency display; since each gate drive module in the display panel is interconnected with the pixel circuit in a staggered multiplexing manner, the partitioned multi-frequency display and the whole screen same-frequency display can be achieved by controlling the frequency of the start signal provided by the start signal line, and the multiplexing of part of the gate drive units of each gate drive module is achieved, that is, the multiplexed gate drive unit can generate two scanning signals, thereby reducing the number of gate drive units and achieving a narrow frame.

[0111] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0112] Based on the same inventive concept, an embodiment of the present application also provides a display device. Fig.13 A display device is provided in an embodiment of the present application. The display device 10000 includes the display panel 1 in the above embodiment.

[0113] It can be understood that the display device 10000 in the embodiment of the present application can be an OLED display device, a QLED display device, electronic paper, a mobile phone, a folding mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device, or any other product or component with a display function, and the embodiments disclosed in the present application are not limited to this.

[0114] like Fig.13 As shown, taking the display device 10000 as a folding mobile phone as an example, the folding mobile phone can perform partitioned multi-frequency display and full-screen same-frequency display. For example, in the partitioned multi-frequency display scenario, the refresh frequency of the first sub-display area 31 is 120 Hz, and the refresh frequency of the second sub-display area 32 is 1 Hz.

[0115] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0116] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: It includes a gate driving circuit, at least two start signal lines and pixel circuits arranged in an array; The gate driving circuit comprises at least two gate driving modules, each of which is connected to the start signal line and the pixel circuit respectively, and different gate driving modules are connected to different start signal lines and pixel circuits; Each of the gate driving modules includes N+m cascaded gate driving units, in each of the gate driving modules, the first-level gate driving unit is connected to the corresponding start signal line, the i-th-level gate driving unit is connected to the j-th row pixel circuit, the i-th-level gate driving unit provides a first scanning signal for the j-th row pixel circuit, the i+m-th-level gate driving unit is connected to the j-th row pixel circuit, and the i+m-th-level gate driving unit provides a second scanning signal for the j-th row pixel circuit, wherein 1≤m≤N-1, i traverses from 1 to N, j traverses from P to P+N-1, P represents the number of rows of the first row of pixel circuits connected to the gate driving module in the display panel, and N represents the number of pixel circuit rows connected to the gate driving module.

2. The display panel according to claim 1, characterized in that: The frequencies of the start signals provided by at least two of the start signal lines are different; Optionally, the start signal lines provide start signals with the same frequency; Optionally, the display panel further comprises a clock signal line, and the clock signal line is respectively connected to each of the gate driving units; Optionally, the display panel further includes a first power signal line and a second power signal line, the first power signal line is connected to each of the gate driving units respectively, and the second power signal line is connected to each of the gate driving units respectively.

3. The display panel according to claim 1, characterized in that: The gate driving unit includes a first output end and a second output end, the first output end is used to provide the first scanning signal, and the second output end is used to provide the second scanning signal, wherein, in each of the gate driving modules, the first output end of the front m-level gate driving unit is connected to the corresponding pixel circuit, the second output end of the front m-level gate driving unit is in a suspended state or connected to the virtual pixel circuit, the first output end of the rear m-level gate driving unit is in a suspended state or connected to the virtual pixel circuit, and the second output end of the rear m-level gate driving unit is connected to the corresponding pixel circuit.

4. The display panel according to claim 1, characterized in that: The gate driving units in the gate driving circuit are arranged along the column direction of the pixel circuit, and the distance between any two adjacent gate driving units is the same; Optionally, in the gate driving circuit, the first gate driving unit in the direction of the pixel circuit column is flush with the first row of pixel circuits in the direction of the pixel circuit row, the last gate driving unit in the direction of the pixel circuit column is flush with the last row of pixel circuits in the direction of the pixel circuit row, and the remaining gate driving units and the remaining pixel circuits are staggered row by row in the direction of the pixel circuit row; Optionally, in the gate driving module, N+m cascaded gate driving units are evenly spaced and the distance between any adjacent gate driving units is the same; Optionally, the distance between adjacent gate driving modules is the same as the distance between adjacent gate driving units.

5. The display panel according to claim 1, characterized in that: The display panel also includes a plurality of connection line groups, each of the connection line groups includes a main connection line and at least one branch connection line, in each of the connection line groups, the main connection line is respectively connected to the output end of the gate driving unit and each of the branch connection lines, different main connection lines are connected to different gate driving units, the main connection lines extend along the row direction of the pixel circuit, and the branch connection lines extend along the column direction of the pixel circuit; wherein each of the gate driving units is connected to the pixel circuit via at least one branch connection line.

6. The display panel according to claim 5, characterized in that: The display panel includes a first connection line group and a second connection line group, wherein the first connection line group includes the main connection line and a target branch connection line, the second connection line group includes the main connection line, a first branch connection line and a second branch connection line, a first end of the first branch connection line and a first end of the second branch connection line are respectively connected to the main connection line in the same second connection line group, a second end of the first branch connection line and a second end of the second branch connection line extend in opposite directions, and the target branch connection line includes the first branch connection line or the second branch connection line; In each of the gate driving modules, the first m-level gate driving units are connected to the pixel circuits of the corresponding rows through the target branch connection lines, the second m-level gate driving units are connected to the pixel circuits of the corresponding rows through the target branch connection lines, the k+m-th level gate driving units are connected to the pixel circuits of the r+m-th row through the first branch connection lines, and the k+m-th level gate driving units are connected to the pixel circuits of the r-th row through the second branch connection lines, wherein k traverses from 1 to Nm, and r traverses from P to P+Nm; Optionally, the target connection lines of each of the gate driving units are parallel to each other, and the target connection lines include at least one of the main connection lines and the branch connection lines; Optionally, in each of the gate driving modules, the distances between the target connection lines of any two adjacent gate driving units are equal.

7. The display panel according to claim 5, characterized in that: The display panel further includes a plurality of first scan lines and a plurality of second scan lines, wherein the first scan lines are connected to pixel circuits located in the same row, and the second scan lines are connected to pixel circuits located in the same row, the first scan lines provide the first scan signals to the pixel circuits, and the second scan lines provide the second scan signals to the pixel circuits, wherein the pixel circuits in the jth row are connected to the i-th level gate driving unit through the first scan lines and the branch connection lines, and the pixel circuits in the jth row are connected to the i+m-th level gate driving unit through the second scan lines and the branch connection lines; Optionally, the pixel circuit includes a first initialization module and a threshold compensation module, wherein the first scan line is connected to the first initialization module of the pixel circuit located in the same row, and the first scan line provides the first scan signal to the first initialization module, and the second scan line is connected to the threshold compensation module of the pixel circuit located in the same row, and the second scan line provides the second scan line to the threshold compensation module.

8. The display panel according to claim 1, characterized in that: The pixel circuit includes a low temperature polysilicon transistor; Optionally, the pixel circuit includes a low temperature polysilicon transistor and a low temperature polycrystalline oxide transistor.

9. A method for driving a display panel, characterized in that: Applied to the display panel according to any one of claims 1 to 8, the method comprises: Controlling at least two start signal lines to provide start signals to the corresponding first-stage gate drive units respectively, so as to start at least two gate drive modules respectively; In each of the at least two gate driving modules, the i-th level gate driving unit is controlled to provide a first scanning signal for the j-th row pixel circuit, and the i+m-th level gate driving unit is controlled to provide a second scanning signal for the j-th row pixel circuit, wherein 1≤m≤N-1, i traverses from 1 to N, and from P to P+N-1, P represents the number of rows of the first row of pixel circuits connected to the gate driving module, and N represents the number of pixel circuit rows connected to the gate driving module.

10. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-8.

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