Data reading circuit, display driving chip, display driving method and display device

Abstract

The invention provides a data reading circuit, a display driving chip, a display driving method and a display device. The data reading circuit comprises a clock circuit, a clock signal processing circuit and a sampling circuit. The clock circuit is configured to generate a first clock signal; the clock signal processing circuit is configured to process the first clock signal to obtain a second clock signal, and the second clock signal has a plurality of sampling signals distributed at intervals in a clock period of the first clock signal; the sampling circuit comprises an input end and a control end, and the control end is used for receiving a second clock signal; when the output end of the clock circuit is connected with the clock signal input end of the target memory and the data output end of the target memory is connected with the input end of the sampling circuit, the target memory periodically outputs data from the data output end under the control of a first clock signal; and the sampling circuit samples the data output by the data output end by using each sampling signal in sequence until correct sampling data is obtained.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and more specifically, to a data reading circuit, a display driving chip, a display driving method, and a display device. Background Art

[0002] In the field of organic light-emitting diode (OLED) display technology, in order to optimize the display effect, it is usually necessary to store compensation data in the Flash chip of the display module. After the display module is turned on, the display driver integrated circuit (DDIC) can read the compensation data from the Flash chip and use it to compensate the display image.

[0003] However, there are many Flash chip manufacturers in the market, and the Flash chips produced by different manufacturers have different specifications and parameters, and the display driver chip cannot match the Flash chips with different specifications and parameters at the same time. Summary of the invention

[0004] The purpose of the present disclosure is to provide a data reading circuit, a display driver chip, a display driving method and a display device to solve the technical problem in the related art that the display driver chip cannot simultaneously match Flash chips with multiple specification parameters.

[0005] In order to achieve the above objectives, the present invention adopts the following technical solutions:

[0006] A first aspect of the present disclosure provides a data reading circuit, the data reading circuit comprising a clock circuit, a clock signal processing circuit and a sampling circuit;

[0007] The clock circuit is configured to generate a first clock signal;

[0008] The input end of the clock signal processing circuit is connected to the output end of the clock circuit, and the clock signal processing circuit is configured to process the first clock signal to obtain a second clock signal, wherein the second clock signal has a plurality of sampling signals distributed at intervals within a clock cycle of the first clock signal, and the sampling signals are at a first level or a second level;

[0009] The sampling circuit includes an input end and a control end. The control end is connected to the output end of the clock signal processing circuit and is used to receive the second clock signal. When the output end of the clock circuit is connected to the clock signal input end of the target memory and the data output end of the target memory is connected to the input end of the sampling circuit, the target memory periodically outputs data from the data output end under the control of the first clock signal. The sampling circuit sequentially uses each sampling signal of the multiple sampling signals distributed at intervals to sample the data output from the data output end until correct sampling data is obtained.

[0010] Optionally, the clock signal processing circuit includes:

[0011] a frequency multiplication circuit, wherein an input end of the frequency multiplication circuit is connected to an output end of the clock circuit, and the frequency multiplication circuit is configured to perform frequency multiplication processing on the first clock signal to obtain a third clock signal;

[0012] A logic gate, wherein the logic gate includes two input terminals and an output terminal, one of the two input terminals is connected to the output terminal of the clock circuit, the other input terminal is connected to the output terminal of the frequency multiplication circuit, and the output terminal is connected to the control terminal of the sampling circuit. The logic gate is configured to perform a logic operation on the first clock signal and the third clock signal to obtain the second clock signal.

[0013] Optionally, when the sampling signal is at the first level, the logic gate is an AND gate.

[0014] Optionally, when the sampling signal is at the second level, the logic gate is an OR gate.

[0015] Optionally, the frequency multiplication circuit is a 3-times frequency multiplication circuit, a 4-times frequency multiplication circuit or a 5-times frequency multiplication circuit.

[0016] Optionally, the input end of the clock circuit is configured to be connected to a crystal oscillator circuit and to process a system clock signal generated by the crystal oscillator circuit to generate the first clock signal.

[0017] Optionally, the sampling circuit is also configured to perform a correctness check on the sampled data obtained by sampling the current sampling signal within a clock cycle of the first clock signal, and if the correctness check fails, continue to sample using the next sampling signal among the multiple spaced sampling signals until the sampled data that passes the correctness check is obtained.

[0018] Optionally, the target memory is a flash memory.

[0019] A second aspect of the present disclosure provides a display driver chip, comprising the data reading circuit as described above.

[0020] A third aspect of the present disclosure provides a display driving method, which is applicable to the display driving chip as described above, and includes:

[0021] Outputting a data read instruction and a first clock signal to a target memory, wherein after receiving the data read instruction, the target memory periodically performs data preparation under the control of the first clock signal and outputs the prepared compensation data through a data output terminal;

[0022] The data output from the data output terminal is sampled in sequence using each sampling signal in a plurality of sampling signals distributed at intervals in the second clock signal until correct sampling data is obtained.

[0023] A fourth aspect of the present disclosure provides a display device, comprising a display panel, a flash memory and a display driver chip as described above, wherein the flash memory stores compensation data, and the display driver chip is configured to use the data reading circuit to read the compensation data from the flash memory and compensate for the image to be displayed.

[0024] The beneficial effects of the present disclosure are as follows:

[0025] The data reading circuit of the disclosed embodiment adds a clock signal processing circuit, uses the clock signal processing circuit to process the first clock signal to obtain the second clock signal, and provides the second clock signal to the sampling circuit, wherein the second clock signal has multiple sampling signals distributed at intervals within a clock cycle of the first clock signal, that is, has multiple sampling time points, so multiple sampling can be performed, and when no data can be sampled at the first sampling time point, the second sampling time point will continue to be used for sampling, and so on until accurate data is collected, which realizes adaptive data collection at appropriate sampling time points for different models of Flash chips, without the need to configure the sampling time points in the display driver chip differently for different models of Flash chips, and because the second clock signal has multiple sampling time points, it can cover a larger range of data preparation time t CLQV That is, under the same configuration, data can be collected for multiple models of Flash chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The specific implementation methods of the present disclosure are further described in detail below with reference to the accompanying drawings.

[0027] Figure 1 For the Flash chip in the related technology CLQV Schematic diagram of the parameters;

[0028] Figure 2This is a timing diagram of the main control chip reading data from the Flash chip in the related art;

[0029] Figure 3 A schematic diagram of the structure of a data reading circuit and a target memory provided by an embodiment of the present disclosure;

[0030] Figure 4 This is a schematic diagram of the structure of a data reading circuit implemented by a frequency multiplication circuit and an AND gate according to an embodiment of the present disclosure;

[0031] Figure 5 A schematic diagram of a third clock signal clk3 and a second clock signal clk2 obtained by processing the first clock signal clk1 by a 3-times frequency multiplication circuit when the first clock signal clk1 is sampled at a high level;

[0032] Figure 6 A schematic diagram of a third clock signal clk3 and a second clock signal clk2 obtained by processing the first clock signal clk1 by a 4-fold frequency multiplication circuit when the first clock signal clk1 is sampled at a high level;

[0033] Figure 7 A schematic diagram of a third clock signal clk3 and a second clock signal clk2 obtained by processing the first clock signal clk1 by a 5-times frequency circuit when the first clock signal clk1 is sampled at a high level;

[0034] Figure 8 A schematic diagram of a third clock signal clk3 and a second clock signal clk2 obtained by processing the first clock signal clk1 by a 3-times frequency circuit when the first clock signal clk1 is sampled at a low level;

[0035] Fig. 9 A flow chart of a display driving method provided by an embodiment of the present disclosure;

[0036] Fig.10 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] As a storage chip, the core function of Flash chip is to store data. Therefore, when reading data from Flash chip, the correctness and reading efficiency of the data must be guaranteed, and the faster the reading speed, the better. CLQV It is a key specification parameter that describes the time interval between when the main control chip needs to read data and when the Flash chip receives the instruction and when the data is ready. The shorter this indicator is, the better the performance of the Flash chip is. Please refer to Figure 1 , Figure 1 Flash chip CLQV Parameter diagram, where CS represents the chip select signal of the Flash chip, CLK represents the clock signal, and t CH Indicates the positive pulse width in one clock cycle, t CL Indicates the negative pulse width within a clock cycle, MISO indicates the output signal of the Flash chip, and LSB out indicates the least significant bit output. Among them, the Flash chips produced by different manufacturers or different models of Flash chips produced by the same manufacturer have different t CLQV The parameters are usually different. For example, at the same voltage (such as 1.8V), the t CLQV The parameter is 7ns, and the t CLQV The parameter is 12.5ns, and A and B represent different models of Flash chips. CLQV Different parameters will result in different data sampling locations in the main control chip.

[0040] Among them, the main control chip reads data from the Flash chip through the SPI communication mode. In the SPI communication mode, the main control chip acts as the master device and the Flash chip acts as the slave device. The master device and the slave device communicate through four lines, namely the clock line (CLK), the host output slave input line (MOSI), the host input slave output line (MISO) and the chip select line (CS). The master device sends the clock signal clk through the clock line. The clock signal clk controls the data transmission rhythm. At the rising or falling edge of the clock signal, the master device sends data to the slave device through the MOSI line, and the slave device sends data to the master device through the MISO line. The CS line is used to select a specific slave device.

[0041] When the main control chip reads data from the Flash chip, it can use rising edge sampling or falling edge sampling. Rising edge sampling means that the main control chip collects the data output by the Flash chip through the data output line (such as the above-mentioned MISO line) at the moment when the clock signal jumps from a low level to a high level; falling edge sampling means that the main control chip collects the data output by the Flash chip at the moment when the clock signal jumps from a high level to a low level. When the main control chip communicates with the Flash chip, the two parties will agree on a certain communication protocol and timing. In the protocol mode of rising edge sampling, the Flash chip will prepare the data and put it on the data line (i.e., the MISO line) at a specific stage of the clock signal. The main control chip will capture the level state on the data line at this time through the internal sampling circuit at the moment of the rising edge of the clock, identify it as a valid data bit, and complete the reading of one bit of data. Similarly, in the protocol mode of falling edge sampling, the Flash chip will output data at the appropriate stage of the clock signal according to the protocol. When the main control chip detects the falling edge of the clock, it triggers the sampling operation and reads the level value on the data line at this time as valid data.

[0042] Please refer to Figure 2 , Figure 2 This is the timing diagram of the main control chip reading data from the Flash chip. Figure 2 Taking rising edge sampling as an example, Figure 2 In the above, Flash clk represents the clock signal of the Flash chip, and sampling clk represents the clock signal of the sampling circuit in the main control chip. In the related art, the frequency of Flash clk is the same as that of sampling clk. Assuming that the frequencies of Flash clk and sampling clk are both 65MHz, the clock period of Flash clk and sampling clk is T = 1 / (65*10 6)=15.4ns. In one clock cycle, the time interval between a falling edge and the next rising edge of Flash clk is t=T / 2=7.69ns. When the main control chip needs to read data from the Flash chip, the main control chip first sends an instruction to the Flash chip. After receiving the instruction, the Flash chip prepares the data at the falling edge of the clock signal Flash clock, and the main control chip generally samples the data at the rising edge of the next clock signal, that is, the sampling time point is a fixed position, which is specifically the rising edge of the next clock signal, such as Figure 2 As shown, the main control chip samples data at the first arrow position t1. For Flash chip A, its data preparation time is t CLQV The data in Flash chip A is ready at time t1, and the main control chip can acquire the data at the rising edge t1. For Flash chip B, its data preparation time is t CLQV is 12.5ns, which is greater than 7.69ns. Therefore, at time t1, the data in Flash chip B is not yet fully prepared, and the main control chip cannot sample data at the rising edge t1. Therefore, for different types of Flash chips, the main control chip needs to configure the data sampling position differently. If the display module replaces a different type of Flash chip, such as changing from Flash chip A to Flash chip B, the code in the main control chip needs to be reconfigured, such as reconfiguring the sampling time point to the second rising edge of the clock signal after the instruction is issued, that is, Figure 2 At time t2, the Flash chip B is adapted. The above reconfiguration process of the main control chip will not only increase the complexity of code management in the main control chip, but also limit the Flash chip models applicable to the display module, which is not conducive to expanding the Flash chip models and chip manufacturers compatible with the main control chip.

[0043] In order to solve the above technical problems, the present disclosure provides a data reading circuit, a display driver chip, a display driving method and a display device. Figure 3 , Figure 3 The data reading circuit provided in the embodiment of the present disclosure is a schematic diagram of the structure of an embodiment of the data reading circuit, which is integrated in the display driver chip and is used for the display driver chip to read data from the Flash memory. The display driver chip is equivalent to the main control chip described above. It can be understood that the data reading circuit can also be integrated in other main control chips for reading data from the Flash memory, and the embodiment of the present disclosure does not limit the specific type of the main control chip.

[0044] like Figure 3As shown, the data reading circuit includes a clock circuit 10, a clock signal processing circuit 20 and a sampling circuit 30. The clock circuit 10 is configured to generate a first clock signal clk1, the input end of the clock signal processing circuit 20 is connected to the output end of the clock circuit 10, the clock signal processing circuit 20 is configured to process the first clock signal clk1 to obtain a second clock signal clk2, the second clock signal clk2 has a plurality of sampling signals distributed at intervals within a clock cycle T1 of the first clock signal clk1, and the sampling signal is a first level or a second level, the sampling circuit 30 includes an input end and a control end, the control end is connected to the output end of the clock signal processing circuit 20, and is used to receive the second clock signal clk2. When the output end of the clock circuit 10 is connected to the clock signal input end CLK of the target memory, and the data output end MISO of the target memory is connected to the input end of the sampling circuit 30, the target memory periodically outputs data from the data output end MISO under the control of the first clock signal clk1, and the sampling circuit 30 sequentially samples the data output by the data output end MISO using each sampling signal of the multiple spaced sampling signals until the correct sampling data is obtained.

[0045] Optionally, in the embodiment of the present disclosure, the target memory is a flash memory, that is, a Flash memory. In other embodiments, the target memory may also be other types of memories using the SPI communication mode. Assuming that the clock cycle of the first clock signal clk1 is recorded as T1, the target memory periodically outputs data from the data output terminal MISO under the control of the first clock signal clk1, which can be understood as the target memory performing an operation of preparing the data and placing it on the data line (that is, the data output terminal MISO) once per clock cycle T1 after receiving the data read instruction.

[0046] In the disclosed embodiment, when the data reading circuit is used to read data from the target memory, the first clock signal clk1 generated by the clock circuit 10, in addition to being used to generate the second clock signal clk2, also needs to be connected to the clock signal input terminal CLK of the target memory, and is used as the clock signal for transmitting data to the target memory, that is, the first clock signal clk1 output from the output terminal of the clock circuit 10 is input to the target memory through the clock line of the target memory.

[0047] In the related art, the first clock signal clk1 not only provides a clock signal for the target memory, but also is provided to the sampling circuit 30, and is used as a control signal of the sampling circuit 30 to control the sampling circuit 30 to sample the data of the output terminal MISO of the target memory. CLQVThe sampling time point of the sampling circuit 30 does not match the sampling time point of the sampling circuit 30. For example, at the sampling time point of the sampling circuit 30, the data in the target memory is not yet fully prepared, which will cause the sampling circuit to fail to sample data. In the embodiment of the present disclosure, the second clock signal clk2 is used to sample data, which can be compatible with a larger range of data preparation time t CLQV .

[0048] Specifically, compared with the first clock signal clk1, the second clock signal clk2 has multiple sampling signals distributed at intervals within a clock cycle T1, each sampling signal corresponds to a sampling time point, and each sampling time point forms a longer sampling time width. As long as the data in the target memory is ready before the last sampling time point in the sampling time width, the sampling circuit 30 can implement sampling of the data. When sampling using the first clock signal clk1, the data in the target memory needs to be ready before the first sampling time point, otherwise the sampling cannot be completed and the sampling time point of the sampling circuit needs to be reconfigured. Therefore, by configuring multiple sampling time points, the target memory can be allowed to have a wider range of data preparation time t CLQV .

[0049] Compared with the related art, the embodiment of the present disclosure increases the clock signal processing circuit 20, processes the first clock signal clk1 by the clock signal processing circuit 20 to obtain the second clock signal clk2, and provides the second clock signal clk2 to the sampling circuit 30, that is, the second clock signal clk2 is used to control the sampling circuit 30 to perform sampling. Since the second clock signal clk2 has multiple sampling signals distributed at intervals within a clock cycle T1 of the first clock signal clk1, that is, it has multiple sampling time points, multiple sampling can be performed. When no data is collected at the first sampling time point, the second sampling time point will continue to be used for sampling. When no data is collected at the second sampling time point, the third sampling time point will continue to be used for sampling, and so on until accurate data is collected. It realizes adaptive data collection at appropriate sampling time points for different models of Flash chips, without the need to configure the sampling time points in the display driver chip differently for different models of Flash chips. In addition, since the second clock signal clk2 has multiple sampling time points, it can cover a larger range of data preparation time t CLQV , that is, data can be collected from multiple models of Flash chips.

[0050] In one possible implementation, Figure 4As shown, the clock signal processing circuit 20 includes a frequency multiplication circuit 210 and a logic gate 220. The input end of the frequency multiplication circuit 210 is connected to the output end of the clock circuit 10, and the frequency multiplication circuit 210 is configured to perform frequency multiplication processing on the first clock signal clk1 to obtain a third clock signal clk3; the logic gate 220 includes two input ends and an output end, one of the two input ends is connected to the output end of the clock circuit 10, and the other input end is connected to the output end of the frequency multiplication circuit 210, and the output end is connected to the control end of the sampling circuit 30, and the logic gate 220 is configured to perform a logic operation on the first clock signal clk1 and the third clock signal clk3 to obtain the second clock signal clk2.

[0051] The frequency multiplication circuit 210 is used to increase the frequency of the first clock signal clk1 to an integral multiple of the original frequency. Assuming that the frequency of the first clock signal clk1 is recorded as f1, the clock period is recorded as T1, and the frequency of the third clock signal clk3 is recorded as f3, then f3=n*f1, where n represents the multiple of the frequency multiplication circuit 210. After being processed by the frequency multiplication circuit 210, the frequency of the first clock signal clk1 can be significantly increased, and it can also be understood that the frequency multiplication circuit 210 is used to process a low-frequency signal to obtain a high-frequency signal.

[0052] Optionally, the frequency multiplication circuit 210 is a 3-times frequency multiplication circuit, a 4-times frequency multiplication circuit, or a 5-times frequency multiplication circuit, that is, the multiple of the frequency multiplication circuit 210 is 3, 4, or 5. Exemplarily, when the frequency multiplication circuit 210 is a 3-times frequency multiplication circuit, n=3, and f3=3*f1. Similarly, when the frequency multiplication circuit 210 is a 4-times frequency multiplication circuit, n=4, and f3=4*f1.

[0053] The logic gate 220 is used to perform a logic operation on the first clock signal clk1 and the third clock signal clk3 to obtain the second clock signal clk2. The second clock signal clk2 needs to satisfy the following requirement: it needs to have multiple sampling signals within one clock cycle T1.

[0054] For the sampling circuit 30, its control signal is usually a low level or a high level, that is, the sampling circuit 30 usually performs sampling when the control end receives a low level or a high level. Since the second clock signal clk2 in the embodiment of the present disclosure is used as the control signal of the sampling circuit 30, one of the first level and the second level is a high level, and the other of the first level and the second level is a low level. Exemplarily, the first level is a high level and the second level is a low level; or the first level is a low level and the second level is a high level. The embodiment of the present disclosure is described by taking the first level as a high level and the second level as a low level as an example.

[0055] The second clock signal clk2 has multiple sampling signals in one clock cycle T1, which can realize the process of the target memory outputting data once. The sampling circuit 30 has multiple sampling points for the output of the target memory, that is, multiple sampling can be performed at different time points. Figures 5 to 7 , Figure 5 is a schematic diagram of a third clock signal clk3 and a second clock signal clk2 obtained by processing the first clock signal clk1 by a 3-times frequency circuit, Figure 6 is a schematic diagram of a third clock signal clk3 and a second clock signal clk2 obtained by processing the first clock signal clk1 by a 4-times frequency circuit, Figure 7 Schematic diagram of the third clock signal clk3 and the second clock signal clk2 obtained by processing the first clock signal clk1 by a 5-fold frequency multiplication circuit. Figures 5 to 7 It can be seen that when the frequency multiplication circuit 210 is a 3-times frequency multiplication circuit or a 4-times frequency multiplication circuit, within one clock cycle T1, the sampling circuit 30 has two sampling points, which are respectively recorded as sampling point 1 and sampling point 2. When the frequency multiplication circuit 210 is a 5-times frequency multiplication circuit, within one clock cycle T1, the sampling circuit 30 has three sampling points, which are respectively recorded as sampling point 1, sampling point 2 and sampling point 3. As the multiple of the frequency multiplication circuit 210 increases, the number of sampling points of the second clock signal clk2 obtained in one clock cycle T1 will also increase. At this time, the data preparation time t that can be applied to the data reading circuit is CLQV The larger the range, the more Flash memory models can be applied.

[0056] It can be understood that the larger the multiple of the frequency multiplication circuit 210 is, the greater the sampling signal (eg Figures 5 to 7 The more high levels 1) shown in FIG. 1 , that is, the more sampling points there are, the larger the t of the applicable target memory is. CLQV The larger the range of the parameter, the larger the multiple, the higher the power consumption of the frequency multiplication circuit 210 and the sampling circuit 30 will be. Therefore, the multiple of the frequency multiplication circuit 210 needs to be determined according to actual needs, such as the applicable t CLQV The parameter value range, power consumption requirements, etc. are set after comprehensive consideration.

[0057] Optionally, when the sampling signal is at the first level, that is, at a high level, the logic gate 220 is an AND gate. Figures 4 to 7 As shown, when the logic gate 220 is an AND gate, the second clock signal clk2 will have multiple high levels in one clock cycle T1. Since the sampling circuit 30 is a high level sampling, the sampling circuit 30 will have multiple sampling points.

[0058] Optionally, when the sampling signal is at the second level, that is, at a low level, the logic gate 220 is an OR gate. Figure 8 , Figure 8 is a schematic diagram of the second clock signal clk2 and the third clock signal clk3 when the logic gate 220 is an OR gate and the frequency multiplication circuit 210 is a 3-time frequency multiplication circuit, Figure 8 It can be seen that at this time, the second clock signal clk2 has two low-level 0s in one clock cycle T1. Since the sampling circuit 30 is low-level sampling, the sampling circuit 30 will have two sampling points. Similarly, for low-level sampling, as the multiple of the frequency multiplication circuit 210 increases, the number of sampling points of the second clock signal clk2 obtained in one clock cycle T1 will also increase. At this time, the data preparation time t CLQV The larger the range, the more Flash memory models can be applied.

[0059] In a possible implementation, the input end of the clock circuit 10 is configured to be connected to a crystal oscillator circuit and to process the system clock signal clk0 generated by the crystal oscillator circuit to generate the first clock signal clk1.

[0060] The display driver chip usually has a crystal oscillator circuit, which generally includes a crystal oscillator and two capacitors. The crystal oscillator circuit generates the system clock signal clk0 required by the display driver chip. The frequency of the system clock signal clk0 is generally in a relatively low frequency range, for example, the frequency range is between 1.2MHZ and 12MHZ. Since the frequency of the clock signal required for reading and writing data in the Flash memory is different from the frequency of the system clock signal clk0, a clock circuit 10 is also set in the display driver chip. The system clock signal clk0 is processed by the clock circuit 10 to obtain the clock signal required by the Flash memory, that is, the first clock signal clk1 can also be understood as Flash clk.

[0061] Optionally, the frequency of the first clock signal clk1 is 30 MHz, 65 MHz, etc. It is understandable that the frequency of the first clock signal clk1 can be within the frequency range of clock signals supported by the Flash memory, and the embodiment of the present disclosure does not limit the specific frequency of the first clock signal clk1.

[0062] In a possible implementation, the sampling circuit is further configured to perform a correctness check on the sampled data obtained by sampling the current sampling signal within a clock cycle T1 of the first clock signal clk1, and to continue sampling using the next sampling signal among a plurality of spaced sampling signals until the sampled data that passes the correctness check is obtained if the correctness check fails.

[0063] In the disclosed embodiment, at each sampling time point (i.e., the current sampling signal), the sampling circuit 30 needs to identify the sampled data after performing the sampling action. If the identification result is that the sampled data is empty, it means that no data has been sampled, and sampling is continued at the next sampling time point. If the identification result is that the sampled data is not empty, it means that data has been sampled, and the sampled data needs to be further corrected. If the correctness check passes, it means that the correct data has been sampled, and the data reading action within the current clock cycle T1 is completed, waiting for the next data reading. If the correctness check fails, it means that the sampled data is incorrect, and sampling is continued at the next sampling point, and the obtained sampled data is continuously identified, and so on until the correctness check passes.

[0064] For example, Figure 7 Taking the high-level sampling shown as an example, when the sampling circuit 30 performs sampling at the first high level, that is, the first rising edge (sampling point 1), the sampled data is identified. If the identification result is that no data is sampled or the data is incorrect, sampling is continued at the second high level, that is, the second rising edge (sampling point 2), and the sampled data is identified, and so on until the correct data is collected.

[0065] Optionally, the correctness check in the embodiments of the present disclosure may be any method such as checksum check, error correction code (ECC) check, end-to-end data protection (E2E Protection), multiple read verification, etc.

[0066] Exemplarily, the sampling multiple read verification method verifies the correctness of the sampled data. The method of the multiple read verification method is: the main control chip reads the same data from the Flash multiple times and compares the results of each read. If the results of multiple reads are consistent, then the data is likely to be correct; if the results of multiple reads are inconsistent, it means that there may be problems with the data. For example: for some key data, three reads can be performed. If the results of the three reads are the same, the data is considered correct; if there are differences, further analysis and processing can be performed.

[0067] It can be understood that the sampling circuit in the embodiment of the present disclosure is a data acquisition circuit in the display driver chip in the related art, and the present disclosure does not improve its specific circuit results. Similarly, the frequency multiplication circuit and logic gate in the embodiment of the present disclosure can be implemented by using the existing frequency multiplication circuit and logic gate circuit in the related art, and the present disclosure does not improve its specific circuit. The embodiment of the present disclosure mainly improves the data reading circuit by using the clock signal processing circuit implemented by the frequency multiplication circuit and the logic gate, and improves the model range of the Flash memory that the data reading circuit can be applied to.

[0068] Based on the same inventive concept, a second aspect of the present disclosure provides a display driver chip, comprising the data reading circuit as described above.

[0069] The display driver chip in the embodiment of the present disclosure is a display driver integrated circuit (DDIC), which integrates various compensation algorithms. The display driver chip uses a data reading circuit to read compensation data from a Flash memory, and the compensation algorithm uses the compensation data to compensate the display image.

[0070] Optionally, the compensation algorithm includes but is not limited to a voltage drop compensation algorithm, a crosstalk compensation algorithm, a color balance compensation algorithm, an aging compensation algorithm, a brightness uneven compensation algorithm, etc., and the compensation data may include compensation data required for the display panel to perform various compensation algorithms.

[0071] It can be understood that, in addition to the data reading circuit as described above, the display driver chip may also include a signal processing unit, which is used to receive image data of the content to be displayed, configure the data reading circuit, compensate the content to be displayed using the compensation data read by the data reading circuit, and control the display panel to display, etc.

[0072] Based on the same inventive concept, the third aspect of the present disclosure provides a display driving method, which is applicable to the display driving chip as described above, such as Fig. 9 As shown, the display driving method includes the following steps:

[0073] Step S101, outputting a data read instruction and a first clock signal to a target memory. After receiving the data read instruction, the target memory periodically prepares data under the control of the first clock signal and outputs the prepared compensation data through a data output terminal.

[0074] Step S102, sequentially sampling the data outputted from the data output terminal using each sampling signal in a plurality of sampling signals distributed at intervals in the second clock signal until correct sampling data is obtained.

[0075] In step S102, sampling is performed in sequence using each sampling signal until the correct sampling data is obtained. This can be understood as: sampling is performed at the first sampling time point, and whether the sampling data is accurate is determined. If accurate data is obtained by sampling, the sampling is terminated, that is, the data reading operation is completed. If no data is sampled or the sampled data is inaccurate, sampling is continued at the second sampling time point. When no data is sampled at the second sampling time point or the data is inaccurate, sampling is continued at the third sampling time point, and so on until accurate data is collected.

[0076] For example, Figure 7 Taking the high-level sampling shown as an example, when the sampling circuit 30 performs sampling at the first high level, that is, the first rising edge (sampling point 1), the sampled data is identified. If the identification result is that no data is sampled or the data is incorrect, sampling is continued at the second high level, that is, the second rising edge (sampling point 2), and the sampled data is identified, and so on until the correct data is collected.

[0077] Based on the same inventive concept, the fourth aspect of the present disclosure provides a display device, including a display panel, a flash memory and a display driver chip as described above, wherein compensation data is stored in the flash memory, and the display driver chip is configured to use the data reading circuit to read the compensation data from the flash memory and compensate for the displayed image.

[0078] Please refer to Fig.10 , Fig.10 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure, such as Fig.10 As shown, the display device includes a display panel 400, a flash memory 500 and a display driver chip 600. The display driver chip 600 is the display driver chip described in the above embodiment, and has a built-in data reading circuit.

[0079] Exemplarily, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., which is not limited in this embodiment.

[0080] The display panel in the implementation of the present disclosure may be an organic light-emitting diode (OLED) display panel. It is understandable that the display panel may be set to other types according to actual needs, for example, the display panel may be a quantum dot light emitting diode (QLED) display panel or a micro light emitting diode (Micro LED) display panel.

[0081] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in this field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A data reading circuit, characterized in that: The data reading circuit includes a clock circuit, a clock signal processing circuit and a sampling circuit; The clock circuit is configured to generate a first clock signal; The input end of the clock signal processing circuit is connected to the output end of the clock circuit, and the clock signal processing circuit is configured to process the first clock signal to obtain a second clock signal, wherein the second clock signal has a plurality of sampling signals distributed at intervals within a clock cycle of the first clock signal, and the sampling signals are at a first level or a second level; The sampling circuit includes an input end and a control end. The control end is connected to the output end of the clock signal processing circuit and is used to receive the second clock signal. When the output end of the clock circuit is connected to the clock signal input end of the target memory and the data output end of the target memory is connected to the input end of the sampling circuit, the target memory periodically outputs data from the data output end under the control of the first clock signal. The sampling circuit sequentially uses each sampling signal of the multiple sampling signals distributed at intervals to sample the data output from the data output end until correct sampling data is obtained.

2. The data reading circuit according to claim 1, characterized in that: The clock signal processing circuit comprises: a frequency multiplication circuit, the input end of the frequency multiplication circuit being connected to the output end of the clock circuit, the frequency multiplication circuit being configured to perform frequency multiplication processing on the first clock signal to obtain a third clock signal; and A logic gate, wherein the logic gate includes two input terminals and an output terminal, one of the two input terminals is connected to the output terminal of the clock circuit, the other input terminal is connected to the output terminal of the frequency multiplication circuit, and the output terminal is connected to the control terminal of the sampling circuit. The logic gate is configured to perform a logic operation on the first clock signal and the third clock signal to obtain the second clock signal.

3. The data reading circuit according to claim 2, characterized in that: When the sampling signal is at the first level, the logic gate is an AND gate.

4. The data reading circuit according to claim 2, characterized in that: When the sampling signal is at the second level, the logic gate is an OR gate.

5. The data reading circuit according to any one of claims 2 to 4, characterized in that: The frequency multiplication circuit is a 3-times frequency multiplication circuit, a 4-times frequency multiplication circuit or a 5-times frequency multiplication circuit.

6. The data reading circuit according to claim 1, characterized in that: The input end of the clock circuit is configured to be connected to a crystal oscillator circuit and to process a system clock signal generated by the crystal oscillator circuit to generate the first clock signal.

7. The data reading circuit according to claim 1, characterized in that: The sampling circuit is also configured to perform a correctness check on the sampled data obtained by sampling the current sampling signal within a clock cycle of the first clock signal, and if the correctness check fails, continue to perform sampling using the next sampling signal among the multiple spaced sampling signals until the sampled data that passes the correctness check is obtained.

8. The data reading circuit according to claim 1, characterized in that: The target memory is a flash memory.

9. A display driver chip, characterized in that: The method comprises the data reading circuit as claimed in any one of claims 1 to 8.

10. A display driving method, characterized in that: The display driving method is applicable to the display driving chip according to claim 9, and the display driving method comprises: Outputting a data read instruction and a first clock signal to a target memory, wherein after receiving the data read instruction, the target memory periodically performs data preparation under the control of the first clock signal and outputs the prepared compensation data through a data output terminal; The data output from the data output terminal is sampled in sequence using each sampling signal in a plurality of sampling signals distributed at intervals in the second clock signal until correct sampling data is obtained.

11. A display device, characterized in that: The display driver chip comprises a display panel, a flash memory and the display driver chip as claimed in claim 9, wherein the flash memory stores compensation data, and the display driver chip is configured to use the data reading circuit to read the compensation data from the flash memory and compensate the image to be displayed.

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