Driving substrate, display panel and display device

Abstract

The invention provides a driving substrate, a display panel and a display device, and belongs to the technical field of display. The driving substrate comprises a decomposition circuit area; the decomposition circuit area comprises a first decomposition circuit subarea and a second decomposition circuit subarea located on the side, away from the display area, of the first decomposition circuit subarea. In the first decomposition circuit subarea, the driving substrate is provided with a plurality of multi-path decomposition circuits arranged in the row direction, and each multi-path decomposition circuit comprises a plurality of transistor units; the first electrodes of the transistors in the same multi-path decomposition circuit are electrically connected with the same source end signal line, and the second electrodes of the transistors in the same transistor unit are electrically connected with the same data line; the second decomposition circuit subarea is provided with a plurality of gating signal lines which are in one-to-one correspondence with the transistor units in the multiple paths of decomposition circuits and extend in the row direction, and grid electrodes of all transistors of the transistor units are electrically connected with the corresponding gating signal lines. The driving substrate can reduce the restriction of the demultiplexing circuit on the performance of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving substrate, a display panel and a display device. Background Art

[0002] Micro OLED technology is an OLED display technology driven by a silicon-based drive substrate, which often has a higher resolution, for example, the resolution can reach more than 3000PPI. As users' demand for small-size products increases, the requirements for display clarity and display effects are also getting higher and higher.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a driving substrate, a display panel and a display device to reduce the restriction of the demultiplexing circuit on the performance of the display panel.

[0005] According to one aspect of the present disclosure, a driving substrate is provided, comprising a display area and a decomposition circuit area; the display area is provided with a data line for applying a data voltage to a pixel driving circuit; the decomposition circuit area comprises a first decomposition circuit sub-area and a second decomposition circuit sub-area located on a side of the first decomposition circuit sub-area away from the display area;

[0006] In the first decomposition circuit sub-area, the driving substrate is provided with a plurality of demultiplexing circuits arranged along a row direction, each demultiplexing circuit comprises a plurality of transistor units; the first electrodes of the transistors in the same demultiplexing circuit are electrically connected to the same source signal line, and the second electrodes of the transistors in the same transistor unit are electrically connected to the same data line;

[0007] The second decomposition circuit sub-area has a plurality of selection signal lines corresponding one-to-one to a plurality of transistor units in the demultiplexing circuit and extending along the row direction, and the gates of the respective transistors of the transistor units are electrically connected to the corresponding selection signal lines.

[0008] According to one embodiment of the present disclosure, the size of the demultiplexing circuit along the column direction is a first size; the distance between the edge of the selection signal line closest to the display area close to the display area and the edge of the selection signal line farthest from the display area farthest from the display area is a second size; the second size is greater than the first size.

[0009] According to an embodiment of the present disclosure, the width of the selection signal line is greater than half the width of the channel region of the transistor in the demultiplexing circuit.

[0010] According to an embodiment of the present disclosure, the driving substrate includes a transistor layer and a plurality of metal layers stacked in sequence; the transistor layer is electrically connected to the first metal layer through a metallized via, and two adjacent metal layers are electrically connected through a metallized via;

[0011] In the second decomposition circuit sub-area, the driving substrate is provided with a first switching line of a strobe signal corresponding to each transistor unit one by one, and the first switching line of the strobe signal extends along the column direction and is electrically connected to the gate of each transistor of the corresponding transistor unit;

[0012] There is at least one metal layer between the metal layer where the first switching line of the selection signal is located and the metal layer where the selection signal line is located.

[0013] According to an embodiment of the present disclosure, the first switching line of the selection signal is arranged to overlap with each of the selection signal lines.

[0014] According to one embodiment of the present disclosure, a fourth select signal adapter wire is provided between the first select signal adapter wire and the electrically connected select signal line, and the first select signal adapter wire is electrically connected to the corresponding select signal line through the fourth select signal adapter wire; when the metal layer where the fourth select signal adapter wire is located is adjacent to the metal layer where the first select signal adapter wire is located, the first select signal adapter wire and the fourth select signal adapter wire are electrically connected to each other through at least two columns of metallized vias, and each column of metallized vias includes at least three metallized vias arranged in sequence along the column direction.

[0015] According to an embodiment of the present disclosure, the first metal layer has a second switching line for a gating signal corresponding to each transistor unit in the first decomposition circuit sub-area, and the second switching line for the gating signal is electrically connected to the gate of each transistor of the corresponding transistor unit through a metallized via;

[0016] The second switching line for the selection signal has a via portion for connecting to the metallized via hole and a routing portion connected to the via portion; the width of the routing portion of the second switching line for the selection signal is smaller than the width of the first switching line for the selection signal.

[0017] According to an embodiment of the present disclosure, the driving substrate includes a transistor layer and a plurality of metal layers stacked in sequence; the transistor layer is electrically connected to the first metal layer through a metallized via, and two adjacent metal layers are electrically connected through a metallized via;

[0018] In the second decomposition circuit sub-area, the driving substrate is provided with a source-end signal first adapter wire extending along the column direction, one end of the source-end signal first adapter wire is electrically connected to the source-end signal line, and the other end is electrically connected to the first electrode of each transistor of at least one transistor unit;

[0019] There is at least one metal layer between the metal layer where the source signal first adapter line is located and the metal layer where the selection signal line is located.

[0020] According to an embodiment of the present disclosure, the transistor unit includes a plurality of transistors connected in parallel, each of the transistors is arranged in sequence along a column direction, and a length direction of a channel region of each transistor is the row direction;

[0021] The driving substrate is provided with a first driving voltage adapter wire in the first decomposition circuit sub-area, which corresponds to the transistor units one by one and extends along the column direction. The first driving voltage adapter wire is electrically connected to the second electrode of each transistor of the transistor unit and is electrically connected to the data line.

[0022] According to an embodiment of the present disclosure, the demultiplexing circuit includes a plurality of transistor unit groups, each of which includes two adjacent transistor units;

[0023] The driving substrate is provided with second source-end signal adapters corresponding to the transistor unit groups in the first decomposition circuit sub-area, and the second source-end signal adapters are electrically connected to the first electrodes of the respective transistors in the corresponding transistor unit groups.

[0024] According to an embodiment of the present disclosure, the driving substrate includes a data line group corresponding to at least part of the transistor unit groups, the data line group includes two non-adjacent data lines, and the pixel driving circuit driven by the two data lines of the data line group is used to drive sub-pixels of the same color;

[0025] One data line of the data line group is electrically connected to the second electrodes of each transistor of a transistor unit of the corresponding transistor unit group, and another data line of the data line group is electrically connected to the second electrodes of each transistor of another transistor unit of the corresponding transistor unit group.

[0026] According to an embodiment of the present disclosure, the first decomposition circuit sub-area has a ring-shaped back-gate structure, and each of the multiplexing circuits is located in a space surrounded by the back-gate structure;

[0027] The gate signal line is located at a side of the back gate structure away from the display area.

[0028] According to an embodiment of the present disclosure, the driving substrate includes a semiconductor substrate and a plurality of metal layers stacked in sequence;

[0029] Wherein, the back gate structure comprises a ring-shaped back gate doping region located in the semiconductor substrate and a back gate wiring located in the first metal layer, and the back gate wiring is electrically connected to the back gate doping region through a metallized via;

[0030] The driving substrate is further provided with a metal structure crossing the back gate structure, and at least one metal layer is spaced between the metal layer where the metal structure crossing the back gate structure is located and the first metal layer.

[0031] According to another aspect of the present disclosure, a display panel is provided, comprising the above-mentioned driving substrate.

[0032] According to yet another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0035] Figure 1 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0036] Figure 2 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0037] Figure 3 The figure is a schematic diagram of a local structure of a driving substrate in one embodiment of the present disclosure.

[0038] Figure 4 The figure is a schematic diagram of a local structure of a driving substrate in one embodiment of the present disclosure.

[0039] Figure 5 The figure is a schematic diagram of a local structure of a driving substrate in one embodiment of the present disclosure.

[0040] Figure 6 The figure is a schematic diagram of the principle of a multiplexing circuit of a driving substrate in one embodiment of the present disclosure.

[0041] Figure 7The present invention is a schematic diagram of a driving timing sequence of a multiplexing circuit of a driving substrate in one embodiment of the present invention.

[0042] Figure 8 It is a schematic diagram of the structure of a doping region of a driving substrate in one embodiment of the present disclosure.

[0043] Fig. 9 FIG. 1 is a schematic structural diagram of a gate layer in one embodiment of the present disclosure.

[0044] Fig.10 It is a schematic diagram of the structure of stacking doped regions and gate layers in one embodiment of the present disclosure.

[0045] Fig.11 It is a partially enlarged schematic diagram of a doping region of a driving substrate in one embodiment of the present disclosure.

[0046] Fig.12 It is a partially enlarged schematic diagram of the stacking of the doped region and the gate layer in one embodiment of the present disclosure.

[0047] Fig.13 This is a schematic structural diagram of the first metal layer in one embodiment of the present disclosure.

[0048] Fig.14 It is a schematic diagram of the stacked structure of a first metal layer, a first metalized via, a gate layer, and a doped region in one embodiment of the present disclosure.

[0049] Fig.15 It is a schematic diagram of the structure of the second metal layer in one embodiment of the present disclosure.

[0050] Fig.16 It is a schematic diagram of the stacked structure of the first metal layer, the second metalized via, and the second metal layer in one embodiment of the present disclosure.

[0051] Fig.17 Schematic diagram of the structure of the third metal layer in one embodiment of the present disclosure.

[0052] Fig.18 It is a schematic diagram of the stacked structure of the second metal layer, the third metalized via, and the third metal layer in one embodiment of the present disclosure.

[0053] Fig.19 It is a schematic structural diagram of the fourth metal layer in one embodiment of the present disclosure.

[0054] Fig. 20 It is a schematic diagram of the stacked structure of the third metal layer, the fourth metalized via, and the fourth metal layer in one embodiment of the present disclosure.

[0055] Fig.21It is a schematic diagram of the stacked structure of a doped region, a gate layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer in one embodiment of the present disclosure.

[0056] Fig. 22 It is a partial schematic diagram of the stacked structure of the doped region, the gate layer, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0058] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0059] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0060] The present disclosure provides a display panel PNL and a driving substrate BP used by the display panel PNL. Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located at least on one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with array-distributed display units UU, and the display units UU include sub-pixels PX and pixel driving circuits PDC driving the sub-pixels PX. The display panel PNL does not provide display units UU in the peripheral area BB, or the provided display units UU are not used to display images. Figure 1 , the display panel PNL is provided with a plurality of scanning signal lines GateL extending along the row direction DH in the display area AA, and each scanning signal line GateL is provided in one-to-one correspondence with each display unit UU row. The pixel driving circuit PDC of each display unit UU in the display unit UU row is electrically connected to the corresponding scanning signal line GateL. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, and each data line DL is provided in one-to-one correspondence with each display unit UU column. The pixel driving circuit PDC of each display unit UU in the display unit UU column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit UU is connected to one scanning signal line GateL and one data line DL. When the scanning signal is loaded on the scanning signal line GateL, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PX according to the written driving voltage.

[0061] In some embodiments of the present disclosure, the sub-pixel PX may include sub-pixels PX of multiple different colors, such as a red sub-pixel for emitting red light, a green sub-pixel for emitting green light, and a blue sub-pixel for emitting blue light. It is understood that in other embodiments of the present disclosure, the sub-pixels PX in the display area AA may also have sub-pixels PX of other colors (such as a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0062] In one embodiment of the present disclosure, see Figure 2 The display panel PNL includes a driving substrate BP and a sub-pixel layer PXL which are stacked in sequence. A light-emitting element LD for emitting light is provided in the sub-pixel layer PXL, for example, an OLED is provided; and a pixel driving circuit PDC for driving the light-emitting element LD is provided in the driving substrate BP. Figure 2 In the example, the sub-pixel PX includes a light-emitting element LD and a color filter unit located on the light-emitting side of the light-emitting element LD (for example, the side away from the driving substrate BP). The light-emitting element LD can emit white light, for example, the light-emitting element LD can emit white light formed by mixing multiple colored lights; the white light emitted by the light-emitting element LD is emitted as colored light after passing through the color filter unit. For example, the white light emitted by the light-emitting element LD is filtered by the red color filter unit and then emits red light, and the sub-pixel PX is a red sub-pixel; the white light emitted by the light-emitting element LD is filtered by the green color filter unit and then emits green light, and the sub-pixel PX is a green sub-pixel; the white light emitted by the light-emitting element LD is filtered by the blue color filter unit and then emits blue light, and the sub-pixel PX is a blue sub-pixel.

[0063] Optionally, the light-emitting element LD may be a current-driven self-luminous element, for example, any one of light-emitting elements such as OLED, PLED, QLED, MicrOLED, MiNiLED, etc.

[0064] In an example, the light emitting element LD is an OLED, for example, a white light OLED.

[0065] It is understandable that in other embodiments of the present disclosure, the sub-pixel PX may also adopt other structures. For example, a light-emitting element such as OLED or MicrOLED may directly serve as the sub-pixel PX for light emission and display without further color conversion.

[0066] In one embodiment of the present disclosure, see Figure 3 The driving substrate BP includes a transistor layer ML and a plurality of metal layers stacked in sequence; the transistor layer ML is provided with transistors, for example, transistors required for the pixel driving circuit PDC, transistors required for the multiplexing circuit DM, etc. The transistors may be NMOS transistors or PMOS transistors as required.

[0067] In the embodiment of the present disclosure, the metal layer closest to the transistor layer ML is referred to as the first metal layer M1. An insulating layer (e.g., an inorganic insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer) is provided between the first metal layer M1 and the transistor layer ML, and between adjacent metal layers; a metallized via (e.g., a tungsten column, etc.) is provided in the insulating layer, so that the first metal layer M1 and the transistor layer ML are electrically connected, and adjacent metal layers are electrically connected.

[0068] In one example, see Figure 3 , the driving substrate BP includes a semiconductor substrate SBT (for example, a single crystal silicon substrate), and a CMOS process can be used to form a desired doped region on the semiconductor substrate SBT, wherein a portion of the doped region can be used as an active region BAA to form a transistor. On the surface of the semiconductor substrate SBT, a gate insulating layer GI and a gate layer GT can be formed in sequence and patterned. In this way, the active region BAA, the gate insulating layer GI and the gate layer GT of the semiconductor substrate SBT can form a desired transistor. In one example, the gate layer GT can be made of a non-metallic material, for example, the gate layer can be made of conductive polysilicon.

[0069] In one example, see Figure 3The driving substrate BP includes a first insulating layer D1, a first metal layer M1, a second insulating layer D2, a second metal layer M2, a third insulating layer D3, a third metal layer M3, a fourth insulating layer D4, a fourth metal layer M4, etc., which are sequentially stacked on one side of the transistor layer ML. Among them, a tungsten column as a first metallized via V1 is embedded in the first insulating layer D1. The transistor layer ML is electrically connected to the first metal layer M1 through the first metallized via V1. For example, the source, drain, gate, etc. of the transistor are electrically connected to the first metal layer M1 through the first metallized via V1. A second metallized via V2 is provided in the second insulating layer D2, and the second metal layer M2 is electrically connected to the first metal layer M1 through the second metallized via V2; a third metallized via V3 is provided in the third insulating layer D3, and the third metal layer M3 is electrically connected to the second metal layer M2 through the third metallized via V3; a fourth metallized via V4 is provided in the fourth insulating layer D4, and the fourth metal layer M4 is electrically connected to the third metal layer M3 through the fourth metallized via V4, and so on. Figure 3 In the example, only four metal layers are shown. As required, the driving substrate BP may be provided with more metal layers.

[0070] In one embodiment of the present disclosure, the driving substrate BP is prepared by using a single crystal silicon CMOS process.

[0071] In one embodiment of the present disclosure, the driving substrate BP can support high-resolution display, for example, 4K display. In one example, the resolution of the display panel PNL can reach 3956 PPI or higher.

[0072] Figure 4 FIG. 1 is a schematic diagram of a planar structure of a driving substrate BP in one embodiment of the present disclosure. Figure 4 In the example of, the driving substrate BP is provided with a decomposition circuit area DMA and a source signal line SL in the peripheral area BB, and a multiple decomposition circuit DM is provided in the decomposition circuit area DMA, and the source signal line SL can be electrically connected to the signal end of the source driving circuit. Among them, the multiple decomposition circuit DM is provided in a one-to-one correspondence with the source signal line SL, and the multiple decomposition circuit DM is electrically connected to multiple data lines DL and multiple selection signal lines. Under the control of the selection signal on the selection signal line, the multiple decomposition circuit DM can make the source signal line SL and the data line DL electrically connected to the multiple decomposition circuit DM be electrically connected one by one and selectively, so that the driving voltage loaded on the source signal line SL is loaded on different data lines DL in a time-sharing manner. In this way, one signal end of the source driving circuit can drive multiple data lines DL, so that the cost or size of the source driving circuit can be reduced.

[0073] In one example, the source driving circuit may be a part of the driving substrate BP, for example, the source driving circuit is prepared synchronously with the display area AA, or the source driving circuit is pre-packaged onto the driving substrate BP through a packaging process.

[0074] In another example, the source driver circuit is not a part of the driver substrate BP, but is connected to the driver substrate BP after the driver substrate BP is prepared. For example, a patch process is used to bind or bond the source driver circuit (which may be a source driver chip or a display driver chip that can realize source drive) to a chip binding area reserved on the driver substrate BP.

[0075] The demultiplexing circuit DM has a plurality of channel units, each of which includes one or more transistors. The channel unit is electrically connected to a data line DL and a strobe signal line, and is electrically connected to a source signal line SL. Specifically, the gates of the transistors in the channel unit are electrically connected to a strobe signal line, the second electrodes of the transistors in the channel unit are electrically connected to a data line DL, and the first electrodes of the transistors in the channel unit are electrically connected to the source signal line SL. When the strobe signal line electrically connected to the channel unit is loaded with a strobe signal that turns on the transistor (for example, a high level or a low level that can turn on each transistor in the channel unit), the channel unit is turned on so that the signal loaded on the source signal line SL can be loaded to the data line DL.

[0076] As an example, the demultiplexing circuit DM may have 3 to 12 channel units, for example, the demultiplexing circuit DM may have 6 channel units.

[0077] In the embodiment of the present disclosure, for the convenience of expression, each conductive structure can be divided into a corresponding signal channel according to the connection relationship with the channel unit, and the signal channel is a set of conductive structures carrying the same type of signals. Among them, the structure electrically connected to the gate of each transistor of the channel unit, such as the gate of the transistor, the gate of the transistor electrically connected to the gate of the transistor, and the routing that electrically connects the gate of the transistor to the gate of the transistor, is used as a gate signal channel. When the gate signal line of the gate signal channel is loaded with a gate signal (such as a low-level signal or a high-level signal), the channel unit controlled by the selected signal channel is turned on. The structure electrically connected to the second pole of each transistor of the channel unit, such as the second pole of the transistor, the data line DL electrically connected to the second pole of the transistor, and the routing that electrically connects the second pole of the transistor to the data line DL, is used as a data voltage channel; when each transistor of the channel unit is turned on, the voltage on the first pole of the transistor can be written into the data voltage channel. A structure electrically connected to the first electrode of each transistor of the channel unit, such as the first electrode of the transistor, a source terminal signal line SL electrically connected to the first electrode of the transistor, and a wiring electrically connecting the first electrode of the transistor to the source terminal signal line SL, is used as a source terminal signal channel. As an example, a demultiplexing circuit DM is connected to a source terminal signal channel, a plurality of selection signal channels and a driving voltage channel.

[0078] In the peripheral area BB, the driving substrate BP may be provided with other circuits, which may be directly manufactured by a CMOS process during the manufacturing process of the driving substrate BP, or may be formed on the driving substrate BP by a packaging process.

[0079] In one example, the driving substrate BP is pre-prepared or packaged with a variety of functional units with different functions on the peripheral area BB, for example, one or more of the functional units such as a memory, a timing controller, a communication interface, an image processing module, a source drive circuit, and a gate drive circuit are arranged on the peripheral area BB.

[0080] In another example, the driving substrate BP is provided with one or more chip binding areas on the peripheral area BB, and the chip binding area is provided with a binding pad for binding with a specific chip. For example, the driving substrate BP can pre-select a chip binding area for binding a display driver chip on the peripheral area BB, and the driving substrate BP can be bound and connected with the display driver chip.

[0081] The present disclosure also provides a display device, which includes any one of the display panels described in the above display panel embodiments. Optionally, the display device can be a display product or component with a high pixel density, such as a wearable device, a personal digital assistant, a clock, a global positioning system receiver / navigator, a virtual reality device, an augmented reality device, a mixed reality device, an extended reality device, a sight, a rangefinder, etc.

[0082] In the related art, the demultiplexing circuit DM is overlapped with the selection signal line that controls the demultiplexing circuit DM, which makes the data line DL connected to any channel overlap with each selection signal line, which increases the load of the data line DL and causes obvious driving voltage transmission delay. Not only is it easy to cause poor picture display effect (such as horizontal stripes, etc.) due to insufficient charging of the sub-pixel PX, but it also limits the improvement of the refresh rate of the display panel PNL.

[0083] The disclosed embodiment optimizes the structure in the decomposition circuit area DMA to reduce interference between different signal channels, thereby improving display quality and refresh rate.

[0084] In the embodiments of the present disclosure, see Figure 5 and Figure 6 , the driving substrate BP is provided with a decomposition circuit area DMA in the peripheral area BB, and the decomposition circuit area DMA includes a first decomposition circuit sub-area DMA1 and a second decomposition circuit sub-area DMA2 located on the side of the first decomposition circuit sub-area DMA1 away from the display area AA. In the first decomposition circuit sub-area DMA1, the driving substrate BP is provided with a plurality of demultiplexing circuits DM arranged in sequence along the row direction DH, and each demultiplexing circuit DM includes a plurality of transistor units MU as channel units; the first electrodes MS of each transistor in the same demultiplexing circuit DM are electrically connected to the same source signal line SL, and the second electrodes MD of each transistor in the same transistor unit MU are electrically connected to the same data line DL. The second decomposition circuit sub-area DMA2 has a plurality of selection signal lines MUXL corresponding to the plurality of transistor units MU in the demultiplexing circuit DM one by one, and the gates MG of each transistor of the transistor unit MU are electrically connected to the corresponding selection signal lines MUXL; the selection signal lines MUXL extend along the row direction DH.

[0085] In the disclosed embodiment, the demultiplexing circuit DM is arranged in the first decomposition circuit sub-area DMA1 and the selection signal line MUXL is arranged in the second decomposition circuit sub-area DMA2, so the second pole MD of each transistor of the demultiplexing circuit DM will not overlap with the selection signal line MUXL, which makes it possible to form no or substantially no coupling capacitance between the driving voltage channel and the selection signal channel, avoiding the problem that the parasitic capacitance of the driving voltage channel is too large, resulting in excessive signal delay when the driving voltage is loaded, and thus avoiding the problem of insufficient charging rate of the pixel driving circuit PDC due to the parasitic capacitance of the driving voltage channel. This can improve the reduction in display quality caused by insufficient charging rate. Moreover, the signal delay of the driving voltage on the driving voltage channel becomes smaller, which is conducive to improving the refresh rate of the display panel.

[0086] On the other hand, no or substantially no coupling capacitance is formed between the selection signal line MUXL and the data line DL, which can reduce the impact of signal changes on the selection signal channel on the signal on the driving voltage channel, thereby improving the accuracy and stability of the driving voltage on the driving voltage channel, thereby improving the quality of the display panel.

[0087] Furthermore, each transistor unit MU of the multiplexing circuit DM serves as a channel unit, which has multiple transistors. These transistors in the same channel unit are arranged in parallel, which is conducive to increasing the current when the source signal channel loads the driving voltage to the driving voltage channel, and avoiding the restriction of the refresh rate due to insufficient driving capability of the transistor unit MU.

[0088] Moreover, the coupling capacitance between the data line DL and the selection signal line MUXL is reduced, which can also reduce the crosstalk of the driving voltage on the driving voltage channel to the selection signal line MUXL, thereby improving the stability of the selection signal on the selection signal line MUXL, thereby avoiding the deterioration of the signal waveform on the selection signal line MUXL and restricting the refresh rate of the display panel PNL.

[0089] exist Figure 6In the example, each demultiplexing circuit DM includes 6 transistor units MU, which are respectively marked as a first transistor unit MU1, a second transistor unit MU2, a third transistor unit MU3, a fourth transistor unit MU4, a fifth transistor unit MU5 and a sixth transistor unit MU6, and each transistor unit MU includes three transistors. Accordingly, the number of the selection signal lines MUXL is 6 and corresponds to the six transistor units MU one by one, namely, a first selection signal line MUXL1, a second selection signal line MUXL2, a third selection signal line MUXL3, a fourth selection signal line MUXL4, a fifth selection signal line MUXL5, and a sixth selection signal line MUXL6. That is, the first selection signal line MUXL1 is electrically connected to the gate MG of each transistor of the first transistor unit MU1, the second selection signal line MUXL2 is electrically connected to the gate MG of each transistor of the second transistor unit MU2, the third selection signal line MUXL3 is electrically connected to the gate MG of each transistor of the third transistor unit MU3, the fourth selection signal line MUXL4 is electrically connected to the gate MG of each transistor of the fourth transistor unit MU4, the fifth selection signal line MUXL5 is electrically connected to the gate MG of each transistor of the fifth transistor unit MU5, and the sixth selection signal line MUXL6 is electrically connected to the gate MG of each transistor of the sixth transistor unit MU6. The source signal line SL is electrically connected to the first electrode MS of each transistor.

[0090] In one embodiment of the present disclosure, see Figure 5 The first decomposition circuit sub-area DMA1 has a ring-shaped back gate structure BG, and each of the multiplexing circuits DM is located in a space surrounded by the back gate structure BG; the selection signal line MUXL is located on a side of the back gate structure BG away from the display area AA.

[0091] Alternatively, see Figure 3 The back gate structure BG includes a ring-shaped back gate doping region BG1 located on the semiconductor substrate SBT and a back gate wiring BG2 located on the first metal layer M1, and the back gate wiring BG2 is electrically connected to the back gate doping region BG1 through a metallized via. The driving substrate BP is also provided with a metal structure crossing the back gate structure BG, and at least one metal layer is spaced between the metal layer where the metal structure crossing the back gate structure BG is located and the first metal layer M1, so as to reduce the coupling between the metal structure crossing the back gate structure BG and the back gate wiring BG2.

[0092] For example, the source signal path needs to cross the back gate structure BG to be electrically connected to the first electrode MS of the transistor. The metal structure of the source signal path crossing the back gate structure BG can be set in the third metal layer M3, the fourth metal layer M4 or a metal layer farther away from the semiconductor substrate SBT.

[0093] For example, the selection signal channel needs to cross the back gate structure BG to be electrically connected to the gate MG of the transistor. The metal structure of the selection signal channel crossing the back gate structure BG can be set in the third metal layer M3, the fourth metal layer M4 or a metal layer farther away from the semiconductor substrate SBT.

[0094] For example, the driving voltage channel needs to cross the back gate structure BG to be electrically connected to the demultiplexing circuit DM. The metal structure of the driving voltage channel crossing the back gate structure BG can be set in the third metal layer M3, the fourth metal layer M4 or a metal layer farther away from the semiconductor substrate SBT.

[0095] In the related art, the gate signal line is overlapped with the demultiplexing circuit DM so that the signal on the gate signal line can be loaded onto the gate of the transistor of the demultiplexing circuit DM. The total width of each gate signal line and the gap between the gate signal lines cannot exceed the width of the demultiplexing circuit DM. However, the width of the demultiplexing circuit DM (the size along the column direction DV) is limited, which results in the width of the gate signal line and the gap between the gate signal lines being restricted. The gate signal line cannot be set with a larger width as required, resulting in a larger impedance of the gate signal line and a larger delay of the gate signal. The size of the gap between the gate signal lines is limited, which makes it easy to generate crosstalk between the gate signal lines, thereby causing the waveform of the gate signal to deteriorate; the coupling capacitance between the gate signal lines is large, which will further increase the load of the gate signal and further increase the delay of the gate signal. Therefore, in the related art, there is a risk of large gate signal delay and waveform deterioration, which in turn restricts the improvement of the refresh rate of the display panel PNL.

[0096] In the embodiment of the present disclosure, the selection signal line MUXL and the demultiplexing circuit DM are no longer overlapped, and the width thereof and the width of the gap between adjacent selection signal lines MUXL are no longer restricted by the size of the demultiplexing circuit DM. Therefore, the delay and waveform of the selection signal can be improved by increasing the width of the selection signal line MUXL, or by increasing the gap between the selection signal lines MUXL, or by increasing the width of the selection signal line MUXL and the gap between the selection signal lines MUXL at the same time.

[0097] In one embodiment of the present disclosure, see Fig.12 , the size of the demultiplexing circuit DM along the column direction DV is a first size X1; see Fig.17, the distance between the edge of the strobe signal line MUXL closest to the display area AA and the edge of the strobe signal line MUXL farthest from the display area AA and farthest from the display area AA is a second size X2; the second size X2 is greater than the first size X1. The second size is the sum of the width of each strobe signal line MUXL and the width of the gap between the strobe signal lines MUXL.

[0098] Optionally, the second size is 1.5 to 5 times the first size. For example, the second size is 1.5, 1.7, 1.9, 2.1, 2.3, 2.5, 2.7, 2.9 or 3.1 times the first size.

[0099] In one embodiment of the present disclosure, the width of the strobe signal line MUXL is greater than half the width of the channel region of the transistor in the demultiplexing circuit DM. In this way, the strobe signal line MUXL has a larger width and can reduce impedance.

[0100] Optionally, the width of the gate signal line MUXL is 0.6 to 1.5 times the width of the channel region of the transistor, for example, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4 or 1.5 times. As an example, the width of the gate signal line MUXL is 0.9 to 1.1 times the width of the channel region of the transistor.

[0101] In one embodiment of the present disclosure, the width of the gap between the gate signal lines MUXL may be no less than 0.2 times the width of the channel region of the transistor in the demultiplexing circuit DM. In this way, the gap between the gate signal lines MUXL is larger, and the parasitic capacitance between adjacent gate signal lines MUXL is smaller, which can reduce the load of the gate signal channel to reduce power consumption, and is conducive to improving the delay and waveform of the gate signal on the gate signal channel.

[0102] Optionally, the width of the selection signal line MUXL is 0.3 to 0.7 times the width of the channel region of the transistor, for example, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65 or 0.7 times.

[0103] In one example, the spacing between the gate signal lines MUXL is not less than 0.5 micrometers, such as 0.5-1.0 micrometers. For example, the spacing between the gate signal lines MUXL is 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers or 1.0 micrometers.

[0104] In one example, the width of the strobe signal line MUXL is not less than 1.75 microns, in particular not less than 2 microns, such as between 2.0 and 3.5 microns. For example, the width of the strobe signal line MUXL is 2.0 microns, 2.3 microns, 2.6 microns, 2.9 microns, 3.2 microns or 3.5 microns.

[0105] In an embodiment of the present disclosure, each of the strobe signal lines MUXL is disposed on the same metal layer, so that the strobe signal lines MUXL are prevented from overlapping and causing excessive coupling capacitance.

[0106] In one embodiment of the present disclosure, see Figure 6 , Fig.13 and Fig.14 In the second decomposition circuit sub-area DMA2, the driving substrate BP is provided with a first selection signal transfer line GL1 corresponding to each transistor unit MU, and the first selection signal transfer line GL1 extends along the column direction DV and is electrically connected to the gate MG of each transistor of the corresponding transistor unit MU. There is at least one metal layer between the metal layer where the first selection signal transfer line GL1 is located and the metal layer where the selection signal line MUXL is located.

[0107] In this embodiment, the selection signal on the selection signal line MUXL can be transferred to the first selection signal transfer line GL1, and then loaded to the gate MG of each transistor of the corresponding transistor unit MU through the first selection signal transfer line GL1. At least part of the first selection signal transfer line GL1 inevitably needs to overlap with the selection signal line MUXL of other selection signal channels in the second decomposition circuit sub-area DMA2. In this embodiment, the first selection signal transfer line GL1 and the selection signal line MUXL are respectively located in non-adjacent metal layers, which can ensure that there is a large spacing between the first selection signal transfer line GL1 and the selection signal lines MUXL of other selection signal channels, thereby reducing the coupling capacitance between the first selection signal transfer line GL1 and the selection signal lines MUXL of other selection signal channels.

[0108] In an example, there are 1 to 3 metal layers between the strobe signal line MUXL and the strobe signal first switching line GL1, for example, there are 1 metal layer, 2 metal layers or 3 metal layers.

[0109] In one example, see Figure 6 and Fig.21 The first switching lines GL1 for the strobe signals are overlapped with the strobe signal lines MUXL. For example, the first switching lines GL1 for the strobe signals have the same length and are overlapped with the strobe signal lines MUXL to ensure that the loads of different strobe signal channels are the same.

[0110] In this embodiment, compared with the first gate signal transfer line GL1, the gate signal line MUXL may be disposed in a metal layer closer to the transistor layer ML, or may be disposed in a metal layer farther away from the transistor layer ML.

[0111] In this embodiment, see Figure 13 to Figure 18 , each metal layer between the first selection signal adapter wire GL1 and the electrically connected selection signal line MUXL can be provided with a fourth selection signal adapter wire GL4 corresponding to the first selection signal adapter wire GL1, and the first selection signal adapter wire GL1, the fourth selection signal adapter wire GL4 adjacent to the first selection signal adapter wire GL1, the adjacent fourth selection signal adapter wire GL4, and the selection signal line MUXL and the adjacent fourth selection signal adapter wire GL4 are electrically connected through metallized vias. In this way, the first selection signal adapter wire GL1 and the corresponding selection signal line MUXL are electrically connected through the metallized vias and the fourth selection signal adapter wire GL4. In other words, on the same selection signal channel, the first selection signal adapter wire GL1 and the first selection signal line MUXL1 are electrically connected through the fourth selection signal adapter wire GL4.

[0112] In one example, see Fig.16 and Fig.18 , the orthographic projection of the fourth switching line GL4 of the selection signal corresponding to the first switching line GL1 of the selection signal on the plane where the driving substrate BP is located is located within the orthographic projection range of the first switching line GL1 of the selection signal on the plane where the driving substrate BP is located, and is located within the orthographic projection range of the corresponding selection signal line MUXL on the plane where the driving substrate BP is located. In this way, the fourth switching line GL4 of the selection signal only overlaps with the first switching line GL1 of the selection signal and the selection signal line MUXL of the same selection signal channel, and does not overlap with the selection signal line MUXL and the first switching line GL1 of the selection signal of other selection signal channels, and does not cause the load of the selection signal channel to increase.

[0113] In one example, see Fig.16 In the same strobe signal channel, the first strobe signal transfer line GL1 and the adjacent fourth strobe signal transfer line GL4 are electrically connected to each other through at least two columns of metallized vias, and each column of metallized vias includes at least three metallized vias sequentially arranged along the column direction DV. In this way, there are multiple metallized vias between the first strobe signal transfer line GL1 and the adjacent fourth strobe signal transfer line GL4, and the resistance is relatively small, which is conducive to reducing the load and delay of the strobe signal channel.

[0114] In this example, the first select signal adapter GL1 is connected to the adjacent fourth select signal adapter GL4 by no less than 6 metallized vias, and these metallized vias are arranged in at least two columns. This is mainly due to the fact that the select signal line MUXL is arranged in the second decomposition circuit sub-area DMA2 and its size is no longer limited by the size of the first decomposition circuit sub-area DMA1, and the electrical connection between different metal layers also has a more flexible design space to reduce resistance. Optionally, the first select signal adapter GL1 is connected to the adjacent fourth select signal adapter GL4 by no less than 6 metallized vias, for example, by 6, 8, 10, 12, 14, 16, 18 or 20 metallized vias, and these metallized vias are arranged in at least two columns. Further, the first select signal adapter GL1 is connected to the adjacent fourth select signal adapter GL4 by at least 10 metallized vias.

[0115] Correspondingly, in the same selection signal channel, adjacent selection signal fourth transfer lines GL4 are connected by no less than 6 metallized vias, and these metallized vias are arranged in at least two columns. For example, they are connected by 6 to 20 metallized vias. It can be understood that when there is only one metal layer between the selection signal first transfer line GL1 and the selection signal line MUXL, only one selection signal fourth transfer line GL4 is set between the selection signal first transfer line GL1 and the selection signal line MUXL instead of multiple selection signal fourth transfer lines GL4.

[0116] Accordingly, see Fig.18 In the same selection signal channel, the fourth selection signal adapter line GL4 is connected to the adjacent selection signal line MUXL through no less than 6 metallized vias, and these metallized vias are arranged in at least two columns; for example, they are connected through 6 to 20 metallized vias. Furthermore, the fourth selection signal adapter line GL4 is connected to the adjacent selection signal line MUXL through at least 10 metallized vias.

[0117] In one embodiment of the present disclosure, see Figure 6 , Fig.13 and Fig.14, the first metal layer M1 has a second switching line GL2 of a strobe signal corresponding to each transistor unit MU in the first decomposition circuit sub-area DMA1, and the second switching line GL2 of the strobe signal is electrically connected to the gate MG of each transistor of the corresponding transistor unit MU through a metallized via. The first metal layer M1 also needs to set a second switching line SL2 of a source signal in the first decomposition circuit sub-area DMA1, and the second switching line SL2 of the source signal is electrically connected to the first pole MS of each transistor of the transistor unit MU through a metallized via. The first metal layer M1 also needs to set a first switching line DL1 of a driving voltage corresponding to each transistor unit MU in the first decomposition circuit sub-area DMA1, and the first switching line DL1 of the driving voltage is electrically connected to the second pole MD of each transistor of the corresponding transistor unit MU. In this way, the first switching line DL1 of the driving voltage, the second switching line GL2 of the strobe signal, and the second switching line SL2 of the source signal are all located in the first metal layer M1 and are all electrically connected to the transistor, but belong to different signal channels. In order to reduce the coupling between the three signal channels, it is necessary to limit the width of the second switching line GL2 of the strobe signal. For example, the second switching line GL2 of the selection signal has a via portion L22 for connecting to the metallized via hole and a routing portion L21 connected to the via portion L22. The via portion has a larger width so that the via portion can be electrically connected to the gate MG of the transistor through more first metallized via holes V1. The width of the routing portion L21 is smaller than the via portion so as to reduce the spacing between the routing portion L21 and the first switching line DL1 of the driving voltage and the second switching line SL2 of the source signal.

[0118] In one example, participating Fig.16 , the width of the routing portion of the second select signal adapter GL2 is smaller than the width of the first select signal adapter GL1. In other words, the first select signal adapter GL1 located in the second decomposition circuit sub-area DMA2 can have a larger width. No driving voltage channel is set in the second decomposition circuit sub-area DMA2, so there is enough space to set the first select signal adapter GL1 with a larger width. Furthermore, the width of the first select signal adapter GL1 is greater than the width of the via portion of the second select signal adapter GL2. Therefore, the resistance of the first select signal adapter GL1 is relatively small, and although the select signal line MUXL is set outside the first decomposition circuit sub-area DMA1, it does not cause a large resistance between the select signal line MUXL and the second select signal adapter GL2.

[0119] In an embodiment of the present disclosure, the first switching line GL1 of the selection signal and the second switching line GL2 of the selection signal are directly connected to each other, or may be switched through other metal structures to ensure the electrical continuity of the selection signal channel.

[0120] In one example, see Figure 6 , the selection signal channel also includes a third selection signal adapter line GL3, which crosses the back gate structure BG and has its two ends electrically connected to the first selection signal adapter line GL1 and the second selection signal adapter line GL2 respectively. It can be understood that the third selection signal adapter line GL3 can be directly electrically connected to the first selection signal adapter line GL1 through the metallized via VV, and can also be indirectly electrically connected to the first selection signal adapter line GL1 through other metal layers. The third selection signal adapter line GL3 can be directly electrically connected to the second selection signal adapter line GL2 through the metallized via VV, and can also be indirectly electrically connected to the second selection signal adapter line GL2 through other metal layers. Furthermore, there is at least one metal layer between the metal layer where the third selection signal adapter line GL3 is located and the first metal layer M1.

[0121] In one embodiment of the present disclosure, see Figure 6 and Fig.16 In the second decomposition circuit sub-area DMA2, the driving substrate BP is provided with a source signal first transfer line SL1 extending along the column direction DV, one end of the source signal first transfer line SL1 is electrically connected to the source signal line SL, and the other end is electrically connected to the first electrode MS of each transistor of at least one transistor unit MU. There is at least one metal layer between the metal layer where the source signal first transfer line SL1 is located and the metal layer where the selection signal line MUXL is located. In this way, the coupling between the source signal channel and the selection signal channel can be reduced.

[0122] In one embodiment of the present disclosure, see Fig.16 The source signal first switching line SL1 and the selection signal first switching line GL1 can be arranged on the same metal layer and arranged side by side.

[0123] In one embodiment of the present disclosure, see Fig.16 The source signal line SL and the source signal first transfer line SL1 can be arranged in the same metal layer. For example, the end of the source signal line SL close to the second decomposition circuit sub-area DMA2 has a side branch extending along the row direction DH, and the end of the source signal first transfer line SL1 close to the source signal line SL is connected to the side branch of the source signal line SL.

[0124] In one embodiment of the present disclosure, see Figure 6, the source signal channel also includes a third source signal adapter line SL3, which crosses the back gate structure BG and has two ends electrically connected to the first source signal adapter line SL1 and the second source signal adapter line SL2. It can be understood that the third source signal adapter line SL3 can be directly electrically connected to the first source signal adapter line SL1 through the metallized via VV, or indirectly electrically connected to the first source signal adapter line SL1 through other metal layers. The third source signal adapter line SL3 can be directly electrically connected to the second source signal adapter line SL2 through the metallized via VV, or indirectly electrically connected to the second source signal adapter line SL2 through other metal layers.

[0125] In one embodiment of the present disclosure, see Figure 6 The driving voltage channel also includes a second driving voltage adapter line DL2, which crosses the back gate structure BG and is electrically connected to the first driving voltage adapter line DL1 and the data line DL at both ends. It can be understood that the second driving voltage adapter line DL2 can be directly electrically connected to the first driving voltage adapter line DL1 through a metallized via VV, or indirectly electrically connected to the first driving voltage adapter line DL1 through other metal layers. The second driving voltage adapter line DL2 can be directly electrically connected to the data line DL through a metallized via VV, or indirectly electrically connected to the data line DL through other metal layers.

[0126] In one embodiment of the present disclosure, see Figure 6 and Fig.12 The transistor unit MU includes a plurality of transistors connected in parallel, each of which is arranged in sequence along the column direction DV, and the length direction of the channel region of each transistor is the row direction DH. In the same transistor unit MU, the gates MG of each transistor are arranged in a straight line along the column direction DV, the first electrodes MS of each transistor are arranged in a straight line along the column direction DV, and the second electrodes MD of each transistor are arranged in a straight line along the column direction DV. The first drive voltage transfer line DL1 electrically connected to the transistor unit MU can extend along the column direction DV and be electrically connected to the second electrodes MD of each transistor through the first metallized via V1.

[0127] Accordingly, see Figure 6 The second switching line GL2 of the selection signal electrically connected to the transistor unit MU may also extend along the column direction DV and be electrically connected to the gate MG of each transistor through the first metallized via V1.

[0128] Accordingly, see Figure 6 The source-end signal second transfer line SL2 electrically connected to the transistor unit MU may also extend along the column direction DV and be electrically connected to the first electrode MS of each transistor through the first metallized via V1.

[0129] In one embodiment of the present disclosure, see Figure 6 and Fig.12 , the demultiplexing circuit DM includes a plurality of transistor unit groups MUS, each of which includes two adjacent transistor units MU; the driving substrate BP is provided with a source-end signal second transfer line SL2 corresponding to each transistor unit group MUS in the first decomposition circuit sub-area DMA1, and the source-end signal second transfer line SL2 is electrically connected to the first electrode MS of each transistor in the corresponding transistor unit group MUS. In other words, two transistor units MU in the same transistor unit group MUS can share the same source-end signal second transfer line SL2, thereby reducing the number of routings such as the source-end signal second transfer line SL2 and the source-end signal first transfer line SL1, which is beneficial to improving the distribution density of the demultiplexing circuit DM in the decomposition circuit area DMA, and also beneficial to reducing the coupling capacitance between the source-end signal channel and the selection signal channel.

[0130] In one example, see Fig.12 The transistor unit group MUS includes a plurality of transistor pairs MP sequentially arranged along the column direction DV, each transistor pair MP includes transistors belonging to two transistor units MU respectively, and the two transistors of the transistor pair MP share a first electrode. The two transistors of the transistor pair are arranged along the row direction DH.

[0131] In one example, see Figure 6 Each transistor unit group MUS is connected to two second switching lines GL2 for selection signals, two first switching lines DL1 for driving voltages and one second switching line SL2 for source signals; along the row direction DH, the first switching line DL1 for driving voltages, the second switching line GL2 for selection signals, the second switching line SL2 for source signals, the second switching line GL2 for selection signals, and the first switching line DL1 for driving voltages are arranged in sequence, and these lines all extend in a straight line along the column direction DV.

[0132] In one example, see Fig.11 and Fig.12, the semiconductor substrate SBT has an active area BAA corresponding to the transistor pair in the first decomposition circuit sub-area DMA1, and a transistor pair MP is arranged in each active area BAA. In other words, the transistor pairs share the same active area. In this way, the arrangement of the transistor pairs can be made more compact. For example, along the row direction DH, the active area includes a first doping area A1, a second doping area B1, a third doping area A2, a fourth doping area B2 and a fifth doping area A3 arranged in sequence. Among them, the doping types of the first doping area A1, the third doping area A2 and the fifth doping area A3 can be the same and be conductorized, and the doping types of the second doping area B1 and the fourth doping area B2 can be opposite to the first doping area A1 and maintain semiconductor characteristics. When the first doping area A1, the third doping area A2 and the fifth doping area A3 are all N-type doped, and the second doping area B1 and the fourth doping area B2 are P-type doped, the transistor of the transistor pair is an N-type transistor, and the gating signal corresponding to the transistor unit MU is a high level. When the first doping region A1, the third doping region A2, and the fifth doping region A3 are all P-type doped, and the second doping region B1 and the fourth doping region B2 are N-type doped, the transistors of the transistor pair are P-type transistors, and the selection signal corresponding to the transistor unit MU is a low level.

[0133] Among them, the first doping region A1, the third doping region A2, and the fifth doping region A3 can be electrically connected to the first driving voltage transfer line DL1, the source signal second transfer line SL2, and the first driving voltage transfer line DL1 through the first metallized via V1 respectively; the second doping region B1 and the fourth doping region B2 can be respectively arranged to overlap with the gates of the two transistors, and respectively overlap with the two selection signal second transfer lines GL2.

[0134] In one example, see Figure 6 The driving substrate BP includes a data line group DLS corresponding to at least part of the transistor unit group MUS, the data line group DLS includes two non-adjacent data lines DL, and the pixel driving circuit PDC driven by the two data lines DL of the data line group DLS is used to drive sub-pixels of the same color. One data line DL of the data line group DLS is electrically connected to the second electrodes MD of each transistor of one transistor unit MU of the corresponding transistor unit group MUS, and another data line DL of the data line group DLS is electrically connected to the second electrodes MD of each transistor of another transistor unit MU of the corresponding transistor unit group MUS.

[0135] For example, in Figure 6In the example, each demultiplexing circuit DM drives six data lines DL, and the six data lines DL are marked as the first data line DL(1), the second data line DL(2), the third data line DL(3), the fourth data line DL(4), the fifth data line DL(5), and the sixth data line DL(6) in the order of arrangement in the row direction DH in the display area AA. Among them, the sub-pixels driven by the first data line DL(1) and the fourth data line DL(4) are red sub-pixels, the sub-pixels driven by the second data line DL(2) and the fifth data line DL(5) are green sub-pixels, and the sub-pixels driven by the third data line DL(3) and the sixth data line DL(6) are blue sub-pixels. The demultiplexing circuit DM includes three transistor unit groups MUS, and each transistor unit group MUS includes two transistor units MU. Along the row direction DH, the six transistor units MU are marked as the first transistor unit MU1, the second transistor unit MU2, the third transistor unit MU3, the fourth transistor unit MU4, the fifth transistor unit MU5, and the sixth transistor unit MU6. The first transistor unit MU1 and the second transistor unit MU2 are the same transistor unit group MUS, the first data line DL(1) and the fourth data line DL(4) are the same data line group DLS, the first transistor unit MU1 drives the first data line DL(1), and the second transistor unit MU2 drives the fourth data line DL(4). The third transistor unit MU3 and the fourth transistor unit MU4 are the same transistor unit group MUS, the second data line DL(2) and the fifth data line DL(5) are the same data line group DLS, the third transistor unit MU3 drives the second data line DL(2), and the fourth transistor unit MU4 drives the fifth data line DL(5). The fifth transistor unit MU5 and the sixth transistor unit MU6 are the same transistor unit group MUS, the third data line DL(3) and the sixth data line DL(6) are the same data line group DLS, the fifth transistor unit MU5 drives the third data line DL(3), and the sixth transistor unit MU6 drives the sixth data line DL(6).

[0136] In this embodiment, although the same transistor unit group MUS provides two different driving voltage channels, the sub-pixels PX driven by the two driving voltage channels are sub-pixels of the same color. Since the driving voltage range required by the sub-pixels of the same color is consistent, the driving voltage fluctuation range is not large, and the driving voltage fluctuation caused by the shared source region of the transistor pair is relatively small, which is conducive to reducing the crosstalk between the two driving voltage channels of the transistor unit group MUS.

[0137] In this embodiment, the strobe signal line MUXL driving the demultiplexing circuit DM corresponds to the data line DL driven by the demultiplexing circuit DM in a one-to-one manner, so as to ensure a correct driving algorithm. For example, the transistor unit MU controlled by the first strobe signal line MUXL1 is used to drive the first data line DL(1), the transistor unit MU controlled by the second strobe signal line MUXL2 is used to drive the second data line DL(2), the transistor unit MU controlled by the third strobe signal line MUXL3 is used to drive the third data line DL(3), the transistor unit MU controlled by the fourth strobe signal line MUXL4 is used to drive the fourth data line DL(4), the transistor unit MU controlled by the fifth strobe signal line MUXL5 is used to drive the fifth data line DL(5), and the transistor unit MU controlled by the sixth strobe signal line MUXL6 is used to drive the sixth data line DL(6). Therefore, it is necessary to determine the strobe signal line MUXL controlling the transistor unit MU according to the data line DL driven by the transistor unit MU, and then change the connection sequence between the strobe signal line MUXL and the transistor unit MU without changing the position of the strobe signal line MUXL.

[0138] For example, in Figure 6 In the example, the first selection signal line MUXL1 is electrically connected to the first selection signal switching line GL1 connected to the first transistor unit MU1, the fourth selection signal line MUXL4 is electrically connected to the first selection signal switching line GL1 connected to the second transistor unit MU2, the second selection signal line MUXL2 is electrically connected to the first selection signal switching line GL1 connected to the third transistor unit MU3, the fifth selection signal line MUXL5 is electrically connected to the first selection signal switching line GL1 connected to the fourth transistor unit MU4, the third selection signal line MUXL3 is electrically connected to the first selection signal switching line GL1 connected to the fifth transistor unit MU5, and the sixth selection signal line MUXL6 is electrically connected to the first selection signal switching line GL1 connected to the sixth transistor unit MU6.

[0139] In one example, see Figure 6 and Fig. 22The driving substrate BP is provided with a transfer area BA between the first decomposition circuit sub-area DMA1 and the display area AA. The driving voltage channel is provided with a driving voltage third transfer line DL3 in the transfer area BA. The driving voltage third transfer line DL3 is used to electrically connect the driving voltage second transfer line DL2 with the corresponding data line DL. Along the row direction DH, the order of the driving voltage second transfer lines DL2 of each transistor unit MU of the demultiplexing circuit DM may be inconsistent with the order of the data lines DL to which each transistor unit MU of the demultiplexing circuit DM needs to be electrically connected. Therefore, at least part of the driving voltage third transfer line DL3 needs to be bent in the row direction DH to ensure that the driving voltage second transfer line DL2 and the data line DL in the same driving voltage channel are electrically connected.

[0140] It is understandable that part of the third driving voltage transition wires DL3 may not be bent in the row direction DH to ensure the electrical continuity of the driving voltage channel.

[0141] In one example, see Figure 6 and Fig. 22 The first driving voltage transfer line DL1 and the second driving voltage transfer line DL2 of the same driving voltage channel can be arranged in a straight line along the column direction DV. In this way, the arrangement order of the ends of the second driving voltage transfer line DL2 is consistent with the order of the driving voltages output by the demultiplexing circuit DM.

[0142] exist Figure 6 and Fig. 22In the example, the driving voltage third adapter line DL3 includes a first sub-adapter line DL31 corresponding to the first transistor unit MU1, a second sub-adapter line DL32 corresponding to the second transistor unit MU2, a third sub-adapter line DL33 corresponding to the third transistor unit MU3, a fourth sub-adapter line DL34 corresponding to the fourth transistor unit MU4, a fifth sub-adapter line DL35 corresponding to the fifth transistor unit MU5, and a sixth sub-adapter line DL36 corresponding to the sixth transistor unit MU6. Among them, the driving voltage second adapter line DL2 corresponding to the first transistor unit MU1 is electrically connected to the first data line DL(1) through the first sub-adapter line DL31; the driving voltage second adapter line DL2 corresponding to the second transistor unit MU2 is electrically connected to the fourth data line DL(4) through the second sub-adapter line DL32; the driving voltage second adapter line DL2 corresponding to the third transistor unit MU3 is electrically connected to the second data line DL(2) through the third sub-adapter line DL33; the driving voltage second adapter line DL2 corresponding to the fourth transistor unit MU4 is electrically connected to the fifth data line DL(5) through the fourth sub-adapter line DL34; the driving voltage second adapter line DL2 corresponding to the fifth transistor unit MU5 is electrically connected to the third data line DL(3) through the fifth sub-adapter line DL35; the driving voltage second adapter line DL2 corresponding to the sixth transistor unit MU6 is electrically connected to the sixth data line DL(6) through the sixth sub-adapter line DL36.

[0143] As follows, Figure 6 Taking the illustrated demultiplexing circuit DM as an example, the driving method of the demultiplexing circuit DM provided by the embodiment of the present disclosure is exemplarily described. Figure 7 FIG. 1 is a driving timing diagram of the multiplexing circuit DM. It can be understood that: Figure 6 The exemplary demultiplexing circuit DM may also be driven using other timing sequences.

[0144] join Figure 7 In a display frame (from one horizontal synchronization signal HSYNC to another horizontal synchronization signal HSYNC), the source signal line SL is loaded with the reset voltage Vofs, the first drive voltage S1, the second drive voltage S2, the third drive voltage S3, the fourth drive voltage S4, the fifth drive voltage S5, and the sixth drive voltage S6 in sequence during the time period t0 to t6. At time t0, the first selection signal line MUXL1 to the sixth selection signal line MUXL6 are loaded with the selection signal at the same time (at Figure 7In the example, the selection signal is a low-level signal), which makes the first transistor unit MU1 to the sixth transistor unit MU6 turned on at the same time, so that the pixel driving circuit PDC on the six data lines DL driven by the multiplexing circuit DM is reset synchronously. At time t1, the first selection signal line MUXL1 is loaded with the selection signal, which makes the first transistor unit MU1 turned on, and the first driving voltage S1 on the source signal line SL is loaded to the data line DL driven by the first transistor unit MU1. At time t2, the second selection signal line MUXL2 is loaded with the selection signal, which makes the second transistor unit MU2 turned on, and the second driving voltage S2 on the source signal line SL is loaded to the data line DL driven by the second transistor unit MU2. Similarly, at time t3, the third selection signal line MUXL3 is loaded with the selection signal, the third transistor unit MU3 is turned on, and the third driving voltage S3 on the source signal line SL is loaded to the data line DL driven by the third transistor unit MU3. At time t4, the fourth selection signal line MUXL4 is loaded with a selection signal, the fourth transistor unit MU4 is turned on, and the fourth driving voltage S4 on the source signal line SL is loaded to the data line DL driven by the fourth transistor unit MU4. At time t5, the fifth selection signal line MUXL5 is loaded with a selection pad, the fifth transistor unit MU5 is turned on, and the fifth driving voltage S5 on the source signal line SL is loaded to the data line DL driven by the fifth transistor unit MU5. At time t6, the sixth selection signal line MUXL6 is loaded with a selection pad, the sixth transistor unit MU6 is turned on, and the sixth driving voltage S6 on the source signal line SL is loaded to the data line DL driven by the sixth transistor unit MU6.

[0145] In an example, the driving substrate BP may be manufactured by using a wafer process, for example, a semiconductor process of 0.04-0.4 microns, for example, a semiconductor process of 0.11 microns.

[0146] In an example, the width-to-length ratio of the channel region of the transistor may be 4:1-8:1, for example, 5:1.

[0147] In one example, the display panel PNL provided in the embodiment of the present disclosure can provide a refresh rate of more than 90 Hz, for example, a refresh rate of 120 Hz, 144 Hz or 180 Hz, by reducing the influence of the demultiplexing circuit DM on the refresh rate.

[0148] For example, the display panel PNL provided in the embodiments of the present disclosure can provide a display capability of 120Hz refresh rate when the resolution reaches 4K (for example, above 3956PPI), and the picture is stable and smooth, which can reduce the dizziness in VR applications and the screen door effect in AR applications, greatly increase the sense of immersion and improve the user experience.

[0149] Figure 8 to Figure 22 for Figure 6 A specific film layer configuration example of the multiplexing circuit DM is shown. Figure 8 to Figure 22 Taking the example of as an example, the configuration of the demultiplexing circuit DM of the driving substrate BP of the embodiment of the present disclosure is exemplarily described. Figure 8 to Figure 22 In the example shown in FIG. 1 , only one demultiplexing circuit DM and its related signal paths are illustrated.

[0150] See also Figure 8 to Figure 22 In the decomposed circuit area DMA, the driving substrate BP includes at least a semiconductor substrate SBT, a gate insulating layer GI, a gate layer GT, a first insulating layer D1, a first metal layer M1, a second insulating layer D2, a second metal layer M2, a third insulating layer D3, a third metal layer M3, a fourth insulating layer D4 and a fourth metal layer M4 which are stacked in sequence.

[0151] See also Figure 8 to Figure 12 , the semiconductor substrate SBT is doped to form active areas BAA and back gate doping areas BG1 corresponding to each transistor pair MP in the first decomposition circuit sub-area DMA1; any active area BAA is divided into a first doping area A1, a second doping area B1, a third doping area A2, a fourth doping area B2, and a fifth doping area A3, and each doping area obtains the expected doping characteristics through subsequent further doping (for example, ion implantation after forming the gate layer GT). The gate layer GT forms the gate MG of each transistor. Among them, each transistor of the same transistor unit MU is set with a common gate, that is, the gate MG of each transistor of the same transistor unit MU is directly connected. The gate MG of the transistor can be overlapped with the second doping area B1 or the fourth doping area B2, so as to protect the second doping area B1 and the fourth doping area B2 during the ion implantation process after forming the gate layer GT.

[0152] The doped region of the semiconductor substrate SBT, the gate insulating layer GI and the gate layer GT together form a transistor layer, so that each transistor required by the transistor unit MU is arranged in the decomposed circuit area DMA.

[0153] See also Figure 13 to Figure 22 The first metal layer M1 to the fourth metal layer M4 are used to lay out various traces to load signals to the demultiplexing circuit DM and enable the demultiplexing circuit DM to output signals. In this example, these traces are mainly distributed in the first metal layer M1 and the third metal layer M3, and the second metal layer M2 and the fourth metal layer M4 are mainly used for signal transfer. In this example, the data line DL is set in the fourth metal layer M4.

[0154] In this example, the first metal layer M1 is provided with a back gate trace BG2 substantially overlapping the back gate doping region BG1 , and the back gate doping region BG1 and the back gate trace BG2 are electrically connected through a first metallized via V1 to form a back gate structure BG.

[0155] In this example, the source signal channel includes a source signal line SL, a first source signal transfer line SL1, a fourth source signal transfer line SL4, a third source signal transfer line SL3, a fifth source signal transfer line SL5, and a second source signal transfer line SL2 connected in sequence, and finally connected to the first electrode MS of the transistor. Among them, the source signal line SL is arranged on the side of the decomposition circuit area DMA away from the display area AA, and is arranged on the first metal layer M1; the end of the first source signal transfer line SL1 close to the decomposition circuit area DMA has a side branch. The first source signal transfer line SL1 is arranged in the first metal layer M1 and is located in the second decomposition circuit sub-area DMA2, and one end close to the source signal line SL is connected to the side branch of the source signal line SL. After the source signal line SL extends to the vicinity of the back gate structure BG, it is transferred to the fourth source signal transfer line SL4 located in the second metal layer M2 through the second metalized via V2; the fourth source signal transfer line SL4 is transferred to the third source signal transfer line SL3 located in the third metal layer M3 through the third metalized via V3. The third source signal transfer line SL3 crosses the back gate structure BG, that is, it is set across the first decomposition circuit sub-area DMA1 and the second decomposition circuit sub-area DMA2. The third source signal transfer line SL3 is located at the end of the first decomposition circuit sub-area DMA1 and is transferred to the fifth source signal transfer line SL5 located in the second metal layer M2 through the third metallized via V3. The fifth source signal transfer line SL5 is transferred to the second source signal transfer line SL2 located in the first decomposition circuit sub-area DMA1 and located in the first metal layer M1 through the second metallized via V2. The second source signal transfer line SL2 is electrically connected to the first electrode MS of the transistor through the first metallized via V1.

[0156] In this example, the selection signal channel includes a selection signal line MUXL, a fourth selection signal transfer line GL4, a first selection signal transfer line GL1, a fifth selection signal transfer line GL5, a third selection signal transfer line GL3, a sixth selection signal transfer line GL6, and a second selection signal transfer line GL2, which are connected in sequence, and are finally connected to the gate MG of the transistor. Among them, the selection signal line MUXL is located in the second decomposition circuit sub-area DMA2 and extends along the row direction DH; the selection signal line MUXL is set in the third metal layer M3. The selection signal line MUXL is electrically connected to the fourth selection signal transfer line GL4 located in the second metal layer M2 through the third metalized via V3, and the fourth selection signal transfer line GL4 is electrically connected to the first selection signal transfer line GL1 located in the first metal layer M1 through the second metalized via V2. The first switching line GL1 of the selection signal extends along the column direction DV to a position close to the back gate structure BG. The end of the first switching line GL1 of the selection signal close to the back gate structure BG is electrically connected to the fifth switching line GL5 of the selection signal located in the second metal layer M2 through the second metallized via V2. The fifth switching line GL5 of the selection signal is electrically connected to the third switching line GL3 of the selection signal located in the third metal layer M3 through the third metallized via V3. The third switching line GL3 of the selection signal crosses the back gate structure BG, that is, one end is located in the first decomposition circuit sub-area DMA1 and the other end is located in the second decomposition circuit sub-area DMA2. The third selection signal transfer line GL3 is located at the end of the first decomposition circuit sub-area DMA1 and is electrically connected to the sixth selection signal transfer line GL6 located on the second metal layer M2 through the third metalized via V3. The sixth selection signal transfer line GL6 is electrically connected to the second selection signal transfer line GL2 located on the first metal layer M1 through the second metalized via V2. The second selection signal transfer line GL2 is electrically connected to the gate MG of the transistor through the first metalized via V1.

[0157] In this example, the first transistor unit MU1 is used to drive the first data line DL(1), so that the first selection signal transfer line GL1 electrically connected to the first transistor unit MU1 is electrically connected to the first selection signal line MUXL1. The second transistor unit MU2 is used to drive the fourth data line DL(4), so that the first selection signal transfer line GL1 electrically connected to the second transistor unit MU2 is electrically connected to the fourth selection signal line MUXL4. The third transistor unit MU3 is used to drive the second data line DL(2), so that the first selection signal transfer line GL1 electrically connected to the third transistor unit MU3 is electrically connected to the second selection signal line MUXL2. The fourth transistor unit MU4 is used to drive the fifth data line DL(5), so that the first selection signal transfer line GL1 electrically connected to the fourth transistor unit MU4 is electrically connected to the fifth selection signal line MUXL5. The fifth transistor unit MU5 is used to drive the third data line DL(3), so that the first selection signal transfer line GL1 electrically connected to the fifth transistor unit MU5 is electrically connected to the fifth selection signal line MUXL5. The sixth transistor unit MU6 is used to drive the sixth data line DL (6), so that the first selection signal adapter line GL1 electrically connected to the sixth transistor unit MU6 is electrically connected to the sixth selection signal line MUXL6. In this way, the source drive circuit can output signals according to the arrangement order of the data lines DL in the display area AA without changing the drive algorithm; the demultiplexing circuit DM loads the source end signal to the corresponding data line DL through hardware conversion.

[0158] In this example, the driving voltage channel includes a second electrode MD of a transistor, a first driving voltage transfer line DL1, a first transfer pad DLP1, a second transfer pad DLP2, a second driving voltage transfer line DL2 and a data line DL connected in sequence, wherein a third driving voltage transfer line DL3 is arranged between the second driving voltage transfer line DL2 and the data line DL, as well as necessary structures required to electrically connect the third driving voltage transfer line DL3 to the second driving voltage transfer line DL2 and the data line DL.

[0159] Among them, the first transfer line DL1 of the driving voltage is arranged on the first metal layer M1 and is located in the first decomposition circuit sub-area DMA1, and is electrically connected to the second electrode MD of the transistor through the first metallized via V1. After the first transfer line DL1 of the driving voltage extends to the end close to the back gate structure BG (the end close to the side of the display area AA), it is transferred to the first transfer pad DLP1 located in the second metal layer M2 through the second metallized via V2; the first transfer pad DLP1 is transferred to the second transfer pad DLP2 located in the third metal layer M3 through the third metallized via V3, and the second transfer pad DLP2 is transferred to the second transfer line DL2 of the driving voltage located in the fourth metal layer M4 through the fourth metallized via V4. Among them, the second transfer line DL2 of the driving voltage crosses the back gate structure BG, that is, one end of the second transfer line DL2 of the driving voltage is located in the first decomposition circuit sub-area DMA1, and the other end extends to the transfer area BA. The data line DL is arranged in the fourth metal layer M4.

[0160] The driving voltage channel connected to the first transistor unit MU1 includes the first sub-switch line DL31 located in the fourth metal layer M4. The driving voltage second switch line DL2, the first sub-switch line DL31, and the first data line DL(1) are all located in the fourth metal layer M4 and are directly connected in sequence.

[0161] The driving voltage channel connected to the second transistor unit MU2 also includes a third transfer pad DLP3, a fourth transfer pad DLP4, a second sub-transfer line DL32, a fifth transfer pad DLP5, and a sixth transfer pad DLP6 which are sequentially connected starting from the second driving voltage transfer line DL2. Among them, the second transfer line DL2 of the driving voltage is connected to the third transfer pad DLP3 located in the third metal layer M3 through the fourth metallized via V4 at the end of the transfer area BA, the third transfer pad DLP3 is connected to the fourth transfer pad DLP4 located in the second metal layer M2 through the third metallized via V3, the fourth transfer pad DLP4 is connected to the second sub-transfer line DL32 located in the first metal layer M1 through the second metallized via V2, the second sub-transfer line DL32 extends along the row direction DH to the position corresponding to the fourth data line DL(4), and is then connected to the fifth transfer pad DLP5 located in the second metal layer M2 through the second metallized via V2, the fifth transfer pad DLP5 is transferred to the sixth transfer pad DLP6 located in the third metal layer M3 through the third metallized via V3, and the sixth transfer pad DLP6 is transferred to the fourth data line DL(4) through the fourth metallized via V4.

[0162] The driving voltage channel connected to the third transistor unit MU3 also includes a third sub-switch line DL33 located in the fourth metal layer M4. The driving voltage second switch line DL2, the third sub-switch line DL33, and the second data line DL(2) are directly connected in sequence.

[0163] The driving voltage channel connected to the fourth transistor unit MU4 also includes a fourth sub-connection line DL34 located in the fourth metal layer M4. The driving voltage second connection line DL2, the fourth sub-connection line DL34, and the fifth data line DL(5) are directly connected in sequence.

[0164] The driving voltage channel connected to the fifth transistor unit MU5 also includes a seventh transfer pad DLP7, an eighth transfer pad DLP8, a fifth sub-transfer line DL35, a ninth transfer pad DLP9, and a tenth transfer pad DLP10 connected in sequence starting from the second driving voltage transfer line DL2. The second transfer line DL2 of the driving voltage is located at the end of the transfer area BA and is connected to the seventh transfer pad DLP7 located on the third metal layer M3 through the fourth metallization via V4. The seventh transfer pad DLP7 is connected to the eighth transfer pad DLP8 located on the second metal layer M2 through the third metallization via V3. The eighth transfer pad DLP8 is connected to the fifth sub-transfer line DL35 located on the first metal layer M1 through the second metallization via V2. After the fifth sub-transfer line DL35 is transferred to the end of the third data line DL(3), it is connected to the ninth transfer pad DLP9 located on the second metal layer M2 through the second metallization via V2. The ninth transfer pad DLP9 is connected to the tenth transfer pad DLP10 located on the third metal layer M3 through the third metallization via V3. The tenth transfer pad DLP10 is connected to the third data line DL(3) located on the fourth metal layer M4 through the fourth metallization via V4.

[0165] The driving voltage channel connected to the sixth transistor unit MU6 also includes a sixth sub-connection line DL36 located in the fourth metal layer M4. The driving voltage second connection line DL2, the sixth sub-connection line DL36, and the sixth data line DL(6) are directly connected in sequence.

[0166] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A driving substrate, comprising a display area and a decomposition circuit area; the display area is provided with a data line for applying a data voltage to a pixel driving circuit; the decomposition circuit area comprises a first decomposition circuit sub-area and a second decomposition circuit sub-area located on a side of the first decomposition circuit sub-area away from the display area; In the first decomposition circuit sub-area, the driving substrate is provided with a plurality of demultiplexing circuits arranged along a row direction, each demultiplexing circuit comprises a plurality of transistor units; the first electrodes of the transistors in the same demultiplexing circuit are electrically connected to the same source signal line, and the second electrodes of the transistors in the same transistor unit are electrically connected to the same data line; The second decomposition circuit sub-area has a plurality of selection signal lines corresponding one-to-one to a plurality of transistor units in the demultiplexing circuit and extending along the row direction, and the gates of the respective transistors of the transistor units are electrically connected to the corresponding selection signal lines.

2. The driving substrate according to claim 1, wherein: The size of the demultiplexing circuit along the column direction is a first size; the distance between the edge of the selection signal line closest to the display area close to the display area and the edge of the selection signal line farthest from the display area farthest from the display area is a second size; the second size is greater than the first size.

3. The driving substrate according to claim 2, wherein: The width of the selection signal line is greater than half the width of the channel region of the transistor in the demultiplexing circuit.

4. The driving substrate according to claim 1, wherein: The driving substrate comprises a transistor layer and a plurality of metal layers stacked in sequence; the transistor layer is electrically connected to the first metal layer through a metallized via, and two adjacent metal layers are electrically connected through a metallized via; In the second decomposition circuit sub-area, the driving substrate is provided with a first switching line of a strobe signal corresponding to each transistor unit one by one, and the first switching line of the strobe signal extends along the column direction and is electrically connected to the gate of each transistor of the corresponding transistor unit; There is at least one metal layer between the metal layer where the first switching line of the selection signal is located and the metal layer where the selection signal line is located.

5. The driving substrate according to claim 4, wherein: The first switching line of the strobe signal is arranged to overlap with each of the strobe signal lines.

6. The driving substrate according to claim 4, wherein: A fourth selection signal adapter wire is provided between the first selection signal adapter wire and the electrically connected selection signal line, and the first selection signal adapter wire is electrically connected to the corresponding selection signal line through the fourth selection signal adapter wire; when the metal layer where the fourth selection signal adapter wire is located is adjacent to the metal layer where the first selection signal adapter wire is located, the first selection signal adapter wire and the fourth selection signal adapter wire are electrically connected to each other through at least two columns of metallized vias, and each column of metallized vias includes at least three metallized vias arranged in sequence along the column direction.

7. The driving substrate according to claim 4, wherein: The first metal layer has a second switching line for a strobe signal corresponding to each transistor unit in the first decomposition circuit sub-area, and the second switching line for a strobe signal is electrically connected to the gate of each transistor of the corresponding transistor unit through a metallized via; The second switching line for the selection signal has a via portion for connecting to the metallized via hole and a routing portion connected to the via portion; the width of the routing portion of the second switching line for the selection signal is smaller than the width of the first switching line for the selection signal.

8. The driving substrate according to claim 1, wherein: The driving substrate comprises a transistor layer and a plurality of metal layers stacked in sequence; the transistor layer is electrically connected to the first metal layer through a metallized via, and two adjacent metal layers are electrically connected through a metallized via; In the second decomposition circuit sub-area, the driving substrate is provided with a source-end signal first adapter wire extending along the column direction, one end of the source-end signal first adapter wire is electrically connected to the source-end signal line, and the other end is electrically connected to the first electrode of each transistor of at least one transistor unit; There is at least one metal layer between the metal layer where the source signal first adapter line is located and the metal layer where the selection signal line is located.

9. The driving substrate according to claim 1, wherein: The transistor unit comprises a plurality of transistors connected in parallel, each of the transistors is arranged in sequence along a column direction, and a length direction of a channel region of each transistor is the row direction; The driving substrate is provided with a first driving voltage adapter wire in the first decomposition circuit sub-area, which corresponds to the transistor units one by one and extends along the column direction. The first driving voltage adapter wire is electrically connected to the second electrode of each transistor of the transistor unit and is electrically connected to the data line.

10. The driving substrate according to claim 1, wherein: The demultiplexing circuit includes a plurality of transistor unit groups, each of which includes two adjacent transistor units; The driving substrate is provided with second source-end signal adapters corresponding to the transistor unit groups in the first decomposition circuit sub-area, and the second source-end signal adapters are electrically connected to the first electrodes of the respective transistors in the corresponding transistor unit groups.

11. The driving substrate according to claim 10, wherein: The driving substrate comprises a data line group corresponding to at least part of the transistor unit groups, the data line group comprises two non-adjacent data lines, and the pixel driving circuit driven by the two data lines of the data line group is used to drive sub-pixels of the same color; One data line of the data line group is electrically connected to the second electrodes of each transistor of a transistor unit of the corresponding transistor unit group, and another data line of the data line group is electrically connected to the second electrodes of each transistor of another transistor unit of the corresponding transistor unit group.

12. The drive substrate according to any one of claims 1 to 11, wherein: The first decomposition circuit sub-area has a ring-shaped back-gate structure, and each of the multiplexing circuits is located in a space surrounded by the back-gate structure; The gate signal line is located at a side of the back gate structure away from the display area.

13. The driving substrate according to claim 12, wherein: The driving substrate comprises a semiconductor substrate and a plurality of metal layers stacked in sequence; Wherein, the back gate structure comprises a ring-shaped back gate doping region located in the semiconductor substrate and a back gate wiring located in the first metal layer, and the back gate wiring is electrically connected to the back gate doping region through a metallized via; The driving substrate is further provided with a metal structure crossing the back gate structure, and at least one metal layer is spaced between the metal layer where the metal structure crossing the back gate structure is located and the first metal layer.

14. A display panel comprising the driving substrate according to any one of claims 1 to 13.

15. A display device comprising the display panel according to claim 14.

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