Memory, access method thereof and electronic equipment

Abstract

A memory, an access method thereof, and an electronic device, the memory comprising at least one memory array, a plurality of bit lines extending in a third direction perpendicular to a substrate, and a plurality of common bit lines extending in a second direction parallel to the substrate, the storage array comprises a plurality of storage units and a plurality of word lines, the storage units are distributed in an array mode in the first direction and the second direction parallel to the substrate, the word lines extend in the first direction, the bit lines, distributed in the second direction, of the same column are connected to the same common bit line, and the bit lines of different columns are connected to different common bit lines. Each bit line is connected to the common bit line through a first gating sub-circuit, the first gating sub-circuit is also connected with a first gating control line, and the first gating sub-circuit is configured to connect or disconnect the bit line and the common bit line according to the control of the first gating control line. According to the scheme provided by the embodiment of the invention, the plurality of bit lines are connected to one common bit line, so that the number of sensing amplifiers used by the memory can be reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a memory and an access method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a memory, comprising at least one memory array, a plurality of bit lines extending along a third direction perpendicular to a substrate, and a plurality of common bit lines extending along a second direction parallel to the substrate, wherein the memory array comprises a plurality of memory cells arranged in an array along a first direction parallel to the substrate and the second direction and a plurality of word lines extending along the first direction, bit lines in the same column arranged along the second direction are connected to the same common bit line, bit lines in different columns are connected to different common bit lines, and each of the bit lines is connected to the common bit line via a first selection subcircuit, the first selection subcircuit is also connected to a first selection control line, and the first selection subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the first selection control line.

[0006] In some embodiments, a plurality of first gating sub-circuits respectively connected to a plurality of bit lines distributed along the first direction are connected to the same first gating control line.

[0007] In some embodiments, the first gating subcircuit includes a first transistor, a gate electrode of the first transistor is connected to the first gating control line, a first electrode is connected to the bit line, and a second electrode is connected to the common bit line.

[0008] In some embodiments, the memory further includes: a plurality of second selection sub-circuits respectively connected to the first end of each of the word lines, the second selection sub-circuits connecting a second selection control line and a word line driver, the second selection sub-circuits being configured to connect or disconnect the word line and the word line driver according to the control of the second selection control line; and a plurality of third selection sub-circuits respectively connected to the second end of each of the word lines, the third selection sub-circuits connecting a third selection control line and a voltage terminal, the third selection sub-circuits being configured to connect or disconnect the word line and the voltage terminal according to the control of the third selection control line, and word lines of the same layer being connected to the same word line driver.

[0009] In some embodiments, the memory includes a plurality of memory arrays stacked along the third direction, the bit lines run through the plurality of memory arrays, the second selection subcircuits connected to the word lines of the same row in different layers are connected to the same second selection control line, the word lines of different rows are connected to different second selection control lines, the third selection subcircuits connected to the word lines of the same row in different layers are connected to the same third selection control line, the word lines of different rows are connected to different third selection control lines, and the word lines of different layers are connected to different word line drivers.

[0010] In some embodiments, a second selection control line connected to a second selection subcircuit connected to the word line of the i-th row is connected to a first selection control line connected to a first selection subcircuit connected to the bit line of the i-th row, where i is 1 to m, and m is the number of rows of word lines contained in each layer of the storage array.

[0011] In some embodiments, the second gating sub-circuit and the third gating sub-circuit connected to the same word line are configured to be in opposite states.

[0012] In some embodiments, the multiple second selection sub-circuits of the memory are configured as follows: the second selection sub-circuit connected to the word line of the target row where the word line to be selected is located is configured to be in a connected state, and the second selection sub-circuit connected to the word line of other rows except the target row is configured to be in a disconnected state.

[0013] In some embodiments, the second gating subcircuit includes a second transistor, a gate electrode of the second transistor is connected to the second gating control line, a first electrode is connected to the first end of the word line, and a second electrode is connected to the word line driver.

[0014] In some embodiments, the third gating subcircuit includes a third transistor, a gate electrode of the third transistor is connected to the third gating control line, a first electrode is connected to the second end of the word line, and a second electrode is connected to the voltage end.

[0015] In some embodiments, the common bit line is disposed on a side of the memory array facing the substrate, or on a side facing away from the substrate.

[0016] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0017] The present disclosure provides a method for accessing a memory, including:

[0018] In the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an on-level signal is loaded on the second selection control line connected to the word line of the target row, and an off-level signal is loaded on the second selection control line connected to the word line of the non-target row; an off-level signal is loaded on the third selection control line connected to the word line of the target row, and an on-level signal is loaded on the third selection control line connected to the word line of the non-target row; an on-level signal is loaded on the first selection control line connected to the bit line of the target row, and an off-level signal is loaded on the first selection control line connected to the bit line of the non-target row; an activation signal is loaded on the word line driver of the target layer, and an inactivation signal is loaded on the word line driver of the non-target layer.

[0019] In some embodiments, it also includes:

[0020] In the precharge stage, an on level signal is loaded on all first strobe control lines, an on level signal is loaded on all second strobe control lines, an off level signal is loaded on all third strobe control lines, and an inactive signal is loaded on all word line drivers.

[0021] In some embodiments, when the second gating control line connected to the second gating subcircuit connected to the word line of the i-th row is connected to the first gating control line connected to the first gating subcircuit connected to the bit line of the i-th row, where i is 1 to m, and m is the number of word line rows included in each layer of the memory array:

[0022] In the data reading and writing stage, a turn-on level signal is loaded on a first selection control line connected to the bit line of the target row, and a turn-off level signal is loaded on a first selection control line connected to the bit line of a non-target row; a turn-on level signal is loaded on a second selection control line connected to the word line of the target row, and a turn-off level signal is loaded on a second selection control line connected to the word line of a non-target row, including: loading the same turn-on level signal to the first selection control line connected to the bit line of the target row, and the second selection control line connected to the word line of the target row; loading the same turn-off level signal to the first selection control line connected to the bit line of the non-target row, and the second selection control line connected to the word line of the non-target row.

[0023] The present application includes a memory and an access method thereof, and an electronic device, wherein the memory includes at least one memory array, a plurality of bit lines extending along a third direction perpendicular to a substrate, and a plurality of common bit lines extending along a second direction parallel to the substrate, wherein the memory array includes a plurality of memory cells arrayed along a first direction and a second direction parallel to the substrate and a plurality of word lines extending along the first direction, wherein the bit lines of the same column distributed along the second direction are connected to the same common bit line, and the bit lines of different columns are connected to different common bit lines, and each of the bit lines is connected to the common bit line through a first selection subcircuit, wherein the first selection subcircuit is also connected to a first selection control line, and the first selection subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the first selection control line. The solution provided in this embodiment reduces the number of sense amplifiers used by the memory by connecting the bit lines of the same column to the common bit line, so that the sense amplifier can be connected through the common bit line.

[0024] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0025] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0027] Figure 1A A three-dimensional schematic diagram of a memory provided as an exemplary embodiment;

[0028] Figure 1B for Figure 1A Schematic diagram of the connection between the storage unit of the qth layer in the xy direction and the bit line and word line;

[0029] Figure 1C for Figure 1A A schematic diagram showing the connection between each layer of memory cells in the qth row in the xz direction and the bit lines and word lines;

[0030] Figure 1D for Figure 1A A schematic diagram showing the connection between each layer of memory cells in the qth column in the yz direction and the bit lines and word lines;

[0031] Figure 2 A memory diagram is provided for an exemplary embodiment. DETAILED DESCRIPTION

[0032] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0033] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0034] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0036] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0037] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0038] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0039] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0040] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0041] Figure 1A A three-dimensional schematic diagram of a memory provided in an embodiment of the present disclosure. Figure 1B for Figure 1A Schematic diagram of the connection between the storage unit of the qth layer in the xy direction and the bit line and word line. Figure 1C for Figure 1A Schematic diagram of the connection between each layer of storage cells in the qth row in the xz direction and the bit lines and word lines. Figure 1D for Figure 1A Schematic diagram of the connection between each layer of storage cells in the qth column in the yz direction and the bit lines and word lines. Figures 1A to 1D As shown, the memory provided in this embodiment includes a multi-layer stacked memory array (k layers, memory array L1 to memory array Lk), and the multi-layer memory array is stacked along a third direction z. Each layer of the memory array includes a plurality of memory cells 100 arrayed along a first direction x and a second direction y, respectively, and a plurality of word lines WL extending along the first direction x. The plurality of word lines WL of each layer are spaced apart along the second direction y. The memory also includes a plurality of bit lines BL extending along the third direction z, and the plurality of bit lines BL are arrayed along the first direction x and the second direction y. Each layer of the memory array includes m rows and n columns of memory cells 100, and includes m word lines WL, wherein the word line of the i-th row of the r-th layer is a word line WL_i_r, i is 1 to m, and r is 1 to k. The memory includes m rows and n columns of bit lines BL, and the bit line of the i-th row and j-th column is a bit line BL_i_j, and j is 1 to n. Figures 1B to 1DIn the description, the memory cell 100 is taken as a 1T1C structure as an example, that is, the memory cell 100 is a structure in which an access transistor and a capacitor Cs are connected, the gate electrode of the access transistor is connected to the word line WL, the first electrode is connected to the bit line BL, the second electrode is connected to the first end of the capacitor Cs, the second end of the capacitor Cs is connected to the common voltage terminal Vcom, and the first end of the capacitor Cs serves as a storage node SN, wherein the memory cell C_i_j_r of the rth layer, the i-th row and the j-th column is connected to the word line WL_i_r and the bit line BL_i_j. Figures 1B to 1D The memory cell of 1T1C structure is shown, but the embodiment of the present disclosure is not limited thereto, and the memory may include memory cells of other structures, such as 2T0C, 2T1C structure, etc. The first direction x and the second direction y are parallel to the substrate ( Figures 1A to 1D The substrate is not shown in the figure), and the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular.

[0042] like Figure 1B As shown, in the qth layer, the memory cell 100 in the i-th row is connected to the word line WL_i_q in the i-th row of the qth layer; i is 1 to m, and the memory cell 100 in the i-th row and the j-th column is connected to the bit line BL_i_j in the i-th row and the j-th column, wherein i is 1 to m, and j is 1 to n. It can be seen that the word line WL extends along the first direction x, and the bit line BL extends along the third direction z perpendicular to the first direction x and the second direction y.

[0043] like Figure 1C As shown, the memory cell 100 of the qth row and the rth layer is connected to the word line WL_q_r of the qth row and the rth layer, where r is 1 to k, and the memory cell 100 of the qth row and the jth column of each layer is connected to the bit line BL_q_j of the qth row and the jth column, where j is 1 to n. It can be seen that the word line WL extends along the first direction x, and the bit line BL extends along the third direction z.

[0044] like Figure 1D As shown, the memory cell 100 of the qth column, rth layer, i-th row is connected to the word line WL_i_r of the ith row, rth layer, r is 1 to k, and i is 1 to m; the memory cell 100 of the ith row, qth column of each layer is connected to the bit line BL_i_q of the ith row and qth column, i is 1 to m. It can be seen that the word line WL extends along the first direction x perpendicular to the second direction y and the third direction z, and the bit line BL extends along the third direction z.

[0045] Figure 2 A memory diagram is provided for an exemplary embodiment. Figure 2 In the figure, the memory cell 100 is not shown, only the word line WL and the bit line BL are shown, and the connection relationship between the word line WL and the bit line BL and the memory cell 100 can be referred to. Figures 1A to 1D, no further details will be given. Figure 2 As shown, the memory also includes a plurality of common bit lines CBL, and the bit lines BL in the same column distributed along the second direction y can be connected to the same common bit line CBL, and the bit lines BL in different columns are connected to different common bit lines CBL, for example, the first column bit line BL is connected to the first common bit line CBL1, the second column bit line BL is connected to the second common bit line CBL2, and the nth column bit line BL is connected to the nth common bit line CBLn. One common bit line CBL is connected to one sense amplifier SA. Compared with the solution in which each bit line BL is connected to one sense amplifier SA, the solution provided in this embodiment can greatly reduce the number of sense amplifiers SA by using the common bit line CBL. Adjacent storage arrays can share the same SA.

[0046] In some embodiments, the common bit line CBL may be disposed on the side of the memory array facing the substrate or away from the substrate. When the memory includes a plurality of stacked memory arrays, the common bit line CBL may be disposed on the side of the stacked memory array facing the substrate or away from the substrate.

[0047] In some embodiments, each bit line BL can be connected to the common bit line CBL through a first gating sub-circuit 10. The first gating sub-circuit 10 is also connected to a first gating control line, and the first gating sub-circuit 10 is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the first gating control line. That is, the signal of the common bit line CBL is loaded or not loaded on the bit line BL under the control of the first gating control line.

[0048] In some embodiments, the first gating sub-circuits 10 connected to the bit lines BL in the same row distributed along the first direction x are connected to the same first gating control line, and the first gating sub-circuits of the bit lines BL in different rows are connected to different first gating control lines. For example, the first gating sub-circuits 10 connected to the bit lines BL in the first row are all connected to the first first gating control line R_1, the first gating sub-circuits 10 connected to the bit lines BL in the second row are all connected to the second first gating control line R_2, and so on, the first gating sub-circuits 10 connected to the bit lines BL in the mth row are all connected to the mth first gating control line R_m. Thus, a bit line BL can be selected through the common bit line CBL and the first gating control line. For example, the jth common bit line CBL is loaded with an activation signal (the other common bit lines are loaded with inactivation signals), the i-th first selection control line R_i selects the corresponding first selection sub-circuit 10 (the other first selection control lines do not select the corresponding first selection sub-circuit 10), then the bit line BL_i_j in the i-th row and j-th column is loaded with an activation signal.

[0049] In some embodiments, only one bit line BL is enabled at a time, which can reduce the capacitive load of the SA and the capacitance of the memory cell.

[0050] In some embodiments, the first gating subcircuit 10 may include a first transistor T1, a gate electrode of the first transistor T1 is connected to the first gating control line, a first electrode is connected to the bit line BL, and a second electrode is connected to the common bit line CBL. The structure of the first gating subcircuit 10 described in this embodiment is only an example, and may be other circuits that can implement gating.

[0051] In some embodiments, the first transistor T1 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the first transistor T1 may be a P-type transistor.

[0052] In some embodiments, the word line WL may be connected to a word line driver, and the word line WL of each layer is connected to the same word line driver, and the word lines WL of different layers are connected to different word line drivers, and the word line drivers may correspond to the number of layers of the memory array. For example, the word line WL of the first layer is connected to the word line driver SWD_1, and the word line WL of the kth layer is connected to the word line driver SWD_k. The word line driver may be connected to the first end of the word line WL.

[0053] Only one word line WL is gated at the same time, so a gate subcircuit can be set to gate the word line WL. In some embodiments, the first end of the word line WL can be connected to the word line driver through a second gate subcircuit 20. The second gate subcircuit 20 is also connected to a second gate control line, and the second gate subcircuit 20 is configured to connect or disconnect the word line driver and the word line WL under the control of the second gate control line. That is, the signal of the word line driver is loaded or not loaded on the word line WL under the control of the second gate control line.

[0054] In some embodiments, the second selection subcircuit 20 connected to the word lines WL of the same row in different layers can be connected to the same second selection control line, and the second selection subcircuit 20 connected to the word lines WL of different rows can be connected to different second selection control lines. For example, the second selection subcircuit 20 connected to the word lines WL of the first row in different layers is connected to the second selection control line S_1, the second selection subcircuit 20 connected to the word lines WL of the second row in different layers is connected to the second selection control line S_2, the second selection subcircuit 20 connected to the word lines WL of the third row in different layers is connected to the second selection control line S_3, and so on, the second selection subcircuit 20 connected to the word lines WL of the mth row in different layers is connected to the second selection control line S_m. The number of second selection control lines is consistent with the number of rows of word lines WL included in a layer of storage array. For example, each layer of storage array includes m rows of word lines (one word line WL is a row), and the second selection control lines include m.

[0055] In some embodiments, a word line WL can be selected by a word line driver and a second selection control line. For example, the word line driver SWD_r corresponding to the storage array of the rth layer is loaded with an activation signal (the other word line drivers are loaded with an inactive signal), the i-th second selection control line S_i selects the corresponding second selection subcircuit 20 (the other second selection control lines do not select the corresponding second selection subcircuit 20), and the word line WL_i_r of the rth layer and the i-th row is loaded with an activation signal. That is, only one word line driver among the word line drivers SWD_1 to SWD_k provides an activation signal to a layer of word lines WL at the same time, and only one word line WL in the layer of word lines WL is connected to the second selection subcircuit 20 turned on, connecting the word line WL and the word line driver providing the activation signal, so that only one word line WL is selected at the same time.

[0056] In some embodiments, the second gating subcircuit 20 may include a second transistor T2, a gate electrode of the second transistor T2 is connected to the second gating control line, a first electrode is connected to the first end of the word line WL, and a second electrode is connected to the word line driver. The structure of the second gating subcircuit 20 described in this embodiment is only an example, and may be other circuits that can implement gating.

[0057] In some embodiments, the second transistor T2 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the second transistor T2 may be a P-type transistor.

[0058] In some embodiments, the second end of the word line WL can be connected to a preset voltage terminal through a third gating subcircuit 30, and the preset voltage terminal can be a low-level signal terminal, such as a ground terminal. The third gating subcircuit 30 is also connected to a third gating control line, and the third gating subcircuit 30 is configured to connect or disconnect the word line WL and the preset voltage terminal under the control of the third gating control line. The third gating subcircuit 30 can prevent the word line WL from being in a floating state when the second gating subcircuit 20 connected to the word line WL is disconnected.

[0059] In some embodiments, the third selection subcircuits 30 connected to the word lines WL of the same row in different layers are connected to the same third selection control line, and the third selection subcircuits 30 connected to the word lines WL of different rows are connected to different third selection control lines. For example, the third selection subcircuits 30 connected to the word lines WL of the first row in different layers are connected to the third selection control line S_1b, the third selection subcircuits 30 connected to the word lines WL of the second row in different layers are connected to the third selection control line S_2b, the third selection subcircuits 30 connected to the word lines WL of the third row in different layers are connected to the third selection control line S_3b, and so on, the third selection subcircuits 30 connected to the word lines WL of the mth row in different layers are connected to the third selection control line S_mb. The number of third selection control lines is consistent with the number of rows of word lines WL included in a layer of storage array. For example, each layer of storage array includes m rows of word lines (one word line WL is a row), and the third selection control lines include m.

[0060] In some embodiments, the third gating subcircuit 30 may include a third transistor T3, a gate electrode of the third transistor T3 is connected to the third gating control line, a first electrode is connected to the second end of the word line WL, and a second electrode is connected to the preset voltage end. The structure of the third gating subcircuit 30 described in this embodiment is only an example, and may be other circuits that can implement gating.

[0061] In some embodiments, the third transistor T3 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the third transistor T3 may be a P-type transistor.

[0062] In some embodiments, the states of the second selection subcircuit 20 and the third selection subcircuit 30 connected to the same word line WL are opposite, that is, when the second selection subcircuit 20 is in the connected state, the third selection subcircuit 30 is in the disconnected state; when the second selection subcircuit 20 is in the disconnected state, the third selection subcircuit 30 is in the connected state. Correspondingly, when the second transistor T2 and the third transistor T3 are transistors of the same type (for example, the second transistor T2 and the third transistor T3 are both N-type MOS transistors, or both are P-type MOS transistors), the signal polarities of the second selection control line connected to the second selection subcircuit 20 connected to the word line WL of the same row and the third selection control line connected to the third selection subcircuit 30 connected to the word line of the row are opposite, for example, when the second selection control line S_2 connected to the second row word line WL is at a high level, the third selection control signal line S_2b connected to the second row word line WL is at a low level. When the second transistor T2 and the third transistor T3 are transistors with opposite polarities (for example, one of the second transistor T2 and the third transistor T3 is an N-type MOS transistor and the other is a P-type MOS transistor), the second selection control line connected to the second selection sub-circuit 20 connected to the word line WL of the same row and the third selection control line connected to the third selection sub-circuit 30 connected to the word line of the row have the same signal polarity. For example, when the second selection control line S_2 connected to the second row word line WL is at a high level, the third selection control signal line S_2b connected to the second row word line WL is at a high level, thereby achieving the opposite states of the second selection sub-circuit 20 and the third selection sub-circuit 30 connected to the same word line WL.

[0063] In some embodiments, the plurality of second gating subcircuits 20 of the memory are configured as follows: the second gating subcircuit 20 connected to the word line of the i-th row where the word line WL to be selected is located (here, the second gating subcircuit 20 connected to the word line of the i-th row of each layer) is configured to be in a connected state, and the second gating subcircuit 20 connected to the word line WL of other rows except the i-th row is configured to be in a disconnected state, i is 1 to m, and m is the number of rows of word lines WL contained in each layer of the memory array. The word line driver connected to the layer where the word line of the i-th row to be selected is located is loaded with an activation signal, and the other layers are loaded with a non-activation signal, so that only one layer of the i-th row word lines in multiple layers is selected. Combined with the previous item, the states of the second selection subcircuit 20 and the third selection subcircuit 30 connected to the same word line WL are opposite, and the third selection subcircuit 30 connected to the word lines WL of other rows except the i-th row is configured to be in a connected state, that is, the word lines WL of other rows except the i-th row are connected to the preset voltage terminal and will not be in a floating state. Among the word lines WL of the i-th row of different layers, the word lines are connected to the word line driver, and the word line driver can load an activation signal or a non-activation signal, that is, the word line WL of the i-th row will not float.

[0064] The memory cell 100 may be a 1T1C structure, or a 2T0C structure, or a 2T1C structure, etc. When the memory cell is a 1T1C structure, one memory cell 100 may be connected to one bit line BL and one word line WL. When the memory cell 100 is a 2T0C structure, one memory cell 100 may be connected to one bit line BL, one read word line RWL, and one write word line WWL; or one memory cell 100 may be connected to one read bit line RBL, one write bit line WBL, one read word line RWL, and one write word line WWL.

[0065] In some embodiments, the bit lines BL of the memory array may include a read bit line RBL and a write bit line WBL, and the word lines WL of the memory array may include a read word line RWL and a write word line WWL. In this case, the read bit line RBL and the read word line RWL may be used as Figure 2 The bit line BL and the word line WL in the writing device are provided with corresponding common bit lines CBL, first gating sub-circuit 10, second gating sub-circuit 20 and third gating sub-circuit 30, and corresponding first gating control line, second gating control line and third gating control line; the writing bit line WBL and the writing word line WWL can be used as Figure 2 The bit lines BL and word lines WL in the embodiment of the present invention are provided with another set of corresponding common bit lines CBL, a first gating sub-circuit 10, a second gating sub-circuit 20 and a third gating sub-circuit 30, as well as corresponding first gating control lines, second gating control lines and third gating control lines.

[0066] In some embodiments, the memory array may include a read word line RWL, a write word line WWL, and a bit line BL (the read bit line RBL and the write bit line WBL are merged). In this embodiment, a corresponding second selection subcircuit 20 and a third selection subcircuit 30, as well as a corresponding second selection control line and a third selection control line, may be respectively set for the read word line RWL and the write word line WWL, and a common bit line, a first selection subcircuit 10, and a first selection control line may be set for the bit line BL. Figure 2 In the structure, the word lines WL at this time include read word lines RWL and write word lines WWL. The read word lines RWL of each layer are connected to a read word line driver, and the read word lines RWL of different layers are connected to different read word line drivers. The write word lines WWL of each layer are connected to a write word line driver, and the write word lines WWL of different layers are connected to different write word line drivers.

[0067] In some embodiments, when the memory cell 100 is a 1T1C structure, the second selection control line S_i connected to the second selection subcircuit 20 connected to the word line WL of the i-th row can be connected to the first selection control line R_i connected to the first selection subcircuit 10 connected to the bit line BL of the i-th row, i is 1 to m, wherein the multiple memory cells 100 connected to the word line WL of the i-th row are respectively connected to the multiple bit lines BL of the i-th row. That is, a selection control line can be used to connect the gate electrode of the second selection subcircuit 20 connected to the word line WL of the i-th row and the gate electrode of the first selection subcircuit 10 connected to the bit line BL of the i-th row. A selection control line is used to control the second selection subcircuit 20 connected to the word line WL of the i-th row and the first selection subcircuit 10 connected to the bit line BL of the i-th row. The solution provided in this embodiment can reduce the number of control lines, reduce the control circuit that generates the control signal, and reduce the device occupied area. However, the embodiments of the present disclosure are not limited thereto, and the second selection control line S_i and the first selection control line R_i can be independently set. When the memory cell 100 is a 2T0C structure and the read bit line RBL and the write bit line WBL are combined, the second selection control line S_i and the first selection control line R_i are independently set and are not connected.

[0068] The present disclosure provides a method for controlling access to a memory, including:

[0069] In the data reading and writing stage, according to the target layer and the target row where the storage unit to be operated is located, an on-level signal is loaded on the second selection control line connected to the word line of the target row (so that the second selection subcircuit connecting the word line of the target row of different layers is in a connected state), and an off-level signal is loaded on the second selection control line connected to the word line of the non-target row (so that the second selection subcircuit connecting the word line of the non-target row of different layers is in an off state); an off-level signal is loaded on the third selection control line connected to the word line of the target row (so that the third selection subcircuit connecting the word line of the target row of different layers is in an off state), and an on-level signal is loaded on the third selection control line connected to the word line of the non-target row (so that the second selection subcircuit connecting the word line of the non-target row of different layers is in an off state). The third selection subcircuit of the word line of the non-target row of the same layer is in a connected state); a turn-on level signal is loaded on the first selection control line connected to the bit line of the target row (so that the first selection subcircuit connected to the bit line of the target row is in a connected state), and a turn-off level signal is loaded on the first selection control line connected to the bit line of the non-target row (so that the first selection subcircuit connected to the bit line of the non-target row is in a turned-off state); an activation signal is loaded on the word line driver of the target layer, and an inactivation signal is loaded on the word line driver of the non-target layer (combined with the fact that only the second selection subcircuit of the target row is in a connected state, at this time, only the word line of the target row of the target layer is loaded with the activation signal, so that the access transistor of the storage unit of the target layer of the target row can be turned on).

[0070] This embodiment provides a memory access method, which can realize the control of bit lines by using fewer control signals, thereby reducing the number of control lines.

[0071] The on-level signal is a signal that can put the corresponding gating subcircuit in a connected state, and the off-level signal is a signal that can put the corresponding gating subcircuit in a closed state.

[0072] In some embodiments, it also includes:

[0073] In the pre-charging stage, an on-level signal is loaded on all first selection control lines (so that all first selection sub-circuits are in a connected state), an on-level signal is loaded on all second selection control lines (so that all second selection sub-circuits are in a connected state), an off-level signal is loaded on all third selection control lines (so that all third selection sub-circuits are in an off state), and an inactive signal is loaded on all word line drivers (so that the access transistors of all storage cells are turned off).

[0074] In some embodiments, when the second gating control line connected to the second gating subcircuit connected to the word line of the i-th row is connected to the first gating control line connected to the first gating subcircuit connected to the bit line of the i-th row, where i is 1 to m, and m is the number of word line rows included in each layer of the memory array:

[0075] In the data reading and writing stage, a first gate control line connected to the bit line of the target row is loaded with a turn-off level signal, and a first gate control line connected to the bit line of the non-target row is loaded with a turn-off level signal; a second gate control line connected to the word line of the target row is loaded with a turn-off level signal, and a second gate control line connected to the word line of the non-target row is loaded with a turn-off level signal, including: loading the same turn-on level signal to the first gate control line connected to the bit line of the target row, and the second gate control line connected to the word line of the target row; loading the same turn-off level signal to the first gate control line connected to the bit line of the non-target row, and the second gate control line connected to the word line of the non-target row. That is, the first gate control line and the second gate control line respectively connected to the bit line and the word line of the same row can be controlled by the same signal, which reduces the control signal and makes the control simpler.

[0076] The following describes the working process of the memory by using an embodiment. Figure 2Taking the memory shown as an example, in this embodiment, the memory cell 100 is a 1T1C structure, the access transistor is an N-type MOS tube, the first transistor T1, the second transistor T2 and the third transistor T3 are all N-type MOS tubes, the second selection control line S_i is connected to the first selection control line R_i, and the following is only described with the second selection control line S_i, that is, the second selection control line S_i also controls the first selection sub-circuit 10. The common bit line CBL can also be connected to the pre-charge sub-circuit. The working stages of the memory may include a pre-charge stage, a data read stage and a data write-back stage, wherein:

[0077] In the precharge stage, all second selection control lines S_i are loaded with high-level signals, i is 1 to m, to turn on all second transistors T2 and first transistors T1. After the second transistor T2 is turned on, all word lines WL are connected to the corresponding word line drivers, and word line drivers SWD_1 to SWD_K are loaded with low-level signals, which are loaded on the word line WL, and the access transistors of all storage cells are turned off, the precharge sub-circuit is turned on, and a precharge voltage of 1 / 2VDD is loaded on each common bit line CBL, and each common bit line CBL loads the precharge voltage to a column of bit lines BL connected thereto. All third selection control lines S_ib are loaded with low-level signals, so that all third transistors T3 are turned off.

[0078] In the data reading stage, the precharge sub-circuit is turned off; taking the data of the storage cell 100 of the p-th layer and the q-th row as an example, the second selection control line S_q maintains a high level signal, and the other second selection control lines S_i, i is 1 to m, and i≠q are loaded with low level signals, thereby turning off the second transistor T2 and the first transistor T1 connected to the second selection control line S_i, i is 1 to m, and i≠q, and the word line drivers SWD_1 to SWD_K, SWD_p is loaded with a high level signal, from The access transistor of the memory cell 100 connected to the word line WL of the p-th layer and the q-th row is turned on, and the access transistors of the other memory cells 100 are turned off. The common bit lines CBL1 to CBLn are respectively connected to the n bit lines of the q-th row, and the storage nodes of the n memory cells 100 of the p-th layer and the q-th row are respectively charged and shared. The sense amplifiers respectively connected to CBL1 to CBLn sense the voltages of CBL1 to CBLn to determine the data stored in the memory cells 100 of the p-th layer and the q-th row. The third selection control line S_qb maintains a low level signal, and the other third selection control lines S_ib, i is 1 to m, and i≠q are loaded with a high level signal, thereby turning on the third transistor T3 connected to the third selection control line S_ib, i is 1 to m, and i≠q, and the word lines WL of other rows except the q-th row are connected to the preset voltage terminal to prevent the word lines WL from floating.

[0079] In the data write back stage, the second select control line S_q maintains a high level signal, and the remaining second select control lines S_i, i is 1 to m, and i≠q are loaded with low level signals, the third select control line S_qb maintains a low level signal, and the remaining third select control lines S_ib, i is 1 to m, and i≠q are loaded with high level signals, and the common bit lines CBL1 to CBLn are respectively connected to the n bit lines in the qth row, and charge is shared with the storage nodes of the n storage cells 100 in the pth layer and the qth row, respectively, to realize data write back.

[0080] The solution provided in this embodiment uses the same control signal to control the bit lines and word lines of the same row, which reduces the number of control signal lines, reduces the required control circuits, and makes the control logic simpler. The disclosed embodiment also provides an electronic device, including the memory of the aforementioned embodiment. The electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0081] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A memory, characterized in that: It includes at least one memory array, a plurality of bit lines extending along a third direction perpendicular to a substrate and a plurality of common bit lines extending along a second direction parallel to the substrate. The memory array includes a plurality of memory cells arranged in an array along a first direction parallel to the substrate and the second direction and a plurality of word lines extending along the first direction. Bit lines in the same column arranged along the second direction are connected to the same common bit line, and bit lines in different columns are connected to different common bit lines. Each of the bit lines is connected to the common bit line via a first selection subcircuit. The first selection subcircuit is also connected to a first selection control line. The first selection subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the first selection control line.

2. The memory according to claim 1, characterized in that: A plurality of first gating sub-circuits respectively connected to a plurality of bit lines distributed along the first direction are connected to the same first gating control line.

3. The memory according to claim 2, characterized in that: The memory also includes: a plurality of second selection sub-circuits respectively connected to the first end of each of the word lines, the second selection sub-circuits connecting a second selection control line and a word line driver, the second selection sub-circuits being configured to connect or disconnect the word line and the word line driver according to the control of the second selection control line; and a plurality of third selection sub-circuits respectively connected to the second end of each of the word lines, the third selection sub-circuits connecting a third selection control line and a voltage terminal, the third selection sub-circuits being configured to connect or disconnect the word line and the voltage terminal according to the control of the third selection control line, and word lines of the same layer being connected to the same word line driver.

4. The memory according to claim 3, characterized in that: The memory includes a plurality of memory arrays stacked along the third direction, the bit lines run through the plurality of memory arrays, the second selection subcircuits connected to the word lines of the same row in different layers are connected to the same second selection control line, the word lines of different rows are connected to different second selection control lines, the third selection subcircuits connected to the word lines of the same row in different layers are connected to the same third selection control line, the word lines of different rows are connected to different third selection control lines, and the word lines of different layers are connected to different word line drivers.

5. The memory according to claim 4, characterized in that: The second selection control line connected to the second selection subcircuit connected to the word line of the i-th row is connected to the first selection control line connected to the first selection subcircuit connected to the bit line of the i-th row, i is 1 to m, and m is the number of rows of word lines contained in each layer of the storage array.

6. The memory according to claim 4, characterized in that: The second gating sub-circuit and the third gating sub-circuit connected to the same word line are configured in opposite states.

7. The memory according to claim 6, characterized in that: The multiple second gating subcircuits of the memory are configured as follows: the second gating subcircuit connected to the word line of the target row where the word line to be selected is located is configured to be in a connected state, and the second gating subcircuit connected to the word line of other rows except the target row is configured to be in a disconnected state.

8. The memory according to claim 1, characterized in that: The first gating subcircuit includes a first transistor, a gate electrode of the first transistor is connected to the first gating control line, a first electrode of the first transistor is connected to the bit line, and a second electrode of the first transistor is connected to the common bit line.

9. The memory according to claim 3, characterized in that: The second gating subcircuit includes a second transistor, a gate electrode of the second transistor is connected to the second gating control line, a first electrode of the second transistor is connected to the first end of the word line, and a second electrode of the second transistor is connected to the word line driver.

10. The memory according to claim 3, characterized in that: The third gating subcircuit includes a third transistor, a gate electrode of the third transistor is connected to the third gating control line, a first electrode of the third transistor is connected to the second end of the word line, and a second electrode of the third transistor is connected to the voltage end.

11. The memory according to any one of claims 1 to 10, characterized in that: The common bit line is arranged on a side of the memory array facing the substrate, or on a side facing away from the substrate.

12. An electronic device, characterized in that: Comprising the memory as claimed in any one of claims 1 to 11.

13. A method for accessing a memory as claimed in claim 4 or 5, characterized in that: include: In the data reading and writing stage, according to the target layer and the target row where the memory cell to be operated is located, an on-level signal is loaded on the second selection control line connected to the word line of the target row, and an off-level signal is loaded on the second selection control line connected to the word line of the non-target row; Loading a turn-off level signal on a third gate control line connected to the word line of the target row, and loading an open level signal on a third gate control line connected to the word line of a non-target row; Loading an on-level signal on a first gate control line connected to a bit line of the target row, and loading an off-level signal on a first gate control line connected to a bit line of a non-target row; An activation signal is loaded on the word line driver of the target layer, and an inactivation signal is loaded on the word line driver of the non-target layer.

14. The memory access method according to claim 13, characterized in that: Also includes: In the precharge stage, an on level signal is loaded on all first strobe control lines, an on level signal is loaded on all second strobe control lines, an off level signal is loaded on all third strobe control lines, and an inactive signal is loaded on all word line drivers.

15. The memory access method according to claim 13, characterized in that: When the second gating control line connected to the second gating subcircuit connected to the word line of the i-th row is connected to the first gating control line connected to the first gating subcircuit connected to the bit line of the i-th row, wherein i is 1 to m, and m is the number of word line rows included in each layer of the memory array: In the data reading and writing stage, the loading of a turn-on level signal on the first selection control line connected to the bit line of the target row, and the loading of a turn-off level signal on the first selection control line connected to the bit line of the non-target row; the loading of a turn-on level signal on the second selection control line connected to the word line of the target row, and the loading of a turn-off level signal on the second selection control line connected to the word line of the non-target row include: loading the same turn-on level signal to the first selection control line connected to the bit line of the target row, and the second selection control line connected to the word line of the target row; loading the same turn-off level signal to the first selection control line connected to the bit line of the non-target row, and the second selection control line connected to the word line of the non-target row.

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