Memory device and memory system including the same

Abstract

A memory device includes a first semiconductor layer and a second semiconductor layer arranged relative to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bit line and a complementary bit line coupled with the memory cell array, a first vertical conductive line coupled with the bit line, and a second vertical conductive line coupled with the complementary bit line. The second semiconductor layer includes a peripheral circuit, a bit line sense amplifier, first and second control lines coupled with the bit line sense amplifier, a third vertical conductive line coupled with the bit line sense amplifier, and a fourth vertical conductive line coupled with the bit line sense amplifier. The bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

Description

Technical Field

[0001] The present invention relates generally to memory devices and, more particularly, to memory devices and memory systems including the memory devices. Background Art

[0002] Examples of dynamic random access memory (DRAM) devices may include, but are not limited to, memory devices that can be operated by recording data using charges that can be stored in cell capacitors of memory cells. Memory cells may be connected to bit lines and / or complementary bit lines. In related DRAM devices, a bit line sense amplifier may amplify the voltage difference between a bit line and a complementary bit line when performing operations such as, but not limited to, a read operation, a refresh operation, etc. However, noise may occur during the sensing and / or amplification operations of the bit line sense amplifier. Noise may be caused, for example, by limitations in semiconductor manufacturing process technology. Therefore, the sensing margin of the bit line sense amplifier may be reduced, and / or the overall performance of the memory device (e.g., a DRAM device) may be degraded. Therefore, there is a need for further improvements in memory devices because the need for data integrity may be constrained by the signal noise of the bit line sense amplifier. Improvements are proposed herein. These improvements may also be applicable to other semiconductor technologies and standards that employ these technologies. Summary of the invention

[0003] One or more example embodiments of the present invention provide a memory device that can potentially improve operational stability.

[0004] Furthermore, one or more example embodiments of the present invention provide a memory system including a memory device.

[0005] According to one aspect of the present disclosure, a memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bit line and a first complementary bit line extending in a first direction, arranged in a second direction intersecting the first direction and coupled to the memory cell array, a first vertical wire and a first bonding pad coupled to the first bit line, and a second vertical wire and a second bonding pad coupled to the first complementary bit line. The second semiconductor layer is arranged in a third direction perpendicular to the first direction and the second direction relative to the first semiconductor layer. The second semiconductor layer includes a peripheral circuit configured to control the memory cell array, a first bit line sense amplifier configured to control the first bit line and the first complementary bit line, a first control line and a second control line coupled to the first bit line sense amplifier, a third bonding pad and a third vertical wire coupled to the first bonding pad and the first bit line sense amplifier, and a fourth bonding pad and a fourth vertical wire coupled to the second bonding pad and the first bit line sense amplifier. The first bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

[0006] According to one aspect of the present invention, a memory system includes a memory device and a memory controller configured to control the operation of the memory device. The memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bit line and a first complementary bit line extending in a first direction, arranged in a second direction intersecting the first direction and coupled to the memory cell array, a first vertical wire and a first bonding pad coupled to the first bit line, and a second vertical wire and a second bonding pad coupled to the first complementary bit line. The second semiconductor layer is arranged in a third direction perpendicular to the first direction and the second direction relative to the first semiconductor layer. The second semiconductor layer includes a peripheral circuit configured to control the memory cell array, a first bit line sense amplifier configured to control the first bit line and the first complementary bit line, a first control line and a second control line coupled to the first bit line sense amplifier, a third bonding pad and a third vertical wire coupled to the first bonding pad and the first bit line sense amplifier, and a fourth bonding pad and a fourth vertical wire coupled to the second bonding pad and the first bit line sense amplifier. The first bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

[0007] According to one aspect of the present disclosure, a memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bit line and a first complementary bit line extending in a first direction, arranged in a second direction intersecting the first direction and coupled to the memory cell array, a first vertical wire and a first bonding pad coupled to the first bit line, and a second vertical wire and a second bonding pad coupled to the first complementary bit line. The second semiconductor layer is arranged in a third direction perpendicular to the first direction and the second direction relative to the first semiconductor layer. The second semiconductor layer includes a peripheral circuit configured to control the memory cell array, a first bit line sense amplifier configured to control the first bit line and the first complementary bit line, a first control line and a second control line coupled to the first bit line sense amplifier, a third bonding pad and a third vertical wire coupled to the first bonding pad and the first bit line sense amplifier, and a fourth bonding pad and a fourth vertical wire coupled to the second bonding pad and the first bit line sense amplifier. The first bit line sense amplifier includes a first pair of P-channel transistors, a first pair of N-channel transistors, a first node coupled to the first pair of P-channel transistors, and a second node coupled to the first pair of N-channel transistors. The first control line is coupled to the first node and shared by the first pair of P-channel transistors. A second control line is coupled to the second node and is shared by the first pair of N-channel transistors.

[0008] In a memory device and a memory system, according to example embodiments, vertical wiring between semiconductor layers may be possible, and therefore, a bit line, a complementary bit line, and / or a control line may be electrically connected to a bit line sense amplifier that may be efficiently arranged without significant space limitations. Alternatively or additionally, a control line may be shared within a bit line sense amplifier, and a stable control voltage may be supplied without being affected by surrounding bit line sense amplifiers. Therefore, when compared to a related memory device, the operational stability of the memory device may potentially be improved.

[0009] Additional aspects may be set forth in part in the description which follows and, in part, may be obvious from the description, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of certain embodiments of the present disclosure may be more apparent from the following description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view of a memory device according to an example embodiment;

[0012] Figure 2 is a perspective view of a memory device according to an example embodiment;

[0013] Figure 3is a circuit diagram of a first bit line sense amplifier included in a memory device according to example embodiments;

[0014] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a schematic diagram illustrating an example of a layout structure of a first bit line sense amplifier included in a memory device according to example embodiments;

[0015] Figure 5A , Figure 5B and Figure 5C is a perspective view of an example of a memory device according to example embodiments.

[0016] Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 is a schematic diagram of an operation of a first bit line sense amplifier included in a memory device according to example embodiments;

[0017] Fig.11 is a block diagram schematically illustrating a two-dimensional memory package according to example embodiments;

[0018] Fig.12 is a schematic diagram for describing a bit line voltage sensing operation of a first bit line sense amplifier included in a memory device according to example embodiments;

[0019] Fig.13 is a block diagram illustrating a memory system according to an example embodiment;

[0020] Fig.14A and Fig. 14B is a cross-sectional view of a memory package according to an example embodiment; and

[0021] Fig.15 is a schematic diagram illustrating a memory package including a memory device according to example embodiments. DETAILED DESCRIPTION

[0022] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, it will be appreciated by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and structures have been omitted for clarity and conciseness.

[0023] With respect to the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that, unless otherwise explicitly stated in the relevant context, the singular form of a noun corresponding to an item may include one or more things. As used herein, each of phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include any one or all possible combinations of the items listed together in a corresponding phrase. As used herein, terms such as "1st" and "2nd" or "first" and "second" may be used to simply distinguish a corresponding component from another component, and do not limit the component in other aspects (e.g., importance or order). It should be understood that if an element (e.g., a first element) is referred to as "coupled with another element (e.g., a second element)", "coupled to another element", "connected to another element", or "connected to another element" with or without the term "operably" or "communicatively", it means that the element may be coupled to another element directly (e.g., wired), wirelessly, or via a third element.

[0024] It should be understood that when an element or layer is referred to as being “over,” “on,” “under,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly over, on, up, below, under, under, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly over,” “directly on,” “directly below,” “directly below,” “directly under,” “directly connected to,” or “directly coupled to,” there are no intervening elements or layers.

[0025] As used herein, when an element or layer is referred to as "covering" another element or layer, the element or layer may cover at least a portion of the other element or layer, wherein the portion may include a portion of the other element or may include the entirety of the other element. Similarly, when an element or layer is referred to as "surrounding" another element or layer, the element or layer may surround at least a portion of the other element or layer, wherein the portion may include a portion of the other element or may include the entire dimension (e.g., length, width, depth) of the other element.

[0026] References throughout this disclosure to "one embodiment," "an embodiment," "an example embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in conjunction with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and therefore, the disclosure is not limited thereto, and may be implemented in various other forms.

[0027] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged. In addition, some blocks can be combined or omitted. The attached claims present the elements of the various blocks in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0028] As shown in the accompanying drawings, the embodiments herein may be described and illustrated in terms of blocks that perform one or more functions described. These blocks (which may be referred to herein as units or modules, etc., or by names such as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits, which include one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0029] In this disclosure, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Where only one item is intended, the term "a" or similar language is used. For example, the term "processor" may refer to a single processor or to multiple processors. When a processor is described as performing an operation and the processor is referred to as performing additional operations, the multiple operations may be performed by any one or combination of the single processor or multiple processors.

[0030] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0031] Figure 1 is a cross-sectional view of a memory device according to example embodiments.

[0032] exist Figure 1In the figure, two directions that are each parallel to or substantially parallel to the first surface (e.g., top surface) of the substrate and intersect each other may be referred to as a first direction D1 (e.g., X-axis direction) and a second direction D2 (e.g., Y-axis direction). In addition, a direction that is perpendicular to or substantially perpendicular to the first surface of the substrate may be referred to as a third direction D3 (e.g., Z-axis direction). For example, the first direction D1 and the second direction D2 may be perpendicular or substantially perpendicular to each other. In addition, the third direction D3 may be perpendicular or substantially perpendicular to both the first direction D1 and the second direction D2. In addition, the direction indicated by the arrow in the figure and its opposite direction may be considered to be the same direction. The first direction D1, the second direction D2, and the third direction D3 may be the same as described above in subsequent figures.

[0033] refer to Figure 1 , the memory device 100 may include a first semiconductor layer 101 and a second semiconductor layer 102 .

[0034] The first semiconductor layer 101 may include a first substrate SUB1, a first insulating layer IL1, a memory cell array MCA including a plurality of memory cells (e.g., a first memory cell MC1 to an Nth memory cell MCN, where N is a positive integer greater than zero (0)), a first bit line BL_1, a first complementary bit line BLB_1, a first vertical wire VL1, a second vertical wire VL2, a first bonding pad BP1, and a second bonding pad BP2. The second semiconductor layer 102 may include a second substrate SUB2, a second insulating layer IL2, a peripheral circuit PERI including a first bit line sense amplifier 150_1, a first control line LA, a second control line LAB, a third vertical wire VL3, a fourth vertical wire VL4, a third bonding pad BP3, and a fourth bonding pad BP4.

[0035] In some example embodiments, the memory device 100 may be and / or may include a volatile memory device. For example, the memory device 100 may be and / or may include any volatile memory, such as, but not limited to, a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, a low power DDR (LPDDR) SDRAM, a graphic DDR (GDDR) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a DDR4 SDRAM, etc. For example, the memory device 100 may have a cell over periphery (COP) structure, in which a peripheral circuit PERI may be formed at the bottom and / or a memory cell array MCA may be stacked on the peripheral circuit PERI within a semiconductor manufacturing process.

[0036] The first semiconductor layer 101 may refer to a layer including a memory cell array MCA for storing data in a memory device having a COP structure. For example, the memory cell array MCA may include a plurality of memory cells MC1 to MCN.

[0037] The first substrate SUB1 may be and / or may include a support layer that may support components of the first semiconductor layer 101. The second substrate SUB2 may be and / or may include a support layer that may support components of the second semiconductor layer 102. For example, each of the first substrate SUB1 and the second substrate SUB2 may be and / or may include a silicon (Si) substrate, and may be referred to as a base substrate. In an embodiment, the first insulating layer IL1 may cover components of the first semiconductor layer 101, and / or the second insulating layer IL2 may cover components of the second semiconductor layer 102.

[0038] The first bit line BL_1 and the first complementary bit line BLB_1 may extend in the first direction D1 and may be connected to the memory cell array MCA. For example, the logic voltage level of the first complementary bit line BLB_1 may be opposite to the logic voltage level of the first bit line BL_1. Figure 2 In the described embodiment, the first bit line BL_1 and the first complementary bit line BLB_1 may be arranged along a second direction D2 that intersects the first direction D1. For example, the first direction D1 may indicate a direction parallel to the first bit line BL_1 and the first complementary bit line BLB_1. As another example, the second direction D2 may indicate a direction perpendicular to the first bit line BL_1 and the first complementary bit line BLB_1 and a direction parallel to the word line (e.g., Figure 2 In an embodiment, data may be read from and / or written to the plurality of memory cells MC1 to MCN via the first bit line BL_1, the first complementary bit line BLB_1, the plurality of word lines, and the first bit line sense amplifier 150_1.

[0039] The first vertical wire VL1 may be connected to the first bit line BL_1, and the second vertical wire VL2 may be connected to the first complementary bit line BLB_1. For example, the first vertical wire VL1 and the second vertical wire VL2 may be part of a plurality of vertical wires electrically connecting the memory cell array MCA and the first bit line sense amplifier 150_1. Alternatively or additionally, the first vertical wire VL1 and the second vertical wire VL2 may be connected to the first bonding pad BP1 and the second bonding pad BP2, respectively.

[0040] The second semiconductor layer 102 may represent a layer of a peripheral circuit PERI other than a memory cell array MCA included in a memory device (e.g., memory device 100) having a COP structure. For example, the peripheral circuit PERI may include a first bit line sense amplifier 150_1. The second semiconductor layer 102 may be arranged in a third direction D3 perpendicular to the first direction D1 and the second direction D2 relative to the first semiconductor layer 101. In an embodiment, the first semiconductor layer 101 may be stacked on the second semiconductor layer 102 in the third direction D3, and the second semiconductor layer 102 may be arranged under the first semiconductor layer 101 in the third direction D3. However, example embodiments are not limited thereto. For example, the memory device 100 may be flipped during a manufacturing process, and therefore, the first semiconductor layer 101 may be stacked on the second semiconductor layer 102 in the third direction D3.

[0041] The third bonding pad BP3 and the fourth bonding pad BP4 may be connected to the first bonding pad BP1 and the second bonding pad BP2, respectively. For example, the third vertical wire VL3 and the fourth vertical wire VL4 may be electrically connected to the first vertical wire VL1 and the second vertical wire VL2 via the third bonding pad BP3 and the fourth bonding pad BP4, respectively. As another example, the third vertical wire VL3 and the fourth vertical wire VL4 may also be connected to the first bit line sense amplifier 150_1. Alternatively or additionally, the third vertical wire VL3 may be connected to the drain of the transistor TR included in the first bit line sense amplifier 150_1, and the fourth vertical wire VL4 may be connected to the source of the transistor TR included in the first bit line sense amplifier 150_1.

[0042] In some example embodiments, the first semiconductor layer 101 and the second semiconductor layer 102 may be connected to each other using a bonding method. For example, the bonding method may refer to a method of electrically and / or physically connecting the first bonding pad BP1 and the second bonding pad BP2 of the first semiconductor layer 101 and the third bonding pad BP3 and the fourth bonding pad BP4 of the second semiconductor layer 102. As another example, the bonding method may refer to a method of electrically and / or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern of the first bonding pad BP1 to the fourth bonding pad BP4 is formed of copper (Cu), the bonding method may be referred to as a Cu-Cu bonding method. Alternatively or additionally, the bonding metal pattern may be formed of other metals, such as but not limited to aluminum (Al), tungsten (W), etc.

[0043] In some example embodiments, the first semiconductor layer 101 may be manufactured by forming a memory cell array MCA, first and second vertical wires VL1 and VL2, first and second bonding pads BP1 and BP2, and a first insulating layer IL1 on a first substrate SUB1. The second semiconductor layer 102 may be manufactured by forming a peripheral circuit PERI, third and fourth vertical wires VL3 and VL4, third and fourth bonding pads BP3 and BP4, and a second insulating layer IL2 on a second substrate SUB2. For example, by flipping the first semiconductor layer 101 and connecting the first bonding pad BP1 to the fourth bonding pad BP4 using a bonding method, the first semiconductor layer 101 and the second semiconductor layer 102 may be electrically connected in the third direction D3.

[0044] The first bit line sense amplifier 150_1 may control the memory cell array MCA and control the first bit line BL_1 and the first complementary bit line BLB_1. For example, when a read operation and / or a refresh operation is performed on the first bit line sense amplifier 150_1 in the memory device 100, a voltage level difference between the first bit line BL_1 and the first complementary bit line BLB_1 may be amplified. As another example, the first bit line sense amplifier 150_1 may be connected to a first control line LA and a second control line LAB that may control the first bit line sense amplifier 150_1. In an embodiment, the first bit line sense amplifier 150_1 may include at least one transistor pair that shares at least one of the first control line LA and the second control line LAB (or is shared by at least one of the first control line LA and the second control line LAB). That is, the situation that at least one transistor pair shares the first control line LA or the second control line LAB (or is shared by the first control line 1a or the second control line LAB) may indicate the situation that both the drain and the source of at least one transistor pair may be commonly connected to the first control line LA or the second control line LAB. In an embodiment, at least one of the first control line LA and the second control line LAB may be connected only to transistors in the first bit line sense amplifier 150_1 so that sensing and amplification operations may be performed without being affected by adjacent or neighboring bit line sense amplifiers.

[0045] refer to Figures 6 to 10 The operation of the first control line LA and the second control line LAB for controlling the first bit line sense amplifier 150_1 is described. Figure 3 One example of a circuit configuration of the first bit line sense amplifier 150_1 is described.

[0046] In the memory device 100, components in different semiconductor layers can be electrically connected via vertical wires, and therefore, the first bit line BL_1, the first complementary bit line BLB_1, and the first control line LA and the second control line LAB electrically connected to the first bit line sense amplifier 150_1 can be effectively arranged without significant space restrictions. The first control line LA and the second control line LAB can be shared within the first bit line sense amplifier 150_1, and a stable control voltage can be supplied without being affected by the surrounding bit line sense amplifiers. Therefore, when compared with related memory devices, the operational stability of the memory device can be improved.

[0047] Figure 2 is a perspective view of a memory device according to example embodiments.

[0048] refer to Figure 2 , the memory device 100a may be Figure 1 An example of a memory device 100. That is, Figure 2 The memory device 100a may include and / or may be similar in many respects to the above referenced Figure 1 The memory device 100 described herein may include additional features not mentioned above. The first semiconductor layer 101a may correspond to Figure 1 The first semiconductor layer 101 in the embodiment of the present invention, and the second semiconductor layer 102a may correspond to Figure 1 The first bit line sense amplifier 150_1a may correspond to the second semiconductor layer 102 in FIG. Figure 1 The first vertical wire VL1 to the fourth vertical wire VL4, the first bonding pad BP1 to the fourth bonding pad BP4, the first control line LA and the second control line LAB, the first bit line BL_1 and the first complementary bit line BLB_1 may include and / or may be similar in many aspects to Figure 1 Therefore, for the sake of brevity, the above references can be omitted Figure 1 The description of the described memory device 100a is repeated.

[0049] For example, the memory device 100a may have a structure in which the first semiconductor layer 101a and the second semiconductor layer 102a may be stacked in the third direction D3. In a certain embodiment, the first semiconductor layer 101a and the second semiconductor layer 102a may be electrically connected via the first vertical wire VL1 to the fourth vertical wire VL4 and the first bonding pad BP1 to the fourth bonding pad BP4. For example, when the first bit line BL_1 and the first complementary bit line BLB_1 are connected to the first bit line sense amplifier 150_1a in the third direction D3, the wiring may be less complex (e.g., more compact) to implement than when the bit line and the complementary bit line are connected to the bit line sense amplifier in the first direction D1 within the same semiconductor layer.

[0050] In some example embodiments, the first bit line sense amplifier 150_1a may include transistors (eg, a first transistor P1_a, a second transistor P1_b, a third transistor N1_a, and a fourth transistor N1_b). Figure 4A As described above, in a plan (or layout) view, the first bit line BL_1 may be electrically connected to the first transistor P1_a and the third transistor N1_a in the first direction D1. As another example, as shown in FIG. Figure 4A Further described, in a plan (or layout) view, the first complementary bit line BLB_1 may be electrically connected to the second transistor P1_b and the fourth transistor N1_b in the first direction D1.

[0051] In an embodiment, the first transistor P1_a and the second transistor P1_b may be arranged adjacent to each other in the second direction D2. The first control line LA may be electrically connected to the first transistor P1_a and the second transistor P1_b. That is, the first transistor P1_a and the second transistor P1_b may share the first control line LA.

[0052] In an embodiment, the third transistor N1_a and the fourth transistor N1_b may be arranged adjacent to each other in the second direction D2. For example, the second control line LAB may be electrically connected to the third transistor N1_a and the fourth transistor N1_b. That is, the third transistor N1_a and the fourth transistor N1_b may share the second control line LAB.

[0053] The first bit line sense amplifier 150_1a may include two pairs of transistors, which may be arranged adjacent to each other in the second direction D2 and may share the first control line LA and the second control line LAB. However, the structure of the bit line sense amplifier is not limited thereto.

[0054] Figure 3 is a circuit diagram of a first bit line sense amplifier included in a memory device according to example embodiments.

[0055] refer to Figure 3 , the first bit line sense amplifier 150_1 can be Figure 1 An example of a first bit line sense amplifier 150_1 in FIG. Figure 3As shown, the first bit line sense amplifier 150_1 may include a first transistor P1_a to a fourth transistor N1_b. In some example embodiments, the first transistor P1_a and the second transistor P1_b may be classified as P-channel transistors, and the third transistor N1_a and the fourth transistor N1_b may be classified as N-channel transistors. For example, the P-channel transistor may be and / or may include a p-type metal oxide semiconductor (PMOS) transistor, and the N-channel transistor may be an n-type metal oxide semiconductor (NMOS) transistor. In an embodiment, the first transistor P1_a and the second transistor P1_b may be referred to as a pair of first P-channel transistors, and / or the third transistor N1_a and the fourth transistor N1_b may be referred to as a pair of first N-channel transistors.

[0056] In an embodiment, the source of the first transistor P1_a and the source of the second transistor P1_b may be connected to the first control line LA via the first node ND1_a. The source of the third transistor N1_a and the source of the fourth transistor N1_b may be connected to the second control line LAB via the second node ND1_b. In an embodiment, the first node ND1_a and the second node ND1_b may be referred to as the first source node and the second source node of the first bit line sense amplifier 150_1, respectively.

[0057] Alternatively or additionally, the drains of the first transistor P1_a and the third transistor N1_a may be connected to the first complementary bit line BLB_1 via the second drain node ND1_d. The drains of the second transistor P1_b and the fourth transistor N1_b may be connected to the first bit line BL_1 via the first drain node ND1_c.

[0058] In an embodiment, the first bit line sense amplifier 150_1 may sense a voltage level change of the first bit line BL_1 and amplify the voltage level change. When the first bit line sense amplifier 150_1 performs sensing and amplification operations, the first node ND1_a may be connected to a power supply voltage terminal of the memory device through the first control line LA, and the second node ND1_b may be connected to a ground terminal through the second control line LAB. Therefore, a power supply voltage may be applied to the first node ND1_a, and a ground voltage may be applied to the second node ND1_b.

[0059] References Figure 3 The circuit structure of the first bit line sense amplifier 150_1 described above can be applied to Fig.12 The second bit line sense amplifier 150_2 to the nth bit line sense amplifier 150_n in FIG. For example, the first bit line sense amplifier 150_1 may be referred to as a bit line sense amplifier shared by an internal node. Figure 3In the embodiment, the first bit line sense amplifier 150_1 may be implemented in a circuit configuration including a pair of first P-channel transistors and a pair of first N-channel transistors and the transistors are cross-coupled. However, the circuit structure of the first bit line sense amplifier 150_1 may not be limited thereto. For example, Figure 3 FIG. 1 shows an equivalent circuit diagram of the first bit line sense amplifier 150_1, and depending on the layout structure of the bit line sense amplifier, the actual circuit structure of the first bit line sense amplifier 150_1 may be different from FIG. Figure 3 The circuit structure is different.

[0060] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a schematic diagram illustrating an example of a layout structure of a first bit line sense amplifier included in a memory device according to example embodiments.

[0061] refer to Figure 4A , the layout structure of the bit line sense amplifier LO can be Figure 1 1. For example, the bit line sense amplifier may include first to fourth transistors P1_a to N1_b.

[0062] The layout structure LO of the bit line sense amplifier may include a first bit line sense amplifier region R_SA1. For example, the first bit line sense amplifier region R_SA1 may include a region R1_a where the third transistor N1_a is arranged, a region R1_b where the fourth transistor N1_b is arranged, a region R1_c where the first transistor P1_a is arranged, and a region R1_d where the second transistor P1_b is arranged.

[0063] In the perspective view, the word line WL, the first bit line BL_1, and the first complementary bit line BLB_1 may be formed in a semiconductor layer different from the first bit line sense amplifier region R_SA1. In the plan view, the word line WL, the first bit line BL_1, and the first complementary bit line BLB_1 may be arranged to overlap the first bit line sense amplifier region R_SA1. Hereinafter, unless otherwise specified, the layout structure LO of the bit line sense amplifier may be described based on the plan view.

[0064] In an example of a transistor arrangement or arrangement in the first bit line sense amplifier region R_SA1, the third transistor N1_a may be arranged adjacent to the fourth transistor N1_b in the second direction D2, and the first transistor P1_a may be arranged adjacent to the second transistor P1_b in the second direction D2. For example, the first transistor P1_a may be arranged adjacent to the third transistor N1_a in the first direction D1. Therefore, in the layout structure LO of the bit line sense amplifier, the source of the first transistor P1_a and the source of the second transistor P1_b may be connected to the first control line LA, and the source of the third transistor N1_a and the source of the fourth transistor N1_b may be connected to the second control line LAB.

[0065] For example, the layout structure LO of the first bit line sense amplifier can stably supply the gate threshold voltage because the first control line LA and the second control line LAB may not be connected to other bit line sense amplifiers. Therefore, the noise generated by other bit line sense amplifiers can be potentially reduced, and the sensing margin of the bit line sense amplifier can be potentially improved.

[0066] refer to Figure 4B , the layout structure LO_a of the first bit line sense amplifier may be an example of a layout structure of a first bit line sense amplifier arranged adjacent to the second bit line sense amplifier. For example, the first bit line sense amplifier may include first to fourth transistors P1_a to N1_b, and the second bit line sense amplifier may include a fifth transistor P2_a, a sixth transistor P2_b, a seventh transistor N2_a, and an eighth transistor N2_b.

[0067] The first bit line sense amplifier layout structure LO_a may include a first bit line sense amplifier region R_SA1 ′. Figure 4A As described above, the first bit line BL_1 and the first complementary bit line BLB_1 may be formed in a first direction D1, and the word line WL may be formed in a second direction D2 perpendicular to the first direction D1. For example, the first bit line sense amplifier region R_SA1' may include a region R1_a' where the third transistor N1_a is arranged, a region R1_b' where the fourth transistor N1_b is arranged, a region R1_c' where the first transistor P1_a is arranged, and a region R1_d' where the second transistor P1_b is arranged.

[0068] The transistor arrangement of the first bit line sense amplifier region R_SA1′ may be similar to Figure 4A The transistor arrangements of the first bit line sense amplifier region R_SA1 in FIG. 1 are substantially similar and / or identical.

[0069] In the example of transistor arrangement in the second bit line sense amplifier region R_SA2', the seventh transistor N2_a may be arranged adjacent to the eighth transistor N2_b in the second direction D2, and the fifth transistor P2_a may be arranged adjacent to the sixth transistor P2_b in the second direction D2. The seventh transistor N2_a may be arranged adjacent to the fifth transistor P2_a in the first direction D1. Therefore, in the first bit line sense amplifier layout structure LO_a, the source of the fifth transistor P2_a and the source of the sixth transistor P2_b may be connected to the third control line LA_b, and the source of the seventh transistor N2_a and the source of the eighth transistor N2_b may be connected to the fourth control line LAB_b.

[0070] In some example embodiments, in the first bit line sense amplifier layout structure LO_a, the second bit line sense amplifier region R_SA2' may be adjacent to the first bit line sense amplifier region R_SA1' in the first direction D1. That is, the second bit line sense amplifier may be arranged adjacent to the first bit line sense amplifier in the first direction D1.

[0071] refer to Figure 4C , the layout structure LO_b of the bit line sense amplifier may be an example of a layout structure of a first bit line sense amplifier arranged adjacent to the second bit line sense amplifier. Figure 4B Duplicate description.

[0072] exist Figure 4C In, with Figure 4B Unlike the layout structure LO_a of the bit line sense amplifier in FIG. 1 , only one pair of N-channel transistors (eg, the third transistor N1_a and the fourth transistor N1_b) among the transistor pairs included in the first bit line sense amplifier can be connected to the second control line LAB_a. That is, the layout structure LO_b of the bit line sense amplifier can represent Figure 3 The layout structure of the bit line sense amplifier in which only a pair of N-channel transistors share the second node ND1_b.

[0073] In an embodiment, the layout structure LO_b of the bit line sense amplifier may include a first bit line sense amplifier region R_SA1″ and a second bit line sense amplifier region R_SA2″. For example, the first bit line sense amplifier region R_SA1″ may include a region R1_a″ where the third transistor N1_a is arranged, a region R1_b″ where the fourth transistor N1_b is arranged, a region R1_c″ where the first transistor P1_a is arranged, and a region R1_d″ where the second transistor P1_b is arranged.

[0074] In the example of transistor arrangement in the first bit line sense amplifier region R_SA1″, the third transistor N1_a may be arranged adjacent to the fourth transistor N1_b in the second direction D2, and the second transistor P1_b may be arranged adjacent to the first transistor P1_a in the second direction D2. The first transistor P1_a may be arranged adjacent to the third transistor N1_a in the first direction D1. Therefore, in the layout structure LO_b of the bit line sense amplifier, the source of the third transistor N1_a and the source of the fourth transistor N1_b may be connected to the second control line LAB_a, and the source of the first transistor P1_a and the source of the second transistor P1_b may be connected to different control lines LA_a and LA_b, respectively.

[0075] Since a transistor arrangement example of the second bit line sense amplifier region R_SA2 ″ may be substantially similar and / or identical to that of the first bit line sense amplifier region R_SA1 ″, a repeated description of the second bit line sense amplifier region R_SA2 ″ may be omitted for the sake of brevity.

[0076] For example, in the layout structure LO_b of the bit line sense amplifier, the first transistor P1_a and the fifth transistor P2_a may be connected to the first control line LA_a, and the second transistor P1_b and the sixth transistor P2_b may be connected to the third control line LA_b.

[0077] refer to Figure 4D , the layout structure LO_c of the bit line sense amplifier may be an example of a layout structure of a first bit line sense amplifier arranged adjacent to the second bit line sense amplifier. Figure 4B Description of the repeated layout structure LO_c.

[0078] exist Figure 4D In, with Figure 4B Unlike the layout structure LO_a of the bit line sense amplifier in the first embodiment, only one pair of P-channel transistors P1_a-P1_b may be connected to the first control line LA_a among the transistor pairs included in the first bit line sense amplifier. That is, the layout structure LO_c of the bit line sense amplifier may indicate that only one pair of P-channel transistors P1_a-P1_b shares the first control line LA_a. Figure 3 Layout structure of the bit line sense amplifier of the first node ND1_a in FIG.

[0079] In an embodiment, the layout structure LO_c of the bit line sense amplifier may include a first bit line sense amplifier region R_SA1''' and a second bit line sense amplifier region R_SA2'''. For example, the first bit line sense amplifier region R_SA1''' may include a region R1_a''' where the third transistor N1_a is arranged, a region R1_b''' where the fourth transistor N1_b is arranged, a region R1_c''' where the first transistor P1_a is arranged, and a region R1_d''' where the second transistor P1_b is arranged.

[0080] In the example of the transistor arrangement in the first bit line sense amplifier region R_SA1''', the first transistor P1_a may be arranged adjacent to the third transistor N1_a in the first direction D1, and the second transistor P1_b may be arranged adjacent to the first transistor P1_a in the second direction D2. The fourth transistor N1_b may be arranged at a distance from the first transistor P1_a in the first direction D1. Therefore, in the layout structure LO_c of the bit line sense amplifier, the source of the first transistor P1_a and the source of the second transistor P1_b may be connected to the first control line LA_a. However, the source of the third transistor N1_a and the source of the fourth transistor N1_b may be connected to different control lines LAB_a and LAB_b, respectively.

[0081] Since a transistor arrangement example of the second bit line sense amplifier region R_SA2 ′″ may be substantially similar and / or identical to that of the first bit line sense amplifier region R_SA1 ′″, a repeated description of the second bit line sense amplifier region R_SA2 ′″ may be omitted for the sake of brevity.

[0082] The layout structure of the memory device according to the example embodiment is not limited thereto. Figure 4B In the layout structure LO_a of the bit line sense amplifier in the embodiment, only two pairs of P-channel transistors (e.g., a first pair having a first transistor P1_a and a second transistor P1_b and a second pair having a fifth transistor P2_a and a sixth transistor P2_b) of the transistor pairs can be connected to the control lines LA_a and LA_b, respectively. For example, the layout structure LO_c of the bit line sense amplifier can be implemented such that a pair of P-channel transistors (e.g., a first transistor P1_a and a second transistor P1_b) share a control line LA_a and a control line LA_b. Figure 3 The first node ND1_a in.

[0083] Figure 5A , Figure 5B and Figure 5C is a perspective view of an example of a memory device according to example embodiments.

[0084] refer to Figure 5A , the memory device 100b may be Figure 1 An example of a memory device 100 in FIG. Figure 5A The memory device 100b may include and / or may be similar in many respects to the above referenced Figure 1 and Figure 2 The memory device 100 and the memory device 100a described above may include additional features not mentioned above. The first vertical wire VL1 to the fourth vertical wire VL4, the first bonding pad BP1 to the fourth bonding pad BP4, the first control line LA and the second control line LAB, the first bit line BL_1 and the first complementary bit line BLB_1 may be connected to the reference Figure 1 and Figure 2 Those described are substantially similar and / or identical. Figure 1 and Figure 2 Therefore, for the sake of brevity, the above references can be omitted. Figure 1 and 2 The description of the described memory device 100b is repeated.

[0085] For example, the memory device 100b may be a device in which the second bit line sense amplifier 150_2b is additionally arranged in Figure 2 As another example, the first semiconductor layer 101b may further include a second bit line BL_2, a second complementary bit line BLB_2, a fifth vertical wire VL5, a sixth vertical wire VL6, a fifth bonding pad BP5, and a sixth bonding pad BP6. In a certain embodiment, the second semiconductor layer 102b may further include a second bit line sense amplifier 150_2b, a third control line LA2, a fourth control line LAB2, a seventh vertical wire VL7, an eighth vertical wire VL8, a seventh bonding pad BP7, and an eighth bonding pad BP8.

[0086] In an embodiment, the second bit line BL_2 and the second complementary bit line BLB_2 may be arranged in the second direction D2 together with the first bit line BL_1 and the first complementary bit line BLB_1. In some example embodiments, the second bit line sense amplifier 150_2b may be arranged in the first direction D1 together with the first bit line sense amplifier 150_1b. The fifth bonding pad BP5 and the sixth bonding pad BP6 may be physically connected to the seventh bonding pad BP7 and the eighth bonding pad BP8, respectively. The third control line LA2 and the fourth control line LAB2 may control the second bit line sense amplifier 150_2b. In an embodiment, as shown in reference Figure 3 As described, a pair of P-channel transistors and a pair of N-channel transistors included in the second bit line sense amplifier 150_2 b may share the third control line LA2 and the fourth control line LAB2 , respectively.

[0087] In an embodiment, the control lines may not be shared between the bit line sense amplifiers. For example, the first bit line sense amplifier 150_1b may be connected to the first control line LA1 and the second control line LAB1, and the second bit line sense amplifier 150_2b may be connected to the third control line LA2 and the fourth control line LAB2. That is, the first bit line BL_1 and the first complementary bit line BLB_1 may be connected to the first bit line sense amplifier 150_1b in the third direction D3, and the second bit line BL_2 and the second complementary bit line BLB_2 may be connected to the second bit line sense amplifier 150_2b in the third direction D3. Therefore, even when the second bit line sense amplifier 150_2b is arranged adjacent to the first bit line sense amplifier 150_1b in the first direction D1, the wiring may be relatively less complicated compared to the associated memory device.

[0088] refer to Figure 5B , the memory device 100c may be Figure 1 An example of a memory device 100 in FIG. Figure 5B The memory device 100c may include and / or may be similar in many respects to the above referenced Figure 1 , Figure 2 and Figure 5A The memory devices 100, 100a and 100b described herein may include additional features not mentioned above. Therefore, for the sake of brevity, the above reference may be omitted. Figure 1 , Figure 2 and Figure 5A The description of the described memory device 100c is repeated.

[0089] For example, the memory device 100c may be one in which the third semiconductor layer 103c may be additionally stacked on Figure 5A In the example of the memory device 100b in the embodiment, the second bit line BL_2 and the second complementary bit line BLB_2 can be arranged on the third semiconductor layer 103c. For example, the third semiconductor layer 103c may include the second bit line BL_2, the second complementary bit line BLB_2, the fifth vertical wire VL5, the sixth vertical wire VL6, the fifth bonding pad BP5 and the sixth bonding pad BP6. For example, the first semiconductor layer 101c may include the first bit line BL_1, the first complementary bit line BLB_1, the first vertical wire VL1, the second vertical wire VL2, the first bonding pad BP1 and the second bonding pad BP2. The second semiconductor layer 102c may be connected to the reference Figure 5A The second semiconductor layer 102b described is substantially similar and / or identical.For example, the fifth bonding pad BP5 and the sixth bonding pad BP6 may be connected to the seventh bonding pad BP7 and the eighth bonding pad BP8, respectively.

[0090] In an embodiment, the first bit line BL_1 and the first complementary bit line BLB_1 may be arranged on the first semiconductor layer 101c, and the second bit line BL_2 and the second complementary bit line BLB_2 may be arranged on the third semiconductor layer 103c. Therefore, even when the second bit line sense amplifier 150_2c is arranged adjacent to the first bit line sense amplifier 150_1c in the first direction D1, the wiring may be relatively less complicated compared to the related memory device.

[0091] exist Figure 5B , an example of a structure in which the second semiconductor layer 102c is arranged between the first semiconductor layer 101c and the third semiconductor layer 103c is shown. In other example embodiments, the second semiconductor layer 102c may be located at the bottom, and various interlayer arrangements of semiconductor layers may be implemented.

[0092] refer to Figure 5C , the memory device 100d may be Figure 1 An example of a memory device 100 in FIG. Figure 5C The memory device 100d may include and / or may be similar in many respects to the above referenced Figure 1 , Figure 2 , Figure 5A and Figure 5B The memory devices 100, 100a, 100b and 100c described herein may include additional features not mentioned above. Therefore, for the sake of brevity, the above reference may be omitted. Figure 1 , Figure 2 , Figure 5A and Figure 5B The description of the described memory device 100d is repeated.

[0093] For example, the memory device 100d may be one in which the third semiconductor layer 103d may be additionally stacked on Figure 5A 1 and 10. The memory device 100b in FIG. 1 and the second bit line sense amplifier 150_2d are arranged on the third semiconductor layer 103c. The third semiconductor layer 103d may include a third control line LA2, a fourth control line LAB2, a second bit line sense amplifier 150_2d, a seventh vertical wire VL7, an eighth vertical wire VL8, a seventh bonding pad BP7, and an eighth bonding pad BP8. The second semiconductor layer 102d may include a first control line LA1, a second control line LAB1, a first bit line sense amplifier 150_1d, a third vertical wire VL3, a fourth vertical wire VL4, a third bonding pad BP3, and a fourth bonding pad BP4. The first semiconductor layer 101d may be connected to the reference Figure 5AThe first semiconductor layer 101b described is substantially similar and / or identical.For example, the fifth bonding pad BP5 and the sixth bonding pad BP6 may be connected to the seventh bonding pad BP7 and the eighth bonding pad BP8, respectively.

[0094] In one embodiment, the first bit line sense amplifier 150_1d and the second bit line sense amplifier 150_2d may be located in the second semiconductor layer 102d and the third semiconductor layer 103d, respectively. Therefore, even when the second bit line sense amplifier 150_2d is arranged adjacent to the first bit line sense amplifier 150_1d in the first direction D1, the wiring may be relatively less complicated compared to the related memory device.

[0095] exist Figure 5C , an example of a structure in which the first semiconductor layer 101d is arranged between the second semiconductor layer 102d and the third semiconductor layer 103d is shown. In other example embodiments, the first semiconductor layer 101d may be located on the top, and various interlayer arrangements of semiconductor layers may be implemented.

[0096] Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 is a schematic diagram of an operation of a first bit line sense amplifier included in a memory device according to example embodiments.

[0097] refer to Figure 6 , the bit line sense amplifier 150_1 may precharge the bit line BL_1 and the complementary bit line BLB_1 to the precharge voltage VPRE. Therefore, the bit line BL_1 and the complementary bit line BLB_1 may be connected to one node and precharged to the precharge voltage VPRE. Therefore, the first control line LA and the second control line LAB may be precharged to the precharge voltage VPRE.

[0098] refer to Figure 7 , the bit line BL_1 may be connected to the first node ND1_a and the gate of the second transistor P1_b, and the complementary bit line BLB_1 may be connected to the second node ND1_b and the gate of the first transistor P1_a. Therefore, the voltage of the first control line LA may be transformed from the precharge voltage VPRE to the power supply voltage VINTA, and the voltage of the second control line LAB may be transformed from the precharge voltage VPRE to the ground voltage VSS. Thereafter, the voltage of the first control line LA may be transformed from the power supply voltage VINTA to the precharge voltage VPRE, and the voltage of the second control line LAB may be transformed from the ground voltage VSS to the precharge voltage VPRE. The offset may be eliminated by the above operation.

[0099] refer to Figure 8, the first node ND1_a and the gate of the second transistor P1_b may be connected to each other, and the second node ND1_b and the gate of the first transistor P1_a may be connected to each other. Therefore, the word line WL connected to the memory cell may be activated, and charge sharing may occur between the charge stored in the cell capacitor of the memory cell and the charge stored in the bit line BL_1.

[0100] refer to Fig. 9 , the first bit line sense amplifier 150_1 can perform a pre-sensing operation and a recovery operation. For example, when data "1" (e.g., one, "high") is stored in the memory cell, the voltage of the bit line BL can be increased to the power supply voltage VINTA, and the voltage of the complementary bit line BLB can be reduced to the ground voltage VSS. On the contrary, when data of '0' (e.g., zero, 'low') is stored in the memory cell MC, the voltage of the bit line BL can be reduced to the ground voltage VSS, and the voltage of the complementary bit line BLB can be increased to the power supply voltage VINTA. The voltage difference sensed and amplified by the first bit line sense amplifier 150_1 can develop the voltages of the bit line BL_1 and the complementary bit line BLB_1 to the power supply voltage VINTA or the ground voltage VSS. After performing the pre-sensing operation, a recovery operation can be performed to store the data in the memory cell based on the developed voltage. Alternatively or additionally, the bit line BL_1 and the complementary bit line BLB_1 whose voltage develops to the voltage VINTA or the ground voltage VSS may be connected to the data line and output data to a data input / output (I / O) circuit (eg, Fig.11 data I / O circuit 160).

[0101] refer to Fig.10 , as referenced above Figures 6 to 9 As described above, the first bit line sense amplifier 150_1 may sequentially perform a precharge operation, an offset canceling operation, a charge sharing operation, a pre-sensing and restoring operation, and a precharge operation, and may sense and output data stored in a memory cell.

[0102] Fig.11 is a block diagram schematically illustrating a two-dimensional memory package according to example embodiments.

[0103] refer to Fig.11 , the memory device 100e, the first semiconductor layer 101e and the second semiconductor layer 102e may be Figure 1 1 , and a first semiconductor layer 101 and a second semiconductor layer 102. The memory device 100e may output data via a data line DQ in response to a command CMD, an address ADDR, and a control signal received from an external device (eg, a memory controller).

[0104] The memory device 100 e may include a memory cell array 110 , an address buffer 120 , a row decoder 130 , a column decoder 140 , a command decoder 112 , a control logic 114 , a bit line sense amplifier module (S / A) 150 , and a data I / O circuit 160 .

[0105] For example, the memory cell array 110 may be located on the first semiconductor layer 101e. As another example, the address buffer 120, the row decoder 130, the column decoder 140, the command decoder 112, the control logic 114, the bit line sense amplifier module 150 and the data input / output circuit 160 may be on the second semiconductor layer 102e.

[0106] The memory cell array 110 may include a plurality of memory cells arranged in rows and columns provided in a matrix form. For example, the memory cell array 110 may include a plurality of word lines and a plurality of bit lines BL connected to the memory cells. For example, a plurality of word lines may be connected to the rows of the memory cells, and a plurality of bit lines BL may be connected to the columns of the memory cells.

[0107] The command decoder 112 may decode a write enable signal that may be received from an external device (eg, a memory controller). , row address strobe signal , column address strobe signal , Chip select signal Etc., so that a control signal corresponding to the command CMD can be generated by the control logic 114. For example, the command CMD may include but is not limited to an active command, a read command, a write command, a precharge command, etc.

[0108] The address buffer 120 may receive an address ADDR from an external device (e.g., a memory controller). The address ADDR may include a row address RA for addressing a row of the memory cell array 110 and / or a column address CA for addressing a column of the memory cell array 110. The address buffer 120 may send the row address RA to the row decoder 130 and the column address CA to the column decoder 140.

[0109] The row decoder 130 may select any one of a plurality of word lines connected to the memory cell array 110. The row decoder 130 may decode the row address RA received from the address buffer 120, select any one word line corresponding to the row address RA, and activate the selected word line.

[0110] The column decoder 140 may select a certain bit line BL from a plurality of bit lines BL of the memory cell array 110. The column decoder 140 may decode a column address CA received from the address buffer 120 and select a specific bit line BL corresponding to the column address CA.

[0111] The bit line sense amplifier module 150 may include a plurality of bit line sense amplifiers respectively connected to a plurality of bit lines BL of the memory cell array 110. For example, the plurality of bit line sense amplifiers may include reference Figure 3 As another example, a plurality of bit line sense amplifiers may sense voltage changes in a plurality of bit lines BL, may amplify the voltage changes, and may output the amplified voltage changes.

[0112] A first bit line sense amplifier included in a plurality of bit line sense amplifiers may be connected to one bit line and one complementary bit line, and sensing and amplification operations may be controlled via a first control line and a second control line. For example, the first control line may be connected to a power supply terminal of the memory device 100e to selectively supply a power supply voltage to a specific node of the first bit line sense amplifier, and the second control line may be connected to a ground terminal of the memory device 100e to ground a specific node of the first bit line sense amplifier. The first control line may be connected to a first node of the first bit line sense amplifier, and the second control line may be connected to a second node of the first bit line sense amplifier.

[0113] The data I / O circuit 160 may output data generated based on the voltage sensed and amplified by the first bit line sense amplifier module 150 to the outside through the data line DQ.

[0114] Fig.12 is a schematic diagram of a bit line voltage sensing operation of a first bit line sense amplifier included in a memory device according to example embodiments.

[0115] refer to Fig.12 , the bit line sense amplifier module 150 may be connected to the first memory cell array block 110a. For example, in a memory device having a COP structure, the first memory cell array block 110a and the bit line sense amplifier module 150 may be located in different semiconductor layers. For example, the first memory cell array block 110a may be connected to a plurality of bit lines (e.g., a first bit line BL_1, a second bit line BL_2 to an nth bit line BL_n, where n is a positive integer greater than two (2)) and to a plurality of complementary bit lines (e.g., a first complementary bit line BLB_1, a second complementary bit line BLB_2 to an nth complementary bit line BLB_n).

[0116] The bit line sense amplifier module 150 may include a plurality of bit line sense amplifiers (e.g., a first bit line sense amplifier 150_1, a second bit line sense amplifier 150_2, to an nth bit line sense amplifier 150_n) respectively connected to a plurality of bit lines BL_1 to BL_n and respectively connected to a plurality of complementary bit lines BLB_1 to BLB_n. For example, the first bit line sense amplifier 150_1 may be connected to the first bit line BL_1 and the first complementary bit line BLB_1, and may perform operations of sensing and amplifying the voltage of the first bit line BL_1. As another example, the plurality of bit line sense amplifiers 150_1 to 150_n may be connected to a first control line LA and a second control line LAB, and the sensing and amplification operations may be controlled via the first control line LA and the second control line LAB. Each of the plurality of bit line sense amplifiers 150_1 to 150_n may be connected to a reference Figure 3 The first bit line sense amplifier 150_1 described is substantially similar and / or identical.

[0117] Fig.13 is a block diagram illustrating a memory system according to example embodiments.

[0118] refer to Fig.13 , the memory system 1000 may include a memory controller 1200 and a memory module 1400. The memory module 1400 may include one or more memory devices 1800 (each of which may include a memory cell array) and a buffer device 1600 to route signals transmitted and received between the memory device 1800 and the memory controller 1200 or to manage memory operations of the memory device 1800. For example, the memory device 1800 and the buffer device 1600 may represent a memory chip and a buffer chip, respectively.

[0119] The memory devices 1800 of the memory module 1400 may be divided into a first rank R1 and a second rank R2. For example, each of the memory devices 1800 may have a reference Figure 1 As another example, each of the memory devices 1800 may include a plurality of bit line sense amplifiers that can sense the reference bit line. FIG. 4A to FIG. 4D The described layout structure of the first bit line sense amplifier is applied to multiple bit line sense amplifiers.

[0120] like Fig.13, an example is shown in which some functions of the memory controller 1200 can be performed in a memory module 1400 of a load-reduced dual in-line memory module (DIMM) (LRDIMM) type. However, the present disclosure is not limited thereto. For example, when a memory module 1400 of a fully buffered DIMM (FBDIMM) type is applied, an advanced memory buffer (AMB) chip can be mounted on the memory module 1400 as a buffer chip. In addition, another type of memory module 1400 can be applied, and the memory module 1400 can be implemented so that at least some functions of the above-mentioned memory controller 1200 can be performed in the memory module 1400.

[0121] Fig.14A and Fig. 14B is a cross-sectional view of a memory package according to example embodiments.

[0122] refer to Fig.14A , the memory package 700 may include a base substrate 710 and a plurality of memory chips (eg, a first memory chip CHP1 , a second memory chip CHP2 , and a third memory chip CHP3 ) stacked on the base substrate 710 .

[0123] Each of the plurality of memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of I / O pads IOPAD. The memory cell layer CLY and the peripheral circuit layer PLY may correspond to reference 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 64, 65, 67, 68, 69, 70, 71, 72, 73, 74, 75 Figure 1 The first semiconductor layer 101 and the second semiconductor layer 102 described herein may further include the elements described herein respectively included in the first semiconductor layer 101 and the second semiconductor layer 102 according to any example embodiments described herein. According to example embodiments, each of the plurality of memory chips CHP1 to CHP3 may include a memory device.

[0124] In some example embodiments, a plurality of memory chips CHP1 to CHP3 may be stacked on the base substrate 710 so that the surface on which a plurality of I / O pads IOPAD are formed faces upward. In some example embodiments, a plurality of I / O pads IOPAD may be arranged near one side of the semiconductor substrate relative to each of the plurality of memory chips CHP1 to CHP3. In this way, a plurality of memory chips CHP1 to CHP3 may be stacked scalariformly (e.g., in a stepped shape) so that a plurality of I / O pads IOPAD of each memory chip may be exposed. In this stacked state, a plurality of memory chips CHP1 to CHP3 may be electrically connected to the base substrate 710 by a plurality of bonding wires BW.

[0125] The plurality of stacked memory chips CHP1 to CHP3 and the plurality of bonding wires BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the base substrate 710 and the plurality of memory chips CHP1 to CHP3. Conductive bumps 720 may be formed on the bottom surface of the base substrate 710 for electrical connection with external devices.

[0126] refer to Fig. 14B , the memory package 800 may include a base substrate 810 and a plurality of memory chips CHP1 to CHP3 stacked on the base substrate 810. Fig.14A The memory package 800 may include and / or may be similar in many respects to the above reference Fig.14A The memory package 700 described herein may include additional features not mentioned above. Therefore, for the sake of brevity, the above reference may be omitted. Fig.14A The description of the memory package 800 described above is repeated.

[0127] Each of the plurality of memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of through silicon vias (TSVs) 830 .

[0128] In some example embodiments, with respect to each of the plurality of memory chips CHP1 to CHP3, the plurality of TSVs 830 may be arranged at the same position in each memory chip. Therefore, the plurality of memory chips CHP1 to CHP3 may be stacked so that the plurality of TSVs 830 of each memory chip may substantially and / or completely overlap (e.g., the arrangement of the plurality of TSVs 830 may perfectly match in the plurality of memory chips CHP1 to CHP3). In this stacked state, the plurality of memory chips CHP1 to CHP3 may be electrically connected to each other and to the base substrate 810 through the plurality of TSVs 830 and the conductive material 840.

[0129] The conductive bump 820 and the sealing member 850 may be connected to the reference Fig.14A The conductive bumps 720 and sealing member 740 are depicted as being substantially similar and / or identical.

[0130] Fig.15 is a schematic diagram illustrating a memory package including a memory device according to example embodiments.

[0131] refer to Fig.15 , the semiconductor package 900 may include one or more stacked memory devices 910 and a processing device 920. For example, the processing device 920 may be a graphics processing unit (GPU).

[0132] The stacked memory device 910 and the processing device 920 may be mounted on an interposer 930, and the interposer 930 on which the stacked memory device 910 and the processing device 920 are mounted may be mounted on a package substrate 940, and the package substrate 940 is mounted on solder balls 950. The processing device 920 may correspond to a semiconductor device that may perform a memory control function, and, for example, the processing device 920 may be implemented as an application processor (AP) or one of various processors.

[0133] The stacked memory device 910 may be implemented in various forms, and the stacked memory device 910 may be and / or may include a memory device in the form of a high bandwidth memory (HBM) in which a plurality of layers are stacked. Therefore, the stacked memory device 910 may be implemented by stacking a plurality of memory chips including the memory device according to example embodiments, as described with reference to Fig.14A and Fig. 14B As described.

[0134] A plurality of stacked memory devices 910 may be mounted on the interposer 930, and the processing device 920 may communicate with the plurality of stacked memory devices 910. For example, each of the stacked memory device 910 and the processing device 920 may include a physical region, and communication may be performed between the stacked memory device 910 and the processing device 920 through the physical region. For example, when the stacked memory device 910 includes a direct access region, a signal may be provided to the stacked memory device 910 through a conductive member (e.g., a solder ball 950) mounted below the package substrate 940 and the direct access region.

[0135] Example embodiments may be applied to various electronic devices and systems that may include memory devices and memory systems. For example, example embodiments may be applied to systems such as, but not limited to, personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0136] The foregoing is an illustration of example embodiments and should not be construed as limiting the same. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A memory device, comprising: The first semiconductor layer comprises: a memory cell array; a first bit line and a first complementary bit line extending in a first direction, arranged along a second direction crossing the first direction, and coupled to the memory cell array; a first vertical conductive line and a first bonding pad coupled to the first bit line; and a second vertical conductive line and a second bonding pad coupled to the first complementary bit line; a second semiconductor layer, arranged relative to the first semiconductor layer in a third direction perpendicular to the first direction and the second direction, the second semiconductor layer comprising: a peripheral circuit configured to control the memory cell array; a first bit line sense amplifier configured to control the first bit line and the first complementary bit line; a first control line and a second control line coupled to the first bit line sense amplifier; a third bonding pad and a third vertical conductive line coupled to the first bonding pad and the first bit line sense amplifier; and a fourth bonding pad and a fourth vertical conductive line coupled to the second bonding pad and the first bit line sense amplifier, The first bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

2. The memory device according to claim 1, wherein: The at least one first transistor pair includes a first pair of P-channel transistors and a first pair of N-channel transistors.

3. The memory device according to claim 2, wherein: The P-channel transistors are arranged along the second direction, wherein the N-channel transistors are arranged along the second direction, and The first pair of P-channel transistors and the first pair of N-channel transistors are arranged along the first direction.

4. The memory device according to claim 2, wherein: The first bit line sense amplifier also includes a first node coupled to the first pair of P-channel transistors, and Wherein, the first control line is coupled to the first node.

5. The memory device according to claim 4, wherein: The first control line is coupled to a supply voltage terminal of the memory device.

6. The memory device according to claim 2, wherein: The first bit line sense amplifier also includes a second node coupled to the first pair of N-channel transistors, and Wherein, the second control line is coupled to the second node.

7. The memory device according to claim 6, wherein: The second control line is coupled to a ground terminal of the memory device.

8. The memory device according to claim 1, wherein: The first semiconductor layer further comprises: a second bit line and a second complementary bit line extending in the first direction, arranged along the second direction crossing the first direction, and coupled to the memory cell array; a fifth vertical conductive line and a fifth bonding pad coupled to the second bit line; and a sixth vertical conductive line and a sixth bonding pad coupled to the second complementary bit line, Wherein, the second semiconductor layer further comprises: a second bit line sense amplifier configured to control the second bit line and the second complementary bit line; a third control line and a fourth control line coupled to the second bit line sense amplifier; a seventh bonding pad and a seventh vertical conductive line coupled to the fifth bonding pad and the second bit line sense amplifier; and an eighth bonding pad and an eighth vertical conductive line coupled to the sixth bonding pad and the second bit line sense amplifier, and The second bit line sense amplifier includes at least one second transistor pair shared by at least one of the third control line and the fourth control line.

9. The memory device according to claim 8, wherein: The at least one second transistor pair includes a second pair of P-channel transistors and a second pair of N-channel transistors.

10. The memory device of claim 9, wherein the second bit line sense amplifier further comprises a third node coupled to the second pair of P-channel transistors, and in, The third control line is coupled to the third node.

11. The memory device according to claim 9, wherein: The second bit line sense amplifier also includes a fourth node coupled to the second pair of N-channel transistors, and Wherein, the fourth control line is coupled to the fourth node.

12. The memory device according to claim 8, wherein: The second bit line sense amplifier is adjacent to the first bit line sense amplifier in the first direction.

13. The memory device according to claim 1, further comprising: a third semiconductor layer arranged in the third direction relative to the second semiconductor layer, Wherein, the third semiconductor layer comprises: a second bit line and a second complementary bit line extending in the first direction and arranged along the second direction; a second memory cell array coupled to the second bit line and the second complementary bit line; a fifth vertical conductive line and a fifth bonding pad coupled to the second bit line; and a sixth vertical conductive line and a sixth bonding pad coupled to the second complementary bit line, Wherein, the second semiconductor layer further comprises: a second bit line sense amplifier configured to control the second bit line and the second complementary bit line; a third control line and a fourth control line coupled to the second bit line sense amplifier; a seventh bonding pad and a seventh vertical conductive line coupled to the fifth bonding pad and the second bit line sense amplifier; and an eighth bonding pad and an eighth vertical conductive line coupled to the sixth bonding pad and the second bit line sense amplifier, and The second bit line sense amplifier includes at least one second transistor pair shared by at least one of the third control line and the fourth control line.

14. The memory device according to claim 1, further comprising: a third semiconductor layer arranged in the third direction relative to the first semiconductor layer, Wherein, the third semiconductor layer comprises: a second peripheral circuit configured to control a second memory cell array; a second bit line sense amplifier configured to control a second bit line and a second complementary bit line; a third control line and a fourth control line coupled to the second bit line sense amplifier; a seventh bonding pad and a seventh vertical conductive line coupled to the fifth bonding pad and the second bit line sense amplifier; and an eighth bonding pad and an eighth vertical conductive line coupled to the sixth bonding pad and the second bit line sense amplifier, and Wherein, the first semiconductor layer further comprises: the second bit line and the second complementary bit line extending in the first direction, arranged along the second direction crossing the first direction, and coupled to the memory cell array; a fifth vertical conductive line and the fifth bonding pad coupled to the second bit line; and a sixth vertical conductive line and the sixth bonding pad coupled to the second complementary bit line, and The second bit line sense amplifier includes at least one second transistor pair shared by at least one of the third control line and the fourth control line.

15. The memory device according to claim 1, wherein: The memory device includes a dynamic random access memory DRAM.

16. The memory device according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer are electrically coupled in the third direction through the first bonding pad, the second bonding pad, the third bonding pad, and the fourth bonding pad.

17. A memory system comprising: Memory devices; as well as Memory a controller configured to control the operation of the memory device, Wherein, the memory device comprises: The first semiconductor layer comprises: a memory cell array; a first bit line and a first complementary bit line extending in a first direction, arranged along a second direction crossing the first direction, and coupled to the memory cell array; a first vertical conductive line and a first bonding pad coupled to the first bit line; and a second vertical conductive line and a second bonding pad coupled to the first complementary bit line; A second semiconductor layer is arranged relative to the first semiconductor layer in a third direction perpendicular to the first direction and the second direction, the second semiconductor layer comprising: a peripheral circuit configured to control the memory cell array; a first bit line sense amplifier configured to control the first bit line and the first complementary bit line; a first control line and a second control line coupled to the first bit line sense amplifier; a third bonding pad and a third vertical conductive line coupled to the first bonding pad and the first bit line sense amplifier; and a fourth bonding pad and a fourth vertical conductive line coupled to the second bonding pad and the first bit line sense amplifier, The first bit line sense amplifier includes at least one first transistor pair shared by at least one of the first control line and the second control line.

18. The memory device according to claim 17, wherein: The at least one first transistor pair includes a first pair of P-channel transistors and a first pair of N-channel transistors, and wherein at least one second transistor pair is between the first pair of P-channel transistors and the first pair of N-channel transistors, and Wherein, the at least one second transistor pair is arranged along the second direction.

19. The memory device according to claim 17, further comprising: Buffer device, configured as: routing signals between the memory device and the memory controller; as well as Managing the operation of the memory device.

20. A memory device comprising: The first semiconductor layer comprises: a memory cell array; a first bit line and a first complementary bit line extending in a first direction, arranged along a second direction crossing the first direction, and coupled to the memory cell array; a first vertical conductive line and a first bonding pad coupled to the first bit line; and a second vertical conductive line and a second bonding pad coupled to the first complementary bit line; A second semiconductor layer is arranged relative to the first semiconductor layer in a third direction perpendicular to the first direction and the second direction, the second semiconductor layer comprising: a peripheral circuit configured to control the memory cell array; a first bit line sense amplifier configured to control the first bit line and the first complementary bit line; a first control line and a second control line coupled to the first bit line sense amplifier; a third bonding pad and a third vertical conductive line coupled to the first bonding pad and the first bit line sense amplifier; and a fourth bonding pad and a fourth vertical conductive line coupled to the second bonding pad and the first bit line sense amplifier, wherein the first bit line sense amplifier comprises a first pair of P-channel transistors, a first pair of N-channel transistors, a first node coupled to the first pair of P-channel transistors, and a second node coupled to the first pair of N-channel transistors, wherein the first control line is coupled to the first node and is shared by the first pair of P-channel transistors, and The second control line is coupled to the second node and is shared by the first pair of N-channel transistors.

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