Refresh method and device

Abstract

The present disclosure provides a refresh method and device, relating to the field of semiconductor technology. The method includes: obtaining an activation count value of a currently activated row address of a memory within a preset duration; if the activation count value belongs to any one of multiple count intervals that exceeds a row hammer threshold, determining whether a preset queue is full; wherein the queue is used to store row addresses that require a row hammer refresh operation; when the queue is not full, placing the row address in the queue, and determining a range of victim row addresses corresponding to the row address based on a target count interval to which the activation count value belongs, and refreshing the victim row address; when the queue is full, performing one of the preset operations, which includes adding 1 to the activation count value. The present disclosure can effectively ensure the stability of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a refresh method and device. Background Art

[0002] As the density of memory continues to increase, when the word line (WL) corresponding to a single row address in the memory cell is frequently turned on or turned on for a long time, it is likely to cause the leakage rate of the capacitors at the adjacent address (generally referred to as the "victim row address") to be higher than the natural leakage rate, thereby causing the capacitors at the adjacent address to lose too much charge before the refresh signal arrives, resulting in data loss. This situation is generally called the row hammer (RH) effect.

[0003] To suppress the RH effect, the victim row address needs to be refreshed in time before data is lost to replenish the charge. However, in the related art, the victim row address often loses data due to lack of timely refresh, thus affecting the stability of the memory. Summary of the Invention

[0004] The present disclosure provides a refresh method and device, which can effectively improve the stability of a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a refresh method, the method comprising:

[0006] Obtaining the activation count value of the currently activated row address of the memory within a preset time length;

[0007] If the activation count value belongs to any one of a plurality of count intervals that exceeds a row hammer threshold, determining whether a preset queue is full; wherein the queue is used to store row addresses for which a row hammer refresh operation is to be performed, and the plurality of count intervals have no intersection;

[0008] When the queue is not full, the row address is placed in the queue, and according to the target counting interval to which the activation count value belongs, a range of victim row addresses corresponding to the row address is determined and the victim row address is refreshed;

[0009] When the queue is full, one of the preset operations is performed, wherein the preset operation includes increasing the activation count by 1.

[0010] In some embodiments, the method further comprises:

[0011] determining the plurality of counting intervals;

[0012] When the number of activations of the row address within the preset time period belongs to different counting intervals, the ranges of victim row addresses corresponding to the row address are different.

[0013] In some embodiments, determining the plurality of counting intervals includes:

[0014] determining the number of victim row addresses adjacent to the row address when the row address is activated for different times within the preset time period;

[0015] The multiple counting intervals are determined according to a range of activation times of the row address within the preset time period when the number of victim row addresses adjacent to the row address is multiple preset values.

[0016] In some embodiments, determining the plurality of counting intervals includes:

[0017] Acquiring process parameters of the memory, wherein the process parameters include the capacity of a capacitor in each memory cell of the memory and / or the distance between adjacent word lines in the memory;

[0018] The plurality of counting intervals are determined according to the process parameters.

[0019] In some embodiments, the method further comprises:

[0020] According to the target counting interval to which the activation count value belongs and the range of victim row addresses corresponding to each counting interval, a refresh range identifier is added to the row address, and the refresh range identifier is used to indicate that the 2n victim row addresses adjacent to the row address need to perform a refresh operation; n is a positive integer, and the value of n is related to the target counting interval.

[0021] In some embodiments, the memory includes a plurality of word lines, the plurality of word lines including edge word lines and non-edge word lines; the edge word line is at least one word line located at an edge position among the plurality of word lines, and the non-edge word line is a word line among the plurality of word lines excluding the edge word line; determining the plurality of counting intervals includes:

[0022] determining a plurality of first counting intervals corresponding to the edge word lines and a plurality of second counting intervals corresponding to the non-edge word lines;

[0023] The first counting interval and the second counting interval corresponding to the same range of victim row addresses do not completely overlap.

[0024] In some embodiments, performing a preset operation includes:

[0025] Determining whether the target counting interval is a counting interval with a maximum count value;

[0026] If the target counting interval is not the counting interval with the largest counting value, the activation counting value is increased by 1;

[0027] If the target counting interval is the counting interval with the largest count value, the queue overflow alarm information is output.

[0028] In some embodiments, the memory includes a selector and a row decoder; the selector is configured to output a victim row address or an activated row address to the row decoder;

[0029] Putting the row address into the queue comprises:

[0030] The row address output by the selector is obtained, and the obtained row address is placed in the queue.

[0031] In a second aspect, an embodiment of the present disclosure provides a refreshing device, the device comprising:

[0032] An acquisition module is used to obtain an activation count value of a row address currently activated in the memory within a preset time period;

[0033] a determination module configured to determine whether a preset queue is full if the activation count value belongs to any one of a plurality of count intervals that exceeds a row hammer threshold, wherein the queue is configured to store row addresses for which a row hammer refresh operation is to be performed, and the plurality of count intervals have no intersection;

[0034] A processing module is used to place the row address into the queue when the queue is not full, and determine the range of the victim row address corresponding to the row address and refresh the victim row address based on the target counting interval to which the activation count value belongs; when the queue is full, perform one of the preset operations, and the preset operation includes adding 1 to the activation count value.

[0035] In some embodiments, the apparatus further comprises a pre-processing module for:

[0036] determining the plurality of counting intervals;

[0037] When the number of activations of the row address within the preset time period belongs to different counting intervals, the ranges of victim row addresses corresponding to the row address are different.

[0038] The refresh method and device provided in the embodiments of the present disclosure can prevent the activation count values ​​of multiple row addresses from reaching the counting threshold at the same time by setting multiple counting intervals, thereby effectively resisting multi-address same-frequency attacks; at the same time, according to the counting interval in which the activation count value of the row address is located, the range of the victim row address corresponding to the row address is determined and the victim row address is refreshed, thereby preventing the situation where some victim row addresses cannot be refreshed in time, further ensuring the stability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic structural diagram of a storage unit of a storage device provided in an embodiment of the present disclosure;

[0040] Figure 2 A schematic diagram of a row hammer refresh process provided in an embodiment of the present disclosure;

[0041] Figure 3 A schematic diagram of a queue overflow provided in an embodiment of the present disclosure;

[0042] Figure 4 A schematic flow chart of the steps of a refreshing method provided in an embodiment of the present disclosure;

[0043] Figure 5 This is a schematic flow chart of another step of a refreshing method provided in an embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of a program module of a refresh device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method separately.

[0046] It should be noted that the brief descriptions of terms in this disclosure are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0047] In the specification and claims of this disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish between similar or similar objects or entities and are not necessarily intended to limit a particular order or precedence, unless otherwise noted. It should be understood that the terms used in this manner are interchangeable where appropriate, e.g., embodiments of the disclosure can be implemented in an order other than that shown or described in the drawings.

[0048] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0049] It should be understood that when an element is referred to as being “connected” or “electrically connected” to other elements in an embodiment of the present disclosure, the element may be directly connected or electrically connected to the other elements; or there may be several intermediate elements, and the element may be connected or electrically connected to the other elements through the several intermediate elements.

[0050] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that can perform the functions associated with the element.

[0051] The embodiments of the present disclosure relate to the field of semiconductor memory technology and can optionally be applied to the design of dynamic random access memory (DRAM) chips, including controlling the refresh mode of DRAM. It should be noted that the refresh method provided in the embodiments of the present disclosure can be applied to both DRAM and various other memories that experience row hammering, and is not limited in the embodiments of the present disclosure.

[0052] It can be understood that a memory generally includes a plurality of bit lines (BL), a plurality of word lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding WL and a corresponding BL.

[0053] In some embodiments, each memory cell includes a transistor and a capacitor, with the gate of the transistor connected to WL, one of the source / drain of the transistor connected to BL, and the other connected to the capacitor. When the signal on WL turns on the transistor, BL can write a high-level signal "1" to the capacitor. When the signal on WL turns off the transistor, the charge on the capacitor slowly leaks out over time. The time it takes for the capacitor to leak from the high-level signal "1" to the intermediate potential is the data retention time of the memory cell. To prevent the loss of data stored in the capacitor, the memory needs to continuously refresh all its stored data within a limited time period.

[0054] Reference Figure 1 , Figure 1 A schematic structural diagram of a storage unit of a storage device provided in an embodiment of the present disclosure.

[0055] In some embodiments, each memory cell 10 includes a transistor 12 and a capacitor 11, wherein the gate of the transistor 12 is connected to WL, the source of the transistor 12 is connected to BL, and the drain of the transistor 12 is connected to the capacitor 11. It should be noted that the source of the transistor 12 may also be connected to the capacitor 11, and correspondingly, the drain of the transistor 12 is connected to BL.

[0056] As memory density continues to increase, the word lines within its storage cells are physically closer, leading to increased capacitive coupling between adjacent word lines. This means that when one word line is turned on, the behavior of its neighboring word lines changes briefly, causing a small amount of charge to leak from the capacitors corresponding to the adjacent word lines. Repeatedly accessing a row of addresses at high frequencies can cause data loss due to repeated charge leakage from the capacitors corresponding to adjacent word lines. This phenomenon is commonly known as row hammering and is often exploited as a system attack vector.

[0057] In the Per Row Hammer Tracking (PRHT) scheme, an activation counter (AC) is added to each WL. Each activation counter consists of several bits (e.g., 16 bits) to record the number of times the corresponding WL is activated. When the count value of any activation counter exceeds a fixed count threshold, the address of the corresponding WL is placed in a designated queue to wait for a row hammer refresh (RHR).

[0058] The queue may be a First Input First Output (FIFO) queue. It should be noted that, due to the physical area reserved for the queue in the memory, no matter which queue is used, the number of row addresses that can be stored is always limited.

[0059] However, in the above-mentioned PRHT scheme, if a multi-address same-frequency attack occurs, it is easy to cause the count values ​​of multiple activation command counters to exceed the above-mentioned counting threshold in a short period of time, causing the above-mentioned queue to overflow due to insufficient storage capacity, resulting in some WL addresses being unable to enter the above-mentioned queue and not receiving timely RHR; thereby affecting the stability of the memory.

[0060] In order to better understand the embodiments of the present disclosure, refer to Figure 2 , Figure 2 A schematic diagram of a row hammer refresh process based on a single threshold provided in an embodiment of the present disclosure.

[0061] exist Figure 2In the memory, the storage queue includes multiple WLs (i, j, k), and so on. Each WL is accompanied by an activation command counter, which consists of several bits and is used to record the number of times the corresponding WL has been activated. When the count value of any activation command counter reaches a specified threshold, the address of the corresponding WL, i.e., the attack row address, is placed in the queue to await the RHR process. The RHR process involves deriving the victim row address based on the attack row address and promptly refreshing the capacitor corresponding to the victim row address to replenish the charge and prevent errors in the stored data.

[0062] In the embodiment of the present disclosure, the victim row address generation module can generate corresponding victim row addresses based on the attack row addresses in the above-mentioned queue and the refresh range of RHR. These victim row addresses can be refreshed simultaneously during the row hammer refresh or refreshed in multiple times, which is not limited in the embodiment of the present disclosure.

[0063] In the embodiment of the present disclosure, after the victim row address generation module generates the victim row address, the generated victim row address RA_RH can be output to the row decoder through the selector 20; when there is no victim row address or after all the generated victim row addresses are sent to the row decoder, the selector 20 is selected to transmit the activated row address RA_ACT to the row decoder.

[0064] Reference Figure 3 , Figure 3 A schematic diagram of a queue overflow provided in an embodiment of the present disclosure.

[0065] It is understandable that, assuming that the count threshold of the activation command counter on the WL is 1024 and the depth of the above queue is 5, then if 7 WLs ( Figure 3 In the example, if two WLs (named by h, i, j, k, l, m, and n, respectively) are activated at the same frequency, then after 7×1024 activation commands, the activation command counters of these 7 WLs will successively reach the above-mentioned counting threshold. Since the depth of the above-mentioned queue is only 5, there will be 2 attack row addresses that cannot enter the above-mentioned queue in time, resulting in the inability to generate the victim row address corresponding to the attack row address, and thus the inability to refresh the victim row address in time. In the embodiment of the present disclosure, after the above-mentioned queue is full, no more data will be written, otherwise errors such as data overwriting will occur. Data that cannot be written to the above-mentioned queue in time will usually be discarded or other cache operations will be performed. In the embodiment of the present disclosure, the situation of being unable to enter the queue temporarily or permanently in time, such as being discarded, can continue to be written when the content in the queue is read out and there is a vacancy.

[0066] like Figure 3As shown in the figure, when the activation command counters of word lines h, i, j, k, and l successively reach the above-mentioned counting threshold, the addresses of word lines h, i, j, k, and l will be successively placed in the queue. When the queue is occupied by the addresses of word lines h, i, j, k, and l, although the activation command counters of word lines m and n have also reached the above-mentioned counting threshold, the above-mentioned queue is full at this time, so the addresses of word lines m and n cannot be placed in the queue, resulting in the addresses of word lines m and n being unable to enter the above-mentioned queue and unable to generate the victim row addresses corresponding to word lines m and n, and thus the victim row addresses cannot be refreshed in time.

[0067] Furthermore, in some embodiments, the refresh range of an RHR is primarily randomly selected. For example, assuming there are eight WLs (named a, b, c, d, e, f, g, and h) awaiting an RHR, the refresh range of these eight WLs can be first determined to be "±1." Then, a portion of these eight WLs can be randomly selected (e.g., b, c, f, and h), and the refresh range of these WLs can be determined to be "±1, ±2." Furthermore, another portion of these selected WLs can be randomly selected (e.g., c and f), and the refresh range of these WLs can be determined to be "±1, ±2, ±3."

[0068] Among them, "±1" means that the first WL on both sides of the attacked WL needs to be refreshed, "±2" means that the second WL on both sides of the attacked WL needs to be refreshed, and "±3" means that the third WL on both sides of the attacked WL needs to be refreshed.

[0069] It is understandable that the row hammering effect of WL will accelerate the change of charge in the storage cells on nearby WLs. After the number of activation times of WL exceeds a certain threshold, the more activation times, the greater the impact range on nearby WLs. If the refresh range of the attacked WL is randomly selected, it is possible that some victim row addresses cannot be refreshed in time, which also affects the stability of the memory.

[0070] To address the above technical issues, the present disclosure provides a refresh method in embodiments that, by setting multiple counting thresholds in the PRHT, prevents the count values ​​of the activation command counters on multiple WLs from reaching the counting thresholds simultaneously, thereby effectively defending against multi-address co-frequency attacks. Furthermore, based on the counting interval within which the WL's activation count falls, the range of victim row addresses corresponding to the WL is determined. This prevents some victim row addresses from failing to be refreshed in a timely manner, further ensuring the stability of the memory. This is illustrated below using a detailed embodiment.

[0071] Reference Figure 4 , Figure 4 Schematic diagram of a refresh method provided in an embodiment of the present disclosure; in some embodiments, the refresh method includes:

[0072] S401: Obtain an activation count value of a row address currently activated in a memory within a preset time period.

[0073] In some implementations, the memory may employ a PRHT scheme to promptly refresh the victim row address to replenish the charge and avoid errors in the stored data.

[0074] An activation command counter is added to each WL. This activation command counter includes several bits and is used to record the number of times the corresponding WL has been activated. After any row address in the memory is activated, the activation count value of the row address within a preset time period can be read from the activation command counter on the WL corresponding to the activated row address.

[0075] S402: Determine whether the activation count value belongs to any of the multiple count intervals exceeding the hammer threshold. If yes, proceed to S403.

[0076] In some embodiments, multiple counting thresholds may be pre-set, and multiple counting intervals may be determined by these thresholds. For example, a first counting threshold D1, a second counting threshold D2, and a third counting threshold D3 may be set, where D1 < D2 < D3. Based on the counting thresholds D1, D2, and D3, three counting intervals may be determined: (D1, D2), [D2, D3), and [D3, ∞).

[0077] The plurality of count intervals all exceed the row hammer threshold, i.e., when the count value of any active command counter falls within any of the plurality of count intervals, it indicates that the address of the corresponding WL needs to perform an RHR. In some embodiments, the first count threshold D1 is the row hammer threshold.

[0078] When the number of activations of the row address within the preset time period belongs to different counting intervals, the number of victim row addresses adjacent to the row address is different.

[0079] Exemplarily, in some embodiments, after obtaining the activation count value of the currently activated row address of the memory within a preset time length, it is determined whether the activation count value belongs to any one of the above-mentioned counting intervals (D1, D2), [D2, D3), [D3, ∞); if the above-mentioned activation count value belongs to any one of the above-mentioned counting intervals (D1, D2), [D2, D3), [D3, ∞), continue to execute S403.

[0080] In some implementations, if the activation count value does not belong to any of the multiple counting intervals, the activation count value is incremented by 1.

[0081] S403, determine whether the preset queue is full. If not, continue to execute S404; if so, execute S405.

[0082] The queue is used to store row addresses that require RHR, and the multiple counting intervals have no intersection.

[0083] Optionally, the queue can be a FIFO queue. A FIFO queue is an in-order queue where the first instruction that enters the queue is completed and retired before the next instruction is executed. The following are some important parameters of FIFO:

[0084] Width: refers to the data bits of a FIFO read or write operation, such as 8 bits, 16 bits, 32 bits, etc.

[0085] Depth: refers to how many N-bit data a FIFO can store (if the width is N). For example, if the FIFO width is 8 bits and the depth is 5, it can store 5 8-bit data. If the depth is 12, it can store 12 8-bit data.

[0086] Full flag: A signal sent by the FIFO status circuit when the FIFO is full or about to be full, to prevent the FIFO write operation from continuing to write data into the FIFO and causing overflow.

[0087] Empty flag: A signal sent by the FIFO status circuit when the FIFO is empty or about to be empty to prevent the FIFO read operation from continuing to read data from the FIFO and causing invalid data to be read (underflow).

[0088] Read clock: The clock followed by the read operation, data is read at each clock edge.

[0089] Write clock: The clock followed by the write operation, data is written at each clock edge.

[0090] Read pointer: points to the next read address and automatically increases by 1 after reading.

[0091] Write pointer: points to the next address to be written, and automatically increases by 1 after writing.

[0092] Among them, the read and write pointers are actually the read and write addresses, but this address cannot be selected arbitrarily, but is continuous. In the actual operation of FIFO, its data full flag can control the continued writing of data, and the empty flag can control the reading of data.

[0093] For example, in some embodiments, if the activation count value falls within any one of the counting intervals (D1, D2), [D2, D3), and [D3, ∞), whether the queue is full can be determined by detecting whether the FIFO status circuit sends a full flag signal. Specifically, if the FIFO status circuit is detected to send a "full flag" signal, the queue is determined to be full; if the FIFO status circuit is not detected to send a "full flag" signal, the queue is determined to be not full.

[0094] S404: Put the row address into the queue, and determine the range of victim row addresses corresponding to the row address according to the target counting interval to which the activation count value belongs, and refresh the victim row addresses.

[0095] In some embodiments, a correspondence between each counting interval and a range of victim row addresses can be pre-established. For example, the range of victim row addresses corresponding to the counting interval (D1, D2) is "±1," the range of victim row addresses corresponding to the counting interval [D2, D3) is "±1, ±2," and the range of victim row addresses corresponding to the counting interval [D3, ∞) is "±1, ±2, ±3." After determining the target counting interval to which the activation count value belongs, the range of victim row addresses corresponding to the row addresses can be determined based on this correspondence.

[0096] For example, when the target counting interval to which the above-mentioned activation count value belongs is (D1, D2), the range of the victim row address corresponding to the above-mentioned row address is determined to be "±1", and the first word line on both sides of the above-mentioned row address is refreshed; when the target counting interval to which the above-mentioned activation count value belongs is [D2, D3), the range of the victim row address corresponding to the above-mentioned row address is determined to be "±1, ±2", and the first and second word lines on both sides of the above-mentioned row address are refreshed; when the target counting interval to which the above-mentioned activation count value belongs is [D3, ∞), the range of the victim row address corresponding to the above-mentioned row address is determined to be "±1, ±2, ±3", and the first, second and third word lines on both sides of the above-mentioned row address are refreshed; and so on.

[0097] S405: Execute one of the preset operations, where the preset operation includes adding 1 to the activation count value.

[0098] In some implementations, when the queue is full, the activation count value may be increased by 1, and then the activation count value of the row address may be accumulated. When the queue is not full, the row address may be placed in the queue.

[0099] The refresh method provided in the embodiment of the present disclosure can prevent the activation count values ​​of multiple row addresses from reaching the counting threshold at the same time by setting multiple counting intervals, thereby effectively resisting multi-address same-frequency attacks; at the same time, according to the counting interval in which the activation count value of the row address is located, the range of the victim row address corresponding to the row address is determined and the victim row address is refreshed, thereby preventing the situation where some victim row addresses cannot be refreshed in time, further ensuring the stability of the memory.

[0100] Based on the content described in the above embodiments, in some embodiments of the present disclosure, the above-mentioned multiple counting intervals can be pre-determined in the following manner:

[0101] Determine the number of victim row addresses adjacent to the row address when the row address of the memory is activated different times within a preset time length; determine the above-mentioned multiple counting intervals based on the range of the number of activation times of the row address within the above-mentioned preset time length when the number of victim row addresses adjacent to the above-mentioned row address is multiple preset values.

[0102] In some embodiments, the memory can be pre-read and written tested. After activating any row address for different times within a preset time period, the number of victim row addresses adjacent to the row address is determined. Then, based on the range of the number of activation times of the row address within the preset time period when the number of victim row addresses adjacent to the row address is multiple preset values, the above-mentioned multiple counting intervals are determined.

[0103] The preset value may include 2, 4, 6, etc., which is not limited in the embodiment of the present disclosure. It is understandable that when the preset value is 2, the victim row address range should be "±1".

[0104] Exemplarily, in some embodiments, assuming that when the number of activations of the above-mentioned row address within the above-mentioned preset time length is greater than D1 and less than D2, the number of victim row addresses adjacent to the row address is 2; when the number of activations of the above-mentioned row address within the above-mentioned preset time length is greater than or equal to D2 and less than D3, the number of victim row addresses adjacent to the row address is 4; when the number of activations of the above-mentioned row address within the above-mentioned preset time length is greater than or equal to D3, the number of victim row addresses adjacent to the row address is 6, then the following 3 counting intervals can be determined: (D1, D2), [D2, D3) and [D3, ∞).

[0105] The refresh method provided in the embodiment of the present disclosure determines the above-mentioned multiple counting intervals by determining the number of victim row addresses adjacent to the row address when the row address is activated different times within a preset time length. Compared with the method of using a single threshold in the related art, it can help to resist multi-address same-frequency attacks.

[0106] In some embodiments of the present disclosure, the above-mentioned multiple counting intervals may also be predetermined in the following manner:

[0107] Acquire process parameters of the memory and determine the plurality of counting intervals based on the process parameters, wherein the process parameters include the capacitance of capacitors in each memory cell of the memory and / or the distance between adjacent word lines in the memory.

[0108] It is understandable that the closer the distance between adjacent word lines, the more likely it is to cause leakage in capacitors at adjacent addresses; and the smaller the capacitance of the capacitor in the memory cell, the more likely the memory cell will lose data due to capacitor charge loss. Therefore, the memory process parameters can be used to set multiple counting intervals for the memory. For example, assuming the memory is set with three counting intervals (D1, D2), [D2, D3), and [D3, ∞), the closer the distance between adjacent word lines and the smaller the capacitance of the capacitor in the memory cell, the smaller the values ​​of D1, D2, and D3.

[0109] In other implementations, the plurality of counting intervals may also be determined based on a ratio between a process parameter of the memory and a default parameter, and a hammering condition corresponding to the default parameter, such as a counting interval setting condition.

[0110] The refresh method provided in the embodiment of the present disclosure determines the above-mentioned multiple counting intervals according to the process parameters of the memory. Compared with the method of using a single threshold in the related art, it can help to resist multi-address same-frequency attacks.

[0111] In some embodiments of the present disclosure, the memory includes multiple word lines, including edge word lines and non-edge word lines; wherein the edge word line is at least one word line located at an edge position among the multiple word lines, and the non-edge word line is a word line among the multiple word lines other than the edge word line. In some implementations, the multiple counting intervals can also be predetermined in the following manner:

[0112] A plurality of first counting intervals corresponding to edge word lines and a plurality of second counting intervals corresponding to non-edge word lines are determined, wherein the first counting intervals and the second counting intervals corresponding to the same range of victim row addresses do not completely overlap.

[0113] In some embodiments, the first counting interval and the second counting interval corresponding to the same range of victim row addresses may not completely overlap and may intersect, but may not completely overlap, that is, the left endpoints or the right endpoints of the two intervals may not be exactly the same.

[0114] It is understandable that edge word lines and non-edge word lines are distributed differently in the memory and therefore experience different row hammering effects. For example, edge word lines are more susceptible to row hammering than non-edge word lines.

[0115] Optionally, in some implementations, the minimum value of the first counting interval corresponding to the same range of victim row addresses is smaller than the minimum value of the second counting interval.

[0116] In some embodiments, when the activation count value of the currently activated row address of the memory within a preset time length is obtained, it is first determined whether the currently activated row address belongs to an edge word line or a non-edge word line. If the currently activated row address is the row address corresponding to the edge word line, it is determined whether the above activation count value belongs to any one of the above multiple first counting intervals. If so, it is determined whether the preset queue is full. If not, the above activation count value is increased by 1; if the currently activated row address is the row address corresponding to the non-edge word line, it is determined whether the above activation count value belongs to any one of the above multiple second counting intervals. If so, it is determined whether the preset queue is full. If not, the above activation count value is increased by 1.

[0117] The refresh method provided in the embodiment of the present disclosure can help edge word lines and non-edge word lines resist multi-address same-frequency attacks by setting differentiated multiple counting intervals for edge word lines and non-edge word lines respectively.

[0118] In some embodiments of the present disclosure, when obtaining the activation count value of the currently activated row address of the memory within a preset time length, if the activation count value belongs to any counting interval of multiple counting intervals that exceed the row hammer threshold, it is determined whether the preset queue is full; when the queue is full, it can be determined whether the target counting interval to which the above-mentioned activation count value belongs is the counting interval with the largest count value among the above-mentioned multiple counting intervals; if the above-mentioned target counting interval is not the counting interval with the largest count value, the activation count value is increased by 1; if the target counting interval is the counting interval with the largest count value, a queue overflow alarm message is output.

[0119] For example, taking the above-mentioned multiple counting intervals as (D1, D2), [D2, D3), [D3, ∞) as an example, when the above-mentioned queue is full, if the target counting interval to which the above-mentioned activation count value belongs is (D1, D2) or [D2, D3), the above-mentioned activation count value in the corresponding activation command counter can be increased by 1, and the activation count value of the above-mentioned row address can continue to be counted; if the target counting interval to which the above-mentioned activation count value belongs is [D3, ∞), the queue overflow alarm information is output.

[0120] In some implementations, a controller corresponding to the memory may receive the alarm information, identify the currently received memory access instruction (read / write instruction) as a malicious attack instruction, and perform a shielding action.

[0121] It can be understood that when the above-mentioned queue is full, if the target counting interval to which the above-mentioned activation count value belongs is not the counting interval with the largest count value among the above-mentioned multiple counting intervals, it can be considered that although the above-mentioned row address is subjected to row hammering, the range of the damaged row address is small. In this case, the above-mentioned activation count value can be increased by 1, and the activation count value of the above-mentioned row address can be continued to be counted. When the above-mentioned queue is not full, the above-mentioned row address can be placed in the above-mentioned queue; if the target counting interval to which the above-mentioned activation count value belongs is the counting interval with the largest count value, it can be considered that the above-mentioned row address is subjected to severe row hammering, and the range of the damaged row address is large, so the alarm information can be overflowed in time for the storage controller used to control the memory to perform adaptive processing or for other modules inside the memory used to avoid attacks to perform adaptive actions.

[0122] In some embodiments, reference may be made to Figure 2 The memory may include a selector and a row decoder. When the activation count value falls within any one of the plurality of count intervals, if the queue is not full, the row address output by the selector is obtained and placed into the queue as the attack row address.

[0123] It is understandable that the selector can send each row address it outputs to the queue. However, during memory operation, the queue will only directly record the currently received row address if the activation count value of the currently activated row address within a preset time period belongs to any of the multiple count intervals that exceed the row hammer threshold, and the queue is not full. In this way, there is no need to rely on other circuits to obtain the row address, thereby simplifying the memory refresh circuit and reducing the memory layout area. In some embodiments, the row address output by the selector can be latched on a certain path.

[0124] In some embodiments, when the above-mentioned queue is not full, the attack row address can be placed in the queue, and a refresh range identifier can be added to the above-mentioned attack row address based on the target counting interval to which the above-mentioned activation count value belongs and the range of victim row addresses corresponding to each counting interval. The refresh range identifier is used to indicate that the 2n victim row addresses adjacent to the above-mentioned attack row address need to perform a refresh operation; wherein n is a positive integer, and the value of n is related to the above-mentioned target counting interval.

[0125] In some embodiments, the 2n victim row addresses include n first victim row addresses and n second victim row addresses; wherein the n first victim row addresses are located on one side of the attack row address, and the n second victim row addresses are located on the other side of the attack row address.

[0126] In some implementations, the victim row address generation module may generate a victim row address corresponding to the attacking row address based on the attacking row address in the queue and the refresh range identifier corresponding to the attacking row address.

[0127] Reference Figure 5 , Figure 5 The figure is a flowchart of the steps of a refresh method provided in an embodiment of the present disclosure.

[0128] In some embodiments, according to the different influence ranges of different activation times on adjacent word lines, three thresholds are set, namely D1, D2, and D3, where D3>D2>D1.

[0129] When the row address j is activated, the activation count value of the AC corresponding to the row address j within the preset time period is obtained.

[0130] Determine whether the AC count value is greater than or equal to D3. If so, determine whether the queue is full. If less than D3, determine whether the AC count value is greater than or equal to D2. If the queue is full, output a queue overflow alarm. If the queue is not full, add row address j to the queue and set flag 3, indicating that the range of victim row addresses corresponding to this row address is "±1, ±2, ±3."

[0131] Furthermore, if the AC count value is less than D3 and greater than or equal to D2, the queue is determined to be full. If the AC count value is less than D2, the queue is determined to be greater than or equal to D1. If the queue is full, the AC count value is incremented by 1. If the queue is not full, row address j is placed in the queue and flag 2 is set, indicating that the range of the victim row address corresponding to this row address is "±1, ±2".

[0132] Furthermore, if the AC count value is less than D2 and greater than or equal to D1, it is determined whether the queue is full. If the AC count value is less than D1, the AC count value is increased by 1. If the result is that the queue is full, the AC count value is increased by 1. If the result is that the queue is not full, the row address j is placed in the queue and the flag 1 is set, indicating that the range of the victim row address corresponding to the row address is "±1".

[0133] In some embodiments, after the row address is stored in the queue, the AC corresponding to row address j is cleared. It is understandable that if the AC count value of a row address reaches a specified threshold after the selector outputs the row address, it can be known that the row address whose AC count value reaches the specified threshold is the row address output by the selector. Therefore, the row address sent to the queue by the selector can be directly written into the queue. At the same time, since the victim row address corresponding to the attack row address written into the queue will be refreshed later to eliminate the impact of the row hammer effect, the AC count value of the attack row address written into the queue needs to be cleared.

[0134] It is understood that the number of levels of the above thresholds varies depending on the memory process. In some embodiments, the number of levels of the above thresholds may be greater than Figure 5 The level 3 in the figure may also be less than level 3, which will not be listed one by one in the embodiments of the present disclosure.

[0135] Based on the contents described in the above embodiments, a refreshing device is also provided in the embodiment of the present disclosure. Figure 6 , Figure 6 Schematic diagram of a program module of a refresh device provided in an embodiment of the present disclosure. In some embodiments, the refresh device 60 includes:

[0136] The acquisition module 601 is configured to acquire an activation count value of a row address currently activated by the memory within a preset time period.

[0137] Determination module 602 is used to determine whether a preset queue is full if the activation count value belongs to any counting interval of multiple counting intervals that exceed the row hammer threshold; wherein the queue is used to store the row address that needs to perform the row hammer refresh operation, and there is no intersection between the multiple counting intervals.

[0138] Processing module 603 is used to put the row address into the queue when the queue is not full, and determine the range of the victim row address corresponding to the row address and refresh the victim row address based on the target counting interval to which the activation count value belongs; when the queue is full, perform one of the preset operations, and the preset operation includes adding 1 to the activation count value.

[0139] The refresh device provided in the embodiment of the present disclosure can prevent the activation count values ​​of multiple row addresses from reaching the counting threshold at the same time by setting multiple counting intervals, thereby effectively resisting multi-address same-frequency attacks; at the same time, according to the counting interval in which the activation count value of the row address is located, the range of the victim row address corresponding to the row address is determined and the victim row address is refreshed, thereby preventing the situation where some victim row addresses cannot be refreshed in time, further ensuring the stability of the memory.

[0140] In some embodiments, the above device further comprises a pre-processing module for:

[0141] Determine the multiple counting intervals; wherein, when the number of activations of the row address within the preset time period belongs to different counting intervals, the ranges of victim row addresses corresponding to the row address are different.

[0142] In some embodiments, the preprocessing module is used to:

[0143] determining the number of victim row addresses adjacent to the row address when the row address is activated for different times within the preset time period;

[0144] The multiple counting intervals are determined according to a range of activation times of the row address within the preset time period when the number of victim row addresses adjacent to the row address is multiple preset values.

[0145] In some embodiments, the preprocessing module is used to:

[0146] Acquiring process parameters of the memory, wherein the process parameters include the capacity of a capacitor in each memory cell of the memory and / or the distance between adjacent word lines in the memory;

[0147] The plurality of counting intervals are determined according to the process parameters.

[0148] In some implementations, the processing module 603 is further configured to:

[0149] According to the target counting interval to which the activation count value belongs and the range of victim row addresses corresponding to each counting interval, a refresh range identifier is added to the row address, and the refresh range identifier is used to indicate that the 2n victim row addresses adjacent to the row address need to perform a refresh operation; n is a positive integer, and the value of n is related to the target counting interval.

[0150] In some embodiments, the memory includes a plurality of word lines, the plurality of word lines including edge word lines and non-edge word lines; the edge word line is at least one word line located at an edge position among the plurality of word lines, and the non-edge word line is a word line among the plurality of word lines excluding the edge word line; the pre-processing module is configured to:

[0151] determining a plurality of first counting intervals corresponding to the edge word lines and a plurality of second counting intervals corresponding to the non-edge word lines;

[0152] The first counting interval and the second counting interval corresponding to the same range of victim row addresses do not completely overlap.

[0153] In some embodiments, the processing module 603 is configured to:

[0154] Determining whether the target counting interval is a counting interval with a maximum count value;

[0155] If the target counting interval is not the counting interval with the largest counting value, the activation counting value is increased by 1;

[0156] If the target counting interval is the counting interval with the largest count value, the queue overflow alarm information is output.

[0157] In some embodiments, the memory includes a selector and a row decoder; the selector is configured to output a victim row address or an activated row address to the row decoder;

[0158] The processing module 603 is configured to:

[0159] The row address output by the selector is obtained, and the obtained row address is placed in the queue.

[0160] It should be noted that the specific execution contents of the acquisition module 601, the determination module 602 and the processing module 603 in the embodiment of the present disclosure can refer to the relevant contents in the above method embodiment, which will not be repeated here.

[0161] It should be understood that the functional modules in the various embodiments of the present disclosure may be integrated into a single processing unit, each module may exist physically separately, or two or more modules may be integrated into a single unit. The aforementioned modules may be implemented in the form of hardware or hardware plus software functional units.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A refreshing method, characterized in that: The method comprises: Obtaining the activation count value of the currently activated row address of the memory within a preset time length; If the activation count value belongs to any one of a plurality of count intervals that exceeds a row hammer threshold, determining whether a preset queue is full; wherein the queue is used to store row addresses for which a row hammer refresh operation is to be performed, and the plurality of count intervals have no intersection; When the queue is not full, the row address is placed in the queue, and according to the target counting interval to which the activation count value belongs, a range of victim row addresses corresponding to the row address is determined and the victim row address is refreshed; When the queue is full, one of the preset operations is performed, wherein the preset operation includes increasing the activation count by 1.

2. The method according to claim 1, characterized in that The method further comprises: determining the plurality of counting intervals; When the number of activations of the row address within the preset time period belongs to different counting intervals, the ranges of victim row addresses corresponding to the row address are different.

3. The method according to claim 2, characterized in that The determining of the plurality of counting intervals includes: determining the number of victim row addresses adjacent to the row address when the row address is activated for different times within the preset time period; The multiple counting intervals are determined according to a range of activation times of the row address within the preset time period when the number of victim row addresses adjacent to the row address is multiple preset values.

4. The method according to claim 2, characterized in that The determining of the plurality of counting intervals includes: Acquiring process parameters of the memory, wherein the process parameters include the capacity of a capacitor in each memory cell of the memory and / or the distance between adjacent word lines in the memory; The plurality of counting intervals are determined according to the process parameters.

5. The method according to claim 2, characterized in that The method further comprises: According to the target counting interval to which the activation count value belongs and the range of victim row addresses corresponding to each counting interval, a refresh range identifier is added to the row address, and the refresh range identifier is used to indicate that the 2n victim row addresses adjacent to the row address need to perform a refresh operation; n is a positive integer, and the value of n is related to the target counting interval.

6. The method according to claim 2, characterized in that The memory includes a plurality of word lines, wherein the plurality of word lines include edge word lines and non-edge word lines; The edge word line is at least one word line located at an edge position among the plurality of word lines, and the non-edge word line is a word line among the plurality of word lines except the edge word line; The determining of the plurality of counting intervals includes: determining a plurality of first counting intervals corresponding to the edge word lines and a plurality of second counting intervals corresponding to the non-edge word lines; The first counting interval and the second counting interval corresponding to the same range of victim row addresses do not completely overlap.

7. The method according to claim 1, characterized in that The performing of the preset operation includes: Determining whether the target counting interval is a counting interval with a maximum count value; If the target counting interval is not the counting interval with the largest counting value, the activation counting value is increased by 1; If the target counting interval is the counting interval with the largest count value, the queue overflow alarm information is output.

8. The method according to claim 1, characterized in that The memory includes a selector and a row decoder; the selector is used to output a victim row address or an activated row address to the row decoder; Putting the row address into the queue comprises: The row address output by the selector is obtained, and the obtained row address is placed in the queue.

9. A refreshing device, characterized in that: The device comprises: An acquisition module is used to obtain an activation count value of a row address currently activated in the memory within a preset time period; a determination module configured to determine whether a preset queue is full if the activation count value belongs to any one of a plurality of count intervals that exceeds a row hammer threshold, wherein the queue is configured to store row addresses for which a row hammer refresh operation is to be performed, and the plurality of count intervals have no intersection; A processing module is used to place the row address into the queue when the queue is not full, and determine the range of the victim row address corresponding to the row address and refresh the victim row address based on the target counting interval to which the activation count value belongs; when the queue is full, perform one of the preset operations, and the preset operation includes adding 1 to the activation count value.

10. The device according to claim 9, characterized in that The device further comprises a pre-processing module, configured to: determining the plurality of counting intervals; When the number of activations of the row address within the preset time period belongs to different counting intervals, the ranges of victim row addresses corresponding to the row address are different.

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