Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are disclosed. A memory device may include a plurality of memory cells, each memory cell including a cell transistor having a back gate shared with an adjacent cell transistor of an adjacent memory cell through a back gate line, a top gate connected to a corresponding word line, and a cell capacitor connected to a first electrode of the cell transistor; a sub word line driver configured to apply a word line driving voltage to the selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to the second electrodes of the cell transistors of the plurality of memory cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0136219 filed in the Korean Intellectual Property Office on October 12, 2023, the entire contents of which are incorporated herein by reference. Background Art

[0003] The present disclosure relates to electronic devices, and more particularly, to a memory device that controls or is configured to control a back gate voltage applied to a back gate in an active period, and a method of operating the memory device.

[0004] Semiconductor memory is widely used to store data in various electronic devices such as computers, wireless communication devices, etc. One type of semiconductor memory, dynamic random access memory (DRAM), writes and reads data by using the charge stored in the cell capacitor of the memory cell. In DRAM, an array of memory cells is connected to bit lines and word lines. The bit lines can be connected to sense amplifiers, and the word lines can be connected to word line driver circuits. Summary of the invention

[0005] The present disclosure provides a memory device configured to adjust a voltage level of a voltage applied to a back gate line corresponding to an enabled word line and a method of operating the memory device.

[0006] According to some aspects of the present inventive concept, there is provided a memory device including a plurality of memory cells, each memory cell including a cell transistor having a back gate shared with an adjacent cell transistor of an adjacent memory cell and connected to a back gate line, a forward gate connected to a word line, and a cell capacitor connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line drive voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to a back gate line corresponding to the selected word line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through a bit line connected to the second electrode of the cell transistor.

[0007] According to some aspects of the present invention, there is provided a memory device, including a cell array structure, the cell array structure including a plurality of word lines, a plurality of bit lines, a plurality of back gate lines and a plurality of memory cells, each memory cell sharing a back gate line with an adjacent memory cell through a back gate line connected thereto; and a peripheral circuit structure, the peripheral circuit structure including a peripheral circuit, the peripheral circuit structure being configured to apply a word line drive voltage to a selected word line among the plurality of word lines, being configured to apply a back gate voltage to a back gate line connected to a memory cell connected to the selected word line, and being configured to sense data through at least one selected bit line among the plurality of bit lines, the peripheral circuit structure vertically overlapping at least a portion of the cell array structure. The peripheral circuit can be configured to change a voltage level of a back gate voltage from a first voltage level to a second voltage level during an active period in which the selected word line is enabled.

[0008] According to some aspects of the present invention, there is provided a method for operating a memory device, the method comprising: applying a first word line drive voltage of a first drive voltage level to a plurality of word lines during a first precharge period; applying a first back gate voltage of a first voltage level to a plurality of back gate lines during the first precharge period; applying a second word line drive voltage of a second drive voltage level higher than the first drive voltage level to a selected word line among the plurality of word lines during an active period after the first precharge period; and applying a second back gate voltage of a second voltage level lower than the first voltage level to a back gate line of a memory cell among the plurality of back gate lines corresponding to the selected word line and connected to a shared back gate during the active period. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present inventive concept and some examples of its embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a memory device according to some embodiments;

[0011] Figure 2 is a diagram schematically illustrating a structure of a memory device according to some embodiments;

[0012] Figure 3 is a circuit diagram of a memory cell array according to some embodiments;

[0013] Figure 4 is a diagram for explaining a parasitic capacitor included in a memory cell array according to some embodiments;

[0014] Figure 5 is a circuit diagram of a sense amplifier according to some embodiments;

[0015] Figure 6is a timing diagram of voltages applied to word lines, bit lines, and back gate lines according to some embodiments;

[0016] Figure 7 is a circuit diagram of a sense amplifier according to some embodiments;

[0017] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a timing diagram of voltages applied to word lines, bit lines, and back gate lines according to some embodiments;

[0018] Fig.12 is a timing diagram for explaining a word line driving voltage applied to each of a selected word line and adjacent word lines according to some embodiments;

[0019] Fig.13 is a timing diagram for explaining an enabled word line driving voltage according to some embodiments;

[0020] Fig.14 is a diagram for explaining a back gate driver according to some embodiments;

[0021] Fig.15 It is schematically shown Fig.14 A diagram showing the structure of a back gate driver;

[0022] Fig.16 is a diagram for explaining a back gate driver according to some embodiments;

[0023] Fig.17 It is schematically shown Fig.16 A diagram showing the structure of a back gate driver;

[0024] Fig.18 is a diagram for explaining a back gate driver according to some embodiments;

[0025] Fig.19 It is schematically shown Fig.18 A diagram showing the structure of a back gate driver;

[0026] Fig. 20 is a graph showing current according to back gate voltage according to some embodiments;

[0027] Fig.21 is a flow chart illustrating a method of operating a memory device according to some embodiments;

[0028] Fig. 22 is a flow chart illustrating a method of operating a memory device according to some embodiments;

[0029] Fig.23 is a flow chart illustrating a method of operating a memory device according to some embodiments;

[0030] Fig.24 is a diagram illustrating a layout of an integrated circuit device according to some embodiments;

[0031] Fig.25 It is along Fig.24 A cross-sectional view taken along the lines X1-X1' and Y1-Y1';

[0032] Fig.26 is a layout diagram illustrating an integrated circuit device according to some embodiments;

[0033] Fig. 27 It is along Fig.26 A cross-sectional view taken along line X2-X2'; and

[0034] Fig.28 It is along Fig.26 A cross-sectional view taken along line Y2-Y2'. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a block diagram of a memory device 100 according to some embodiments.

[0037] refer to Figure 1 , the memory device 100 may correspond to, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0038] The memory device 100 may include a memory cell array 110 and a peripheral circuit 111 .

[0039] The memory cell array 110 may include a plurality of memory cells arranged in rows and columns.

[0040] The peripheral circuit 111 may include a row decoder 120, a sub-word line driver (SWD) 121, a back gate driver (BGD) 122, a sense amplifier 123, a column decoder 124, a refresh control circuit 125, a command decoder 126, a mode register set / extended mode register set (MRS / EMRS) circuit 127, an address buffer 128 and a data input / output circuit 129.

[0041] The row decoder 120 can decode the row address of the address signal ADD output from the address buffer 128, and can specify the word line connected to the memory cell, where the data DQ is to be input or output. That is, in the data write mode or the data read mode, the row decoder 120 can select the corresponding word line (which may be referred to as the selected word line herein) by decoding the row address output from the address buffer 128. In addition, in the self-refresh mode, the row decoder 120 can select the corresponding word line by decoding the row address generated from the address counter (not shown) of the command decoder 126, which will be discussed in more detail herein.

[0042] The sub-word line driver 121 may apply a word line drive voltage to the selected word line. The voltage level of the word line drive voltage may vary depending on the operation period. For example, the operation period may include a precharge period and an active period. The precharge period may be a period in which the memory device 100 performs a precharge operation in response to a precharge command. The active period may be a period in which the memory device 100 performs various operations in response to an active command. Various operations in the active period may include, for example, charge sharing operations, sensing operations, recovery operations, etc. For example, during the precharge period, the voltage level of the word line drive voltage applied to a specific (selected) word line may be a first voltage level, and during the active period, the voltage level of the word line drive voltage applied to a specific (selected) word line may be a second voltage level. The word line selected in the active period may be referred to as an enabled word line in this article.

[0043] In some embodiments, the sub-word line driver 121 may apply a first word line driving voltage to the selected word line during the active period, and may apply a second word line driving voltage to at least one adjacent word line during the active period. The at least one adjacent word line may be or may include a word line adjacent to the selected word line.

[0044] The back gate driver 122 can apply a back gate voltage to the back gate line. During the precharge period, the back gate driver 122 can apply a back gate voltage of a first voltage level to the back gate line. In the active period, the back gate driver 122 can change the back gate voltage from a first level to a second level. For each memory device 100, the second level to which the back gate voltage changes in the active period can be set differently. The back gate driver 122 can be implemented as a regulator, such as a low voltage difference (LDO) regulator.

[0045] As used herein, reference to an event occurring during or within a period (e.g., an event occurring "during an active period" or "in a precharge period") may be used to refer to an event occurring at any point included in the period. For example, stating that an event occurs during or in a particular period may be used to refer to an event occurring at any point from the beginning of the particular period to the end of the particular period.

[0046] In some embodiments, the back gate driver 122 may restore or change the back gate voltage from the second level back to the first level during the active period.

[0047] In some other embodiments, the back gate driver 122 may restore or change the back gate voltage from the second level back to the first level in a precharge period after the active period.

[0048] The sense amplifier 123 may sense the data of the memory cells of the memory cell array 110 through the bit lines. The sense amplifier 123 may sense and amplify the data DQ of the memory cells. The sense amplifier 123 may store the data DQ received from the outside of the memory device 100 in the memory cells, and may be or may include a write driver, but the present disclosure is not limited thereto. The sense amplifier 123 may be implemented as a cross-coupled amplifier connected between the bit lines and the complementary bit lines (bit line bars) included in the memory cell array 110. The precharge operation, the charge sharing operation, the sensing operation, and / or the recovery operation may be performed sequentially so that the sense amplifier 123 senses the data DQ stored in the memory cells.

[0049] The column decoder 124 may decode the column address in the address signal ADD output from the address buffer 128 to specify the bit line connected to the memory cell through which the data DQ is to be input or output. The memory cell array 110 may output data from the memory cell specified by the row address and the column address, or write data to the memory cell.

[0050] The refresh control circuit 125 may control a self-refresh operation of the memory device 100 in response to a command output from the command decoder 126 .

[0051] As a non-limiting example, the command decoder 126 may include an address counter, a timer, and a core voltage generator. The address counter may generate a row address, which may be a self-refresh target, in response to a self-refresh input command output from the command decoder 126, and may apply the generated row address to the row decoder 120. The address counter may stop the counting operation in response to a self-refresh end command output from the command decoder 126.

[0052] The command decoder 126 may receive a command signal CMD applied from outside the memory device 100 , decode the command signal CMD, and internally generate a decoded command signal, such as a self refresh entry command or a self refresh exit command.

[0053] The MRS / EMRS circuit 127 may set an internal mode register in response to an MRS / EMRS command and an address signal ADD, which may specify an operating mode of the memory device 100. The MRS / EMRS circuit 127 may be programmed to set operating parameters, options, various functions, features, and modes of the memory device 100. The MRS / EMRS circuit 127 may store a parameter code, which may include a bit value (e.g., an appropriate bit value) provided by a command / address CA bus of a memory bus when an MRS command is issued from a memory controller coupled to the memory device 100.

[0054] For example, the MRS / EMRS circuit 127 can be used to control burst length, read / write latency, dynamic voltage, frequency scaling mode, etc. The burst length can be provided to set the maximum number of column locations accessible by a read and / or write command. The read / write latency can be provided to define the clock cycle delay between a read and / or write command and the first bit of valid output and / or input data.

[0055] The data DQ input through the data input / output circuit 129 can be written to the memory cell array 110 based on the address signal ADD, and the data DQ read from the memory cell array 110 based on the address signal ADD can be output to the outside of the memory device 100 through the data input / output circuit 129. The address signal ADD can be input to the address buffer 128 to specify the memory cell through which data is to be written or read. The address buffer 128 can temporarily store the address signal ADD input from outside the memory device 100.

[0056] The memory device 100 may also include a clock circuit configured to generate a clock signal, a voltage detection circuit configured to detect a voltage level of a power generation circuit used to generate or distribute an internal voltage by receiving a power supply voltage applied from outside the memory device 100, and a control circuit configured to control the operation of the peripheral circuit 111.

[0057] According to some embodiments, there can be an effect of reducing leakage current that may occur in a memory cell, an effect of improving the refresh characteristics of the memory device 100 according to the reduced leakage current, and an effect of improving the reliability of the memory device 100 by adjusting the voltage level of the voltage applied to the back gate line in response to an enabled word line or a selected word line.

[0058] Figure 2is a diagram schematically illustrating a structure of a memory device 100 according to some embodiments.

[0059] refer to Figure 2 , the memory device 100 may include a cell array structure CAS and a peripheral circuit structure PCS. The cell array structure CAS may be on top of the peripheral circuit structure PCS in a vertical direction (e.g., Z direction). That is, the peripheral circuit structure PCS may be covered below the cell array structure CAS in a direction perpendicular to the horizontal extension direction (e.g., X direction and Y direction) of the cell array structure CAS. In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS may be bonded to each other in a vertical direction (e.g., Z direction) through a pad. The bonding method may be, for example, bonding between a copper (Cu) pad and a copper (Cu) pad, but the present disclosure is not limited thereto.

[0060] The cell array structure CAS may include Figure 1 The memory cell array 110 of the present invention can include a plurality of word lines WL, a plurality of bit lines BL and a plurality of back gate lines BGL connected to a plurality of memory cells MC. For example, a plurality of bit lines BL can extend in a first direction (e.g., Y direction) and can be arranged side by side in a second direction (e.g., X direction). Each of the plurality of word lines WL and the plurality of back gate lines BGL can extend in a second direction (e.g., X direction) and can be arranged parallel to each other in a first direction (e.g., Y direction). Each memory cell MC can be connected to a bit line BL in a plurality of bit lines BL, a word line WL in a plurality of word lines WL and a back gate line BGL in a plurality of back gate lines BGL. Each memory cell MC can include a cell transistor and a cell capacitor. In some embodiments, the cell transistor of each memory cell MC can include a top gate connected to the corresponding word line WL and a back gate connected to the corresponding back gate line BGL. Each memory cell MC can share a back gate with an adjacent memory cell through a back gate line BGL.

[0061] The peripheral circuit structure PCS may include Figure 1 The peripheral circuit 111 may be configured to apply a word line driving voltage to a word line (e.g., WL) selected from a plurality of word lines. The peripheral circuit 111 may be configured to apply a back gate voltage to a back gate line (e.g., BGL) connected to a memory cell (e.g., MC) connected to the selected word line (e.g., WL). The peripheral circuit 111 may be configured to sense data through at least one bit line (e.g., BL) selected from a plurality of bit lines.

[0062] Because the memory device 100 according to some embodiments may include a stacked cell array structure CAS and a peripheral circuit structure PCS, a word line may not be interrupted by a circuit configuration other than a memory cell in the cell array structure CAS and may extend in the cell array structure CAS.

[0063] Figure 3 is a circuit diagram of a memory cell array according to some embodiments.

[0064] refer to Figure 2 and Figure 3 , the memory cell array 110 may include a plurality of word lines, a plurality of bit lines, a plurality of back gate lines, and a plurality of memory cells. Figure 3 , for example, first to eighth word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7 and WL8, first to third bit lines BL1, BL2 and BL3, first to fourth back gate lines BGL1, BGL2, BGL3 and BGL4, and 24 memory cells are shown Figure 3 However, the word lines, bit lines, gate lines, and memory cells are not limited thereto.

[0065] Each of the plurality of memory cells may include a cell transistor CT and a cell capacitor CC. The cell transistor CT may include a plurality of electrodes, a top gate connected to a corresponding word line WL, and a back gate connected to a back gate line BGL shared with an adjacent cell transistor CT. For example, the cell transistor CT of the first memory cell MC1 may include a top gate connected to the first word line WL1, a back gate connected to the first back gate line BGL1, a first electrode of the cell capacitor CC connected to the first memory cell MC1, and a second electrode connected to the first bit line BL1. For example, the cell transistor CT of the second memory cell MC2 may include a top gate connected to the second word line WL2, a back gate connected to the first back gate line BGL1, a first electrode of the cell capacitor CC connected to the second memory cell MC2, and a second electrode connected to the first bit line BL1. For example, the cell transistor CT of the third memory cell MC3 may include a top gate connected to the third word line WL3, a back gate connected to the second back gate line BGL2, a first electrode of the cell capacitor CC connected to the third memory cell MC3, and a second electrode connected to the first bit line BL1. The cell transistor CT of the first memory cell MC1 and the cell transistor CT of the second memory cell MC2 can share a back gate through the first back gate line BGL1. The cell transistor CT of the first memory cell MC1 and the cell transistor CT of the second memory cell MC2 can be cell transistors adjacent to each other. In some embodiments, the channel of the cell transistor CT can be formed in a vertical direction (e.g., Z direction). The cell transistor CT including a channel formed in a vertical direction (e.g., Z direction) can be referred to as a vertical channel transistor. In some embodiments, the cell transistor CT can be implemented as an n-type transistor, but the present disclosure is not limited thereto. If the cell transistor CT is provided with a back gate, the floating body can be controlled, and the threshold voltage of the cell transistor CT can be more easily controlled. In addition, when adjacent cell transistors and the cell transistor CT share a back gate line, the chip size of the memory device 100 can be reduced, and the integration of the memory device 100 can be facilitated. In some embodiments, a back gate line can be shared by every two word lines. However, the present disclosure is not limited thereto.

[0066] The cell capacitor CC of each memory cell may store a charge having a capacity corresponding to unit data (e.g., bit "0" or bit "1"). According to some embodiments, the cell capacitor CC may store a charge having a capacity corresponding to multi-bit data (e.g., 2-bit data). The cell capacitor CC may be restored to an amount of charge corresponding to the capacity of the unit data or multi-bit data. The cell capacitor CC may be connected between the first electrode of the cell transistor CT and the ground. For example, the first electrode of the cell capacitor CC may be connected to the first electrode of the cell transistor CT, and the second electrode of the cell capacitor CC may be connected to the ground.

[0067] Figure 4 FIG. 1 is a diagram for explaining parasitic capacitors PC1, PC2, PC3, and PC4 included in a memory cell array according to some embodiments. For ease of explanation, the following will be described based on a first bit line BL1, a first word line WL1, a second word line WL2, a first back gate line BGL1, a second back gate line BGL2, and first to third memory cells MC1, MC2, and MC3. Figure 4 The parasitic capacitors PC1, PC2, PC3 and PC4 are shown in FIG.

[0068] refer to Figure 4 , the first memory cell MC1 and the second memory cell MC2 can be connected to the first back gate line BGL1, and the third memory cell MC3 can be connected to the second back gate line BGL2. When the second word line WL2 is selected, the second word line WL2 can be enabled. For example, a high voltage higher than the conduction level of the cell transistor CT for turning on the second memory cell MC2 connected to the second word line WL2 can be applied to the second word line WL2 as a word line drive voltage. In this case, the first word line WL1 and the third word line WL3 can be disabled. Since there is a first parasitic capacitor PC1 coupled between the first back gate line BGL1 and the second word line WL2, when the word line drive voltage is applied to the second word line WL2, the potential of the first back gate line BGL1 may generate ripples or fluctuations. When the potential of the first back gate line BGL1 fluctuates, the potential of the first electrode and the second electrode of the cell transistor CT of the first memory cell MC1 may also fluctuate, and the potential of the first word line WL1 may also fluctuate through the second parasitic capacitor PC2 and the third parasitic capacitor PC3 between the first back gate line BGL1 and the cell transistor CT of the first memory cell MC1. Therefore, since the potential of the first word line WL1 also fluctuates, the threshold voltage of the cell transistor CT of the first memory cell MC1 may change (e.g., decrease). When the threshold voltage of the cell transistor CT of the first memory cell MC1 decreases, the cell transistor CT may be turned on, and therefore, the charge stored in the cell capacitor CC of the first memory cell MC1 may leak to the first bit line BL through the turned-on cell transistor CT. That is, leakage current may occur. If leakage current occurs in the first memory cell MC1, the reliability of the data stored in the first memory cell MC1 may be reduced.

[0069] When the selected second word line WL2 is enabled, the potential of the disabled third word line WL3 may fluctuate through the fourth parasitic capacitor PC4 between the second word line WL2 and the third word line WL3. Therefore, since the potential of the third word line WL3 also fluctuates, the threshold voltage of the cell transistor CT of the third memory cell MC3 changes (e.g., decreases), and leakage current may occur at the third memory cell MC3.

[0070] In order to prevent a change in the threshold voltage of the memory cell connected to the disabled word line, adjusting the voltage applied to the back gate line corresponding to the enabled word line may be performed.

[0071] Figure 5 is a circuit diagram of a sense amplifier 123_1 according to some embodiments.

[0072] refer to Figure 5 , the sense amplifier 123_1 may include a bit line sense amplifier circuit SA and a precharge and equalize circuit EQ.

[0073] The bit line sense amplifier circuit SA may include a p-type sense amplifier PSA (including a p-type transistor) and an n-type sense amplifier NSA (including an n-type transistor).

[0074] The p-type sense amplifier PSA may include a first p-type transistor P11 and a second p-type transistor P12 connected in series between a bit line BL and a complementary bit line BLB. A first sense drive voltage line LA may be connected to the source of the first p-type transistor P11 and the second p-type transistor P12. The complementary bit line BLB may be connected to the gate of the first p-type transistor P11. The bit line BL may be connected to the gate of the second p-type transistor P12. Depending on the implementation, the sizes of the first p-type transistor P11 and the second p-type transistor P12 may be the same or different. The first sense drive voltage may be supplied through the first sense drive voltage line LA, and the first sense drive voltage of the bit line sense amplifier circuit SA may be a power supply voltage (VDD) supplied for the operation of the memory cell array 110 (or an internal voltage generated inside the memory device 100). The p-type sense amplifier PSA connected to the first sense drive voltage line LA may provide a high level of amplified voltage level during the sensing and amplification operation of the data of the memory cell MC connected to the bit line BL.

[0075] The n-type sense amplifier NSA may include a first n-type transistor N11 and a second n-type transistor N12 connected in series between a bit line BL and a complementary bit line BLB. A second sense drive voltage line LAB may be connected to the source of the first n-type transistor N11 and the second n-type transistor N12. The complementary bit line BLB may be connected to the gate of the first n-type transistor N11. The bit line BL may be connected to the gate of the second n-type transistor N12. Depending on the implementation, the sizes of the first n-type transistor N11 and the second n-type transistor N12 may be the same or different. The second sense drive voltage may be supplied by the second sense drive voltage line LAB, and the second sense drive voltage of the bit line sense amplifier circuit SA may be a second power supply voltage VSS (e.g., ground voltage) of the memory device 100. The n-type sense amplifier NSA connected to the second sense drive voltage line LAB may provide a low-level amplified voltage level during the sensing and amplification operation of the data of the memory cell MC connected to the bit line BL.

[0076] The precharge and equalization circuit EQ may equalize the bit line BL and the complementary bit line BLB to the bit line precharge voltage VEQ level in response to the equalization signal PEQ. The precharge and equalization circuit EQ may include a third n-type transistor N13 connected between the bit line precharge voltage VEQ and the bit line BL, a fourth n-type transistor N14 connected between the bit line precharge voltage VEQ and the complementary bit line BLB, and a fifth n-type transistor N15 connected between the bit line BL and the complementary bit line BLB. According to some embodiments, in addition to the fifth n-type transistor N15, the precharge and equalization circuit EQ may include one of the third n-type transistor N13 or the fourth n-type transistor N14. The gates of the third n-type transistor N13 to the fifth n-type transistor N15 may be connected to the equalization signal PEQ. The equalization signal PEQ may be provided from the control logic circuit based on a command provided to the memory device 100. The equalization signal PEQ may be applied at a logic high level during a precharge operation of the bit line sense amplifier circuit SA to turn on the first to third n-type transistors N13, N14, and N15, and may precharge the bit line BL and the complementary bit line BLB to the bit line precharge voltage VEQ level. During a sensing operation, the equalization signal PEQ may be applied at a logic low level to turn off the first to third n-type transistors N13, N14, and N15.

[0077] Figure 6 is a timing diagram of voltages applied to word lines, bit lines, and back gate lines according to some embodiments.

[0078] refer to Figure 1 , Figure 5 and Figure 6, the precharge period may be a period in which the memory device 100 performs a precharge operation in response to a precharge command. The first precharge period PCG1 may be a period corresponding to the first time t1 to the second time t2. In the first precharge period PCG1, the voltage level of the word line drive voltage applied to the word line WL may be a first drive voltage level. At this time, the word line WL may be disabled. The bit line precharge voltage VEQ may be applied to the bit line BL and the complementary bit line BLB. The potential of the bit line BL and the complementary bit line BLB may be, for example, half (VDD / 2) of the voltage level of the first power supply voltage VDD. The voltage level of the back gate voltage applied to the back gate line BGL may be a first voltage level.

[0079] The active period action may be a period in which the memory device 100 performs a charge sharing operation, a sensing operation, and a recovery operation in response to an active command. The active period ACT may include a charge sharing period CS and a sensing period and a recovery period S&R. The active period ACT may be a period corresponding to the second time t2 to the fourth time t4. The charge sharing period CS may be a period from the second time t2 to the third time t3. The sensing period and the recovery period S&R may be a period corresponding to the third time t3 to the fourth time t4. At the second time t2, a word line drive voltage of a second drive voltage level may be applied to the word line WL. In this case, the potential of the word line WL rises, and the word line WL may be enabled. The potential of one of the bit line BL and the complementary bit line BLB may rise, while the potential of the other of the bit line BL and the complementary bit line BLB may drop. In some embodiments, the voltage level of the back gate voltage applied to the back gate line BGL within the charge sharing period CS may be changed from a first voltage level to a second voltage level. For example, the first voltage level may be higher than the second voltage level. Reference Figure 6, for example, the voltage level of the back gate voltage can be reduced from the first voltage level to the second voltage level from the second time t2. However, the time when the voltage level of the back gate voltage starts to decrease (for example, the second time t2) is not limited thereto, and the voltage level of the back gate voltage can be reduced from the first voltage level to the second voltage level from any time between the second time t2 and the third time t3. At the third time t3, the potential of each of the bit line BL and the complementary bit line BLB can further rise or fall. In some embodiments, the voltage level of the back gate voltage applied to the back gate line BGL can return to the first voltage level from the second voltage level within the sensing period and the recovery period S&R. For example, starting from any time between the third time t3 and the fourth time t4, the voltage level of the back gate voltage can be increased from the second voltage level to the first voltage level. However, the time when the voltage level of the back gate voltage starts to increase (for example, any time between the third time t3 and the fourth time t4) is not limited thereto, and in some other embodiments, the voltage level of the back gate voltage can be changed from the second voltage level to the first voltage level within the second precharge period PCG2 after the sensing period and the recovery period S&R. The second precharge period PCG2 may arrive after the active period ACT.

[0080] According to the above-described embodiments, the refresh characteristics of the memory device 100 may be improved by reducing the leakage current.

[0081] Figure 7 is a circuit diagram of a sense amplifier 123_2 according to some embodiments. Specifically, Figure 7 is a circuit diagram showing a bit line sense amplifier circuit and an offset cancellation circuit included in the sense amplifier 123_2.

[0082] refer to Figure 7 , the sense amplifier 123_2 may include first and second p-type transistors P11 and P12, first and second n-type transistors N11 and N12, and first and second offset cancellation transistors OCT1 and OCT2. The first and second p-type transistors P11 and P12 and the first and second n-type transistors N11 and N12 may be included in Figure 5 Although not shown, the sense amplifier 123_2 may further include Figure 5 Pre-charge and equalization circuit EQ.

[0083] The first p-type transistor P11 and the first n-type transistor N11 may be connected to each other and implemented as a first inverter. The second p-type transistor P12 and the second n-type transistor N12 may be connected to each other and implemented as a second inverter.

[0084] The first offset cancellation transistor OCT1 and the second offset cancellation transistor OCT2 may be devices for removing the offset of the threshold voltage of the first n-type transistor N11 and the second n-type transistor N12, respectively. The first offset cancellation transistor OCT1 and the second offset cancellation transistor OCT2 may operate in response to the offset cancellation signal OC. For example, the first offset cancellation transistor OCT1 and the second offset cancellation transistor OCT2 may be turned on by receiving the offset cancellation signal OC of the on level. The offset cancellation signal OC may be generated by conjunction.

[0085] A first electrode of the first offset cancellation transistor OCT1 may be connected to a bit line BL. A second electrode of the first offset cancellation transistor OCT1 may be connected to a gate electrode of the second p-type transistor P12. A first electrode of the second offset cancellation transistor OCT2 may be connected to a complementary bit line BLB. A second electrode of the second offset cancellation transistor OCT2 may be connected to a gate electrode of the first p-type transistor P11.

[0086] The active period ACT may further include an offset cancellation period. When the first offset cancellation transistor OCT1 and the second offset cancellation transistor OCT2 are turned on in the offset cancellation period, the first n-type transistor N11 and the second n-type transistor N12 may operate as diodes.

[0087] Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a timing diagram of voltages applied to word lines, bit lines, and back gate lines according to some embodiments. Figure 8 , Fig. 9 , Fig.10 and Fig.11 In the description of each of the timing diagrams of Figure 6 Same description given.

[0088] refer to Figure 8 , Fig. 9 , Fig.10 and Fig.11 The potentials of the word line WL, the bit line BL and the complementary bit line BLB are as shown in the reference Figure 6 The activity period ACT may also include an offset elimination period OC. The offset elimination period OC may be Figure 8 The period from the second time t2 to the third time t3.

[0089] The voltage level of the back gate voltage may change from the first voltage level to the second voltage level in the charge sharing period CS. In addition, the voltage level of the back gate voltage may change from the second voltage level to the first voltage level in any one of the active period ACT and the second precharge period PCG2 after the active period ACT.

[0090] refer to Figure 8 and Fig. 9 For example, within the charge sharing period CS (eg, starting from any time between the third time t3 and the fourth time t4), the voltage level of the back gate voltage may be changed from the first voltage level to the second voltage level. Figure 8 For example, during the sensing period and the recovery period S&R (eg, starting from any time between the fourth time t4 and the fifth time t5), the voltage level of the back gate voltage may be changed from the second voltage level to the first voltage level. Fig. 9 , for example, within the second precharge period PCG2 (eg, starting from the fifth time t5), the voltage level of the back gate voltage may be changed from the second voltage level to the first voltage level.

[0091] When the voltage level of the back gate voltage changes, a predetermined delay time may occur. According to the delay time, the voltage level of the back gate voltage may change from the first voltage level to the second voltage level in a period between the first precharge period PCG1 and the charge sharing period CS in which the word line WL is disabled. The period between the first precharge period PCG1 and the charge sharing period CS may be, for example, an offset cancellation period OC. The voltage level of the back gate voltage may change from the second voltage level to the first voltage level in any one of the active period ACT and the second precharge period PCG2.

[0092] refer to Fig.10 and Fig.11 For example, during the offset cancellation period OC (eg, starting from any time between the second time t2 and the third time t3), the voltage level of the back gate voltage may be changed from the first voltage level to the second voltage level. Fig.10 , for example, during the sensing period and the recovery period S&R, the voltage level of the back gate voltage may be changed from the second voltage level to the first voltage level. Fig.11 , for example, starting from a fifth time t5 included in the second precharge period PCG2 , the voltage level of the back gate voltage changes from the second voltage level to the first voltage level, and the first voltage level may be maintained until the next active period ACT.

[0093] Fig.12 is a timing diagram for explaining a word line driving voltage applied to a selected word line and each of adjacent word lines according to some embodiments.

[0094] refer to Figure 3 , Figure 4 and Fig.12 The potentials of the bit line BL and the complementary bit line BLB are as shown in the reference Figure 6 The back gate voltage applied to the back gate line BGL may be as described above. Figures 8 to 11 The described embodiments may be changed as described above.

[0095] In some embodiments, during the active period ACT in which the selected word line WLs is enabled, the voltage level of the word line driving voltage applied to the adjacent word line WLa may be reduced. For example, it may be assumed that the selected word line WLs is Figure 2 , and the adjacent word line WLa is the third word line WL3. At the time when the charge sharing period CS of the active period ACT starts, for example, at the third time t3, the potential of the second word line WL2 increases from the first driving voltage level to the second driving voltage level. In addition, at the third time t3, the voltage level of the word line driving voltage applied to the third word line WL3 may be reduced. That is, the potential of the third word line WL3 may be reduced. At the time when the sensing period and the recovery period S&R start, for example, at the fourth time t4, the voltage level of the word line driving voltage applied to the third word line WL3 may be increased. That is, the potential of the third word line WL3 may be increased. The potential of the third word line WL3 after the fourth time t4 may be the same as the potential of the third word line WL3 before the third time t3. As described above with reference to Figure 4 This can be to prevent the potential of the third word line WL3 from increasing due to the fourth parasitic capacitor PC4 when the second word line WL2 is enabled. Therefore, by preventing the threshold voltage of the adjacent memory cell connected to the disabled adjacent word line from decreasing, there can be an effect of reducing the leakage current occurring in the adjacent memory cell.

[0096] exist Fig.12 In the example, the active period ACT also includes the offset elimination period OC, but if Figure 6 As shown, the offset cancellation period OC may be omitted.

[0097] Fig.13 is a timing diagram for explaining an enabled word line driving voltage according to some embodiments.

[0098] refer to Figure 3 and Fig.13 The potentials of the bit line BL and the complementary bit line BLB are as shown in the reference Figure 6 The back gate voltage applied to the back gate line BGL may be as described above. Figures 8 to 11 The described embodiments may be changed as described above.

[0099] In some embodiments, within the active period ACT, the voltage level of the word line drive voltage may increase from the first drive voltage level to the third drive voltage level. That is, the potential of the word line WL may increase from the first drive voltage level to the third drive voltage level. The third drive voltage level may be higher than the second drive voltage level for turning on the cell transistor CT. The second drive voltage level may be a voltage level higher than the turn-on level for conduction. For example, in the first precharge period PCG1, the potential of the word line WL may be the first drive voltage level. In the charge sharing period CS, the potential of the word line WL may be the third drive voltage level. In the sensing period and the recovery period S&R, the potential of the word line WL may be a drive voltage level (e.g., the second drive voltage level) lower than the third drive voltage level. In the second precharge period PCG2, the potential of the word line WL may be the first drive voltage level. Reference Figure 4 For example, when the selected second word line WL2 is enabled, the back gate voltage applied to the first back gate line BGL1 may be reduced. This can prevent the reduction of the on-cell current generated in the memory cell connected to the enabled second word line WL2. Therefore, there is an effect of preventing the reduction of the on-cell current and reducing the leakage current.

[0100] Fig.14 is a diagram for explaining a back gate driver according to some embodiments of the present disclosure. Fig.15 It is schematically shown Fig.14 Diagram of the structure of the back gate driver.

[0101] refer to Figure 3 and Fig.14 , the sub-word line driver 121 can be connected to multiple word lines, for example, the first word line to the eighth word line WL1, WL2, WL3, WL4, WL5, WL6, WL7 and WL8. The back gate driver 122a can be implemented as a single back gate driver connected to multiple back gate lines (for example, the first back gate line to the fourth back gate line BGL1, BGL2, BGL3 and BGL4). The back gate driver 122a can apply a back gate voltage to each of the multiple back gate lines (for example, the first back gate line to the fourth back gate line BGL1, BGL2, BGL3 and BGL4). That is to say, in the active period ACT, the potentials of all back gate lines BGL can be reduced from the first voltage level to the second voltage level.

[0102] refer to Figure 2 and Fig.15, the middle area MIDDLE of the peripheral circuit structure PCS may include a command decoder, an address buffer, and a data input / output circuit. Each of the areas other than the middle area MIDDLE of the peripheral circuit structure PCS may include a row decoder R / D, a column decoder C / D, and a memory body BANK. The row decoder R / D may include a back gate driver BGD. Fig.15 The back gate driver BGD can correspond to Fig.14 The back gate driver 122a of the memory bank BANK may include one or more pads MAT. One pad MAT may include a bit line sense amplifier BLSA and a sub word line driver SWD. One pad MAT may also include a connection (conjunction, CONJ).

[0103] Fig.16 is a diagram for explaining a back gate driver according to some embodiments. Fig.17 It is schematically shown Fig.16 Diagram of the structure of the back gate driver.

[0104] refer to Figure 3 and Fig.16 , the plurality of back gate lines may include a first back gate line group and a second back gate line group. For example, the first back gate line group may include odd-numbered back gate lines, and the second back gate line group may include even-numbered back gate lines. Fig.16 , for example, odd back gate lines include the first back gate line BGL1, the third back gate line BGL3, etc., and even back gate lines include the second back gate line BGL2, the fourth back gate line BGL4, etc. The first back gate driver 122b1 can be connected to each back gate line included in the first back gate line group, for example, the first back gate line BGL1 and the third back gate line BGL3. The second back gate driver 122b2 can be connected to each back gate line included in the second back gate line group, for example, the second back gate line BGL2 and the fourth back gate line BGL4. Depending on whether the numbering of the selected word line is odd or even, the potential of the corresponding back gate line can be changed between the first voltage level and the second voltage level by the first back gate driver 122b1 or the second back gate driver 122b2.

[0105] refer to Figure 2 and Fig.17 , the peripheral circuit structure PCS can be compared with the above reference Fig.16 The peripheral circuit structure PCS described is the same. Each of the regions except the middle region MIDDLE of the peripheral circuit structure PCS may include a row decoder R / D, a column decoder C / D, and a memory bank BANK. The row decoder R / D may include a first back gate driver BGD1 and a second back gate driver BGD2. Fig.17 The first back gate driver BGD1 and the second back gate driver BGD2 may correspond to Fig.16The first back gate driver 122b1 and the second back gate driver 122b2 are configured.

[0106] Fig.18 is a diagram for explaining a back gate driver according to some embodiments. Fig.19 It is schematically shown Fig.18 Diagram of the structure of the back gate driver.

[0107] refer to Figure 3 and Fig.18 , the back gate driver group 122c may include a plurality of back gate drivers connected to each of the plurality of back gate lines respectively. For example, the first back gate driver 122c1 is connected to the first back gate line BGL1, the second back gate driver 122c2 is connected to the second back gate line BGL2, the third back gate driver 122c3 is connected to the third back gate line BGL3, and the fourth back gate driver 122c4 is connected to the fourth back gate line BGL4. According to the numbering of the selected word line, the potential of the corresponding back gate line can be changed between the first voltage level and the second voltage level in the active period ACT by the back gate driver connected to the back gate line corresponding to the selected word line.

[0108] refer to Figure 2 and Fig.19 , the peripheral circuit structure PCS is the same as the above reference Fig.16 The peripheral circuit structure PCS described is the same. Each of the regions except the middle region MIDDLE of the peripheral circuit structure PCS may include a row decoder R / D, a column decoder C / D, and a memory cell BANK. One pad MAT may include a bit line sense amplifier BLSA, a sub-word line driver SWD, a connection CONJ, and a back gate driver BGD. Fig.19 The back gate driver BGD can correspond to Fig.18 The back gate driver group 122c.

[0109] Fig. 20 is a graph showing current according to back-gate voltage according to some embodiments.

[0110] refer to Fig. 20 , the second voltage level of the back gate voltage VBG can be set differently for each memory device 100. For example, depending on the memory device, the back gate voltage VBG can be set to 2 [V], 1 [V], 0 [V], -1 [V] or -2 [V]. However, the setting of the back gate voltage VBG is not limited thereto. As the second voltage level of the back gate voltage VBG gradually decreases, the voltage level of the threshold voltage Vth can increase. In addition, as the second voltage level of the back gate voltage VBG gradually decreases, the leakage current can be reduced.

[0111] Fig.21is a flow chart illustrating a method of operating the memory device 100 according to some embodiments.

[0112] refer to Fig.21 , in operation S100 , the memory device 100 may receive a first precharge command.

[0113] In operation S110, the memory device 100 may apply a first word line driving voltage having a first driving voltage level to a plurality of word lines. For example, in the first precharge period PCG1, the first word line driving voltage having the first driving voltage level may be applied to the plurality of word lines. In another example, the first word line driving voltage having the first driving voltage level may be applied to the enabled word lines in the active period ACT after the first precharge period PCG1.

[0114] In operation S120, the memory device 100 may apply a first back gate voltage having a first voltage level to the plurality of back gate lines. For example, in the first precharge period PCG1, the first back gate voltage having a first voltage level may be applied to the plurality of back gate lines.

[0115] In operation S200 , the memory device 100 may receive an active command.

[0116] In operation S210, the memory device 100 may apply a second word line drive voltage having a second drive voltage level higher than the first drive voltage level to a word line selected from a plurality of word lines. For example, in an active period ACT after the first precharge period PCG1, a second word line drive voltage having a second drive voltage level may be applied to the selected word line (e.g., the second word line WL2).

[0117] In operation S220, the memory device 100 may apply a second back gate voltage having a second voltage level lower than the first voltage level to the back gate line BGL of the memory cell connected to the selected word line and connected to the shared back gate line BGL. For example, the second back gate voltage having the second voltage level may be applied to the back gate line (e.g., the first back gate line BGL1) of the memory cell connected to the selected word line (e.g., the second word line WL2) and connected to the shared back gate line BGL.

[0118] In some embodiments, the active period ACT may include a charge sharing period CS and a sensing period and a recovery period S&R. In operation S220, the memory device 100 may change the first back gate voltage to the second back gate voltage within the charge sharing period CS.

[0119] In some embodiments, the active period ACT may include an offset cancellation period OC, a charge sharing period CS, and a sensing period and a recovery period S&R. In operation S220, the memory device 100 may change the first back gate voltage to the second back gate voltage within the offset cancellation period.

[0120] Fig. 22 is a flow chart illustrating a method of operating the memory device 100 according to some embodiments.

[0121] refer to Fig.21 and Fig. 22 , Fig. 22 The method may further include operation S230 and operation S300.

[0122] In operation S230 after operation S220 , the memory device 100 may apply a first back gate voltage to the back gate line BGL within the active period ACT.

[0123] In operation S300 , the memory device 100 may receive a second precharge command.

[0124] Fig.23 is a flow chart illustrating a method of operating the memory device 100 according to some embodiments.

[0125] refer to Fig.21 and Fig.23 , Fig.23 The method may further include operation S300 and operation S310. Operation S300 is similar to the above reference Fig. 22 In operation S310 after operation S300 , the memory device 100 may apply a first back gate voltage to the back gate line BGL within the second precharge period PCG2 .

[0126] Fig.24 is a diagram illustrating a layout of an integrated circuit device 200 according to some embodiments. Fig.25 It is along Fig.24 A cross-sectional view taken along lines X1-X1' and Y1-Y1'.

[0127] refer to Fig.24 and Fig.25 , the integrated circuit device 200 may include a substrate 210, a plurality of first conductive lines 220, a channel layer 230, a gate electrode 240, a gate insulating layer 250, and a capacitor structure 280. The integrated circuit device 200 may include a memory device including a vertical channel transistor VCT. The vertical channel transistor VCT may refer to a structure in which a channel length of the channel layer 230 extends from the substrate 210 in a vertical direction.

[0128] The lower insulating layer 212 may be on the substrate 210, and the plurality of first conductive lines 220 may be spaced apart from each other along the first direction (X direction) and extend along the second direction (Y direction) on the lower insulating layer 212. A plurality of first insulating patterns 222 may be arranged on the lower insulating layer 212, and may be in the spaces between the plurality of first conductive lines 220 (e.g., fill the spaces between the plurality of first conductive lines 220). The plurality of first insulating patterns 222 may extend in the second direction (Y direction), and the upper surfaces of the plurality of first insulating patterns 222 may be at the same level (e.g., coplanar) as the upper surfaces of the plurality of first conductive lines 220.

[0129] The plurality of first conductive lines 220 may be used as bit lines of the integrated circuit device 200. In example embodiments, the plurality of first conductive lines 220 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines 220 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x or RuO x , or a combination of two or more thereof, but the present disclosure is not limited thereto. The plurality of first conductive lines 220 may include a single layer or multiple layers of the above materials. In some embodiments, the plurality of first conductive lines 220 may include a two-dimensional semiconductor material, such as graphene or carbon nanotubes, or a combination thereof.

[0130] The channel layer 230 may be arranged in a matrix form, wherein the channel layer 230 is spaced apart in a first direction (X direction) and a second direction (Y direction), and may be on a plurality of first conductive lines 220. The channel layer 230 may have a first width in a first direction (X direction) and a first height in a third direction (Z direction), wherein the first height may be greater than the first width. For example, the first height may be in the range of about 2 times to about 10 times the first width, but the present disclosure is not limited thereto. The bottom of the channel layer 230 is used as a first source / drain region (not shown), the upper portion of the channel layer 230 is used as a second source / drain region (not shown), and the portion of the channel layer 230 between the first source / drain region and the second source / drain region may be used as a channel region (not shown).

[0131] In example embodiments, the channel layer 230 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Siz O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O or In x Ga y O, or a combination of two or more thereof. The channel layer 230 may include a single layer or multiple layers of an oxide semiconductor. In some embodiments, the channel layer 230 may have a band gap energy greater than the band gap energy of silicon. For example, the channel layer 230 may have a band gap energy in the range of about 1.5eV to about 5.6eV. For example, when the channel layer 230 has a band gap energy in the range of about 2.0eV to about 4.0eV, the channel layer 230 may have a relatively optimal channel performance. For example, the channel layer 230 may be polycrystalline or amorphous, but the present disclosure is not limited thereto. In some embodiments, the channel layer 230 may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0132] The gate electrode 240 may extend along a first direction (X direction) on a first sidewall and a second sidewall of the channel layer 230 (e.g., along the Y direction). The gate electrode 240 may include a first sub-gate electrode 240P1 facing the first sidewall of the channel layer 230, and a second sub-gate electrode 240P2 facing the second sidewall opposite to the first sidewall of the channel layer 230. Since one channel layer 230 is between the first sub-gate electrode 240P1 and the second sub-gate electrode 240P2, the integrated circuit device 200 may have a dual-gate transistor structure. However, the present disclosure is not limited thereto, and the second sub-gate electrode 240P2 may be omitted, and only the first sub-gate electrode 240P1 facing the first sidewall of the channel layer 230 may be formed to form a single-gate transistor structure. The gate electrode 240 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrode 240 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x or RuO x , or a combination of two or more thereof, but the present disclosure is not limited thereto.

[0133] The gate insulating layer 250 may surround the sidewalls of the channel layer 230, and may be between the channel layer 230 and the gate electrode 240. For example, the entire sidewall of the channel layer 230 may be surrounded by the gate insulating layer 250, and a portion of the sidewall of the gate electrode 240 may contact the gate insulating layer 250. In some embodiments, the gate insulating layer 250 may extend in an extension direction (e.g., a first direction (X direction)) of the gate electrode 240, and among the sidewalls of the channel layer 230, only two sidewalls facing the gate electrode 240 may contact the gate insulating layer 250.

[0134] In some embodiments, the gate insulating layer 250 may include a silicon oxide film, a silicon oxynitride film, or a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination of two or more thereof. The high-k dielectric film may include a metal oxide or a metal oxynitride. For example, a high-k dielectric film that may be used as the gate insulating layer 250 or used in the gate insulating layer 250 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 or Al 2 O 3 , or a combination of two or more thereof, but the present disclosure is not limited thereto.

[0135] The plurality of second insulation patterns 232 may extend along the second direction (Y direction) on the plurality of first insulation patterns 222, and each channel layer 230 may be between two adjacent second insulation patterns 232 among the plurality of second insulation patterns 232. In addition, the first buried layer 234 and the second buried layer 236 may be in the space between the two adjacent channel layers 230 and between the two adjacent second insulation patterns 232. The first buried layer 234 may be at the bottom of the space between the two adjacent channel layers 230, and the second buried layer 236 may be formed in the remaining space on the first buried layer 234 between the two adjacent channel layers 230 (and may fill the remaining space).

[0136] The upper surface of the second buried layer 236 may be at the same level as the upper surface of the channel layer 230, and the second buried layer 236 may cover the upper surface of the gate electrode 240. In some embodiments, the plurality of second insulating patterns 232 may be formed as a continuous material layer together with the plurality of first insulating patterns 222, and / or the second buried layer 236 may be formed as a continuous material layer together with the first buried layer 234.

[0137] A plurality of capacitor contacts 260 may be on each channel layer 230. The capacitor contacts 260 may be arranged to overlap vertically with the channel layer 230, and may be arranged in a matrix form, wherein the capacitor contacts 260 are spaced apart in a first direction (X direction) and a second direction (Y direction). The capacitor contacts 260 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x or RuO x , or a combination of two or more thereof, but the present disclosure is not limited thereto. The upper insulating layer 262 may surround the sidewalls of the capacitor contact 260 on the plurality of second insulating patterns 232 and the second buried layer 236 .

[0138] An etch stop layer 270 may be on the upper insulating layer 262, and a capacitor structure 280 may be on the etch stop layer 270. The capacitor structure 280 may include a lower electrode 282, a capacitor dielectric layer 284, and an upper electrode 286.

[0139] The lower electrode 282 may penetrate or extend through the etch stop layer 270 and may be electrically connected to the upper surface of the capacitor contact 260. The lower electrode 282 may be formed into a columnar shape extending in a third direction (Z direction), but the present disclosure is not limited thereto. In some embodiments, the lower electrode 282 may be arranged to overlap vertically with the capacitor contact 260 and may be arranged in a matrix form, wherein the lower electrode 282 is spaced apart in a first direction (X direction) and a second direction (Y direction). In some embodiments, a landing pad (not shown) may be provided between the capacitor contact 260 and the lower electrode 282, and the lower electrode 282 may be arranged in a hexagonal shape.

[0140] Fig.26 is a diagram showing a layout of an integrated circuit device 300 according to some embodiments, Fig. 27 It is along Fig.26 A cross-sectional view taken along the line X2-X2', Fig.28 It is along Fig.26 A cross-sectional view taken along line Y2-Y2'.

[0141] refer to Fig.26 , Fig. 27 and Fig.28 , the integrated circuit device 300 may correspond to Figure 1 The memory device 100 of FIG. 300 may include a lower substrate 310, a first groove 320, a channel layer 331, a top gate insulating layer 332, a first insulating layer 333, a first top gate 335a and a second top gate 335b, a word line insulating layer 336, a first back gate insulating layer 337a, a second gate insulating layer 337b and a third back gate insulating layer 334, a back gate 338, a second groove 340 and an upper substrate 350. The integrated circuit device 300 may be a memory device including a vertical channel transistor.

[0142] The lower substrate 310 may be, for example, formed based on silicon. The lower substrate 310 may include a bit line 311, a barrier metal (BM) layer 312, a first polycrystalline layer (poly layer) 313, a spacer 314, and a shielding structure (shield) 315. The bit line 311, the BM layer 312, and the first polysilicon layer 313 may be stacked in sequence. The spacer 314 and the shielding structure 315 may be between the stacked structure including the bit line 311, the BM layer 312, and the first polysilicon layer 313. The spacer 314 may have a convex shape toward the upper substrate 350. The shielding structure 315 may be inside the spacer 314. The structure from the upper surface of the shielding structure 315 to the upper surface of the spacer 314 may be referred to as a bit line groove.

[0143] The first groove 320 may be a direct contact (DC) field oxide groove, and may be disposed at a constant distance from the lower substrate 310 toward the upper substrate 350 .

[0144] The channel layer 331 may be a vertical channel of a vertical channel transistor. The channel layer 331 may include an oxide semiconductor, and may include a single layer or multiple layers of an oxide semiconductor. For example, the channel layer 331 may be polycrystalline or amorphous, but the present disclosure is not limited thereto. The top gate insulating layer 332 may correspond to the gate insulating layer 250. The first insulating layer 333 may be on the top gate insulating layer 332. The first top gate 335a and the second top gate 335b may correspond to the first gate electrode 240P1 and the second sub-gate electrode 240P2. The word line insulating layer 336 may be between the first top gate 335a and the second top gate 335b. The first back gate insulating layer 337a and the second back gate insulating layer 337b may be formed on the back gate 338 and may surround the back gate 338. The third back gate insulating layer 334 may be formed on another back gate (not shown), and may surround the other back gate (not shown) together with the fourth back gate insulating layer (not shown). The back gate 338 may be provided in the vertical channel transistor and may be shared by adjacent vertical channel transistors.

[0145] The second groove 340 may be a buried contact (BC) field oxide groove, and may be formed from the first insulating layer 333 to the upper substrate 350 .

[0146] The upper substrate 350 includes a second polycrystalline layer 351, a second insulating layer 352, a buried contact (BC) layer 353, a metal silicide layer 354, a metal layer 355, and a third insulating layer 356. The second polycrystalline layer 351 may be a layer composed of a graded doped polycrystalline (poly), and may be on the second groove 340 and the channel layer 331. The second insulating layer 352 may be between the second polycrystalline layers 351. The BC layer 353 may be on the second polycrystalline layer 351. The metal silicide layer 354 may be on the BC layer 353, and may include, for example, cobalt silicide (CoSi x ). The metal layer 355 may be formed by mixing BM and other metals, and may be on the metal silicide layer 354. A third insulating layer 356 may be between the stacked structure including the BC layer 353, the metal silicide layer 354, and the metal layer 355.

[0147] It is clear to those skilled in the art that the structure of the present disclosure can be modified or changed in various ways without departing from the scope or technical spirit of the present disclosure. In view of the above description, the present disclosure is intended to include modifications and changes to the present disclosure that fall within the scope of the appended claims and equivalents.

[0148] While the inventive concept has been particularly shown and described with reference to certain examples of embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A memory device, comprising: a plurality of memory cells, each memory cell including a cell transistor having a back gate shared with an adjacent cell transistor of an adjacent memory cell and connected to a back gate line, a top gate connected to a corresponding word line, and a cell capacitor connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a voltage level of a back gate voltage applied to a back gate line corresponding to the selected word line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and A sense amplifier is configured to sense data through a bit line connected to the second electrodes of the cell transistors of the plurality of memory cells.

2. The memory device according to claim 1, wherein: The active period includes a charge sharing period, a sensing period, and a recovery period, and The voltage level of the back-gate voltage changes from a first voltage level to a second voltage level during a charge sharing period.

3. The memory device according to claim 2, wherein: A voltage level of the back gate voltage changes from a second voltage level to a first voltage level during a sensing period and a recovery period.

4. The memory device according to claim 1, wherein: The voltage level of the back gate voltage changes from the second voltage level to the first voltage level during an active period or during a precharge period in which a selected word line is disabled, the precharge period being subsequent to the active period.

5. The memory device according to claim 1, wherein: The active period includes an offset cancellation period, a charge sharing period, a sensing period, and a recovery period, and The voltage level of the back gate voltage changes from a first voltage level to a second voltage level during an offset cancellation period or a charge sharing period.

6. The memory device according to claim 1, wherein: The plurality of memory cells include: A first memory cell including a first cell transistor connected to a first word line, a first bit line and a first back gate line, the first memory cell further including a first cell capacitor connected between a first electrode of the first cell transistor and a ground; a second memory cell including a second cell transistor connected to a second word line adjacent to the first word line, the first bit line, and the first back gate line, the second memory cell further including a second cell capacitor connected between a first electrode of the second cell transistor and ground; and The third memory cell includes a third cell transistor connected to a third word line adjacent to the second word line, the first bit line and the second back gate line, and the third memory cell also includes a third cell capacitor connected between the first electrode of the third cell transistor and ground.

7. The memory device according to claim 6, wherein: The first voltage level is higher than the second voltage level, and During an active period in which the second word line is enabled, a voltage level of a back-gate voltage applied to the first back-gate line is reduced from a first voltage level to a second voltage level.

8. The memory device according to claim 7, wherein: During the active period in which the second word line is enabled, a voltage level of a third word line driving voltage applied to the third word line is lowered.

9. The memory device according to claim 1, wherein: The unit transistor includes an n-type transistor, wherein the second voltage level is lower than the first voltage level, wherein during the active period, the voltage level of the word line driving voltage increases from a first driving voltage level to a third driving voltage level higher than a second driving voltage level for turning on the cell transistor, and During the active period, the voltage level of the back-gate voltage decreases from a first voltage level to a second voltage level.

10. A memory device comprising: A cell array structure including a plurality of word lines, a plurality of bit lines, a plurality of back gate lines and a plurality of memory cells, each memory cell being configured to share a back gate with an adjacent memory cell via a back gate line connected thereto; and a peripheral circuit structure, comprising a peripheral circuit, the peripheral circuit being configured to apply a word line driving voltage to a selected word line among the plurality of word lines, being configured to apply a back gate voltage to a back gate line connected to a memory cell connected to the selected word line, and being configured to sense data through at least one selected bit line among the plurality of bit lines, the peripheral circuit structure vertically overlapping at least a portion of the cell array structure, The peripheral circuit is configured to change the voltage level of the back gate voltage from a first voltage level to a second voltage level during an active period in which the selected word line is enabled.

11. The memory device according to claim 10, wherein: The voltage level of the back gate voltage changes from the second voltage level to the first voltage level during the active period or during a second precharge period after the active period during which the selected word line is disabled.

12. The memory device according to claim 10, wherein: The peripheral circuit includes a single back gate driver connected to the plurality of back gate lines and configured to apply a back gate voltage to each of the plurality of back gate lines.

13. The memory device according to claim 10, wherein: The plurality of back gate lines include a first back gate line group and a second back gate line group, and The peripheral circuit includes a first back-gate driver connected to each back-gate line included in the first back-gate line group and a second back-gate driver connected to each back-gate line included in the second back-gate line group.

14. The memory device according to claim 10, wherein: The peripheral circuit includes a plurality of back gate drivers respectively connected to each of the plurality of back gate lines.

15. The memory device of claim 10, wherein: During the active period, the voltage level of the word line driving voltage applied to the selected word line is reduced.

16. The memory device of claim 10, wherein: the second voltage level is lower than the first voltage level, wherein the voltage level of the word line driving voltage increases from a first driving voltage level to a third driving voltage level higher than the second driving voltage level during the active period, and The voltage level of the back-gate voltage decreases from a first voltage level to a second voltage level during the active period.

17. The memory device of claim 10, wherein: The plurality of memory cells include: a first memory cell including a first vertical channel transistor connected to a first word line, a first bit line and a first back gate line, and a first cell capacitor connected between a first electrode of the first vertical channel transistor and a ground; a second memory cell including a second vertical channel transistor connected to a second word line adjacent to the first word line, the first bit line, and the first back gate line, and a second cell capacitor connected between a first electrode of the second vertical channel transistor and ground; and The third memory cell includes a third vertical channel transistor connected to a third word line adjacent to the second word line, the first bit line and the second back gate line, and a third cell capacitor connected between a first electrode of the third vertical channel transistor and ground.

18. A method of operating a memory device, the method comprising: During a first precharge period, applying a first word line driving voltage of a first driving voltage level to the plurality of word lines; During a first precharge period, applying a first back-gate voltage of a first voltage level to a plurality of back-gate lines; applying a second word line driving voltage of a second driving voltage level higher than the first driving voltage level to a selected word line of the plurality of word lines during an active period after the first precharge period; and During the active period, a second back gate voltage of a second voltage level lower than the first voltage level is applied to a back gate line among the plurality of back gate lines corresponding to the selected word line and connected to the memory cells sharing the back gate. 19 . The method of claim 18 , further comprising, after applying the second back-gate voltage to the back-gate line corresponding to the selected word line, applying the first back-gate voltage to the back-gate line corresponding to the selected word line during the active period.

20. The method of claim 18, further comprising, during a second precharge period after the active period, applying a first back gate voltage to a back gate line corresponding to the selected word line.

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