Packaging structure and forming method thereof

Abstract

The invention provides a packaging structure and a forming method thereof, and the forming method comprises the steps: firstly forming a bridge chip assembly, enabling a silicon through hole of a bridge chip to be exposed in a mode of firstly depositing a protection layer and then thinning the silicon through hole, enabling the protection layer to protect a substrate in the thinning process, and enabling the substrate to be not damaged. Metal ions generated by thinning the silicon through hole can be prevented from being migrated and diffused into the substrate. Meanwhile, in the packaging structure formed by the forming method, the adhesion layer is arranged between the dielectric layer and the base body (or the bottom welding pad), the thermal expansion coefficient of the adhesion layer is larger than that of the bottom welding pad and that of the base body and smaller than that of the dielectric layer, and the adhesion layer serves as a thermal expansion coefficient transition layer. On one hand, the defect that the bottom rewiring layer and the bridging chip are split due to the fact that the thermal expansion coefficient difference between the dielectric layer and the base body or the bottom welding pad is too large can be overcome, on the other hand, the shear stress of the conductive connection structure can be slowly transmitted through the dielectric layer and the adhesion layer, and the structural strength and reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] Advanced Packaging is a new type of electronic packaging technology that aims to integrate multiple chips or other electronic components with higher integration, smaller size, lower power consumption and higher reliability through innovative technical means.

[0003] Wafer Level Package (WLP) is a packaging process in which most of the process steps are performed on wafers. The demand for wafer level packaging is not only limited by the requirements of smaller package size and height, but also must meet the requirements of simplifying the supply chain, reducing overall costs, and improving overall performance.

[0004] Fan-out wafer-level packaging can be divided into die first and die last according to the process. The die first process simply means putting the chip on first and then wiring (Redistribution layer, referred to as RDL), while the die last process means wiring first, and then putting the chip on after the unit passes the test. In the advanced packaging structure using the die last, a bridge chip (Si Bridge Die) needs to be buried in the wiring insertion layer (interposer), and the bridge chip is a structure with TSV and DTC functions. However, the reliability of this advanced packaging structure needs to be improved.

[0005] Therefore, how to improve the reliability of the packaging structure of the embedded bridge chip has become the focus of current research. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a packaging structure and a forming method thereof, which can improve the reliability of the packaging structure.

[0007] In order to solve the above problems, the present invention provides a method for forming a packaging structure, comprising: forming a bridge chip component, the bridge chip component comprising: a bridge chip, a protective layer, a bottom pad and an adhesive layer, the bridge chip comprising a substrate and a silicon through hole penetrating the substrate, the protective layer being arranged on the bottom surface of the substrate, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole, the bottom pad being arranged at least on the bottom surface of the silicon through hole, the adhesive layer covering the bottom surface of the protective layer and the bottom pad; arranging the bridge chip component on the top surface of a carrier, the adhesive layer being in contact with the top surface of the carrier; plastic sealing to form a first plastic sealing layer, the first plastic sealing layer covering the side surface of the bridge chip component and the top surface of the carrier; forming a chip packaging component on the top surface of the first plastic sealing layer and the top surface of the bridge chip component, the bridge chip component being electrically connected to the chip packaging component; The carrier board is removed; an opening is formed in the area corresponding to the adhesion layer and the bottom solder pad, the size of the opening is smaller than the size of the bottom solder pad; a bottom redistribution layer is formed on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, the bottom redistribution layer includes a dielectric layer covering the adhesion layer and a conductive bump located in the dielectric layer, the conductive bump extends into the opening and is in contact with the bottom solder pad, wherein the thermal expansion coefficient of the adhesion layer is greater than the thermal expansion coefficient of the bottom solder pad and the substrate, and the thermal expansion coefficient of the adhesion layer is less than the thermal expansion coefficient of the dielectric layer; a conductive connection structure is formed on the bottom redistribution layer, the conductive connection structure covers the conductive bump and part of the dielectric layer, and in a direction perpendicular to the substrate, the adhesion layer, the dielectric layer and the conductive connection structure overlap in a partial area within the range of the positive projection of the conductive connection structure on the substrate.

[0008] The embodiment of the present invention also provides a packaging structure, including: a bridge chip component, the bridge chip component including: a bridge chip, a protective layer, a bottom pad and an adhesive layer, the bridge chip including a substrate and a silicon through hole penetrating the substrate, the protective layer is arranged on the bottom surface of the substrate, the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer, the bottom pad is at least arranged on the bottom surface of the silicon through hole, the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the bottom pad, the adhesive layer has an opening, the size of the opening is smaller than the size of the bottom pad, and the opening exposes part of the bottom surface of the bottom pad; a first plastic sealing layer, the first plastic sealing layer covers the side of the bridge chip component; a chip packaging component, arranged on the top surface of the first plastic sealing layer and the top surface of the bridge chip component, the bridge The chip connection component is electrically connected to the chip packaging component; a bottom redistribution layer is arranged on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip component, the bottom redistribution layer includes a dielectric layer covering the adhesion layer and a conductive bump located in the dielectric layer, the conductive bump extends into the opening and is in contact with the bottom pad, wherein the thermal expansion coefficient of the adhesion layer is greater than the thermal expansion coefficient of the bottom pad and the substrate, and the thermal expansion coefficient of the adhesion layer is less than the thermal expansion coefficient of the dielectric layer; a conductive connection structure covers the conductive bump and part of the dielectric layer, and in a direction perpendicular to the substrate, the adhesion layer, the dielectric layer and the conductive connection structure overlap in a partial area within the range of the positive projection of the conductive connection structure on the substrate.

[0009] The packaging structure and the method for forming the same provided by the embodiments of the present invention first form a bridge chip assembly, wherein the through silicon vias of the bridge chip are exposed by first depositing a protective layer and then thinning the through silicon vias. During the thinning process, the protective layer can protect the substrate, thereby preventing metal ions (such as copper ions) generated by the thinning of the through silicon vias from migrating and diffusing into the substrate, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions. At the same time, in the packaging structure formed by the formation method, the adhesion layer is arranged between the dielectric layer and the substrate (or the bottom pad), and the coefficient of thermal expansion (CTE) of the adhesion layer is greater than the coefficient of thermal expansion of the bottom pad and the substrate, and less than the coefficient of thermal expansion of the dielectric layer. The adhesion layer serves as a transition layer of thermal expansion coefficient. On the one hand, it can reduce the defect of splitting the bottom redistribution layer and the bridge chip caused by the excessive difference in thermal expansion coefficient between the dielectric layer and the substrate or the bottom pad. On the other hand, it can slowly transfer the shear stress of the conductive connection structure through the dielectric layer and the adhesion layer to avoid the defect of splitting the conductive connection structure and the bottom redistribution layer, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 is a schematic diagram of steps of a method for forming a packaging structure provided by an embodiment of the present invention;

[0012] Figures 2 to 18 is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention;

[0013] Figure 19-20 It is a process flow chart of a method for forming a packaging structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0014] The specific implementation manner of the packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0015] Figure 1 is a schematic diagram of the steps of a method for forming a packaging structure provided by an embodiment of the present invention. Figure 1The formation method comprises: step S10, forming a bridge chip component, the bridge chip component comprises: a bridge chip, a protective layer, a bottom pad and an adhesive layer, the bridge chip comprises a substrate and a silicon through hole penetrating the substrate, the protective layer is arranged on the bottom surface of the substrate, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole, the bottom pad is at least arranged on the bottom surface of the silicon through hole, and the adhesive layer covers the bottom surface of the protective layer and the bottom pad; step S11, arranging the bridge chip component on the top surface of a carrier, the adhesive layer contacts the top surface of the carrier; step S12, plastic sealing, forming a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip component and the top surface of the carrier; step S13, forming a chip packaging component on the top surface of the first plastic sealing layer and the top surface of the bridge chip component, the bridge chip component is electrically connected to the chip packaging component; step S14, removing the Carrier; step S15, forming an opening in the area corresponding to the adhesion layer and the bottom solder pad, the size of the opening is smaller than the size of the bottom solder pad; step S16, forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, the bottom redistribution layer includes a dielectric layer covering the adhesion layer and a conductive bump located in the dielectric layer, the conductive bump extends into the opening and is in contact with the bottom solder pad, wherein the thermal expansion coefficient of the adhesion layer is greater than the thermal expansion coefficient of the bottom solder pad and the substrate, and the thermal expansion coefficient of the adhesion layer is less than the thermal expansion coefficient of the dielectric layer; step S17, forming a conductive connection structure on the bottom redistribution layer, the conductive connection structure covers the conductive bump and part of the dielectric layer, and in a direction perpendicular to the substrate, the adhesion layer, the dielectric layer and the conductive connection structure overlap in a partial area within the range of the positive projection of the conductive connection structure on the substrate.

[0016] The method for forming a packaging structure provided in an embodiment of the present invention first forms a bridge chip component, wherein the silicon via of the bridge chip is exposed by first depositing a protective layer and then thinning the silicon via. During the thinning process, the protective layer can protect the substrate, thereby preventing metal ions (such as copper ions) generated by the thinning of the silicon via from migrating and diffusing into the substrate, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions. At the same time, in the packaging structure formed by the formation method, the adhesion layer is arranged between the dielectric layer and the substrate (or the bottom pad), and the coefficient of thermal expansion (CTE) of the adhesion layer is greater than the coefficient of thermal expansion of the bottom pad and the substrate, and less than the coefficient of thermal expansion of the dielectric layer. The adhesion layer serves as a transition layer of thermal expansion coefficient. On the one hand, it can reduce the defect of splitting the bottom redistribution layer and the bridge chip caused by the excessive difference in thermal expansion coefficient between the dielectric layer and the substrate or the bottom pad. On the other hand, it can slowly transfer the shear stress of the conductive connection structure through the dielectric layer and the adhesion layer to avoid the defect of splitting the conductive connection structure and the bottom redistribution layer, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure.

[0017] Figures 2 to 18 It is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention.

[0018] See also Figure 1 and Fig.10 , step S10, forming a bridge chip component 100, the bridge chip component 100 includes: a bridge chip 110, a protective layer 120, a bottom pad 130 and an adhesion layer 140, the bridge chip 110 includes a substrate 111 and a silicon through hole 112 penetrating the substrate 111, the protective layer 120 is arranged on the bottom surface of the substrate 111, wherein the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120 by first depositing the protective layer 120 and then thinning the silicon through hole 112, the bottom pad 130 is at least arranged on the bottom surface of the silicon through hole 112, and the adhesion layer 140 covers the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130.

[0019] In the bridge chip assembly 100 provided in the embodiment of the present invention, the bottom surface of the silicon through via 112 is flush with the bottom surface of the protective layer 120. When manufacturing the bridge chip assembly 100, the protective layer 120 is first deposited, and then the bottom surface of the silicon through via 112 is ground. During the grinding process, the protective layer 120 can protect the substrate 111, and can prevent the metal ions (such as copper ions) generated by grinding the silicon through via 112 from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions.

[0020] In one embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper column, and the protective layer 120 is a single layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitrogen silicon dioxide. In one embodiment, a passivation layer 113 (marked at Figure 2 In some embodiments, the adhesion layer 140 is a die attachment film (DAF) having excellent thermal conductivity and adhesion.

[0021] The bottom pad 130 is disposed on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112. In one embodiment, the bottom pad 130 is a micro pad (μPad). The bottom pad 130 is disposed on the bottom surface of the through silicon via 112, so that the first plastic encapsulation layer 150 (refer to FIG. 1 ) covering the bridge chip component 100 can be reduced in the packaging structure using the bridge chip component 100. Fig.12 ) thickness, thereby reducing the warpage of the partial structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad 130 is larger than the cross-sectional area of ​​the through silicon via 112, so as to ensure that the through silicon via 112 can be fully in contact with the bottom pad 130, reduce the contact resistance, and further reduce the delay of the electrical signal.

[0022] The embodiment of the present invention further provides a method for forming a bridge chip assembly 100. Specifically, the steps of forming the bridge chip assembly 100 further include:

[0023] See also Figure 2 , providing a device wafer, the device wafer comprising a bridge chip 110, the bridge chip 110 comprising an initial substrate 300, an initial silicon via 310 extending from the top surface of the initial substrate 300 to the inside of the initial substrate 300, and the side and bottom surfaces of the initial silicon via 310 are covered with a passivation layer 113.

[0024] In some embodiments, the bridge chip 110 further includes a deep trench capacitor (DTC) 116, and the deep trench capacitor 116 is disposed in the initial substrate 300. In some embodiments, the deep trench capacitor 116 extends from the top surface of the initial substrate 300 to the inside of the initial substrate 300. In one embodiment, the device wafer further includes an internal redistribution layer 114 and a conductive column 115, the internal redistribution layer 114 is disposed on the top surface of the initial substrate 300, the conductive column 115 is disposed on the top surface of the internal redistribution layer 114, and the deep trench capacitor 116 is electrically connected to the internal redistribution layer 114.

[0025] In some embodiments, the step of providing a device wafer specifically includes: providing an initial wafer, the initial wafer including an initial substrate 300, an initial silicon through hole 310 extending from the top surface of the initial substrate 300 to the inside of the initial substrate 300, and a deep trench capacitor 116; forming an internal redistribution layer 114 and a conductive column 115 on the top surface of the initial substrate 300, the internal redistribution layer 114 is electrically connected to the top surface of the initial silicon through hole 310, and the conductive column 115 is arranged on the top surface of the internal redistribution layer 114 and is electrically connected to the internal redistribution layer 114. The internal redistribution layer 114 includes a dielectric layer and a conductive circuit located in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the initial silicon through hole 310, and the other side is electrically connected to the conductive column 115. The initial silicon through hole 310 includes but is not limited to a copper column, the conductive column 115 includes but is not limited to a copper column, and the dielectric layer includes but is not limited to a silicon dioxide layer or a silicon nitride layer. The initial substrate 300 includes but is not limited to a silicon substrate. In some embodiments, the top surfaces of the initial TSV 310 and the deep trench capacitor 116 are flush with the top surface of the initial substrate 300 .

[0026] Optionally, in some embodiments, in order to support the device wafer in the subsequent step of processing the bottom surface of the device wafer (for example, thinning the initial substrate 300), the step of providing the device wafer further includes: Figure 3 , bonding the support substrate 320 to the front side of the device wafer. The support substrate 320 includes but is not limited to a glass substrate. Further, the step of bonding the support substrate 320 to the front side of the device wafer includes: bonding the support substrate 320 to a side of the device wafer having the conductive pillar 115. Specifically, this step includes: forming a covering layer 330 on the front side of the device wafer, the covering layer 330 covering the conductive pillar 115 and covering the surface of the internal redistribution layer 114; bonding the support substrate 320 to the device wafer using the surface of the support substrate 320 and the surface of the covering layer 330 as bonding surfaces.

[0027] See also Figure 4 and Figure 5 , a portion of the initial substrate 300 is removed from the bottom surface of the initial substrate 300 to form the substrate 111 , and the initial silicon through vias 310 protrude from the bottom surface of the substrate 111 .

[0028] In some embodiments, this step may include the following two steps:

[0029] See also Figure 4 , a portion of the initial substrate 300 is removed from the bottom surface of the initial substrate 300 to a set distance from the passivation layer 113 of the bottom surface of the initial silicon via 310. Specifically, the initial substrate 300 is processed by a mechanical thinning and flattening process from the bottom surface of the initial substrate 300 to a position close to the initial silicon via 310, the initial silicon via 310 is covered by the passivation layer 113, the passivation layer 113 is covered by the initial substrate 300, and the initial silicon via 310 is still not exposed, which can prevent the initial silicon via 310 from exposing copper ions to contaminate the substrate 111. During the thinning process, the supporting substrate 320 supports the device wafer. Figure 4 As shown, in this step, the support substrate 320 is facing downward, and the device wafer is located above the support substrate 320 .

[0030] See also Figure 5 , continue to remove part of the initial substrate 300 from the bottom surface of the initial substrate 300 to form a substrate 111, the initial silicon through-holes 310 protrude from the bottom surface of the substrate 111, and the deep trench capacitors are not exposed from the bottom surface of the substrate 111. Figure 5 As shown, when performing this step, the support substrate 320 is facing downward, and the device wafer is located above the support substrate 320. In this step, the initial silicon through via 310 is not removed, so that the initial silicon through via 310 protrudes from the bottom surface of the substrate 111. In some embodiments, a dry etching process can be used to remove part of the initial substrate 300. The dry etching material can etch the initial substrate 300 without etching the passivation layer 113 on the surface of the initial silicon through via 310, thereby preventing copper ions from contaminating the substrate 111 and the cavity of the subsequent process.

[0031] See also Figure 6, forming a protective layer 120 on the bottom surface of the substrate 111. In this embodiment, the protective layer 120 also covers the surface of the passivation layer 113. In this step, the protective layer 120 can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) and other processes. The protective layer 120 is a single-layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitrogen silicon dioxide. In other embodiments, the protective layer 120 may also only cover the bottom surface of the substrate 111.

[0032] See also Figure 7 , the passivation layer 113 and the initial silicon via 310 are thinned from the bottom surface of the initial silicon via 310 to form the silicon via 112, so that the bottom surface of the silicon via 112 is flush with the bottom surface of the protective layer 120, and the side surface of the silicon via 112 is covered with the passivation layer 113. In this step, when the initial silicon via 310 is thinned, the passivation layer 113 on the bottom surface of the initial silicon via 310 is thinned first, and when the initial silicon via 310 is further thinned, the passivation layer 113 on the side surface of the initial silicon via 310 is also removed synchronously. In this step, the initial silicon via 310 can be polished by a chemical mechanical polishing process until the formed silicon via 112 meets the preset height requirement. In some embodiments, the bottom surface of the protective layer 120 is polished at the same time to provide a flat surface for subsequent processes. In this step, when grinding the initial silicon through via 310, the surface of the substrate 111 is covered by the protective layer 120, and the metal ions generated during grinding cannot diffuse into the substrate 111, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions.

[0033] See also Figure 8 , the bottom pad 130 is formed on the bottom surface of the through silicon via 112, and the bottom pad 130 is arranged on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112. The bottom pad 130 serves as a structure for connecting the through silicon via 112 to the outside. In one embodiment, the bottom pad 130 is a micro pad (μPad). The bottom pad 130 can be formed by a photolithography process and an electroplating process.

[0034] In some embodiments, the step of forming the bottom pad 130 further includes: forming a seed layer 131 on the bottom surface of the protection layer 120 and the bottom surface of the through silicon via 112; and forming the bottom pad 130 on the seed layer 131 on the bottom surface of the through silicon via 112 by electroplating. The seed layer 131 may be a copper layer or a titanium layer or a multi-layer metal layer. Figure 8As shown, the forming method further includes: removing the seed layer 131 not covered by the bottom pad 130 , and only retaining the seed layer 131 located in the bottom pad 130 area.

[0035] See also Fig. 9 , forming the adhesion layer 140. The adhesion layer 140 covers the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130. Specifically, in this step, the adhesion layer 140 is formed on the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130. The bridge chip assembly 100 is fixed on the wafer ring 350 through the adhesion layer 140. In some embodiments, the bottom surface of the device wafer is fixed on the wafer ring 350 through the adhesion layer 140, and the supporting substrate 320 faces upward. The adhesion layer 140 is made of a material with a certain viscosity, such as an acrylic resin series. In some embodiments, the adhesion layer 140 is a die attachment film (DAF), which has excellent thermal conductivity and adhesion.

[0036] In some embodiments, the step of forming the adhesion layer 140 further includes: Fig.10 , debonding the support substrate 320, and singulating the device wafer to form the bridge chip assembly 100. In this step, after debonding the support substrate 320, the cover layer 330 on the front side of the device wafer is also removed, and the conductive pillar 115 is exposed. In some embodiments, a suitable debonding process can be selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc. The device wafer is singulated to form a plurality of independent bridge chip assemblies 100.

[0037] The above is an embodiment of forming the bridge chip assembly 100 .

[0038] See also Figure 1 as well as Fig.11 , step S11 , disposing the bridge chip assembly 100 on the top surface of a carrier 600 , and the adhesive layer 140 is in contact with the top surface of the carrier 600 .

[0039] In some embodiments, the carrier 600 is a glass substrate, and its surface has a temporary bonding layer 601 and a buffer metal layer 602. The bridge chip assembly 100 is disposed on the buffer metal layer 602 through a die attach or die bonding (DA) process. In some embodiments, this step further includes disposing a metal column 160 on the surface of the carrier 600.

[0040] See also Figure 1 and Fig.12, step S12, plastic encapsulation, forming a first plastic encapsulation layer 150, wherein the first plastic encapsulation layer 150 covers the side surface of the bridge chip assembly 100 and the top surface of the carrier 600. Specifically, this step further includes: using a plastic encapsulation material to cover the bridge chip assembly 100, the metal column 160 and the surface of the buffer metal layer 602 covering the carrier 600; preliminarily thinning the plastic encapsulation material to expose the metal column 160 and the conductive column 115 on the top surface of the bridge chip assembly 100; etching the metal column 160 and the conductive column 115 on the top surface of the bridge chip assembly 100 to a preset height; continuing to thin the plastic encapsulation material to form the first plastic encapsulation layer 150, wherein the top surface of the first plastic encapsulation layer 150 is flush with the top surface of the metal column 160 and the top surface of the conductive column 115, and the top surface of the metal column 160 and the top surface of the conductive column 115 are not covered by the first plastic encapsulation layer 150. After initially thinning the molding compound, the metal pillar 160 and the conductive pillar 115 are etched. On the one hand, a preset height can be formed. On the other hand, the oxide layer on the surface of the metal pillar 160 and the conductive pillar 115 can be removed to expose the substrate, thereby reducing the contact resistance between the metal pillar 160 and the conductive pillar 115 and other device layers (such as the top redistribution layer 171).

[0041] See also Figure 1 and Fig.13 , step S13 , forming a chip packaging component 170 on the top surface of the first plastic packaging layer 150 and the top surface of the bridge chip component 100 , and the bridge chip component 100 is electrically connected to the chip packaging component 170 .

[0042] In one embodiment, the chip package assembly 170 includes a top redistribution layer 171, a top pad 172, and a top device 173. The steps of forming the chip package assembly 170 on the top surface of the first plastic encapsulation layer 150 and the top surface of the bridge chip assembly 100 include:

[0043] A top redistribution layer 171 is formed on the top surface of the first plastic encapsulation layer 150 and the top surface of the bridge chip assembly 100. The top redistribution layer 171 includes a dielectric layer and a plated wire located in the dielectric layer, and the plated wire is in contact with and connected to the conductive pillar 115 of the bridge chip assembly 100, wherein the plated wire is formed by an electroplating process. In one embodiment, the top redistribution layer 171 can be formed by a photolithography process and an electroplating process, for example, by adding layers and stacking them through processes such as coating, exposure, development, electroplating, and degumming to form the top redistribution layer 171.

[0044] A top pad 172 is formed on the top surface of the top redistribution layer 171 , and the top pad 172 is electrically connected to the top redistribution layer 171 .

[0045] A top device 173 is disposed on the top redistribution layer 171, and the top device 173 is soldered to the top pad 172. In some embodiments, the top device 173 is flip-chip mounted on the top redistribution layer 171. The top device 173 is soldered to the top pad 172 via a conductive bump.

[0046] The top device 173 is encapsulated to form a second encapsulation layer 175, and the second encapsulation layer 175 covers the top device 173. In some embodiments, before encapsulating the top device 173, the method further includes filling a filling layer 174 between the bottom of the top device 173 and the top redistribution layer 171, and the second encapsulation layer 175 also covers the filling layer 174.

[0047] See also Figure 1 and Fig.14 Step S14, removing the carrier 600. The bottom surface of the first plastic encapsulation layer 150, the bottom surface of the metal pillar 160, and the bottom surface of the adhesive layer 140 are exposed.

[0048] In this step, a suitable debonding process is selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc., to remove the carrier 600. After removing the carrier 600, the buffer metal layer 602 on the surface of the substrate is also removed by etching. Optionally, after removing the carrier 600, a cleaning process is also included to remove residues.

[0049] See also Figure 1 and Fig.15 , step S15, forming an opening 141 in the region corresponding to the adhesive layer 140 and the bottom pad 130, wherein the size of the opening 141 is smaller than the size of the bottom pad 130, and the opening 141 exposes a portion of the bottom pad 130, and the periphery of the bottom pad 130 is also covered with the adhesive layer 140. In one embodiment, the opening 141 is formed in the region corresponding to the adhesive layer 140 and the bottom pad 130 by a laser drilling process.

[0050] See also Figure 1 and Fig.18 , step S16, forming a bottom redistribution layer 180 on the bottom surface of the first plastic packaging layer 150 and the bottom surface of the bridge chip assembly 100, the bottom redistribution layer 180 includes a dielectric layer 181 covering the adhesion layer 140 and a conductive bump 182 located in the dielectric layer 181, the conductive bump 182 extends into the opening 141 and is in contact with the bottom pad 130, wherein the thermal expansion coefficient of the adhesion layer 140 is greater than the thermal expansion coefficient of the bottom pad 130 and the substrate 111, and the thermal expansion coefficient of the adhesion layer 140 is less than the thermal expansion coefficient of the dielectric layer 181.

[0051] In the structure formed in this step, the thermal expansion coefficient of the adhesion layer 140 is between the thermal expansion coefficients of the dielectric layer 181, the substrate 111 and the bottom pad 130. The adhesion layer 140 can serve as a thermal expansion coefficient transition layer. On the one hand, it can reduce the defect of splitting between the bottom redistribution layer 180 and the bridge chip 110 caused by the excessive difference in thermal expansion coefficients between the dielectric layer 181 and the substrate 111 or the bottom pad 130. On the other hand, it can slowly transfer the shear stress of the conductive connection structure 190 formed in the subsequent steps through the dielectric layer 181 and the adhesion layer 140, avoiding the defect of splitting between the conductive connection structure 190 and the bottom redistribution layer 180, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure.

[0052] In some embodiments, the step of forming a bottom redistribution layer 180 on the bottom surface of the first plastic encapsulation layer 150 and the bottom surface of the bridge chip assembly 100 further includes:

[0053] See also Fig.16 A dielectric layer 181 is formed on the bottom surface of the first plastic packaging layer 150 and the bottom surface of the bridge chip assembly 100, and the dielectric layer 181 is filled in the opening 141. In this step, the dielectric layer 181 can be formed by a coating process. The material of the dielectric layer 181 can be a polymer material such as polybutylene styrene (PBO) and polyimide (PI).

[0054] See also Fig.17 , a through hole 183 exposing the bottom pad 130 is formed on the dielectric layer 181. In this step, the through hole 183 can be formed on the dielectric layer 181 by a single exposure process or a double exposure process. In some embodiments, if the distance between the surface of the bottom pad 130 and the surface of the dielectric layer 181 is too far, the through hole 183 may not be able to fully expose the bottom pad 130 by using a single exposure process, then the through hole 183 may be formed on the dielectric layer 181 by a double exposure process, so that the through hole 183 can fully expose the bottom pad 130.

[0055] In this embodiment, the size of the through hole 183 is smaller than the size of the opening 141, and the dielectric layer 181 also covers the sidewall of the opening 141. That is, the through hole 183 is located within the range of the opening 141, so that the dielectric layer 181 in the opening 141 is not completely removed, and the sidewall of the opening 141 is still covered with the dielectric layer 181.

[0056] See also Fig.18, a conductive bump 182 is formed in the through hole 183 by sputtering and / or electroplating, and the conductive bump 182 is in contact with the bottom pad 130. In this step, the conductive bump 182 is formed by sputtering and electroplating, and tin (Sn) welding is not required, which eliminates the aging problem of tin welding during the process, and there is no problem of voids (Void) and cracks (Crack) appearing at the welding point, which improves the reliability of the packaging structure, and the combination of sputtering and electroplating can take into account both efficiency and cost.

[0057] Please continue reading Figure 1 and Fig.18 , step S17, forming a conductive connection structure 190 on the bottom redistribution layer 180, the conductive connection structure 190 covers the conductive bump 182 and a portion of the dielectric layer 181, and in a direction perpendicular to the substrate 111, the adhesion layer 140, the dielectric layer 181 and the conductive connection structure 190 overlap in a partial area within the range of the positive projection of the conductive connection structure 190 on the substrate 111.

[0058] In the embodiment of the present invention, the conductive connection structure 190 and the conductive bump 182 are formed in the same step. Specifically, a photoresist coating is applied on the dielectric layer 181; the photoresist coating is patterned and the through hole 183 is formed in the dielectric layer 181; the conductive bump 182 and the conductive connection structure 190 are formed by electroplating; and the photoresist coating is removed.

[0059] In the structure formed in this step, the conductive connection structure 190 is electrically connected to the conductive bump 182, and the conductive connection structure 190 also covers the surface of the dielectric layer 181, so that in the direction perpendicular to the substrate 111 (such as Fig.18 In the Z direction), in a partial area within the positive projection range of the conductive connection structure 190 on the substrate 111, the adhesion layer 140, the dielectric layer 181 and the conductive connection structure 190 overlap. The adhesion layer 140 serves as a thermal expansion coefficient transition layer, which can slowly transfer the shear stress of the conductive connection structure 190 through the dielectric layer 181 and the adhesion layer 140, thereby avoiding the defect of splitting between the conductive connection structure 190 and the bottom redistribution layer 180, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure.

[0060] In some embodiments, the conductive connection structure 190 includes but is not limited to a controllably collapsed chip connection bump ( C4 ).

[0061] Optionally, after or before forming the conductive connection structure 190, the second plastic encapsulation layer 175 is thinned to expose the top surface of the top device 173, which is useful for device heat dissipation. Optionally, after forming the conductive connection structure 190, singulation is performed to form a plurality of independent package structures, each of which may include a plurality of the bridge chip components 100 and a plurality of the top devices 173.

[0062] In the above embodiment, in the step of forming the bottom redistribution layer 180 on the bottom surface of the first plastic encapsulation layer 150 and the bottom surface of the bridge chip assembly 100, the size of the through hole 183 formed in the dielectric layer 181 is smaller than the size of the opening 141 formed in the adhesion layer 140. In other embodiments, the size of the through hole 183 is larger than the size of the opening 141, and the through hole 183 exposes a portion of the bottom surface of the adhesion layer 140, and the conductive bump 182 also covers a portion of the bottom surface of the adhesion layer 140.

[0063] Specifically, Figure 19-20 It is a process flow chart of a method for forming a packaging structure provided by another embodiment of the present invention.

[0064] In some embodiments, the step of forming a bottom redistribution layer 180 on the bottom surface of the first plastic encapsulation layer 150 and the bottom surface of the bridge chip assembly 100 further includes:

[0065] A dielectric layer 181 is formed on the bottom surface of the first plastic encapsulation layer 150 and the bottom surface of the bridge chip assembly 100, and the dielectric layer 181 fills the opening 141. In this step, the dielectric layer 181 can be formed by coating or other processes. Fig.16 .

[0066] See also Fig.19 , a through hole 183 exposing the bottom pad 130 is formed on the dielectric layer 181. In this step, the through hole 183 can be formed on the dielectric layer 181 by a single exposure or double exposure process. In this embodiment, the size of the through hole 183 is larger than the size of the opening 141, and the through hole 183 exposes part of the bottom surface of the adhesion layer 140. That is, the opening 141 is located within the range of the through hole 183, the dielectric layer 181 in the opening 141 is completely removed, and the adhesion layer 140 around the opening 141 is exposed to the through hole 183.

[0067] See also Fig. 20 , a conductive bump 182 is formed in the through hole 183 by sputtering and / or electroplating, and the conductive bump 182 is in contact with the bottom pad 130 . The conductive bump 182 also covers a portion of the bottom surface of the adhesive layer 140 .

[0068] Please continue reading Fig. 20 A conductive connection structure 190 is formed on the bottom surface of the bottom redistribution layer 180. In this embodiment, the conductive connection structure 190 and the conductive bump 182 are formed in the same step.

[0069] The method for forming a packaging structure provided in an embodiment of the present invention exposes the through silicon via 112 of the bridge chip 110 by first depositing a protective layer 120 and then thinning the through silicon via 112, thereby preventing metal ions (such as copper ions) generated by thinning the through silicon via 112 from migrating and diffusing into the substrate 111, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions. At the same time, the adhesion layer 140 is arranged between the dielectric layer 181 and the substrate 111 (or the bottom solder pad). The adhesion layer 140 serves as a thermal expansion coefficient transition layer. On the one hand, it can reduce the defect of the bottom redistribution layer 180 and the bridge chip 110 being split due to the excessive difference in thermal expansion coefficient between the dielectric layer 181 and the substrate 111 or the bottom solder pad 130. On the other hand, it can slowly transfer the shear stress of the conductive connection structure 190 through the dielectric layer 181 and the adhesion layer 140, avoiding the defect of the conductive connection structure 190 and the bottom redistribution layer 180 being split, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure.

[0070] Based on the same inventive concept, an embodiment of the present invention also provides a packaging structure formed by the above-mentioned forming method. Figures 2 to 18The packaging structure includes: a bridge chip component 100, the bridge chip component 100 includes: a bridge chip 110, a protective layer 120, a bottom pad 130 and an adhesive layer 140, the bridge chip 110 includes a substrate 111 and a silicon through hole 112 penetrating the substrate 111, the protective layer 120 is arranged on the bottom surface of the substrate 111, the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120, the bottom pad 130 is at least arranged on the bottom surface of the silicon through hole 112, the adhesive layer The first plastic encapsulation layer 150 covers the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130, and the adhesive layer 140 has an opening 141. The size of the opening 141 is smaller than the size of the bottom pad 130, and the opening 141 exposes a portion of the bottom surface of the bottom pad; the first plastic encapsulation layer 150, the first plastic encapsulation layer 150 covers the side surface of the bridge chip component 100; the chip packaging component 170 is arranged on the top surface of the first plastic encapsulation layer 150 and the top surface of the bridge chip component 100, and the bridge The chip connection component 100 is electrically connected to the chip packaging component 170; the bottom redistribution layer 180 is arranged on the bottom surface of the first plastic packaging layer 150 and the bottom surface of the bridge chip component 100, the bottom redistribution layer 180 includes a dielectric layer 181 covering the adhesion layer 140 and a conductive bump 182 located in the dielectric layer 181, the conductive bump 182 extends into the opening 141 and is in contact with the bottom pad 130, wherein the thermal expansion coefficient of the adhesion layer 140 is greater than the thermal expansion coefficient of the bottom pad 130 and the substrate 111, and the thermal expansion coefficient of the adhesion layer 140 is less than the thermal expansion coefficient of the dielectric layer 181; the conductive connection structure 190 covers the conductive bump 182 and part of the dielectric layer 181, and in the direction perpendicular to the substrate 111, the adhesion layer 140, the dielectric layer 181 and the conductive connection structure 190 overlap in a partial area within the range of the positive projection of the conductive connection structure 190 on the substrate 111.

[0071] In the packaging structure provided by the embodiment of the present invention, the bottom surface of the silicon through via 112 is flush with the bottom surface of the protective layer 120. When manufacturing the bridge chip component 100, the protective layer 120 is first formed, and then the bottom surface of the silicon through via 112 is ground. During the grinding process, the protective layer 120 can protect the substrate 111, and can prevent the metal ions (such as copper ions) generated by grinding the silicon through via 112 from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions. Furthermore, the adhesion layer 140 is disposed between the dielectric layer 181 and the substrate 111 (or the bottom pad), and the coefficient of thermal expansion (CTE) of the adhesion layer 140 is greater than the coefficients of thermal expansion of the bottom pad 130 and the substrate 111, and less than the coefficient of thermal expansion of the dielectric layer 181. The adhesion layer 140 serves as a transition layer for thermal expansion coefficient. On the one hand, it can reduce the defect of the bottom redistribution layer 180 and the bridge chip 110 being split due to the large difference in thermal expansion coefficients between the dielectric layer 181 and the substrate 111 or the bottom pad 130. On the other hand, it can slowly transfer the shear stress of the conductive connection structure 190 through the dielectric layer 181 and the adhesion layer 140, thereby avoiding the defect of the conductive connection structure 190 and the bottom redistribution layer 180 being split, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure.

[0072] The bottom surface of the silicon through via 112 is electrically connected to other structural layers (such as the bottom redistribution layer 180) through the bottom pad 130, which reduces the thickness of the first plastic packaging layer 150 covering the bridge chip assembly 100, thereby reducing the warping of this part of the structure, which is more conducive to production and yield.

[0073] In one embodiment, the bottom pad 130 is a micro pad (μPad). The bottom pad 130 is arranged on the bottom surface of the through silicon via 112, so that the thickness of the first plastic encapsulation layer 150 covering the bridge chip component 100 can be reduced in the packaging structure using the bridge chip component 100, thereby reducing the warping of this part of the structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad 130 is larger than the cross-sectional area of ​​the through silicon via 112 to ensure that the through silicon via 112 can be fully in contact with the bottom pad 130, reduce the contact resistance, and thereby make the delay of the electrical signal smaller.

[0074] In one embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper column, and the protective layer 120 is a single layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitride silicon dioxide.

[0075] In one embodiment, the bridge chip assembly 100 further includes a seed layer 131 disposed between the bottom pad 130 and the bottom surface of the through silicon via 112, and the bottom pad 130 is formed by electroplating on the surface of the seed layer 131. The seed layer 131 can be a copper layer or a titanium layer or multiple metal layers.

[0076] In one embodiment, a passivation layer 113 is further disposed on the side of the TSV 112 , and the passivation layer 113 is used to isolate the TSV 112 from the substrate 111 to prevent metal ions in the TSV 112 from diffusing into the substrate 111 .

[0077] In one embodiment, the bridge chip assembly 100 further includes an internal redistribution layer 114 and a conductive column 115. The internal redistribution layer 114 is disposed on the top surface of the substrate 111 and is electrically connected to the top surface of the through silicon via 112. The conductive column 115 is disposed on the top surface of the internal redistribution layer 114 and is electrically connected to the internal redistribution layer 114. The chip packaging assembly 170 is electrically connected to the conductive column 115. The internal redistribution layer 114 includes a dielectric layer and a conductive circuit located in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the through silicon via 112, and the other side is electrically connected to the conductive column 115. The conductive column 115 includes but is not limited to a copper column, and the dielectric layer may be a silicon dioxide layer or a silicon nitride layer.

[0078] In one embodiment, the bridge chip 110 further includes a deep trench capacitor (DTC) 116, which is disposed in the substrate 111. In some embodiments, the deep trench capacitor 116 extends from the top surface of the substrate 111 to the inside of the substrate 111, and the deep trench capacitor 116 is electrically connected to the internal redistribution layer 114.

[0079] In some embodiments, the packaging structure further includes a metal column 160, the metal column 160 penetrates the first plastic packaging layer 150, and the bottom surface of the metal column 160 is flush with the bottom surface of the first plastic packaging layer 150. In one embodiment, the top surface of the metal column 160 is flush with the top surface of the conductive column 115. The metal column 160 and the conductive column 115 can be made of the same material, for example, both are copper. The packaging structure may include a plurality of the bridge chip components 100 and a plurality of the metal columns 160, the metal columns 160 are distributed around the bridge chip components 100 and between two adjacent bridge chip components 100. In some embodiments, the bottom redistribution layer 180 also covers the bottom surface of the metal column 160, and the metal column 160 is electrically connected to the bottom redistribution layer 180.

[0080] In some embodiments, the chip package assembly 170 includes a top redistribution layer 171 , a top pad 172 , a top device 173 , and a second plastic layer 175 .

[0081] The top redistribution layer 171 is arranged on the top surface of the first plastic encapsulation layer 150 and the top surface of the bridge chip assembly 100. The top redistribution layer 171 includes a dielectric layer and a plated wire located in the dielectric layer. The plated wire is in contact with and connected to the conductive column 115 of the bridge chip assembly 100. In some embodiments, the top surface of the metal column 160 is in contact with and connected to the plated wire. In some embodiments, the material of the dielectric layer may be a polymer material such as polystyrene butyrate (PBO) and polyimide (PI). The plated wire refers to a wire formed by an electroplating process. In one embodiment, the plated wire is formed on the surface of the through silicon via 112 and the metal column 160 by an electroplating process, and there is no need to use tin (Sn) welding, which eliminates the aging problem of tin welding during process processing, and there is no problem of voids (Void) and cracks (Crack) appearing at the welding point, thereby improving the reliability of the packaging structure.

[0082] The top pad 172 is disposed on the top surface of the top redistribution layer 171 and is electrically connected to the top redistribution layer 171. In one embodiment, the top pad 172 is a micro pad (μPad).

[0083] The top device 173 is disposed on the top redistribution layer 171 and is welded to the top pad 172. The top device 173 may be flip-chip disposed on the top redistribution layer 171 and is welded to the top pad 172. The top device 173 may be a SOC device or the like.

[0084] The second plastic encapsulation layer 175 covers the top device 173. In some embodiments, the package structure further includes a filling layer 174 filled between the bottom of the top device 173 and the top redistribution layer 171, and the filling layer 174 is used to protect the conductive structure of the top device 173 and the top pad 172. The second plastic encapsulation layer 175 covers the top device 173, the surface of the top redistribution layer 171, and the surface of the filling layer 174.

[0085] In one embodiment, the dielectric layer 181 has a through hole 183 exposing the bottom pad 130, the conductive bump 182 is disposed in the through hole 183, the size of the through hole 183 is smaller than the size of the opening 141, and the dielectric layer 181 also covers the side wall of the opening 141. Fig.17The sidewall of the conductive bump 182 is in contact with the dielectric layer 181, and the sidewall of the conductive bump 182 is not in contact with the adhesion layer 140, that is, the opening 141 of the adhesion layer 140 is filled with the dielectric layer 181 and the conductive bump 182. Fig.18 shown.

[0086] In another embodiment, if Fig.19 As shown, the dielectric layer 181 has a through hole 183 exposing the bottom pad 130, the size of the through hole 183 is larger than the size of the opening 141, and the through hole 183 exposes a portion of the bottom surface of the adhesion layer 140; Fig. 20 As shown, the conductive bump 182 is disposed in the through hole 183 and covers a portion of the bottom surface of the adhesion layer 140 , and the conductive bump 182 completely fills the opening 141 .

[0087] The packaging structure provided by the embodiment of the present invention exposes the silicon via of the bridge chip by first depositing a protective layer and then thinning the silicon via, which can prevent the metal ions (such as copper ions) generated by the thinning of the silicon via from migrating and diffusing into the substrate, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions. At the same time, the adhesion layer is arranged between the dielectric layer and the substrate (or the bottom pad). The adhesion layer serves as a transition layer of thermal expansion coefficient. On the one hand, it can reduce the defect of the bottom redistribution layer and the bridge chip splitting caused by the large difference in thermal expansion coefficient between the dielectric layer and the substrate or the bottom pad. On the other hand, it can slowly transfer the shear stress of the conductive connection structure through the dielectric layer and the adhesion layer, avoiding the defect of the conductive connection structure and the bottom redistribution layer splitting, thereby improving the structural strength and reliability of the heterogeneous integrated packaging structure.

[0088] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0089] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a packaging structure, characterized in that: include: Forming a bridge chip assembly, the bridge chip assembly comprising: a bridge chip, a protective layer, a bottom pad and an adhesive layer, the bridge chip comprising a substrate and a through silicon via penetrating the substrate, the protective layer being arranged on the bottom surface of the substrate, wherein the bottom surface of the through silicon via is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the through silicon via, the bottom pad being arranged at least on the bottom surface of the through silicon via, and the adhesive layer covering the bottom surface of the protective layer and the bottom surface of the bottom pad; The bridge chip assembly is arranged on a top surface of a carrier board, wherein the adhesive layer is in contact with the top surface of the carrier board; Plastic encapsulation to form a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the side surface of the bridge chip component and the top surface of the carrier; a chip packaging component is formed on the top surface of the first plastic encapsulation layer and the top surface of the bridge chip component, and the bridge chip component is electrically connected to the chip packaging component; removing the carrier plate; forming an opening in a region of the adhesive layer corresponding to the bottom pad, wherein a size of the opening is smaller than a size of the bottom pad; A bottom redistribution layer is formed on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, wherein the bottom redistribution layer includes a dielectric layer covering the adhesion layer and a conductive bump located in the dielectric layer, wherein the conductive bump extends into the opening and is in contact with and connected to the bottom pad, wherein the thermal expansion coefficient of the adhesion layer is greater than the thermal expansion coefficient of the bottom pad and the substrate, and the thermal expansion coefficient of the adhesion layer is less than the thermal expansion coefficient of the dielectric layer; A conductive connection structure is formed on the bottom redistribution layer, the conductive connection structure covers the conductive bump and a portion of the dielectric layer, and in a direction perpendicular to the substrate, the adhesion layer, the dielectric layer and the conductive connection structure overlap in a partial area within the range of the positive projection of the conductive connection structure on the substrate.

2. The method for forming a packaging structure according to claim 1, characterized in that: The steps of forming the bridge chip assembly further include: Providing a device wafer, the device wafer comprising a bridge chip, the bridge chip comprising an initial substrate, an initial through silicon via extending from the top surface of the initial substrate to the inside of the initial substrate, the side and bottom surfaces of the initial through silicon via being covered with a passivation layer; Removing a portion of the initial substrate from the bottom surface of the initial substrate to form the substrate, wherein the initial through silicon vias protrude from the bottom surface of the substrate; forming a protective layer on the bottom surface of the substrate; Thinning the passivation layer and the initial through silicon via from the bottom surface of the initial through silicon via to form the through silicon via, so that the bottom surface of the through silicon via is flush with the bottom surface of the protection layer, and the side surface of the through silicon via is covered with the passivation layer; forming the bottom pad on the bottom surface of the through silicon via; The adhesion layer is formed.

3. The method for forming a packaging structure according to claim 2, wherein: The step of forming a bottom pad further includes: forming a seed layer on the bottom surface of the protective layer and the bottom surface of the silicon via; forming the bottom pad on the seed layer on the bottom surface of the silicon via by electroplating; and removing the seed layer not covered by the bottom pad.

4. The method for forming a packaging structure according to claim 2, wherein: After the step of providing the device wafer, the step further includes: bonding the support substrate to the front side of the device wafer; after the step of forming the adhesion layer, the step further includes: debonding the support substrate and singulating the device wafer to form the bridge chip assembly.

5. The method for forming a packaging structure according to claim 4, characterized in that: The step of providing a device wafer further includes: forming an internal redistribution layer and a conductive column on the top surface of the initial substrate, wherein the internal redistribution layer is electrically connected to the top surface of the initial through silicon via, and the conductive column is disposed on the top surface of the internal redistribution layer and is electrically connected to the internal redistribution layer; The step of bonding the support substrate to the front side of the device wafer includes: bonding the support substrate to a side of the device wafer having the conductive pillars.

6. The method for forming a packaging structure according to claim 1, characterized in that: The step of arranging the bridge chip assembly on the top surface of a carrier board also includes: arranging a metal column on the top surface of the carrier board; and in the step of plastic encapsulation, the first plastic encapsulation layer also covers the side surface of the metal column.

7. The method for forming a packaging structure according to claim 1, characterized in that: The step of forming a chip package assembly on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly further includes: A top redistribution layer is formed on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, wherein the top redistribution layer includes a dielectric layer and electroplated wires located in the dielectric layer, and the electroplated wires are electrically connected to the bridge chip assembly. Wherein, the electroplated wire is formed by an electroplating process; forming a top pad on a top surface of the top redistribution layer, wherein the top pad is electrically connected to the top redistribution layer; Disposing a top device on the top redistribution layer, wherein the top device is welded to the top pad; Plastic encapsulation is performed to form a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the top device.

8. The method for forming a packaging structure according to claim 1, wherein: The step of forming an opening in a region of the adhesion layer corresponding to the bottom pad further includes: forming the opening using a laser drilling process.

9. The method for forming a packaging structure according to claim 1, wherein: The step of forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly further includes: Forming a dielectric layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, and the dielectric layer is filled in the opening; forming a through hole on the dielectric layer to expose the bottom pad; A conductive bump is formed in the through hole by sputtering and / or electroplating, and the conductive bump is in contact with and connected to the bottom pad.

10. The method for forming a packaging structure according to claim 9, characterized in that: The size of the through hole is smaller than the size of the opening, and the dielectric layer also covers the sidewall of the opening.

11. The method for forming a packaging structure according to claim 9, wherein: The size of the through hole is larger than the size of the opening, the through hole exposes a portion of the bottom surface of the adhesion layer, and the conductive bump also covers a portion of the bottom surface of the adhesion layer.

12. A packaging structure, characterized in that: include: A bridge chip component, the bridge chip component comprising: a bridge chip, a protective layer, a bottom pad and an adhesive layer, the bridge chip comprising a substrate and a through silicon via penetrating the substrate, the protective layer being arranged on the bottom surface of the substrate, the bottom surface of the through silicon via being flush with the bottom surface of the protective layer, the bottom pad being arranged at least on the bottom surface of the through silicon via, the adhesive layer covering the bottom surface of the protective layer and the bottom pad, the adhesive layer having an opening, the size of the opening being smaller than the size of the bottom pad, and the opening exposing a portion of the bottom surface of the bottom pad; A first plastic sealing layer, wherein the first plastic sealing layer covers a side surface of the bridge chip assembly; A chip packaging component, arranged on the top surface of the first plastic packaging layer and the top surface of the bridge chip component, the bridge chip component is electrically connected to the chip packaging component; A bottom redistribution layer is arranged on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, the bottom redistribution layer includes a dielectric layer covering the adhesion layer and a conductive bump located in the dielectric layer, the conductive bump extends into the opening and is in contact with the bottom pad, wherein the thermal expansion coefficient of the adhesion layer is greater than the thermal expansion coefficient of the bottom pad and the substrate, and the thermal expansion coefficient of the adhesion layer is less than the thermal expansion coefficient of the dielectric layer; The conductive connection structure covers the conductive bump and part of the dielectric layer, and in a direction perpendicular to the substrate, the adhesion layer, the dielectric layer and the conductive connection structure overlap in a partial area within the orthographic projection range of the conductive connection structure on the substrate.

13. The packaging structure according to claim 12, characterized in that: The dielectric layer has a through hole exposing the bottom pad, the conductive bump is arranged in the through hole, the size of the through hole is smaller than the size of the opening, and the dielectric layer also covers the side wall of the opening.

14. The packaging structure according to claim 12, characterized in that: The dielectric layer has a through hole exposing the bottom pad, the conductive bump is arranged in the through hole, the size of the through hole is larger than the size of the opening, the through hole exposes part of the bottom surface of the adhesion layer, and the conductive bump also covers part of the bottom surface of the adhesion layer.

15. The packaging structure according to claim 12, characterized in that: A passivation layer is also provided on the side of the through silicon via.

16. The packaging structure according to claim 12, characterized in that: The bridge chip assembly also includes: An internal redistribution layer is disposed on the top surface of the substrate and is electrically connected to the top surface of the through silicon via; A conductive column is disposed on the top surface of the internal redistribution layer and is electrically connected to the internal redistribution layer. The chip packaging component is electrically connected to the conductive column.

17. The packaging structure according to claim 12, characterized in that: The bridge chip further includes a deep trench capacitor, which is disposed in the substrate.

18. The packaging structure according to claim 12, characterized in that: The chip packaging assembly comprises: A top redistribution layer is disposed on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, the top redistribution layer includes a dielectric layer and electroplated wires located in the dielectric layer, and the electroplated wires are electrically connected to the bridge chip assembly; A top pad, disposed on the top redistribution layer and electrically connected to the top redistribution layer; A top device is disposed on the top redistribution layer, and the top device is welded to the top pad; The second plastic packaging layer covers the top device.

19. The packaging structure according to claim 12, characterized in that: The bridge chip assembly further includes a seed layer disposed between the bottom pad and a bottom surface of the through silicon via.

20. The packaging structure according to claim 12, characterized in that: The packaging structure further includes a metal column, which penetrates the first plastic packaging layer, and the bottom surface of the metal column is flush with the bottom surface of the first plastic packaging layer.

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