High-speed LVDS transmission system

Abstract

The application discloses a high-speed LVDS transmission system, which comprises a protocol layer and an implementation layer, wherein the protocol layer comprises a synchronization sequence and a transmission frame; the implementation layer comprises a sending end and a receiving end; the sending end comprises a bit scrambling module, a framing module, a check value calculation module and an output parallel / serial conversion module; the receiving end comprises an input delay adjustment module, an input serial / parallel conversion module, a single-path synchronization module, a check value check module, a multi-path synchronization module, an output control module and a bit unwinding module; the transmission rate of the application is high, 8b / 10b coding is not needed; arbitrary-path data parallel reliable transmission is supported; the efficiency is high, all LVDS lines are used for data transmission, and no state / control signals occupy additional LVDS lines; real-time dynamic self-adaptive training is adopted to adapt to the rapid change of signal delay; resource consumption is less, only one point needs to be sampled for each-path data, and sampling and data delay resources are saved.

Description

Technical Field

[0001] This invention relates to a system for high-speed data transmission via LVDS, suitable for high-speed data transmission within or between devices. Background Technology

[0002] With the ever-increasing demands for functional performance and the growing complexity of processing protocols in modern electronic devices, data transmission rates within and between devices have gradually become a bottleneck in electronic device design. Traditional synchronous data transmission schemes can only achieve a stable transmission rate of up to 150 Mbps between chips, and only about 75 Mbps across circuit boards. Furthermore, for synchronous transmission systems, the more parallel data paths there are, the worse the timing consistency becomes, and the lower the maximum achievable rate, significantly reducing the communication efficiency between chips. To avoid these problems with synchronous data transmission, the mainstream solution currently is to use high-speed serial interfaces such as GTX, transmitting data at speeds of up to tens of Gbps via a pair of high-speed LVDS. However, the application of high-speed serial interfaces such as GTX requires dedicated hardware resources, and the peripheral circuits also need to be designed accordingly, resulting in poor versatility and flexibility.

[0003] To avoid the many inconveniences of using a dedicated high-speed serial interface, some FPGA manufacturers, literature, and patents have discussed a solution of using a chip with dynamic delay adjustment function for external pins to achieve high-speed communication through a common LVDS interface.

[0004] The principle of high-speed communication using ordinary LVDS is as follows: Figure 1 As shown, due to factors such as circuit characteristics and clock phase noise, data will have a certain degree of uncertainty at the boundary with other data. That is, the sampled data may be data from the "left" side of the boundary, data from the "right" side of the boundary, or other "illegal" data. Therefore, the sampling results at the data boundary are meaningless. In contrast, the data obtained at the optimal sampling point can be considered reliable. The solutions provided in the following materials all find the optimal sampling point through various methods.

[0005] In its xapp585 manual, "LVDS Source Synchronous 7:1 Serialization and Deserialization Using Clock Multiplication," FPGA manufacturer Xilinx samples the input data at two sampling points with a phase difference of 1 / 2 data cycle and statistically analyzes the results. When the data is sufficiently random, if the data obtained from the two sampling points are significantly different, they are considered to have sampled different data; if the data obtained from the two sampling points are significantly the same, they are considered to have sampled the same data. Based on this statistical pattern, the positions of the two sampling points are synchronously adjusted, ultimately placing one sampling point in the middle of the transmitted data and the other at the boundary between the transmitted data. The sampling point located in the middle of the transmitted data can be considered as the transmitted data. The drawbacks of this scheme are as follows: First, because it requires sampling twice per symbol period, it consumes twice the hardware resources compared to a scheme that only requires sampling once per symbol period, especially considering the scarcity of input delay adjustment resources in typical FPGAs or chips. Second, the sampling data is unreliable when adjusting the sampling point position, so the sampling position cannot be dynamically adjusted during service data transmission. Therefore, the transmitting and receiving ends must be from the same source, and the sampling position must remain unchanged; otherwise, it cannot be used. Third, this scheme only synchronizes a single pair of LVDS lines and does not involve synchronization technology for parallel transmission of multiple pairs of LVDS lines. Finally, in certain scenarios, the randomness of transmitted data cannot be guaranteed, which also limits the application of this scheme. FPGA manufacturer Xilinx, in its xapp523 manual "LVDS 4x Asynchronous Oversampleing Using 7SeriesFPGAs," adopted a scheme similar to the xapp585, setting four sampling points for the input data, spaced 1 / 2 data period apart, and dynamically adjusting the sampling position through an algorithm. The drawback of this scheme is that it uses more resources, consuming four times the hardware resources compared to a scheme that only needs to be sampled once per symbol period.

[0006] The paper "Implementation of High-Speed ​​LVDS Interface Based on FPGA" by Li Dapeng et al., *Aerospace Computing Technology*, presents a high-speed LVDS interface design based on FPGA. The drawbacks of this scheme are: first, the transmitting and receiving ends must have synchronized clocks; second, training is only performed during initialization, which cannot adapt to dynamic changes in data latency; third, additional control signals exist at both ends; and finally, although it supports parallel transmission of multiple LVDS lines, synchronization between multiple lines relies solely on the delay control word, making synchronization relatively fragile. The paper "FPGA Design and Implementation of High-Speed ​​LVDS Interface" by Liu Huafeng, *Science & Technology Vision*, presents a high-speed LVDS interface with automatic alignment based on 8B / 10B encoding. The drawbacks of this scheme are: first, the transmitting and receiving ends must have synchronized clocks; second, the use of 8b / 10b encoding reduces the transmission rate; and finally, it does not support parallel transmission of multiple LVDS lines. The paper "Application of SERDES Technology with Adaptive Dynamic Delay Adjustment in Broadband Data Transmission" by Zhang Feng, Telecommunications Technology, proposes a solution for high-speed transmission based on SERDES technology to meet the needs of broadband high-speed data transmission. The disadvantages of this solution are: first, the transmitting and receiving ends must be clocked from the same source; second, training is only performed during initialization and cannot adapt to dynamic changes in data delay; and finally, it does not support parallel transmission of multiple pairs of LVDS lines.

[0007] Patent CN202010117247.7 discloses a method and system for implementing clock synchronization in high-speed LVDS serial communication. The disadvantages of this scheme are: firstly, the transmitting and receiving ends must have the same clock source; secondly, training is only performed during initialization, which cannot adapt to dynamic changes in data latency; and finally, it does not support parallel transmission of multiple LVDS lines. Patent CN202110563176.8 discloses an asynchronous serial LVDS high-speed stable transmission system and method. The disadvantages of this scheme are: firstly, the transmitting and receiving ends must have the same clock source; secondly, it uses 8b / 10b encoding, resulting in low transmission efficiency; thirdly, it uses the control word in the 8b / 10b encoding for training, and training is only performed once when a control word error is detected, requiring retransmission to complete reliable transmission, increasing system complexity and resource overhead; and finally, it does not support parallel transmission of multiple LVDS lines. Patent CN201910068468.7 discloses a multi-channel high-speed serial LVDS data reordering method and circuit based on FPGA. The disadvantages of this scheme are that, firstly, the receiving end performs triple oversampling on the received data, which consumes a large amount of general and scarce resources; secondly, it does not support parallel transmission of multiple pairs of LVDS lines.

[0008] In summary, the current research has the following weaknesses: 1. Some schemes use 8b / 10b encoding, resulting in low transmission efficiency; 2. Some schemes employ oversampling techniques (i.e., sampling the same data multiple times at different locations), increasing the overhead on general and scarce resources; 3. The synchronization techniques in some schemes cannot achieve real-time dynamic adjustment; 4. The vast majority of schemes require strict source or system synchronization at both the transmitting and receiving ends; 5. Most schemes only study high-speed transmission of a single LVDS pair, failing to propose schemes for parallel transmission of multiple LVDS lines. Even in schemes involving parallel transmission of multiple LVDS lines, the reliability is poor; 6. Some schemes employ retransmission techniques, increasing the complexity at both the transmitting and receiving ends and reducing transmission efficiency. Summary of the Invention

[0009] To address the shortcomings of existing technologies, the present invention aims to provide a high-speed LVDS transmission system. This system is a reliable and stable high-speed LVDS transmission system that is high-speed, efficient, supports parallel transmission, has low resource overhead, can be dynamically adjusted in real time, and does not require strict synchronization of transmission and reception, thereby overcoming the aforementioned problems in existing technologies.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0011] A high-speed LVDS transmission system includes a protocol layer and an implementation layer. The protocol layer includes a synchronization sequence and a transmission frame. The implementation layer includes a transmitter and a receiver. The transmitter includes a bit scrambling module, a framing module, a checksum calculation module, and an output parallel-to-serial conversion module. The receiver includes an input delay adjustment module, an input serial-to-parallel conversion module, a single-channel synchronization module, a checksum verification module, a multi-channel synchronization module, an output control module, and a bit dewinding module.

[0012] The present invention also includes the following technical features:

[0013] Specifically, the synchronization sequence is used for training and synchronization at the receiving end. The synchronization sequence cannot be sent continuously and must use transmission frames as intervals. The transmission frames are subdivided into empty frames and data frames. The empty frames are used to separate the two synchronization sequences when there are no data frames, and are also used to monitor the transmission status when there are no data frames. The data frames are used to carry service data.

[0014] Specifically, the synchronization sequence is a known sequence; the transmission frame format includes a frame header, frame length, data, and checksum, wherein the frame length is optional; the frame header is used to locate the start of the transmission frame in the data stream, the frame length is used to locate the end of the transmission frame, the data part is used to carry the actual transmitted data, and the checksum protects the frame length and data part to ensure that the transmission is correct, and is also used for multi-channel synchronization check at the receiving end.

[0015] Specifically, the bit scrambling module scrambles the data input to the scrambling polynomial, making the 0-1 distribution of the output data random, and selects the scrambling polynomial commonly used in the PCIe protocol; the framing module is used to assemble the scrambled data into a transmission frame format and output it, while controlling the output, that is, when there is no service data, the synchronization sequence and empty frames are sent alternately, and the empty frames are optional; when there is data, the framed data is sent. This module does not calculate the check value, and the position of the output check value is left blank; the check value calculation module is used to calculate and fill the blank check value of the framed data, which includes data frames and empty frames; the output parallel / serial conversion module converts the low-speed parallel data into high-speed serial data for transmission.

[0016] Specifically, the single-channel synchronization module is used to determine the position of the synchronization sequence in the transmitted data and adaptively adjust the tap coefficients based on the synchronization sequence; after the adjustment is completed, word synchronization is performed to recover the synchronization sequence; then the frame header is searched and the frame is deframed according to the transmission frame format until the synchronization sequence is detected again.

[0017] Specifically, the workflow of the single-channel synchronization module includes: When the single-channel synchronization module starts working, it is in an initialization state. It then detects the input data sequence until a synchronization sequence is detected, and begins training the delay coefficient. Assuming the delay coefficient range is 0 to X-1, the delay coefficients are sequentially set from 0 to X-1. After the preceding stage stabilizes, the input data is sampled and stored, ultimately yielding X sample values. The X sample values ​​are searched to obtain a continuous interval with the same sample value in the largest range. The midpoint of this interval is the optimal delay coefficient, and the delay coefficient is set to this value. The frame header of the transmission frame is searched, and a waiting timer is started simultaneously. If a frame header has been detected, the frame is deframed according to the frame format until the current frame ends. After the current frame ends, the data at the next moment is judged. If it is a transmission frame header, deframeding continues; if it is a synchronization sequence, the delay coefficient is recalculated. If the waiting counter reaches a given value and no frame header is found, the process jumps back to the initialization state and synchronization is restarted.

[0018] Specifically, the input delay adjustment module is controlled by the single-channel synchronization module to adjust the input data delay so that the sampling point is within the optimal sampling range; the input serial-to-parallel conversion module and the output parallel-to-serial conversion module are functionally symmetrical, converting high-speed serial data into low-speed parallel data for use by subsequent modules; the checksum verification module is used to perform checksum verification on the serially received data to detect whether there are bit errors or anomalies during transmission; the multi-channel synchronization module is used to perform multi-channel synchronization on the serial data; the output control module is used to receive the data after multi-channel synchronization and perform checksum verification to detect whether there are bit errors or anomalies during transmission and multi-channel synchronization. If the checksum verification is incorrect, no output is made to ensure the reliability of the output data; the bit dewinding module corresponds to the bit scrambling module and is used to restore the scrambled data to the original data.

[0019] Specifically, the workflow of the multi-channel synchronization module includes: the multi-channel synchronization module stores each input data separately; for the write address of the first data channel, it outputs it to the read controller after a delay; and the read controller synchronously reads the data in all memories and outputs it.

[0020] Specifically, when the system performs high-speed data transmission, the processing at the transmitting end includes: splitting the data and sending it to a bit scrambling module for bit scrambling; sending the scrambled data to a framing module, which frames the scrambled data according to the transmission frame format determined by the protocol; sending the framed data to a checksum calculation module, which calculates the checksum and fills it into the position specified in the protocol; and outputting the parallel / serial conversion module converts the data into groups and outputs it through the chip's output pins.

[0021] Specifically, the processing at the receiving end includes: data input to the chip's LVDS pin, entering the input delay adjustment module; the input delay adjustment module delays the input data according to the currently set delay coefficient; the input serial-to-parallel conversion module restores the delayed data; the single-channel synchronization module performs single-channel synchronization for each data channel; the checksum calculation module performs checksum verification on the synchronized data; the multi-channel synchronization module performs multi-channel synchronization on the data; the output control module verifies the input data, and if the verification is correct, the data is output; if the verification is incorrect, the current frame of data is skipped; the bit dewinding module dewinds the output of the output control module according to the groups to restore the original data.

[0022] Compared with the prior art, the present invention has the following technical effects:

[0023] This invention features high transmission rate, eliminating the need for 8b / 10b encoding; it supports reliable parallel transmission of any data path; it boasts high efficiency, with all LVDS lines used for data transmission, eliminating the need for additional LVDS lines for status / control signals; it enables real-time dynamic adaptive training, adapting to rapid changes in signal delay; and it consumes fewer resources, requiring only one sampling point per data path (per LVDS line pair), saving sampling and data delay resources. Attached Figure Description

[0024] Figure 1 This is based on the principle of high-speed LVDS transmission.

[0025] Figure 2 This describes the workflow of a single-channel synchronous module.

[0026] Figure 3 This is a block diagram of a multi-channel synchronization module.

[0027] Figure 4 This is a structural diagram of the single-channel transmitter of the present invention.

[0028] Figure 5 This is a schematic diagram of the multi-channel transmitter structure of the present invention.

[0029] Figure 6 This is a structural diagram of the single-channel receiver of the present invention.

[0030] Figure 7 This is a schematic diagram of the multi-channel receiver structure of the present invention. Detailed Implementation

[0031] The following are specific embodiments of the present invention. It should be noted that the present invention is not limited to the following specific embodiments. All equivalent modifications made based on the technical solutions of this application fall within the protection scope of the present invention.

[0032] Example:

[0033] like Figures 2 to 7 As shown, this embodiment provides a high-speed LVDS transmission system, including a protocol layer and an implementation layer. The protocol layer includes the design of the transmission protocol between the transceiver and the receiver, including synchronization sequences and transmission frames. The implementation layer includes the implementation design of the transmitter and the receiver, including a transmitter and a receiver. The transmitter includes a bit scrambling module, a framing module, a checksum calculation module, and an output parallel / serial conversion module. The receiver includes an input delay adjustment module, an input serial / parallel conversion module, a single-channel synchronization module, a checksum verification module, a multi-channel synchronization module, an output control module, and a bit dewinding module.

[0034] The transmission protocol is designed as follows: the data sent from the sender to the receiver consists of two sequences:

[0035] The first type is the synchronization sequence, used for training and synchronization at the receiving end. Synchronization sequences cannot be sent continuously; transmission frames must be used as intervals. The second type is the transmission frame, which can be further subdivided into empty frames and data frames. Empty frames are used to separate the preceding and following synchronization sequences when no data frames are available, and also for monitoring transmission status when no data frames are available. Data frames carry service data. The synchronization sequence is a known sequence. The transmission frame format consists of a frame header, frame length (optional), data, and checksum. The frame header is used to locate the start of the transmission frame in the data stream, the frame length is used to locate the end of the transmission frame (optional), the data portion carries the actual transmitted data, and the checksum protects the frame length (optional) and the data portion to ensure correct transmission; it is also used for multi-channel synchronization verification at the receiving end.

[0036] The bit scrambling module scrambles the data input by the scrambling polynomial, making the 0-1 distribution of the output data more random. Common scrambling polynomials used in protocols such as PCIe can be selected. The framing module is used to assemble the scrambled data into transmission frames and output them. It also controls the output, i.e., when there is no service data, it alternately sends the synchronization sequence and empty frames (optional), and sends the framed data when there is data. This module does not calculate the check value and leaves the position where the check value should be output blank. The check value calculation module is used to calculate and fill the blank check values ​​in the framed data (including data frames and empty frames). The parallel-to-serial conversion module converts low-speed parallel data into high-speed serial data for transmission.

[0037] The single-channel synchronization module is used to determine the position of the synchronization sequence in the transmitted data and adaptively adjust the tap coefficients based on the synchronization sequence; after the adjustment is completed, word synchronization is performed to recover the synchronization sequence; then the frame header is searched and the frame is deframed according to the transmission frame format until the synchronization sequence is detected again.

[0038] like Figure 2 The workflow of a single-channel synchronous module includes:

[0039] When the single-channel synchronization module starts working, it is in the initialization state. It then detects the input data sequence until a synchronization sequence is detected, at which point delay coefficient training begins. Assuming the selectable range for the delay coefficient is 0 to X-1, the delay coefficients are set sequentially from 0 to X-1. After a period of time until the preceding stage stabilizes, the input data is sampled and stored, resulting in X sampled values. These X sampled values ​​are then searched to find the largest consecutive interval with the same sampled value. The midpoint of this interval is considered the optimal delay coefficient, and this value is set as the delay coefficient. After another period of time, the module begins searching for the frame header of the transmission frame, while simultaneously starting a waiting timer to prevent training errors or other situations from causing the frame header to fail to be detected within the expected time, which could lead to the module being in an abnormal state for an extended period and causing system malfunction. If a frame header has been detected, the frame is deframed according to the frame format until the current frame ends. After the current frame ends, the data at the next moment is evaluated. If it is a transmission frame header, deframeding continues; if it is a synchronization sequence, the delay coefficient is recalculated. If the waiting counter reaches a given value and no frame header is found, the module returns to the initialization state and synchronization is restarted.

[0040] The input delay adjustment module, controlled by the single-channel synchronization module, adjusts the input data delay to ensure the sampling point is within the optimal sampling range. The input serial-to-parallel conversion module is functionally symmetrical to the output parallel-to-serial conversion module, converting high-speed serial data into low-speed parallel data for use by subsequent modules. The checksum verification module performs checksum verification on the serially received data, detecting any errors or anomalies during transmission. The multi-channel synchronization module performs multi-channel synchronization on the serial data. The output control module receives the synchronized data and performs checksum verification, detecting any errors or anomalies during transmission and multi-channel synchronization. If the checksum verification is incorrect, no output is made, ensuring reliable output data. The bit dewinding module corresponds to the bit scrambling module, restoring the scrambled data to its original state.

[0041] like Figure 3 The workflow of the multi-channel synchronization module includes: the multi-channel synchronization module stores each input data separately, and outputs the write address of the first data to the read controller after a delay of several clock cycles. The read controller synchronously reads the data in all the memory and outputs it.

[0042] In this embodiment, it is assumed that there is a need for high-speed data transmission between two chips via LVDS lines. Both the transmitting and receiving chips operate at 200MHz, with a maximum data transmission rate approaching 3200Mbps. Therefore, at a 200MHz clock speed, 16 parallel data transmissions are required. Assuming a high-speed LVDS transmission system is used with a serial-to-parallel conversion factor of 4 (i.e., the serial-to-parallel conversion module converts one 800MHz data stream to four 200MHz data streams, and the parallel-to-serial conversion module converts four 200MHz data streams to one 800MHz data stream), data transmission requires four lines at a line rate of 800Mbps.

[0043] In this case, the sending end's processing procedure is as follows:

[0044] The data is split and sent to the bit scrambling module for bit scrambling;

[0045] The scrambled data is sent to the framing module, which then frames the scrambled data according to the transmission frame format determined by the protocol (leaving the checksum part blank).

[0046] The completed framed data is sent to the check value calculation module, which calculates the data, obtains its check value, and fills it into the position specified in the protocol.

[0047] The output parallel / serial conversion module converts four groups of 200Mbps data into four groups of 800Mbps data, and outputs them through the chip's output pins.

[0048] The receiving end's processing includes:

[0049] Four 800Mbps data inputs are sent to four pairs of LVDS pins on the chip and enter the input delay adjustment module; the input delay adjustment module delays the input data according to the currently set delay coefficient.

[0050] The input serial-to-parallel conversion module restores the delayed 4 channels of 800Mbps data into 4 sets of 4 channels of 200Mbps data;

[0051] Each single-channel synchronization module performs single-channel synchronization for each data channel.

[0052] The checksum calculation module performs checksum verification on the synchronized data;

[0053] The multi-channel synchronization module performs multi-channel synchronization of four groups of 200Mbps data.

[0054] The output control module verifies the input data. If the verification is correct, the data is output; if the verification is incorrect, the data in this frame is skipped.

[0055] The bit dewinding module dewinds the output of the output control module according to the grouping to recover the original data.

[0056] The undisclosed technologies in this invention are common knowledge to those skilled in the art.

[0057] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0058] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0059] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A high-speed LVDS transmission system, characterized in that, It includes both the protocol layer and the implementation layer, with the protocol layer including synchronization sequences and transmission frames; The implementation includes a transmitter and a receiver. The transmitter includes a bit scrambling module, a framing module, a checksum calculation module, and an output parallel / serial conversion module. The receiver includes an input delay adjustment module, an input serial / parallel conversion module, a single-channel synchronization module, a checksum verification module, a multi-channel synchronization module, an output control module, and a bit descrambling module. The synchronization sequence is used for training and synchronization at the receiving end. The synchronization sequence cannot be sent continuously and must be separated by transmission frames. The transmission frame is divided into empty frames and data frames. The empty frame is used to separate the two synchronization sequences when there is no data frame, and is also used to monitor the transmission status when there is no data frame. The data frame is used to carry service data. The workflow of the single-channel synchronization module includes: When the single-channel synchronization module starts working, it is in an initialization state. It then detects the input data sequence until a synchronization sequence is detected, and begins training the delay coefficient. Assuming the delay coefficient range is 0 to X-1, the delay coefficients are sequentially set from 0 to X-1. After the preceding stage stabilizes, the input data is sampled and stored, ultimately yielding X sampled values. The X sampled values ​​are searched to find the largest consecutive interval with the same sampled value. The midpoint of this interval is the optimal delay coefficient, and this value is set as the delay coefficient. The frame header of the transmission frame is searched, and a waiting timer is started simultaneously. If a frame header has been detected, the frame is deframed according to the frame format until the current frame ends. After the current frame ends, the data at the next moment is judged. If it is a transmission frame header, deframeding continues; if it is a synchronization sequence, the delay coefficient is recalculated. If the waiting timer reaches a given value and no frame header is found, the module jumps back to the initialization state and resynchronizes. The input delay adjustment module is controlled by the single-channel synchronization module and adjusts the input data delay based on the optimal delay coefficient to ensure that the sampling point is within the optimal sampling interval. The input serial-to-parallel conversion module and the output parallel-to-serial conversion module are functionally symmetrical, converting high-speed serial data into low-speed parallel data for use by subsequent modules. The checksum verification module is used to verify the serially received data and detect whether there are bit errors or anomalies during transmission. The multi-channel synchronization module is used to perform multi-channel synchronization of serial data. The output control module is used to receive the data after multi-channel synchronization and perform checksum verification to detect whether there are bit errors or anomalies during transmission and multi-channel synchronization. If the checksum verification is incorrect, no output is made to ensure the reliability of the output data. The bit descrambling module corresponds to the bit scrambling module and is used to restore the scrambled data to the original data. The workflow of the multi-channel synchronization module includes: the multi-channel synchronization module stores each input data separately; for the write address of the first data, it outputs it to the read controller after a delay; and the read controller synchronously reads the data in all memories and outputs it.

2. The high-speed LVDS transmission system as described in claim 1, characterized in that, The synchronization sequence is a known sequence; the transmission frame format includes a frame header, frame length, data, and checksum, wherein the frame length is optional; The frame header is used to locate the beginning of the transmitted frame in the data stream, the frame length is used to locate the end of the transmitted frame, the data portion is used to carry the actual transmitted data, and the checksum protects the frame length and the data portion to ensure that the transmission is correct. It is also used for multi-channel synchronization check at the receiving end.

3. The high-speed LVDS transmission system as described in claim 2, characterized in that, The bit scrambling module scrambles the data input from the scrambling polynomial to make the 0-1 distribution of the output data random, and selects the scrambling polynomial commonly used in the PCIE protocol; the framing module is used to assemble the scrambled data into a transmission frame format and output it, and at the same time control the output, that is, when there is no service data, the synchronization sequence and empty frames are sent alternately, and the empty frames are optional; when there is data, the framed data is sent. This module does not calculate the check value, and the position of the output check value is left blank. The check value calculation module is used to calculate and fill in the check values ​​left blank in the framed data. The framed data includes data frames and empty frames. The output parallel-to-serial conversion module converts low-speed parallel data into high-speed serial data for transmission.

4. The high-speed LVDS transmission system as described in claim 3, characterized in that, The single-channel synchronization module is used to determine the position of the synchronization sequence in the transmitted data and adaptively adjust the delay coefficient based on the synchronization sequence; after the adjustment is completed, word synchronization is performed to recover the synchronization sequence; then the frame header is searched and the frame is deframed according to the transmission frame format until the synchronization sequence is detected again.

5. The high-speed LVDS transmission system as described in claim 1, characterized in that, When the system performs high-speed data transmission, the processing at the transmitting end includes: splitting the data and sending it to a bit scrambling module for bit scrambling; sending the scrambled data to a framing module, which frames the scrambled data according to the transmission frame format determined by the protocol; sending the framed data to a checksum calculation module, which calculates the checksum and fills it into the position specified by the protocol; and outputting the parallel / serial conversion module converts the data into groups and outputs it through the chip's output pins.

6. The high-speed LVDS transmission system as described in claim 5, characterized in that, The receiving end's processing includes: data input to the chip's LVDS pin, entering the input delay adjustment module; the input delay adjustment module delays the input data according to the currently set delay coefficient; the input serial-to-parallel conversion module restores the delayed data; the single-channel synchronization module performs single-channel synchronization for each data channel; the checksum calculation module performs checksum verification on the synchronized data; the multi-channel synchronization module performs multi-channel synchronization on the data; the output control module verifies the input data, outputting the data if the verification is correct, and skipping the current frame if the verification is incorrect; the bit descrambling module descrambles the output of the output control module according to the groups to recover the original data.

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