Semiconductor structure and preparation method thereof, and three-dimensional memory

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of complex preparation process. The semiconductor structure comprises a stack structure, a first channel layer, a selection gate, a second channel layer, a gate dielectric layer and a bit line contact structure. The stacked structure comprises first dielectric layers and gate layers which are alternately stacked. The first channel layer passes through the stack structure along a first direction. The selection gate is located on the stack structure. The second channel layer at least partially surrounds the selection gate, and the side, close to the stacking structure, of the second channel layer is connected with the first channel layer. The gate dielectric layer is located between the second channel layer and the selection gate. And the bit line contact structure is connected with one side, deviating from the stacking structure, of the second channel layer. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a three-dimensional memory, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] Currently, three-dimensional memory structures are still optimized for space. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a three-dimensional memory, aiming to improve the problem of complex manufacturing process.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor structure is provided. The semiconductor structure includes: a stack structure, a first channel layer, a selection gate, a second channel layer, a gate dielectric layer and a bit line contact structure. The stack structure includes a first dielectric layer and a gate layer alternately stacked. The first channel layer penetrates the stack structure along a first direction. The selection gate is located on the stack structure. The second channel layer The second channel layer at least partially surrounds the selection gate, and the second channel layer is connected to the first channel layer on a side close to the stack structure. The gate dielectric layer The gate dielectric layer is located between the second channel layer and the selection gate. The bit line contact structure is connected to a side of the second channel layer away from the stack structure.

[0008] In the embodiment of the present application, since the second channel layer is at least partially arranged around the selection gate, the gate dielectric layer is located between the second channel layer and the selection gate, the second channel layer, the gate dielectric layer and the selection gate together constitute a top selection transistor, so that a top selection transistor is connected to a first channel layer. Compared with the need to set a layer of selection gate layer and partition the selection gate layer by setting a selection gate cut line, in the embodiment of the present application, there is no need to set a selection gate cut line, that is, the mask used in preparing the selection gate cut line is reduced, which is conducive to reducing the manufacturing process steps of the semiconductor structure. Furthermore, since the gate dielectric layer is located between the second channel layer and the selection gate, it is also conducive to increasing the isolation effect between different selection gates.

[0009] In some embodiments, the second channel layer includes a first part, a second part and a third part, the first part is connected to the first channel layer, the first part and the third part are arranged opposite to each other along the first direction, the second part connects the first part and the third part, and the third part is connected to the bit line contact structure.

[0010] In some embodiments, an end of the third portion facing away from the stack structure extends into the bit line contact structure.

[0011] In some embodiments, in the first direction, a ratio of a distance between the first portion and the third portion to a thickness of the third portion is in a range of 3-5.

[0012] In some embodiments, in the first direction, a thickness of an edge portion of the third portion is smaller than a thickness of a central portion of the third portion.

[0013] In some embodiments, the second portion is disposed around at least a portion of an edge of the first portion;

[0014] The semiconductor structure further includes a connection line, which is located on a side of the stack structure close to the second channel layer. The connection line passes through the second portion and contacts the selection gate.

[0015] In some embodiments, the third portion includes a first edge and a second edge adjacent to each other end to end, the projection shape of the first edge on the reference plane includes a major arc, the projection shape of the second edge on the reference plane includes a secant, and the first edge is connected to the edge of the second portion; the reference plane is parallel to the gate layer.

[0016] In some embodiments, the semiconductor structure further includes a second dielectric layer, the second dielectric layer is located on a side of the stacked structure close to the second channel layer, and the second channel layer, the connecting line and a portion of the bit line contact structure are located in the second dielectric layer.

[0017] In some embodiments, the number of the second channel layers is multiple, and the multiple second channel layers are arranged into at least one channel group, the channel group includes two rows of channel rows, and the channel row includes multiple second channel layers spaced apart along a second direction; the second direction is perpendicular to the first direction and parallel to the gate layer;

[0018] In each of the channel groups, the connection line is located between two rows of the channel rows and connects a plurality of the selection gates in the two rows of the channel rows.

[0019] In some embodiments, in each of the channel groups, the second channel layers in two rows of the channel rows are staggered along the second direction.

[0020] On the other hand, a method for preparing a semiconductor structure is provided, comprising: providing a stacked structure, the stacked structure comprising a first film layer and a second film layer alternately stacked; forming a first channel layer, the first channel layer penetrating the stacked structure along a first direction; forming a second channel layer, the second channel layer being located on the stacked structure, and the second channel layer being connected to the first channel layer on a side close to the stacked structure; forming a selection gate, the second channel layer at least partially surrounding the selection gate; forming a gate dielectric layer, the gate dielectric layer being located between the second channel layer and the selection gate; and forming a bit line contact structure, the bit line contact structure being connected to a side of the second channel layer facing away from the stacked structure.

[0021] In some embodiments, after providing the stacked structure and before forming the first channel layer, it includes: forming an intermediate dielectric layer on one side of the stacked structure; forming the first channel layer includes: forming a channel hole penetrating the stacked structure and the intermediate dielectric layer, the channel hole including a first hole segment and a second hole segment, the first hole segment penetrating the stacked structure, and the second hole segment being located at an end of the first hole segment away from the stacked structure; forming the first channel layer in the first hole segment.

[0022] In some embodiments, the forming of the second channel layer includes: forming a first sublayer in the second hole segment, the first sublayer is arranged to form a first groove; forming a channel sacrificial layer in the first groove, the channel sacrificial layer and the first sublayer are arranged to form a second groove; forming a second sublayer in the second groove, the second sublayer is connected to the first sublayer; removing part of the second sublayer and part of the first sublayer to form the second channel layer having an opening; wherein the first sublayer covering the first channel layer constitutes a first part, the first sublayer covering the hole wall of the second hole segment constitutes a second part, and the second sublayer constitutes a third part.

[0023] In some embodiments, the first film layer is a first dielectric layer, and the second film layer is a gate sacrificial layer; after forming the second sublayer in the second groove and before removing part of the second sublayer and part of the first sublayer, it also includes: replacing the gate sacrificial layer with the gate layer to form a stacked structure.

[0024] In some embodiments, while removing part of the second sub-layer and part of the first sub-layer, part of the intermediate dielectric layer and part of the channel sacrificial layer are also removed to form a connecting groove; forming a select gate includes: removing the remaining channel sacrificial layer to obtain a filling space surrounded by the first part, the second part and the third part, the filling space is connected to the connecting groove through the opening; filling the filling space and the connecting groove with conductive material, the conductive material in the filling space constitutes the select gate.

[0025] In some embodiments, after forming the selection gate and before forming the bit line contact structure, the preparation method further includes: removing part of the conductive material in the connection groove, and the remaining conductive material in the connection groove constitutes a connection line, and the connection line is connected to the selection gate; forming an isolation part in the connection groove, and the isolation part and the intermediate dielectric layer together constitute a second dielectric layer.

[0026] In some embodiments, after removing the remaining channel sacrificial layer and before filling the filling space and the connecting groove with a conductive material, the method further includes: forming the gate dielectric layer in the filling space.

[0027] In some embodiments, forming the bit line contact structure includes: forming a third dielectric layer on the second dielectric layer; removing a portion of the third dielectric layer to form a first contact hole extending through the third portion; and forming a bit line contact structure in the first contact hole.

[0028] In some embodiments, while removing a portion of the third dielectric layer, a portion of the second dielectric layer is also removed, so that an end of the third portion away from the stacking structure extends into the first contact hole.

[0029] In some embodiments, after forming the first contact hole and before forming the bit line contact structure in the first contact hole, it also includes: forming a photoresist layer on the third dielectric layer, and the photoresist layer also fills the first contact hole; removing part of the photoresist layer, part of the third dielectric layer and part of the second dielectric layer to form a second contact hole that penetrates the connecting line; while forming the bit line contact structure in the first contact hole, also forming a select gate contact structure in the second contact hole.

[0030] In yet another aspect, a storage system is provided, comprising: the semiconductor structure as described above, and a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

[0031] On the other hand, an electronic device is provided, comprising the storage system as described above.

[0032] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, three-dimensional memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 A block diagram of a storage system provided in an embodiment of the present application;

[0035] Figure 2 A structural block diagram of a memory card provided in an embodiment of the present application;

[0036] Figure 3 A structural block diagram of another memory card provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application;

[0038] Figure 5 A cross-sectional view of a three-dimensional memory provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a semiconductor structure provided in some embodiments;

[0040] Figure 7 A schematic structural diagram of another semiconductor structure provided for some embodiments;

[0041] Figure 8 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0042] Fig. 9 for Figure 8 A cross-sectional view of the semiconductor structure along the A1-A1 section line;

[0043] Fig.10 for Figure 8 A cross-sectional view of the semiconductor structure along the A2-A2 section line;

[0044] Fig.11A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0045] Fig.12 A structural diagram after forming a channel hole in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0046] Fig.13 A structural diagram after a channel structure is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0047] Fig.14 A flowchart of a method for preparing a second channel layer of a semiconductor structure provided in an embodiment of the present application;

[0048] Fig.15 A structural diagram after forming a first sub-layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0049] Fig.16 A structural diagram after forming a gate sacrificial material in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0050] Fig.17 A structural diagram after a gate sacrificial layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0051] Fig.18 A structural diagram after forming a second sub-layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0052] Fig.19 A partial structural diagram after removing the second sub-layer covering the intermediate dielectric layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0053] Fig. 20 An overall structural diagram after removing the second sub-layer covering the intermediate dielectric layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0054] Fig.21 A structural diagram after a gate sacrificial layer is replaced with a gate layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0055] Fig. 22 A structural diagram after a second mask layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0056] Fig.23 A structural diagram after forming a connection groove in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0057] Fig.24A structural diagram after a filling space is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0058] Fig.25 A structural diagram after a gate dielectric layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0059] Fig.26 A structural diagram after forming a select gate in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0060] Fig. 27 A structural diagram after forming connecting lines in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0061] Fig.28 A structural diagram after forming an isolation layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0062] Fig.29 A structural diagram of a semiconductor structure after grinding an isolation layer in a method for preparing the semiconductor structure provided in an embodiment of the present application;

[0063] Fig.30 A structural diagram after a third dielectric layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0064] Fig.31 A structural diagram after a first contact hole is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0065] Fig.32 A structural diagram after a photoresist layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0066] Fig.33 A structural diagram after forming a first contact hole and a second contact hole in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0067] Fig.34 A structural diagram after a bit line contact structure and a select gate contact structure are formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0068] Fig.35 A structural diagram of a bit line contact structure and a select gate contact structure after grinding in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0069] Fig.36 A top view of a bit line contact structure and a select gate contact structure after grinding in a method for preparing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0071] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0072] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0073] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0074] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0075] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0076] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0077] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0078] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0079] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0080] The embodiment of the present application provides an electronic device, which may be a mobile phone, a mobile phone, a desktop computer, a tablet computer, a laptop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (such as a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, a server, or any other suitable electronic device having a storage device. The embodiment of the present application does not specifically limit the specific form of the above-mentioned electronic device, and it may be any electronic device having a storage device. In some embodiments, the electronic device may include a printed circuit board in addition to a storage device. The printed circuit board is coupled to the storage device and integrated into the electronic device.

[0081] The storage device may be a universal flash storage (UFS) package or an embedded Multi Media Card (eMMC) package, wherein the storage system may be integrated into various types of storage devices.

[0082] Figure 1 A block diagram of a storage system provided in an embodiment of the present application. Figure 1 As shown, in some embodiments, the storage system 1 mainly includes one or more memory devices 2 and a memory controller 3, and the memory controller 3 is coupled to the memory device 2 to control the storage data of the memory device 2. Among them, the storage system 1 can be integrated into a variety of memory cards such as a personal computer memory card international association (PCMCIA or PC), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD), a universal flash storage (UFS) and a solid state drive (SSD). The embodiment of the present application does not limit the number of memory devices 2 included in the storage system 1, and it can be reasonably set according to actual conditions.

[0083] The memory controller 3 is configured to operate in a low duty cycle environment, which may include, for example, an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0084] Alternatively, the memory controller 3 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage of mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0085] Alternatively, the memory controller 3 is configured to manage data stored in the memory device 2 and communicate with an external device (e.g., a host) according to a specific communication protocol. The communication protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-E protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a FireWire protocol.

[0086] The memory controller 3 may also be configured to control the operation of the memory device 2, such as read, erase, and program operations. In some embodiments, the memory controller 3 may also be configured to manage various functions regarding data stored or to be stored in the memory device 2, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the memory controller 3 may also be configured to process error correction codes regarding data read from the memory device 2 or written to the memory device 2. The memory controller 3 may also perform any other suitable functions, such as formatting the memory device 2.

[0087] In some embodiments, Figure 1 As shown, the storage system 1 includes a host 4. For example, the host 4 is coupled to a memory controller 3.

[0088] Exemplarily, the storage system 1 may be integrated into the above-mentioned electronic device. The host 4 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 4 may be configured to send or receive data to and from the memory device 2.

[0089] The memory controller 3 is coupled to the memory device 2 and the host 4, and is configured to control the memory device 2. The memory controller 3 may manage data stored in the memory device 2, and communicate with the host 4.

[0090] In some embodiments, the memory controller 3 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some other embodiments, the memory controller 3 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card 28 (eMMC), and an enterprise storage array used as a data storage device for mobile devices, such as smart phones, tablets, laptops, etc. The memory controller 3 can be configured to control the operations of the memory device 2, such as read, erase, and program operations.

[0091] In some embodiments, the memory controller 3 is configured to control the array of memory cells through the first peripheral circuit and the second peripheral circuit. The memory controller 3 may also be configured to manage various functions related to data stored in or to be stored in the memory device 2, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 3 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 2. Any other appropriate functions may also be performed by the memory controller 3, for example, formatting the memory device 2. The memory controller 3 may communicate with an external device (e.g., a host 4) according to a specific communication protocol. For example, the memory controller 3 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0092] The memory controller 3 and one or more memory devices 2 can be integrated into various types of memory devices, for example, included in the same package (such as a universal Flash storage (UFS) package or an eMMC package). That is, the memory system 1 can be implemented and packaged into different types of final electronic devices.

[0093] Figure 2 A structural block diagram of a memory card provided in an embodiment of the present application. In some embodiments, Figure 2As shown, the memory controller 3 and the single memory device 2 may be integrated into the memory card 11. The memory card 11 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 11 may further include a processor that connects the memory card 11 to a host (e.g., Figure 1 A memory card connector 5 coupled to a host 4).

[0094] Figure 3 FIG. 1 is a block diagram of another memory card provided in an embodiment of the present application. Figure 3 As shown, the memory controller 3 and the plurality of memory devices 2 may be integrated into the SSD 12. The SSD 12 may further include a method for connecting the SSD 12 to a host (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 12 is higher than the storage capacity and / or operating speed of the memory card 11.

[0095] Exemplarily, a memory device 2 is also shown. Figure 4 A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application; Figure 5 A cross-sectional view of a three-dimensional memory provided in an embodiment of the present application. Figure 4 and Figure 5 As shown, taking three-dimensional memory as an example, Figure 4 A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application, Figure 5 A cross-sectional view of a three-dimensional memory.

[0096] It should be noted that in Figure 4 and Figure 5 In the embodiment, the three-dimensional memory extends in the XY plane, and the third direction Z and the second direction Y are, for example, two orthogonal directions in the plane where the source layer SL is located: the second direction Y is, for example, the extension direction of the word line WL, and the third direction Z is, for example, the extension direction of the bit line BL. The first direction X is perpendicular to the ZY plane.

[0097] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a first direction X when the substrate or source layer is located in the lowest plane of the semiconductor device in the first direction X. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0098] In order to more clearly illustrate the structure of the device, Figure 5 In the figure, a view of the array area CA and a view of the step area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the step area SS is based on the left coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the step area SS shows the cross-sectional structure along the X direction.

[0099] See also Figure 4 and Figure 5 Some embodiments of the present disclosure provide a memory device 2. The memory device 2 may include an array device 20. The memory device 2 may also include a source layer SL coupled to the array device 20, and a peripheral device 30 coupled to the array device 20. The peripheral device 30 may be disposed on a side of the array device 20 away from the source layer SL.

[0100] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0101] The array device 20 may include memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 40 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 40 .

[0102] Specifically, see Figure 4 and Figure 5 The memory cell string 40 may include a plurality of transistors, one transistor may be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor (for example, each transistor) may be formed by a semiconductor channel and a gate line G surrounding the semiconductor channel. The gate line G is configured to control the conduction state of the transistor.

[0103] It should be noted that the number of transistors is only illustrative, and the storage cell string of the three-dimensional memory provided in the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0104] Further, along the first direction X, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor at the bottom, thereby controlling the conduction state of the source end channel in the memory cell string 40. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor at the top, thereby controlling the conduction state of the drain end channel in the memory cell string 40. The gate line located in the middle among the multiple gate lines G can be constructed as multiple word lines WL. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (for example, transistor T) in the memory cell string 40 can be completed.

[0105] Continue to see Figure 4 and Figure 5 In some embodiments, the array device 20 may further include an array interconnect layer 29. The array interconnect layer 29 may be coupled to the memory cell string 40. The array interconnect layer 29 may include a drain terminal (i.e., a bit line BL) of the memory cell string 40, and the drain terminal may be coupled to a semiconductor channel of each transistor in at least one memory cell string 40.

[0106] The array interconnect layer 29 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292 and coupled to the drain select gate SGD. The array interconnect layer 29 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as a bit line BL, and a word line connection line WL-CL coupled to a word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0107] The peripheral device 30 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0108] Specifically, in some embodiments, the peripheral device 30 may include a substrate 11 a , a transistor 12 disposed on the substrate 11 a , and a peripheral interconnect layer 13 disposed on the substrate 11 a . The peripheral circuit may include the transistor 12 .

[0109] The material of the substrate 11 a may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0110] The peripheral interconnection layer 13 is coupled to the transistor 12 to transmit electrical signals between the transistor 12 and the peripheral interconnection layer 13. The peripheral interconnection layer 13 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnection conductor layers 132. Different second interconnection conductor layers 132 may be coupled through contacts. The material of the second interconnection conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0111] The peripheral interconnect layer 13 can be coupled to the array interconnect layer 29, so that the array device 20 and the peripheral device 30 can be coupled. Specifically, since the peripheral interconnect layer 13 is coupled to the array interconnect layer 29, the peripheral circuit in the peripheral device 30 can be coupled to the storage cell string in the array device 20 to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 50 can be provided between the peripheral interconnect layer 13 and the array interconnect layer 29, and the peripheral interconnect layer 13 and the array interconnect layer 29 can be bonded and coupled to each other through the bonding interface 50.

[0112] The embodiment of the present application further provides a semiconductor structure 10, which may be the above-mentioned three-dimensional memory. Alternatively, the semiconductor structure may also be a part of the above-mentioned three-dimensional memory, for example, it may include the array device 20 in the above-mentioned embodiment. The embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0113] The semiconductor structure may include a substrate (not shown in the figure). The material of the substrate may include, for example, a semiconductor material, such as silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, etc. The substrate may also be P-type doped or N-type doped.

[0114] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of the present application; Figure 7 A schematic diagram of another semiconductor structure provided in some embodiments. Figure 6 As shown, the semiconductor structure 10 includes a stack structure 100 and a channel structure 600 disposed on a substrate.

[0115] In some embodiments, the semiconductor structure 10 further includes a select gate layer 90 and a select gate channel (topselective gate channel hole, TSG CH). The select gate layer 90 is at least one gate layer located on one side of the stacked structure 100, and the select gate channel CH is arranged through the select gate layer 90, and the select gate channel CH is connected to the channel structure 600. Each channel structure 600 can form at least one field effect transistor (or also called a top select transistor) at a position corresponding to the select gate layer 90.

[0116] In some embodiments, the semiconductor structure 10 further includes a selection gate cut line CUT. The selection gate cut line CUT runs through the selection gate layer 90 and is used to divide the memory cell string into a plurality of regions. For example, the positive projection of the selection gate cut line CUT on the stacked structure 100 may be located between two adjacent channel structures 600, and the selection gate layer 90 located in each region may be controlled separately, thereby realizing the storage function of a single memory cell.

[0117] However, different masks need to be used in the process steps of preparing the selection gate cut line CUT and the selection gate channel CH, and they need to be implemented in different process steps during preparation, resulting in a long preparation process flow.

[0118] In view of this, the semiconductor structure 10 in the embodiment of the present application further includes a selection gate, a second channel layer, a gate dielectric layer and a bit line contact structure.

[0119] Figure 8 A schematic diagram of the structure of a semiconductor structure 10 provided in an embodiment of the present application; Fig. 9 for Figure 8 A cross-sectional view of the semiconductor structure 10 along the A1-A1 section line. Figure 8 and Fig. 9 As shown, the stacking structure 100 includes a plurality of first dielectric layers 101 and a plurality of gate layers 102 which are alternately stacked in sequence. It is understood that the alternate stacking arrangement means that the gate layer 102 and the first dielectric layer 101 are stacked and arranged in an alternating manner; for example, in the direction from the bottom to the top of the stacking structure 100, a gate layer 102 is first arranged, and then a first dielectric layer 101 is arranged on the gate layer 102, and then a gate layer 102 is continuously arranged on the first dielectric layer 101, and the stacking structure 100 is formed in such a cycle. Among them, the specific number of the stacking layers of the gate layer 102 / the first dielectric layer 101 can be set according to actual conditions. The gate layer 102 can be made of a conductive material, for example, it can include one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon and / or silicide. The first dielectric layer 101 can be made of an insulating material, for example, it can include one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0120] In some embodiments, a gate contact dielectric layer (not shown in the figure) may be disposed between the gate layer 102 and the first dielectric layer 101. The material of the gate contact dielectric layer may include titanium nitride, for example.

[0121] For the sake of convenience, the second direction Y and the third direction Z are perpendicular to the first direction X, and are parallel to the gate layer 102 , and intersect with each other. For example, the second direction Y may be perpendicular to the third direction Z.

[0122] The channel structure 600 penetrates the stack structure 100. Fig. 9, the channel structure 600 may be a roughly columnar structure, and a barrier layer 601, a storage layer 602, a tunneling layer 603, a first channel layer 604 and a filling layer 605 are sequentially arranged along a direction perpendicular to the extension thereof. The barrier layer 601 may include a layer, for example, the barrier layer 601 includes a silicon dioxide (SiO2) layer; the barrier layer 601 may also include multiple layers, for example, the barrier layer 601 includes a silicon dioxide and aluminum oxide (Al2O3) stack. The storage layer 602 may include a layer, for example, the storage layer 602 includes a silicon nitride (SiN) layer; the storage layer 602 may also include multiple layers, for example, the storage layer 602 includes silicon nitride, silicon oxynitride (SiON), and a silicon nitride stack. The tunneling layer 603 may include multiple layers, for example, the tunneling layer 603 includes silicon monoxide (SiO), silicon oxynitride, and a silicon oxide stack. The material of the channel layer may include a semiconductor material, for example, polycrystalline silicon and / or single crystal silicon. The material of the filling layer 605 may include an insulating material, for example, silicon dioxide.

[0123] The selection gate 703 is located on the stack structure 100. Exemplarily, the selection gate 703 may be a block, the number of the selection gates 703 may be multiple, and one selection gate 703 may face one channel structure 600. The material of the selection gate 703 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel. This embodiment of the present application is not limited to this.

[0124] The second channel layer 701 at least partially surrounds the selection gate 703, and the side of the second channel layer 701 close to the stack structure 100 is connected to the first channel layer 604. Among them, the entire second channel layer 701 can surround the selection gate 703, or part of the second channel layer 701 can surround the selection gate 703. Exemplarily, the second channel layer 701 can extend to the side of the selection gate 703 close to the stack structure 100, so that the second channel layer 701 and the first channel layer 604 are connected. The gate dielectric layer 702 is located between the second channel layer 701 and the selection gate 703. The material of the gate dielectric layer 702 can include silicon oxide, etc. This embodiment of the present application is not limited to this. Through the above arrangement, the selection gate 703, the second channel layer 701 and the gate dielectric layer 702 constitute the top selection transistor 700.

[0125] In some embodiments, a select gate contact dielectric layer (not shown in the figure) may be disposed between the select gate 703 and the gate dielectric layer 702. The material of the select gate contact dielectric layer may include titanium nitride, for example.

[0126] In some embodiments, the number of the channel structures 600 may be multiple, and the multiple channel structures 600 may be distributed in multiple rows and columns. Accordingly, the number of the top selection transistors 700 may also be multiple, and the multiple top selection transistors 700 may also be distributed in multiple rows and columns. Through the above configuration, one channel structure 600 may correspond to one top selection transistor 700.

[0127] In the embodiment of the present application, since the second channel layer 701 is at least partially arranged around the selection gate 703, the gate dielectric layer 702 is located between the second channel layer 701 and the selection gate 703, the second channel layer 701, the gate dielectric layer 702 and the selection gate 703 together constitute a top selection transistor 700, so that a top selection transistor 700 is connected to a first channel layer 604. Compared with the need to set a selection gate 703 cut line to partition the selection gate 703, in the embodiment of the present application, there is no need to set a selection gate 703 cut line, that is, the mask plate used when preparing the selection gate cut line CUT is reduced, which is conducive to reducing the manufacturing process steps of the semiconductor structure 10. Furthermore, since the gate dielectric layer 702 is located between the second channel layer 701 and the selection gate 703, it is also conducive to increasing the isolation effect between different selection gates 703.

[0128] Based on the above structure, continue to refer to Figure 8 , the semiconductor structure 10 further includes a bit line contact structure 500. The bit line contact structure 500 is connected to the side of the second channel layer 701 away from the stacked structure 100. The bit line contact structure 500 is also connected to the bit line structure. The material of the bit line contact structure 500 may include, for example, a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel. The embodiment of the present application is not limited to this. Through the above arrangement, the bit line structure can be electrically connected to the second channel layer 701 through the bit line contact structure 500, and then electrically connected to the first channel layer 604.

[0129] Furthermore, there may be multiple bit line contact structures 500 , and the multiple bit line contact structures 500 are distributed in multiple rows and columns, so that one bit line contact structure 500 may correspond to one top selection transistor 700 .

[0130] In some embodiments, the second channel layer 701 may be substantially a barrel-shaped structure, and the bit line contact structure 500 contacts the side of the second channel layer 701 away from the stack structure 100. However, since the side of the second channel layer 701 away from the stack structure 100 may have a ring-shaped sidewall, the bit line contact structure 500 may wrap the sidewall. However, through the above arrangement, the contact area between the bit line contact structure 500 and the second channel layer 701 is small, which leads to a reduction in the connection reliability between the second channel layer 701 and the bit line contact structure 500.

[0131] Meanwhile, the small contact area between the bit line contact structure 500 and the second channel layer 701 will also result in poor alignment accuracy between patterns during the photolithography process.

[0132] In some other embodiments, continue to refer to Fig. 9 The second channel layer 701 may include a first portion 711, a second portion 712 and a third portion 713. The first portion 711 is connected to the first channel layer 604, the first portion 711 and the third portion 713 are arranged opposite to each other along the first direction X, the second portion 712 connects the first portion 711 and the third portion 713, and the third portion 713 is connected to the bit line contact structure 500.

[0133] Exemplarily, the second channel layer 701 is sequentially arranged with a first portion 711, a second portion 712 and a third portion 713 from top to bottom, the second portion 712 is arranged around the selection gate 703, the first portion 711 is located on the side of the selection gate 703 away from the stack structure 100, and the third portion 713 is located between the selection gate 703 and the stack structure 100. Among them, the first portion 711 and the third portion 713 can be roughly plate-shaped structures, and the second portion 712 can be roughly cylindrical. By providing the third portion 713 and connecting the third portion 713 to the bit line contact structure 500, it is beneficial to increase the contact area between the bit line contact structure 500 and the second channel layer 701, and further to improve the connection reliability between the second channel layer 701 and the bit line contact structure 500.

[0134] Continue to refer to Figure 8 , one end of the third portion 713 away from the stack structure 100 can extend into the bit line contact structure 500. Exemplarily, the bit line contact structure 500 can be substantially in a columnar structure, and one end of the bit line contact structure 500 close to the stack structure 100 can surround one end of the third portion 713 away from the stack structure 100, so that part of the third portion 713 can extend into the bit line contact structure 500. Through the above arrangement, it is helpful to improve the connection strength between the third portion 713 and the bit line contact structure 500, and improve the connection reliability between the third portion 713 and the bit line contact structure 500.

[0135] Furthermore, the orthographic projection of the third portion 713 on the stacked structure 100 is located within the orthographic projection of the bit line contact structure 500 on the stacked structure 100. The above arrangement is conducive to further increasing the contact area between the bit line contact structure 500 and the second channel layer 701, thereby facilitating the improvement of the connection reliability between the second channel layer 701 and the bit line contact structure 500. At the same time, it is also conducive to improving the alignment accuracy between patterns during the photolithography process and increasing the process window.

[0136] Continue to refer to Fig. 9, in the first direction X, the ratio of the spacing D1 between the first part 711 and the third part 713 to the thickness D2 of the third part 713 is in the range of 3 to 5. For example, the ratio of the spacing D1 between the first part 711 and the third part 713 to the thickness D2 of the third part 713 may be in the range of 3, 4 or 5. Among them, the first part 711, the second part 712 and the third part 713 can jointly enclose an accommodation space, and the selection gate 703 is located in the accommodation space, and the spacing D1 between the first part 711 and the third part 713 is also the height of the accommodation space. When the ratio of the spacing D1 between the first part 711 and the third part 713 to the thickness D2 of the third part 713 is close to 3, the thickness D3 of the third part 713 is relatively thick, so as to avoid the third part 713 from being damaged by pressure, which is conducive to ensuring the connection reliability between the third part 713 and the bit line contact structure 500. When the ratio of the distance D1 between the first portion 711 and the third portion 713 to the thickness D3 of the third portion 713 approaches 5, the height of the accommodation space is relatively high, which is conducive to ensuring that the select gate 703 has sufficient accommodation space.

[0137] Further, in the first direction X, the thickness of the edge portion of the third portion 713 may be less than the thickness of the center portion of the third portion 713. Exemplarily, the surface of the third portion 713 away from the first portion 711 may be a plane, and the surface of the third portion 713 close to the first portion 711 may be an arc surface, and the arc surface is curved toward the side close to the first portion 711. Through the above configuration, the thickness of the edge portion of the third portion 713 is relatively small, which is conducive to increasing the distance D1 between the first portion 711 and the third portion 713, and ensuring that the select gate 703 has sufficient accommodation space; the thickness of the center portion of the third portion 713 is relatively large, which is conducive to preventing the third portion 713 from being damaged due to pressure, and is conducive to ensuring the connection reliability between the third portion 713 and the bit line contact structure 500.

[0138] In some embodiments, the second portion 712 may be arranged around at least a portion of the edge of the first portion 711. Exemplarily, the second portion 712 may be a cylindrical structure, the first portion 711 may be a plate-like structure, and the first portion 711 may block the opening of the second portion 712 toward the stacking structure 100. The above arrangement is conducive to improving the connection reliability between the second portion 712 and the second portion 712.

[0139] Further, the second portion 712 may have an opening M2, and the opening M2 may be adjacent to the third portion 713. The second channel layer 701 may form a filling space M1 having an opening M2, so that the selection gate 703 may be formed into the filling space M1 through the opening M2.

[0140] Fig.10 for Figure 8 A cross-sectional view of the semiconductor structure 10 along the A2-A2 section line. Based on the above structure, combined with Figure 8 , Fig. 9 as well as Fig.10 The semiconductor structure 10 may further include a connection line 800 . The connection line 800 is located on a side of the stacked structure 100 close to the second channel layer 701 . The connection line 800 passes through the second portion 712 and contacts the select gate 703 .

[0141] The surface of the second channel layer 701 away from the stacked structure 100 exceeds the surface of the connecting line 800 away from the stacked structure 100. For example, the third portion 713 of the second channel layer 701 is farther away from the stacked structure 100 than the connecting line 800. The above configuration is helpful to reduce the size of the semiconductor structure 10 in the stacking direction.

[0142] Exemplarily, the number of the connection lines 800 may be multiple, and the present application does not limit the number of the connection lines 800. The multiple connection lines 800 are arranged at intervals along the third direction Z, and the extension direction of the connection lines 800 may intersect with the direction in which the multiple connection lines 800 are arranged at intervals. For example, each connection line 800 extends along the second direction Y. Each connection line 800 may contact multiple selection gates 703, so that each connection line 800 can control multiple top selection transistors 700.

[0143] In some embodiments, the number of the second channel layers 701 is multiple, and the multiple second channel layers 701 are arranged into at least one channel group C1, and the channel group C1 includes two rows of channel rows C2, and the channel rows C2 include multiple second channel layers 701 arranged at intervals along the second direction Y. In each channel group C1, the connecting line 800 is located between the two rows of channel rows C2, and connects the multiple selection gates 703 in the two rows of channel rows C2. Through the above arrangement, the connecting line 800 is connected to a row of channel rows C2 in a channel group C1 along one side of the third direction Z, and the connecting line 800 is connected to another row of channel rows C2 in a channel group C1 along the other side of the third direction Z, that is, the multiple selection gates 703 in the two rows of channel rows C2 can be controlled by the same connecting line 800.

[0144] Furthermore, the above configuration is helpful to reduce the distance between two rows of channel rows C2 in the same channel group C1 along the third direction Z, thereby helping to reduce the size of the semiconductor structure 10 along the third direction Z.

[0145] Of course, in some other embodiments, a connection line 800 may be arranged through the second channel layer 701 in a channel row C2. Through the above arrangement, a plurality of selection gates 703 in a channel row C2 may be controlled by a connection line 800.

[0146] Based on the above structure, in each channel group C1, the second channel layers 701 in two rows of channel rows C2 can be staggered along the second direction Y. Exemplarily, the multiple second channel layers 701 in each channel row C2 are arranged at intervals along the second direction Y. As shown in the figure, there is a gap between two adjacent second channel layers 701 on the upper side, and one gap corresponds to one second channel layer 701 on the lower side. Through the above arrangement, it is helpful to further reduce the spacing between the two rows of channel rows C2 in the same channel group C1 along the third direction Z, and then it is helpful to reduce the size of the semiconductor structure 10 along the third direction Z.

[0147] Furthermore, the second channel layers 701 in two adjacent channel groups C1 and two adjacent channel rows C2 may also be arranged alternately along the second direction Y. The above arrangement is conducive to reducing the spacing between different channel groups C1 along the third direction Z, thereby helping to reduce the size of the semiconductor structure 10 along the third direction Z.

[0148] Of course, in some other embodiments, in each channel group C1, the second channel layers 701 in the two channel rows C2 may also be arranged along the third direction Z. The above configuration is conducive to improving the regularity of the arrangement of the plurality of second channel layers 701 in the channel group C1.

[0149] In some embodiments, the third portion 713 may include a first edge 7131 and a second edge 7132 adjacent to each other end to end, the projection shape of the first edge 7131 on the reference plane includes a major arc, the projection shape of the second edge 7132 on the reference plane includes a secant line, and the first edge 7131 is connected to the edge of the second portion 712. Here, the reference plane may be parallel to the gate layer 102.

[0150] Exemplarily, the projection of the second edge 7132 on the reference plane may coincide with the projection of the edge of the connection line 800 on the reference plane, and the projection of the first edge 7131 on the reference plane may be adjacent to the projection of the edge of the connection line 800 on the reference plane. The above arrangement is conducive to further reducing the spacing between the two rows of channel rows C2 in the same channel group C1 along the third direction Z, thereby helping to reduce the size of the semiconductor structure 10 along the third direction Z.

[0151] In some embodiments, the semiconductor structure 10 may further include a second dielectric layer 200, the second dielectric layer 200 is located on one side of the stacked structure 100 close to the second channel layer 701, and the second channel layer 701, the connecting line 800 and a portion of the bit line contact structure 500 are located in the second dielectric layer 200. Exemplarily, the material of the first dielectric layer 101 may include silicon oxide, silicon nitride or silicon oxynitride, etc. The material of the first dielectric layer 101 and the material of the second dielectric layer 101 may be the same or different. This embodiment of the present application is not limited to this.

[0152] Exemplarily, by disposing a plurality of second channel layers 701 inside the second dielectric layer 200, the plurality of second channel layers 701 can be electrically isolated through the second dielectric layer 200. Similarly, by disposing a plurality of connection lines 800 inside the second dielectric layer 200, the plurality of connection lines 800 can be electrically isolated through the second dielectric layer 200.

[0153] Exemplarily, one end of the bit line contact structure 500 close to the stack structure 100 may extend into the second dielectric layer 200, so that the bit line contact structure 500 may contact the second channel layer 701 in the second dielectric layer 200. Furthermore, the bit line contact structure 500 and the connection line 800 connected to the same second channel layer 701 may also be electrically isolated by the second dielectric layer 200.

[0154] In some embodiments, the semiconductor structure 10 may further include a third dielectric layer 300. The third dielectric layer 300 may be located on a side of the second dielectric layer 200 away from the stacked structure 100. The third dielectric layer 300 may be a single-layer dielectric layer. Alternatively, it may be a plurality of dielectric layers stacked in sequence. This is not limited in the present embodiment of the application. The material of the third dielectric layer 300 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0155] Exemplarily, the bit line contact structure 500 may penetrate the third dielectric layer 300, and the side of the bit line contact structure 500 close to the stacked structure 100 extends from the third dielectric layer 300 and extends into the second dielectric layer 200, so that the bit line contact structure 500 contacts the second channel layer 701 in the second dielectric layer 200. By disposing the bit line contact structure 500 in the third dielectric layer 300 and the second dielectric layer 200, multiple bit line contact structures 500 can be electrically isolated through the third dielectric layer 300 and the second dielectric layer 200.

[0156] In some embodiments, a bit line contact dielectric layer (not shown in the figure) may be further provided between the bit line contact structure 500 and the third dielectric layer 300. The bit line contact dielectric layer may cover the sidewalls of the bit line contact structure 500 and the surface of the bit line contact structure 500 close to the second dielectric layer 200. The material of the bit line contact dielectric layer may include titanium nitride, for example.

[0157] In some embodiments, continue to refer to Figure 8 The semiconductor structure 10 may further include a selection gate contact structure 400 . The number of the selection gate contact structures 400 may be multiple, and one selection gate contact structure 400 may be connected to one connection line 800 .

[0158] Exemplarily, a plurality of selection gate contact structures 400 are arranged at intervals along the third direction Z. The selection gate contact structure 400 may penetrate the third dielectric layer 300, and a side of the selection gate contact structure 400 close to the stack structure 100 may extend from the third dielectric layer 300 and extend into the second dielectric layer 200, so that the selection gate contact structure 400 contacts the connection line 800 in the second dielectric layer 200. By arranging the selection gate contact structure 400 in the third dielectric layer 300 and the second dielectric layer 200, the plurality of selection gate contact structures 400 can be electrically isolated through the third dielectric layer 300 and the second dielectric layer 200.

[0159] Fig.11 A flowchart of a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.11 , the present application embodiment provides a method for preparing a semiconductor structure 10, the method comprising S1-S6:

[0160] S1. Provide a laminated structure, wherein the laminated structure includes a first film layer and a second film layer that are alternately laminated.

[0161] In some embodiments, a stacked structure 100a may be formed on a substrate, and the material of the substrate may be as described in the above embodiments, which will not be described in detail in the embodiments of the present application.

[0162] The embodiment of the present application does not limit the number of the first film layer 1011 and the second film layer 1021. The stacked structure 100a may include a combination of multiple first film layers 1011 and second film layers 1021, and the number of the combination can be set according to the actual application scenario. Further, the embodiment of the present application does not limit the topmost film layer on the side of the stacked structure 100a facing away from the substrate. That is, the topmost film layer of the stacked structure 100a can be the first film layer 1011 or the second film layer 1021.

[0163] In some embodiments, the first film layer 1011 and the second film layer 1021 may be respectively the first dielectric layer 101 and the gate layer 102. For example, the first film layer 1011 is the first dielectric layer 101, and the second film layer 1021 is the gate layer 102, or the first film layer 1011 is the gate layer 102, and the second film layer 1021 is the first dielectric layer 101. With the above arrangement, there is no need to perform a replacement process later, and the above-mentioned stacked structure 100a is also the stacked structure 100.

[0164] Fig.12 This is a structural diagram of a semiconductor structure 10 after a channel hole 103 is formed in a method for preparing the semiconductor structure 10 provided in an embodiment of the present application. Fig.12In some other embodiments, the first film layer 1011 and the second film layer 1021 may be the first dielectric layer 101 and the gate sacrificial layer, respectively. For example, the first film layer 1011 is the first dielectric layer 101, and the second film layer 1021 is the gate sacrificial layer, or the first film layer 1011 is the gate sacrificial layer, and the second film layer 1021 is the first dielectric layer 101. The gate sacrificial layer is used to be replaced by the gate layer 102 later, so that the gate layer 102 and the first dielectric layer 101 form a stacked structure 100.

[0165] The following description only takes the case where the first film layer 1011 is the first dielectric layer 101 and the second film layer 1021 is the gate sacrificial layer as an example to illustrate the method for preparing the semiconductor structure 10 according to the embodiment of the present application.

[0166] In the above embodiment, the materials of the first dielectric layer 101 and the gate sacrificial layer are different, so that the material of the first dielectric layer 101 and the material of the gate sacrificial layer have an etching selectivity ratio. Through the above setting, when the gate sacrificial layer is removed by etching, the first dielectric layer 101 can be retained. Exemplarily, the material of the first dielectric layer 101 may include silicon oxide, silicon nitride or silicon oxynitride, etc. The material of the sacrificial gate layer may include silicon nitride, for example. This embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0167] In the embodiment of the present application, after providing the stacked structure 100 a , the method for preparing the semiconductor structure 10 further includes: forming an intermediate dielectric layer 201 on one side of the stacked structure 100 a .

[0168] Exemplarily, the topmost film layer of the stacked structure 100a is the second film layer 1021, and the intermediate dielectric layer 201 may be located on the side of the topmost film layer away from the first film layer 1011. Further, the thickness of the intermediate dielectric layer 201 may be greater than the thickness of the first film layer 1011 or the second film layer 1021. The above arrangement facilitates the subsequent formation of the top selection transistor 700 in the intermediate dielectric layer.

[0169] In the embodiment of the present application, after the intermediate dielectric layer 201 is formed, the method for preparing the semiconductor structure 10 further includes step S2.

[0170] S2. Form a first channel layer, wherein the first channel layer penetrates the stacked structure along a first direction.

[0171] Reference Fig.12The steps of forming the first channel layer 604 provided in the embodiment of the present application may include: forming a channel hole 103 penetrating the stacked structure 100a and the intermediate dielectric layer 201, the channel hole 103 including a first hole segment 103a and a second hole segment 103b, the first hole segment 103a penetrating the stacked structure 100a, and the second hole segment 103b is located at an end of the first hole segment 103a away from the stacked structure 100.

[0172] A first mask layer may be formed on a side of the intermediate dielectric layer 201 away from the stacked structure 100 , and the first mask layer may have a mask pattern. The intermediate dielectric layer 201 and the stacked structure 100 are etched using the first mask layer as a mask to form the channel hole 103 .

[0173] In the embodiment of the present application, after forming the channel hole 103 penetrating the stacked structure 100 a and the intermediate dielectric layer 201 , the step of forming the first channel layer 604 may further include: forming the first channel layer 604 in the first hole segment 103 a .

[0174] A barrier layer 601, a storage layer 602, a tunneling layer 603, a first channel layer 604 and a filling layer 605 may be sequentially formed in the channel hole 103, and the materials of the above film layers may be as described in the above embodiment, which will not be described again. In addition, the above film layers also sequentially cover the surface of the intermediate dielectric layer 201.

[0175] After the barrier layer 601 , the storage layer 602 , the tunneling layer 603 , the first channel layer 604 and the filling layer 605 are sequentially formed in the channel hole 103 , the filling layer 605 in the second hole segment 103 b is removed, and at the same time, the filling layer 605 covering the surface of the intermediate dielectric layer 201 is also removed.

[0176] Fig.13 FIG. 1 is a structural diagram of a semiconductor structure 10 after a channel structure 600 is formed in a method for preparing the semiconductor structure 10 provided in an embodiment of the present application. Fig.13 As shown, further, the storage layer 602, the tunneling layer 603 and the first channel layer 604 in the second hole segment 103b are removed, and at the same time, the storage layer 602, the tunneling layer 603 and the channel layer covering the surface of the intermediate dielectric layer 201 are also removed. The barrier layer 601, the storage layer 602, the tunneling layer 603, the channel layer and the filling layer 605 retained in the first hole segment 103a together constitute the channel structure 600.

[0177] In the embodiment of the present application, after forming the first channel layer 604 , the method for preparing the semiconductor structure 10 further includes step S3 .

[0178] S3. Form a second channel layer, where the second channel layer is located on the stacked structure, and a side of the second channel layer close to the stacked structure is connected to the first channel layer.

[0179] Fig.14 This is a flowchart of a method for preparing a second channel layer 701 of a semiconductor structure 10 provided in an embodiment of the present application. Fig.14 , the step of forming the second channel layer 701 may include steps S31-S34.

[0180] S31. Form a first sublayer in the second hole segment, wherein the first sublayer is arranged to form a first groove.

[0181] Fig.15 FIG. 1 is a structural diagram after forming a first sub-layer 710 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.15 As shown, the channel material can be filled into the second hole segment 103b to form a first sublayer 710. Since the hole wall of the second hole segment 103b is also covered with a barrier layer 601, the first sublayer 710 is also covered on the barrier layer 601, and the first sublayer 710 is also covered on the surface of the channel structure 600 close to the second hole segment 103b, and the first sublayer 710 covered on the barrier layer 601 and the first sublayer 710 covered on the channel structure 600 jointly enclose the first groove 104. Further, the first sublayer 710 is also covered on the side of the intermediate dielectric layer 201 away from the stacked structure 100a.

[0182] In the embodiment of the present application, after forming the first sub-layer 710 in the second hole segment 103 b , the step of forming the second channel layer 701 may further include step S32 .

[0183] S32, forming a channel sacrificial layer in the first groove, wherein the channel sacrificial layer and the first sub-layer surround a second groove.

[0184] Fig.16 This is a structural diagram after forming a channel sacrificial material 721 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.16 As shown, illustratively, the first groove 104 may be filled with a channel sacrificial material 721 , and the channel sacrificial material 721 may also cover a side of the intermediate dielectric layer 201 away from the stacked structure 100 a .

[0185] Fig.17 This is a structural diagram of a semiconductor structure 10 provided in an embodiment of the present application after a gate sacrificial layer is formed in a method for preparing the semiconductor structure 10. Fig.16 and Fig.17 As shown, after the channel sacrificial material 721 is filled, the channel sacrificial material 721 covering the intermediate dielectric layer 201 and part of the channel sacrificial material 721 located in the first groove 104 can also be removed, and the channel sacrificial material 721 remaining in the first groove 104 is the channel sacrificial layer 720.

[0186] In the embodiment of the present application, after forming the channel sacrificial layer 720 in the first groove 104 , the step of forming the second channel layer 701 may further include step S33 .

[0187] S33, forming a second sub-layer in the second groove, wherein the second sub-layer is connected to the first sub-layer.

[0188] Fig.18 FIG. 1 is a structural diagram after forming a second sub-layer in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.18 As shown, the channel material 731 may continue to be filled into the second groove 105 , and the channel material 731 may also cover the side of the intermediate dielectric layer 201 away from the stacked structure 100 a .

[0189] Fig.19 A partial structural diagram after removing the second sub-layer 730 covering the intermediate dielectric layer 201 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application; Fig. 20 This is an overall structural diagram after removing the second sub-layer 730 covering the intermediate dielectric layer 201 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application.

[0190] Combination Fig.18 , Fig.19 and Fig. 20 As shown, after the channel material 731 is filled, the channel material 731 covering the intermediate dielectric layer 201 can be removed to form a second sublayer 730. The second sublayer 730 and the first sublayer 710 can be made of the same material to improve the connection strength between the first sublayer 710 and the second sublayer 730.

[0191] Furthermore, after the second sub-layer 730 is formed, chemical mechanical polishing may be performed on the surface of the second sub-layer 730 facing away from the stacked structure 100 a to form a planarized surface.

[0192] Fig.21 This is a structural diagram of a semiconductor structure 10 provided in an embodiment of the present application after the gate sacrificial layer is replaced by a gate layer 102. Fig. 20 and Fig.21In the embodiment of the present application, after the second sublayer 730 is formed in the second groove 105, the method for preparing the semiconductor structure 10 further includes: replacing the gate sacrificial layer (i.e., the second film layer 1021) with the gate layer 102 to form a stacked structure 100. The semiconductor structure 10 may further include a gate line gap, and the gate line gap may penetrate the stacked structure 100a. The step of replacing the gate sacrificial layer with the gate layer 102 may include: removing the gate sacrificial layer in the stacked structure 100a through the gate line gap, so that there is a first gap between the first dielectric layers 101, and then forming the gate layer 102 in the first gap through the gate line gap.

[0193] In the embodiment of the present application, after the gate sacrificial layer is replaced with the gate layer 102 , the step of forming the second channel layer 701 may further include step S34 .

[0194] S34, removing part of the second sublayer and part of the first sublayer to form a second channel layer with an opening; wherein the first sublayer covering the first channel layer constitutes the first part, the first sublayer covering the hole wall of the second hole segment constitutes the second part, and the second sublayer constitutes the third part.

[0195] Fig. 22 This is a structural diagram after forming a second mask layer 901 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig. 22 , a second mask layer 901 may be formed on the side of the second sub-layer 730 away from the stacked structure 100, and the second mask layer 901 has a mask pattern. For example, the mask pattern may include a plurality of rectangular openings spaced apart. The first sub-layer 710, the second sub-layer 730, the gate sacrificial layer (i.e., the second film layer 1021), and the intermediate dielectric layer 201 are etched using the second mask layer 901 as a mask. The material of the second mask layer 901 may include, for example, any one of oxide, nitride, photoresist (PR) or photoinitiator (PI). For example, the material of the second mask layer 901 may be silicon dioxide (SiO2), silicon nitride (Si3N4) or polysilicon (ploy).

[0196] Fig.23 This is a structural diagram after forming a connection groove in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.23 As shown, after removing part of the first sublayer 710 and part of the second sublayer 730 through the above steps, the remaining first sublayer 710 and the second sublayer 730 together constitute the second channel layer 701. For example, the first sublayer 710 covering the first channel layer 604 constitutes the first portion 711, the first sublayer 710 covering the hole wall of the second hole segment 103b constitutes the second portion 712, and the second sublayer 730 constitutes the third portion 713.

[0197] In the embodiment of the present application, after forming the second channel layer 701, the method for preparing the semiconductor structure 10 further includes:

[0198] S4. Form a selection gate, wherein the second channel layer at least partially surrounds the selection gate.

[0199] Continue to refer to Fig.23 As described in the above embodiment, during the etching process using the second mask layer 901 as a mask, while removing part of the second sub-layer 730 and part of the first sub-layer 710 , part of the intermediate dielectric layer 201 and part of the channel sacrificial layer 720 are also removed to form the connection groove 202 .

[0200] For example, the number of the connecting grooves 202 can be multiple, and the extending direction of the connecting grooves 202 is parallel to the second direction Y, and the multiple connecting grooves 202 are arranged at intervals along the third direction Z. As described in the above embodiment, in combination with Fig.10 The plurality of second channel layers 701 arranged along the second direction Y form a channel row C2, and two adjacent rows of channel rows C2 arranged along the third direction Z form a channel group C1. Each connection groove 202 is located in a channel group C1 and between two rows of channel rows C2.

[0201] Fig.24 This is a structural diagram after a filling space M1 is formed in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.24 Based on the above structure, the step of forming the selection gate 703 in the embodiment of the present application includes: removing the remaining channel sacrificial layer 720 to obtain a filling space M1 surrounded by the first part 711, the second part 712 and the third part 713, and the filling space M1 is connected to the connecting groove 202 through the opening M2.

[0202] Exemplarily, the intermediate dielectric layer 201 forms the bottom of the connection groove 202, and the second channel layer 701, the channel sacrificial layer 720 and the intermediate dielectric layer 201 form the groove wall of the connection groove 202. Since the channel sacrificial layer 720 can be exposed through the connection groove 202, the channel sacrificial layer 720 can be etched through the connection groove 202, thereby removing the remaining channel sacrificial layer 720.

[0203] Furthermore, combined with Fig.10Since a connection groove 202 is located between two rows of channel rows C2, multiple channel sacrificial layers 720 in the two rows of channel rows C2 can be removed simultaneously through the connection groove 202, thereby forming multiple filling spaces M1. Among them, the connecting port between each filling space M1 and the connection groove 202 is the opening M2 of the second channel layer 701, and the opening M2 is adjacent to the third portion 713 of the second channel layer 701, so that the filling space M1 is close to the stacking structure 100 relative to the connection groove 202. In addition, multiple filling spaces M1 in the two rows of channel rows C2 can be connected to the same connection groove 202 through the corresponding openings M2.

[0204] S5. Form a gate dielectric layer, wherein the gate dielectric layer is located between the second channel layer and the selection gate.

[0205] Fig.25 FIG. 1 is a structural diagram after a gate dielectric layer 702 is formed in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.25 As shown, after forming the filling space M1, the preparation method of the semiconductor structure 10 further includes: filling the filling space M1 and the connecting groove 202 with a gate dielectric material, and the gate dielectric material in the filling space M1 constitutes a gate dielectric layer 702. Exemplarily, since the filling space M1 and the connecting groove 202 are interconnected, the gate dielectric material can be filled into the filling space M1 through the connecting groove 202. Among them, the gate dielectric material in the filling space M1 can cover the inner wall of the filling space M1. At the same time, the gate dielectric material in the connecting groove 202 covers the groove wall and groove bottom of the connecting groove 202, and the gate dielectric material in the connecting groove 202 constitutes an intermediate isolation layer.

[0206] Fig.26 This is a structural diagram after forming a select gate 703 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.26 As shown, after forming the filling space M1 and forming the gate dielectric layer 702, the step of forming the selection gate 703 further includes: filling the filling space M1 and the connection groove 202 with a conductive material 740, and the conductive material 740 in the filling space M1 constitutes the selection gate 703. The conductive material 740 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel. Exemplarily, after forming the selection gate 703 in the filling space M1, the gate dielectric layer 702 is located between the second channel layer 701 and the selection gate 703.

[0207] At the same time, the conductive material 740 is also filled in the connection groove 202 , and the conductive material 740 also covers the side of the intermediate dielectric layer 201 away from the stacked structure 100 .

[0208] Fig. 27This is a structural diagram of a semiconductor structure 10 after forming a connecting line 800 in a method for preparing the semiconductor structure 10 provided in an embodiment of the present application. Fig.26 and Fig. 27 In the embodiment of the present application, after forming the selection gate 703, the preparation method of the semiconductor structure 10 may further include: removing part of the conductive material 740 in the connection groove 202, and the remaining conductive material 740 in the connection groove 202 constitutes a connection line 800, and the connection line 800 is connected to the selection gate 703.

[0209] For example, the conductive material 740 covering the side of the intermediate dielectric layer 201 away from the stacked structure 100 can be removed by etching, and the conductive material 740 located at the upper portion of the connection groove 202 can also be removed, and the conductive material 740 remaining in the connection groove 202 constitutes the connection line 800. The selection gate 703 and the connection line 800 prepared by the above steps can be an integrated structure, which is conducive to improving the connection reliability of the selection gate 703 and the connection line 800.

[0210] Fig.28 This is a structural diagram after forming an isolation layer 203 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.28 After forming the connection line 800, the method for preparing the semiconductor structure 10 may further include: forming an isolation portion in the connection groove 202, wherein the isolation portion and the intermediate dielectric layer 201 together constitute the second dielectric layer 200. Exemplarily, since the conductive material in the connection groove 202 is removed, there is still a remaining space in the connection groove 202, and the isolation material is further filled in the remaining space, and the isolation material in the remaining space constitutes the isolation portion.

[0211] Fig.29 This is a structural diagram of a semiconductor structure 10 after grinding the isolation layer 203 in a method for preparing the semiconductor structure 10 provided in an embodiment of the present application. Fig.28 and Fig.29 , the isolation material also covers the side of the intermediate dielectric layer 201 away from the stacked structure 100. After filling the isolation material, chemical mechanical polishing is performed on the side of the isolation material away from the stacked structure 100 until the isolation material covering the intermediate dielectric layer is removed and the third sub-portion of the second channel layer 701 is exposed. Through the above process steps, the surface of the isolation portion away from the stacked structure 100 and the surface of the second channel layer 701 away from the stacked structure 100 can be located in the same plane.

[0212] In summary, the isolation portion, the middle isolation layer 203 and the connection line 800 are sequentially stacked in the connection groove 202. The isolation layer 203, the middle isolation layer 203 and the middle dielectric layer 201 may be made of the same material, so that the isolation layer 203, the middle isolation layer 203 and the middle dielectric layer 201 form an integrated structure, and the isolation layer 203, the middle isolation layer 203 and the middle dielectric layer 201 together form the second dielectric layer 200.

[0213] In the embodiment of the present application, after forming the second dielectric layer 200 , the method for preparing the semiconductor structure 10 further includes step S6 .

[0214] S6. Form a bit line contact structure, wherein the bit line contact structure is connected to a side of the second channel layer away from the stacked structure.

[0215] Fig.30 FIG. 1 is a structural diagram of a semiconductor structure 10 after a third dielectric layer 300 is formed in a method for preparing the semiconductor structure 10 provided in an embodiment of the present application. Fig.30 As shown, the step of forming the bit line contact structure 500 may include: forming a third dielectric layer 300 on the second dielectric layer 200. Exemplarily, the third dielectric layer 300 may include a plurality of film layers stacked, for example, the third dielectric layer 300 may include a silicon nitride layer and an oxide layer, wherein the silicon nitride layer may be located between the oxide layer and the second dielectric layer 200.

[0216] Fig.31 This is a structural diagram after forming a first contact hole 301 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.31 After forming the third dielectric layer 300, the step of forming the bit line contact structure 500 may further include: removing part of the third dielectric layer 300 to form a first contact hole 301 penetrating to the third portion 713. Exemplarily, a third mask layer may be formed on the third dielectric layer 300, the third mask layer having a mask pattern, and the third dielectric layer 300 is etched using the third mask layer as a mask until the third sub-portion of the second channel layer 701 is exposed to form the first contact hole 301.

[0217] Furthermore, while removing a portion of the third dielectric layer 300, a portion of the second dielectric layer 200 is also removed, so that an end of the third portion 713 away from the stacked structure 100 extends into the first contact hole 301. Exemplarily, a portion of the second dielectric layer 200 surrounding the third sub-portion is also removed, so that the first contact hole 301 also extends into a portion of the second dielectric layer 200.

[0218] The step of forming the bit line contact structure 500 in the first contact hole 301 may further include: forming the bit line contact structure 500 in the first contact hole 301 .

[0219] Fig.32 This is a structural diagram after a photoresist layer 902 is formed in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.32 After forming the first contact hole 301 and before forming the bit line contact structure 500 in the first contact hole 301, the method further includes: forming a photoresist layer 902 on the third dielectric layer 300, and the photoresist layer 902 also fills the first contact hole 301. Exemplarily, the photoresist layer 902 also covers a side of the third dielectric layer 300 away from the stacked structure 100.

[0220] After forming the photoresist layer 902, the method for preparing the semiconductor structure 10 further includes: removing a portion of the photoresist layer 902, a portion of the third dielectric layer 300, and a portion of the second dielectric layer 200 to form a second contact hole 302 penetrating to the connecting line 800. Exemplarily, there may be a plurality of second contact holes 302, and the plurality of second contact holes 302 are arranged at intervals along the third direction Z, one second contact hole 302 corresponds to one connecting line 800, and one connecting line 800 may be exposed in one second contact hole 302.

[0221] Fig.33 This is a structural diagram after forming a first contact hole 301 and a second contact hole 302 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.33 After forming the second contact hole 302 , the method for preparing the semiconductor structure 10 may further include: removing the photoresist layer 902 located in the first contact hole 301 .

[0222] Fig.34 This is a structural diagram after forming a bit line contact structure 500 and a select gate contact structure 400 in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.34 After removing the photoresist layer 902 of the first contact hole 301, a bit line contact structure 500 can be formed in the first contact hole 301. In the embodiment of the present application, while forming the bit line contact structure 500 in the first contact hole 301, a select gate contact structure 400 is also formed in the second contact hole 302.

[0223] For example, the first contact hole 301 and the second contact hole 302 may be filled with a conductive material at the same time, thereby simultaneously forming the bit line contact structure 500 and the select gate contact structure 400. That is, the bit line contact structure 500 and the select gate contact structure 400 may be made of the same material, and the materials of the bit line contact structure 500 and the select gate contact structure 400 may be as described in the above embodiment, and will not be described in detail herein.

[0224] Fig.35A structural diagram of a bit line contact structure 500 and a select gate contact structure 400 after grinding in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application; Fig.36 A top view of a bit line contact structure 500 and a select gate contact structure 400 after grinding in a method for preparing a semiconductor structure 10 provided in an embodiment of the present application. Fig.34 , Fig.35 as well as Fig.36 The conductive material may also cover the surface of the third dielectric layer 300 away from the stacked structure 100. After the conductive material is filled, a chemical mechanical polishing process may be performed to remove the conductive material covering the third dielectric layer 300. Through the above arrangement, the bit line contact structure 500 and the select gate contact structure 400 are isolated from each other.

[0225] In summary, the method for preparing the semiconductor structure 10 provided in the embodiment of the present application can form the selection gate 703 and the connection line 800 in the same process step, thereby saving process steps, simplifying the process flow, and reducing the preparation cost.

[0226] At the same time, since the conductive material is filled in the connection groove 202 to form the selection gate 703 and the connection line 800, that is, the pattern shape of the connection line 800 can be defined by the shape of the connection groove 202, that is, the connection line 800 can be formed without adopting a photolithography process, which saves the mask layer required for preparation, and reduces the influence of the alignment accuracy of the patterns between different layers during the photolithography process, which is conducive to increasing the process window.

[0227] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacked structure, comprising a first dielectric layer and a gate layer alternately stacked; A first channel layer extending through the stack structure along a first direction; A select gate, located on the stack structure; a second channel layer, wherein the second channel layer at least partially surrounds the select gate, and a side of the second channel layer close to the stack structure is connected to the first channel layer; a gate dielectric layer, wherein the gate dielectric layer is located between the second channel layer and the selection gate; A bit line contact structure is connected to a side of the second channel layer away from the stack structure.

2. The semiconductor structure according to claim 1, characterized in that: The second channel layer includes a first part, a second part and a third part, the first part is connected to the first channel layer, the first part and the third part are arranged opposite to each other along the first direction, the second part connects the first part and the third part, and the third part is connected to the bit line contact structure.

3. The semiconductor structure according to claim 2, characterized in that: One end of the third portion away from the stack structure extends into the bit line contact structure.

4. The semiconductor structure according to claim 2, characterized in that: In the first direction, a ratio of a distance between the first portion and the third portion to a thickness of the third portion is in a range of 3-5.

5. The semiconductor structure according to claim 2, characterized in that: In the first direction, a thickness of an edge portion of the third portion is smaller than a thickness of a central portion of the third portion.

6. The semiconductor structure according to claim 2, characterized in that: The second portion is disposed around at least a portion of an edge of the first portion; The semiconductor structure further includes a connection line, which is located on a side of the stack structure close to the second channel layer. The connection line passes through the second portion and contacts the selection gate.

7. The semiconductor structure according to claim 2, characterized in that: The third part includes a first edge and a second edge adjacent to each other end to end, the projection shape of the first edge on the reference plane includes a major arc, the projection shape of the second edge on the reference plane includes a secant, and the first edge is connected to the edge of the second part; the reference plane is parallel to the gate layer.

8. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further includes a second dielectric layer, which is located on a side of the stacked structure close to the second channel layer. The second channel layer, the connecting line and a portion of the bit line contact structure are located in the second dielectric layer.

9. The semiconductor structure according to claim 1, characterized in that: There are multiple second channel layers, and the multiple second channel layers are arranged into at least one channel group, the channel group includes two rows of channel rows, and the channel row includes multiple second channel layers arranged at intervals along a second direction; the second direction is perpendicular to the first direction and parallel to the gate layer; In each of the channel groups, the connection line is located between two rows of the channel rows and connects a plurality of the selection gates in the two rows of the channel rows.

10. The semiconductor structure according to claim 9, characterized in that: In each of the channel groups, the second channel layers in two rows of the channel rows are staggered along the second direction.

11. A method for preparing a semiconductor structure, characterized in that: include: Providing a laminated structure, the laminated structure comprising a first film layer and a second film layer alternately laminated; forming a first channel layer, wherein the first channel layer penetrates the stacked structure along a first direction; forming a second channel layer, wherein the second channel layer is located on the stacked structure, and a side of the second channel layer close to the stacked structure is connected to the first channel layer; forming a select gate, wherein the second channel layer at least partially surrounds the select gate; forming a gate dielectric layer, wherein the gate dielectric layer is located between the second channel layer and the select gate; A bit line contact structure is formed, wherein the bit line contact structure is connected to a side of the second channel layer away from the stacked structure.

12. The preparation method according to claim 11, characterized in that: After providing the stacked structure and before forming the first channel layer, the method includes: forming an intermediate dielectric layer on one side of the stacked structure; The forming of the first channel layer comprises: Forming a channel hole penetrating the stacked structure and the intermediate dielectric layer, the channel hole comprising a first hole segment and a second hole segment, the first hole segment penetrating the stacked structure, and the second hole segment being located at an end of the first hole segment away from the stacked structure; The first channel layer is formed in the first hole segment.

13. The preparation method according to claim 12, characterized in that: The forming of the second channel layer comprises: forming a first sublayer in the second hole segment, wherein the first sublayer is arranged to form a first groove; forming a channel sacrificial layer in the first groove, wherein the channel sacrificial layer and the first sub-layer surround a second groove; forming a second sub-layer in the second groove, wherein the second sub-layer is connected to the first sub-layer; Part of the second sublayer and part of the first sublayer are removed to form the second channel layer having an opening; wherein the first sublayer covering the first channel layer constitutes a first part, the first sublayer covering the hole wall of the second hole segment constitutes a second part, and the second sublayer constitutes a third part.

14. The preparation method according to claim 13, characterized in that: The first film layer is a first dielectric layer, and the second film layer is a gate sacrificial layer; After forming the second sub-layer in the second groove and before removing part of the second sub-layer and part of the first sub-layer, the method further includes: The gate sacrificial layer is replaced by the gate layer to form a stacked structure.

15. The preparation method according to claim 14, characterized in that: While removing part of the second sub-layer and part of the first sub-layer, part of the intermediate dielectric layer and part of the channel sacrificial layer are also removed to form a connection groove; The forming of the selection gate comprises: Removing the remaining channel sacrificial layer to obtain a filling space surrounded by the first part, the second part and the third part, wherein the filling space is connected to the connecting groove through the opening; A conductive material is filled in the filling space and the connecting groove, and the conductive material in the filling space constitutes the selection gate.

16. The preparation method according to claim 15, characterized in that: After forming the select gate and before forming the bit line contact structure, the preparation method further includes: Removing part of the conductive material in the connecting groove, so that the remaining conductive material in the connecting groove forms a connecting line, and the connecting line is connected to the select gate; An isolation portion is formed in the connection groove, and the isolation portion and the intermediate dielectric layer together constitute a second dielectric layer.

17. The preparation method according to claim 15, characterized in that: After removing the remaining channel sacrificial layer and before filling the filling space and the connecting groove with a conductive material, the method further includes: The gate dielectric layer is formed in the filling space.

18. The preparation method according to claim 16, characterized in that: The forming of the bit line contact structure comprises: forming a third dielectric layer on the second dielectric layer; removing a portion of the third dielectric layer to form a first contact hole penetrating to the third portion; A bit line contact structure is formed in the first contact hole.

19. The preparation method according to claim 18, characterized in that: While removing a portion of the third dielectric layer, a portion of the second dielectric layer is also removed, so that an end of the third portion away from the stacking structure extends into the first contact hole.

20. The preparation method according to claim 19, characterized in that: After forming the first contact hole and before forming a bit line contact structure in the first contact hole, the method further includes: forming a photoresist layer on the third dielectric layer, wherein the photoresist layer is also filled in the first contact hole; removing a portion of the photoresist layer, a portion of the third dielectric layer, and a portion of the second dielectric layer to form a second contact hole penetrating to the connecting line; While forming the bit line contact structure in the first contact hole, a select gate contact structure is also formed in the second contact hole.

21. A storage system, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 10; The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

22. An electronic device, characterized in that: Comprising the storage system of claim 21.

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